A memory error detection method and device, electronic equipment and readable storage medium

Abstract

The application provides a memory error test method and device, electronic equipment and a readable storage medium, and relates to the technical field of storage testing. The memory error test method comprises the following steps: inputting an error test instruction into the memory; the error test instruction comprises a first error test frequency; reading error test execution parameters of the memory; the error test execution parameters comprise a second error test frequency; and the memory error test is passed when the first error test frequency and the second error test frequency are equal. In the application, the error test execution parameters of the memory are changed in real time along with actual operation in the actual operation process, so that the error test execution parameters are consistent with the actual operation, thus, only the error test execution parameters of the memory need to be obtained after the error test instruction is input, the error test frequencies in the two parameters are compared, and the test is passed when the two parameters are consistent, without the need of inputting errors into the memory. The test method is simple, time-consuming and efficient, and the test accuracy is high.

Description

Technical Field

[0001] This invention relates to the field of storage testing technology, and in particular to a method and apparatus for testing memory leaks and errors, an electronic device, and a readable storage medium. Background Technology

[0002] During use, memory inevitably accumulates correctable errors (CEs) over time. While CEs do not affect memory usage, frequent errors can negatively impact user experience. Therefore, CEs are filtered out to reduce their frequency.

[0003] Currently, memory error testing involves injecting errors into the memory using an error-injecting device, or testing with memory that has already failed.

[0004] However, the existing memory error tests mentioned above are complex, time-consuming, costly, and have low accuracy. Summary of the Invention

[0005] This invention provides a method and apparatus for testing memory errors, an electronic device, and a readable storage medium, aiming to solve the problems of existing memory error testing being complex, time-consuming, costly, and having low accuracy.

[0006] A first aspect of the present invention provides a method for testing memory leaks, the method comprising:

[0007] Input an error-leaking instruction into memory; the error-leaking instruction includes: a first error-leaking frequency;

[0008] Read the error-free execution parameters from the memory; the error-free execution parameters include: a second error-free frequency;

[0009] The memory error test passes when the first error frequency and the second error frequency are equal.

[0010] In this invention, the memory's error execution parameters change in real time during actual operation, ensuring consistency between the parameters and the actual operation. Therefore, it is only necessary to obtain the memory's error execution parameters after inputting the error instruction, compare the error frequency between the two, and verify the result if they match. Firstly, this invention eliminates the need for injecting repairable errors using injection devices or tools, simplifying testing conditions and reducing costs. Furthermore, since no repairable errors are injected, there is no need to remove or repair them after testing, saving both economic and time costs. Secondly, the absence of injected repairable errors eliminates the time required for such injections, resulting in shorter testing time and higher efficiency. Thirdly, the second error frequency in the error execution parameters remains consistent with the actual error operation during memory operation, ensuring high testing accuracy.

[0011] Optionally, the language of the first error frequency is a first language, which is different from machine language; the error execution parameters for reading the memory include:

[0012] Read the machine language error execution parameters from the memory; the machine language error execution parameters include: the second error frequency of the machine language;

[0013] Before the memory error test passes when the first error frequency and the second error frequency are equal, the method further includes:

[0014] The second error frequency of the machine language is converted into the second error frequency of the first language;

[0015] The condition that the memory error test passes when the first error frequency and the second error frequency are equal includes:

[0016] The memory error test passes when the first error frequency of the first language is equal to the second error frequency of the first language.

[0017] Optionally, if the second error frequency of the first language is a decimal, and if the first error frequency of the first language and the second error frequency of the first language are equal, before the memory error test passes, the method further includes:

[0018] The second error frequency of the first language is rounded down to obtain the integer second error frequency of the first language;

[0019] The condition that the memory error test passes when the first error frequency of the first language is equal to the second error frequency of the first language includes:

[0020] The memory error test passes when the first error frequency of the first language and the second error frequency of the integer in the first language are equal.

[0021] Optionally, at least one of the memory settings is located in the server, and the step of inputting the error correction instruction into the memory includes: inputting the error correction instruction into all memory locations in the server;

[0022] The error execution parameters for reading the memory include:

[0023] Read at least one of the memory-related error execution parameters from the server;

[0024] The condition that the memory error test passes when the first error frequency and the second error frequency are equal includes:

[0025] For the same memory, if the first error frequency and the second error frequency are equal, the error test of the memory passes.

[0026] Optionally, the server includes: at least one central processing unit, the central processing unit corresponding to at least one of the memory; the step of reading the error execution parameters of at least one of the memory in the server includes:

[0027] Read the error execution parameters of at least one memory of at least one of the central processing units in the server;

[0028] The condition that the memory error test passes when the first error frequency and the second error frequency are equal for the same memory includes:

[0029] For the same memory in the same central processing unit, the memory passes the error test when the first error frequency and the second error frequency are equal.

[0030] Optionally, the step of inputting the error message into memory includes:

[0031] In the interface of the basic input / output system, the error instruction is input into the memory.

[0032] Optionally, converting the second error frequency of the machine language into the second error frequency of the first language includes:

[0033] The second error frequency of the machine language is converted into the second error frequency of the first language through a register.

[0034] A second aspect of the present invention provides a memory error testing apparatus, the apparatus comprising: an input module for inputting error instructions into memory; the error instructions comprising: a first error frequency;

[0035] An execution parameter reading module is used to read the error-prone execution parameters from the memory; the error-prone execution parameters include: a second error-prone frequency;

[0036] The testing module is used to ensure that the memory error test passes when the first error frequency and the second error frequency are equal.

[0037] A third aspect of the present invention provides an electronic device comprising: a processor, a memory, and a computer program stored in the memory and executable on the processor, wherein the computer program, when executed by the processor, implements the steps of any of the aforementioned memory error testing methods.

[0038] A fourth aspect of the present invention provides a readable storage medium storing a computer program that, when executed by a processor, implements the steps of any of the aforementioned memory error testing methods.

[0039] The memory error testing device, electronic device, and readable storage medium in this invention all have the same or similar beneficial effects as any of the aforementioned memory error testing methods. Attached Figure Description

[0040] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0041] Figure 1 A flowchart illustrating the steps of a first memory error testing method according to an embodiment of the present invention is shown;

[0042] Figure 2 A schematic diagram of a memory error instruction input interface according to an embodiment of the present invention is shown;

[0043] Figure 3 This invention illustrates a schematic diagram of a second error frequency recording of a first language in memory according to an embodiment of the present invention.

[0044] Figure 4A schematic diagram of the structure of a memory error testing device according to an embodiment of the present invention is shown;

[0045] Figure 5 A schematic diagram of the interface for reading memory error execution parameters is shown in an embodiment of the present invention. Detailed Implementation

[0046] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0047] Figure 1 A flowchart illustrating the steps of a first memory error testing method according to an embodiment of the present invention is shown. (Refer to...) Figure 1 As shown, the testing method may include the following steps:

[0048] Step 101: Input an error leakage instruction into memory; the error leakage instruction includes: a first error leakage frequency.

[0049] Error-skipping instructions are instructions on how memory should skip errors. These instructions may include a first error-skipping frequency. The error-skipping frequency refers to how many correctable errors should be missed per unit of time. The unit of time can be 1 second, 1 minute, 1 hour, 1 day, etc. For example, the error-skipping instruction could include: 1 error / second, meaning that 1 correctable error can be missed per second. As another example, the error-skipping instruction could include: 1 error / minute, meaning that 1 correctable error can be missed per minute.

[0050] For example, for a memory A input error instruction, the error instruction includes: a first error frequency, which is 1 error per second. This can mean that, for correctable errors, memory A can reduce the number of error reports by one for all correctable errors generated within one second.

[0051] Specifically, for recoverable errors in memory, they are usually logged and reported so that operations and maintenance personnel can understand the memory's operational status in a timely manner. However, frequent error reporting can degrade the user experience, especially during a storm of recoverable errors, which can drastically worsen the user experience. The "error omission" here refers to reducing the number of error reports after a recoverable error occurs.

[0052] Typically, it is necessary for maintenance personnel to understand the memory's operating status in a timely manner, while minimizing the impact on the user experience. In general, the error frequency of different memory types may vary, but this invention does not impose specific limitations on this.

[0053] A funnel counter or a funnel specifically responding to the leakage error frequency can be set, but in this embodiment of the invention, no specific limitation is made.

[0054] Step 102: Read the error execution parameters of the memory; the error execution parameters include: second error frequency.

[0055] Memory error detection primarily refers to testing whether the first error frequency in the error-prone instructions input to memory matches the second error frequency actually executed by the memory. The inventors have creatively discovered that during actual operation, the memory's error-prone execution parameters change in real time, ensuring consistency between these parameters and the actual operation. Specifically, this ensures that the error frequency within the error-prone execution parameters matches the actual error frequency. Therefore, this step involves reading the memory's error-prone execution parameters, which may include the second error frequency. The second error frequency refers to the number of correctable errors that can be missed during actual memory operation per unit of time. The unit of time can be 1 second, 1 minute, 1 hour, 1 day, etc.

[0056] In the aforementioned example, step 102 involves reading the error execution parameters of memory A, which may include: the second error frequency.

[0057] It should be noted that there are no specific restrictions on how to read memory leak execution parameters. For example, memory leak execution parameters can be read using ras.mem_leakybucket_check().

[0058] Step 103: If the first error leakage frequency and the second error leakage frequency are equal, the memory error leakage test is passed.

[0059] In other words, if the first error frequency in the error-prone instruction input to memory matches the second error frequency in the execution parameters during actual memory operation, it means that the memory accurately received and executed the error-prone instruction, and therefore the memory error test passes. If the first and second error frequencies are not equal, the memory error test fails.

[0060] For example, in the aforementioned case, if the second error frequency in the error execution parameters of memory A is 1 error per second, and the first error frequency of 1 error per second in the error instruction input to memory A is equal to the second error frequency of 1 error per second in the error execution parameters of memory A during actual operation, it indicates that memory A accurately received and executed the error instruction, and therefore the error test of memory A passed.

[0061] More specifically, the inventors discovered that the main reasons why existing memory error testing is complex, time-consuming, costly, and has low accuracy are as follows: Existing memory error testing compares the actual memory error results with a known number of injectable correctable errors, or compares the actual memory error results with a known number of correctable errors in already faulty memory. Firstly, injecting correctable errors requires injection devices such as the XDP injection device, or injection tools such as the memory injection tool Rastool, or already faulty memory, making the testing conditions complex and costly. Furthermore, after injecting correctable errors, the injected errors must be removed or repaired, incurring significant economic and time costs. Secondly, injecting a large number of correctable errors takes considerable time, resulting in lengthy testing. Thirdly, it is often difficult to match the frequency of injected errors or correctable errors in already faulty memory with the frequency of memory errors, or to match them one-to-one with the frequency of multiple memory errors under test, leading to poor testing accuracy. Specifically, if the injected error frequency is one repairable error every 10 seconds, and the missed error frequency is one error per second, then the missed errors far outweigh the injected repairable errors, making accurate testing impossible. Alternatively, if faulty memory is used, the timing and number of repairable errors are random, making accurate testing of missed errors impossible. Moreover, faulty memory may contain other faults, further reducing the accuracy of missed error testing.

[0062] To address the aforementioned problems, the inventors have creatively discovered that existing memory error testing methods are all result-oriented, neglecting the execution process of memory errors. This leads to complex, time-consuming, and costly memory error testing with relatively low accuracy. The inventors have creatively discovered that during actual operation, the memory's error execution parameters change in real time with the actual operation, ensuring consistency between the parameters and the actual operation. In particular, the error frequency in the execution parameters matches the actual error frequency. Therefore, by inputting an error instruction into the memory and obtaining the second error frequency in the memory's error execution parameters, the actual error result of the memory can be characterized. In this invention, the entire testing process does not require injecting repairable errors into the memory, nor does it require memory that has already failed. Firstly, it eliminates the need for error-injecting devices or tools to inject repairable errors, simplifying the testing conditions and reducing costs. Secondly, since no repairable errors are injected, there is no need to remove or repair the injected errors after the test, saving both economic and time costs. Secondly, since no correctable errors are injected, the time required for injecting correctable errors is eliminated, resulting in shorter testing time and higher testing efficiency. Thirdly, the second error frequency in the error execution parameters is consistent with the actual error operation during memory operation, ensuring high testing accuracy.

[0063] In summary, in this invention, the error execution parameters of the memory change in real time during actual operation, ensuring consistency between the error execution parameters and the actual operation. Therefore, it is only necessary to obtain the error execution parameters of the memory after inputting the error instruction, compare the error frequency of the two, and verify that they are consistent. There is no need to inject errors into the memory. The testing method is simple, has low testing cost, low time consumption, high testing efficiency, and high testing accuracy.

[0064] Optionally, the language with the aforementioned first error frequency is referred to as the first language, which is different from machine language. Machine language is a programming language or instruction code that a machine can directly recognize without translation. Each opcode has a corresponding circuit inside the computer to complete it, or it refers to a programming language or instruction code that can be directly understood and accepted by the machine without translation. This first language can be one of assembly language, high-level language, natural language, mathematical language, etc. Specifically, this first language is the language with the first error frequency. Programming language is a formal language used to define computer programs and to issue instructions to the computer. Programming languages ​​can include machine language, assembly language, and high-level language. Assembly language essentially operates directly on hardware, and due to the use of mnemonics, it is easier to write and read than machine language. In high-level languages, multiple assembly program statements are combined into more concise programming statements, while automatically completing tasks such as stack and register allocation and management, making it easier for programmers to develop programs. Natural language usually refers to a language that evolves naturally with culture and is used in daily work and life. Mathematical language can include mathematical symbols, mathematical formulas, and characters or graphics that aid in calculation and facilitate thinking. Step 102 may include: reading the machine language error execution parameters of the memory, the machine language error execution parameters including: a second error frequency of the machine language. Before step 103, the method may further include: converting the second error frequency of the machine language into the second error frequency of the first language. Step 103 may include: if the first error frequency of the first language and the second error frequency of the first language are equal, the memory error test passes.

[0065] Specifically, since memory is a hardware device, the error execution parameters read from memory are usually in machine language. For ease of input, the aforementioned first error frequency is typically in an easily understood or recognizable language. Therefore, the second error frequency in machine language is converted into a second error frequency in an easily understood and recognizable first language. Then, the second error frequency, which is in an easily understood and recognizable first language, is compared with the first error frequency. Compared to methods where both are machine language or the languages ​​are inconsistent, this invention converts machine language into an easily understood and recognizable first language, which is also the language corresponding to the first error frequency. Therefore, this method is easier to compare and understand, resulting in higher testing efficiency.

[0066] Figure 2 A schematic diagram of a memory error instruction input interface according to an embodiment of the present invention is shown. For example, refer to... Figure 2As shown, the first error frequency in the error-leaking instruction can be: "Set Leaky Bucket Time (Unit / Second)", "Leaky Bucket Time 1", or "Leaky Bucket Count 1". This first error frequency can be from a high-level language or natural language, etc. Therefore, for this example, the obtained second error frequency from the machine language needs to be converted to the second error frequency from the high-level language or natural language to facilitate comparison.

[0067] It should be noted that for the machine language conversion step, a more easily understood or recognized reference language can be selected from assembly language, high-level language, natural language, mathematical language, etc. Both the first and second error frequencies can be converted to this more easily understood or recognized reference language, which is equally easy to compare and understand, and improves testing efficiency. In this case, if the language of the first error frequency differs from the reference language, it is also necessary to convert the first error frequency to the corresponding first error frequency in the reference language.

[0068] For example, if the reference language chosen from assembly language, high-level language, natural language, and mathematical language is a high-level language, and the language with the first error frequency is assembly language, while the language with the second error frequency is machine language, then the first error frequency of assembly language is converted to the first error frequency of the high-level language, and the second error frequency of machine language is converted to the second error frequency of the high-level language. Then, the first and second error frequencies, both being high-level languages, are compared. If they are equal, the memory error test passes.

[0069] Optionally, the aforementioned conversion of the second error frequency in machine language to the second error frequency in the first language can include: converting the second error frequency in machine language to the second error frequency in the first language using a register. The register is not specifically limited; for example, it could be a register containing error information in memory. More specifically, the register could record relevant data about recoverable errors in memory. Converting the second error frequency in machine language to the second error frequency in the first language using a register leverages the existing capabilities of registers for machine language conversion, thus ensuring compatibility with existing register performance and simplifying testing. It should be noted that the specific implementation of this conversion using registers is not specifically limited.

[0070] Optionally, if the second error frequency in the first language is a decimal, before the memory error test passes when the first error frequency and the second error frequency in the first language are equal, the method may further include: rounding the second error frequency in the first language to obtain an integer second error frequency in the first language. The aforementioned passing of the memory error test when the first error frequency and the second error frequency in the first language are equal may include: the memory error test passing when the first error frequency in the first language is equal to the integer second error frequency in the first language.

[0071] In other words, converting the second error frequency in machine language to the second error frequency in first language might result in a decimal value for the second error frequency in first language. However, frequencies are usually integers. To better reflect reality, the decimal second error frequency in first language needs to be rounded down to an integer value. When the first error frequency in first language and the rounded down second error frequency in first language are equal, the memory error test passes, further improving test accuracy.

[0072] Figure 3 A schematic diagram illustrating a second error frequency recording of a first language in memory according to an embodiment of the present invention is shown. For example, refer to... Figure 3 As shown, if Figure 3 In line 44, the value 1.01 in the column containing the memory frequency of 4800MHz represents the second error frequency of the first language for that memory. Combining this with the unit 'Sec' after 1.01 in line 44 (Sec being the abbreviation for second), the second error frequency in the error execution parameters for the 4800MHz memory is 1.01 times / second. Rounding this to the nearest integer yields 1 time / second. It should be noted that this rounding can be done using rounding to the nearest integer or using a rounding method corresponding to the machine language or the first language; in this embodiment of the invention, no specific limitation is made.

[0073] For example, regarding Figure 3 In line 44, the second error rate in the execution parameters of the memory with a frequency of 2666MHz is 1.81 times / second, which, after rounding, can be 2 times / second.

[0074] Optionally, at least one of the aforementioned memory locations is in the server, and step 101 may include: inputting the error-detection instruction to all memory locations in the server. Step 102 may include: reading the error-detection execution parameters of at least one memory location in the server. Step 103 may include: for the same memory location, if the first error-detection frequency and the second error-detection frequency are equal, the error-detection test for that memory location passes.

[0075] Specifically, there is no fixed limit to the number of memory modules configured in a server. This means that error-checking instructions can be input to all memory modules on the server, reducing redundant work. To specifically test the error check of a particular memory module or modules, the error check execution parameters for that memory module or modules can be read. For the same memory module, if the first error check frequency and the second error check frequency are equal, the test for that memory module passes. This method not only reduces redundant work but also offers flexibility and versatility for testing error checks on multiple memory modules within a server, making it more widely applicable.

[0076] For example, if a server has 32 memory modules, error detection instructions can be input to all 32 memory modules. Then, the error detection execution parameters of the 32 memory modules can be read. For each of the 32 memory modules, its corresponding first error detection frequency and second error detection frequency are compared sequentially. If the two are equal, the error detection test for that memory module passes. Thus, the error detection test for all 32 memory modules in the server is completed in one go.

[0077] Alternatively, in the above example, the error execution parameters of memory 0 out of the 32 memory locations in the server can be read. For memory 0, the corresponding first error frequency and second error frequency can be compared. If the two are equal, the error test of memory 0 passes. Then, the error test is performed only on memory 0 in the server.

[0078] Alternatively, in the above example, the error execution parameters of memory 0 and memory 1 of the 32 memory locations in the server can be read. For memory 0, the corresponding first error frequency and second error frequency are compared. If they are equal, the error test for memory 0 passes. For memory 1, the corresponding first error frequency and second error frequency are compared. If they are equal, the error test for memory 1 passes. Thus, error tests are performed on memory 0 and memory 1 in the server.

[0079] Alternatively, in the above example, the error execution parameters of memory locations 0 to 30 (a total of 31 memory locations) in the server can be read. For memory location 0, its corresponding first error frequency and second error frequency are compared. If they are equal, the error test for memory location 0 passes. For memory location 1, the first error frequency and second error frequency are compared. If they are equal, the error test for memory location 1 passes. For memory location 2, the first error frequency and second error frequency are compared. If they are equal, the error test for memory location 2 passes. This process continues until memory location 30 is tested. Thus, the error test for memory locations 0 to 30 in the server is performed.

[0080] Optionally, the aforementioned server includes at least one central processing unit (CPU), with no specific limitation on the number of CPUs included in the server. Each CPU corresponds to at least one of the aforementioned memory units. There is also no specific limitation on the number of memory units corresponding to one CPU. The aforementioned error-checking execution parameters for reading at least one memory unit in the server may include: error-checking execution parameters for reading at least one memory unit of the aforementioned central processing unit in the server. The aforementioned requirement that the error check test for the same memory unit passes when the first error check frequency and the second error check frequency are equal may include: the error check test for the same memory unit of the same central processing unit passes when the first error check frequency and the second error check frequency are equal.

[0081] In other words, to specifically test for errors in the memory of a particular CPU or specific memory modules within a server, the error execution parameters for that memory module on that CPU or specific memory modules can be read. If the first error frequency and the second error frequency are equal for the same memory module on the same CPU, then the test for that memory module on that CPU passes. This method not only reduces repetitive work but also offers flexibility and versatility for testing errors in multiple memory modules across multiple CPUs on a server, making it more widely applicable.

[0082] For example, a server includes CPUs 0 through 7, each with 8 memory modules (0 through 7). Error-checking instructions can be input to all memory modules in the server, meaning 8 x 8 = 64 memory modules can be configured with error-checking instructions. Then, the error-checking execution parameters for these 64 memory modules under CPUs 0 through 7 can be read. For each of these 64 memory modules, its corresponding first error-checking frequency and second error-checking frequency are compared sequentially. If they are equal, the error-checking test for that memory module passes. This process is repeated until all memory modules have undergone error-checking, thus completing the error-checking test for all 64 memory modules under CPUs 0 through 7 in one operation.

[0083] For example, in the above scenario, error-checking instructions can be input to all memory locations in the server, that is, to input error-checking instructions to all 8×8=64 memory locations in the server. Then, the error-checking execution parameters of the 32 memory locations under CPUs 0 to 3 can be read. For each of the 32 memory locations under CPUs 0 to 3, its corresponding first error-checking frequency and second error-checking frequency are compared sequentially. If the two are equal, the error-checking test for that memory location passes. This process is repeated until the error-checking test for all memory locations is completed, thus completing the error-checking test for all 32 memory locations under CPUs 0 to 3 in the server in one go.

[0084] For example, in the above scenario, error-checking instructions can be input to all memory locations in the server, meaning error-checking instructions can be input to all 8 × 8 = 64 memory locations in the server. Then, the error-checking execution parameters of memory location 2 under CPU 0 can be read. The first and second error-checking frequencies of memory location 2 under CPU 0 are compared. If they are equal, the error-checking test for memory location 2 under CPU 0 passes. Thus, the error-checking test for memory location 2 under CPU 0 in the server is completed.

[0085] Optionally, step 101 may include: inputting the error instruction into the memory through the Basic Input Output System (BIOS) interface. This method is compatible with existing BIOSes, and the testing is simple and inexpensive. The BIOS may also store programs, etc., which are not specifically limited in this invention.

[0086] It should be noted that in the above memory error testing method, the order of certain steps is not specifically limited, as long as the aforementioned technical effect is achieved. Specifically, step 102 is executed after step 101.

[0087] Figure 4 A schematic diagram of a memory error testing device according to an embodiment of the present invention is shown. The present invention also provides a reference... Figure 4 As shown, the device may include:

[0088] The input module 201 is used to input error leakage instructions into the memory; the error leakage instructions include: a first error leakage frequency.

[0089] The execution parameter reading module 202 is used to read the error execution parameters of the memory; the error execution parameters include: a second error frequency.

[0090] The test module 203 is used to ensure that the memory error test passes when the first error frequency and the second error frequency are equal.

[0091] Optionally, the language of the first error frequency is a first language, which is different from the machine language; the execution parameter reading module 202 may include: an execution parameter first reading submodule, used to read the machine language error execution parameters in the memory; the machine language error execution parameters include: a second error frequency of the machine language.

[0092] The device may also include:

[0093] The conversion module is used to convert the second error frequency of the machine language into the second error frequency of the first language.

[0094] Test module 203 may include:

[0095] The first test submodule is used to ensure that the memory error test passes when the first error frequency of the first language and the second error frequency of the first language are equal.

[0096] Optionally, if the second error frequency in the first language is a decimal, the apparatus may further include:

[0097] The rounding module is used to round the second error frequency of the first language to obtain an integer second error frequency of the first language.

[0098] The test submodule may include:

[0099] The testing unit is configured to ensure that the memory error test passes when the first error frequency of the first language and the second error frequency of the first language of the integer are equal.

[0100] Optionally, at least one of the memory settings is in the server, and the input module 201 may include: a first input submodule for inputting the error instruction to all memory locations in the server.

[0101] The execution parameter reading module 202 may include: a second execution parameter reading submodule, used to read at least one of the memory error execution parameters in the server.

[0102] Test module 203 may include:

[0103] The second testing submodule is used to ensure that the memory passes the error test when the first error frequency and the second error frequency are equal.

[0104] Optionally, the server includes: at least one central processing unit, the central processing unit corresponding to at least one of the memory; and an execution parameter second reading submodule, which may include:

[0105] A reading unit is used to read the error execution parameters of at least one memory of at least one of the central processing units in the server.

[0106] The second test submodule may include:

[0107] The testing unit is configured to pass the error test of the same memory in the same central processing unit when the first error frequency and the second error frequency are equal.

[0108] Optionally, the input module 201 may include: a second input submodule, used to input the error instruction into the memory in the interface of the basic input / output system.

[0109] Optionally, the conversion module may include: a conversion submodule, used to convert the second error frequency of the machine language into the second error frequency of the first language via a register.

[0110] This memory error testing device has the same or similar beneficial effects as any of the aforementioned memory error testing methods, and they can be referred to each other. To avoid repetition, it will not be described again here.

[0111] The present invention also provides an electronic device, which includes a processor, a memory, and a computer program stored in the memory and executable on the processor, wherein the computer program, when executed by the processor, implements the steps of any of the aforementioned memory leak test methods.

[0112] The processors mentioned above can be general-purpose processors, including central processing units (CPUs), network processors (NPs), etc.; they can also be digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0113] The memory may include random access memory (RAM) or non-volatile memory, such as at least one disk storage device. Optionally, the memory may also be at least one storage device located remotely from the aforementioned processor.

[0114] This invention also provides a readable storage medium storing a computer program, which, when executed by a processor, implements the steps of any of the aforementioned memory leak test methods.

[0115] The application will be further explained below with reference to specific embodiments.

[0116] Example

[0117] Reference Figure 3 As shown, the server includes CPU 0, and memory 0 is configured under CPU 0 in the server.

[0118] First step, refer to Figure 2 As shown, the error message is input to all memory of the server through the BIOS interface. The error message includes: a first error frequency of 1 time / second. The language of the first error frequency is a high-level language or natural language.

[0119] The second step, Figure 5 This diagram illustrates a memory error execution parameter reading interface according to an embodiment of the present invention. (Refer to...) Figure 5 As shown, the error-checking parameters for memory location 0 under CPU 0 are read using `ras.mem_leakybucket_check()`. Memory location 0 is located on CPU 0, and its frequency is 4800MHz. The error-checking parameters for the memory location can be as follows:

[0120] The value of limit is 0.

[0121] DCLK = 2400MHz

[0122] leaky_bkt_cfg_hi=0x12

[0123] leaky_bkt_cfg_lo==0x0f

[0124] The third step is to write the error execution parameters from memory location 0 under CPU 0 into the register. (Refer to...) Figure 2 As shown, the value of limit is 0, filled into line 16, representing CPU 0. 0x12 and 0x0f are filled into line 44. The second error frequency in the machine language of the error execution parameters for memory location 0 under CPU 0 is read and converted into the first language of either high-level or natural language. The converted data 1.01 is then filled into the line. Figure 2 In the column corresponding to the frequency of 4800MHz under CPU 0 in row 44, combined with the unit Sec in the column following 1.01 in row 44, the second error frequency of the converted first language can be 1.01 times / second.

[0125] It should be noted that the 0 in line 15 refers to reading memory under CPU 0. To determine which row or column to fill in the second error frequency of the converted first language in this step, select the row based on the unit duration of the second error frequency of the converted first language, and select the column based on the memory frequency corresponding to the second error frequency. For example, if the unit duration of the second error frequency of the converted first language in this step is seconds, then rows 40 to 45 can be filled in; if the memory frequency of the second error frequency of the converted first language in this step is 4800MHz, then the column that can be filled in is determined.

[0126] The fourth step is to round the second error frequency of the first language, which is 1.01 times / second, to obtain an integer value of 1 time / second.

[0127] The fifth step is to compare the first error frequency of 1 time / second with the second error frequency of 1 time / second for the first language of integers. If they are equal, the error test for memory 0 under CPU 0 is passed.

[0128] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0129] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in the various embodiments of the present invention.

[0130] The embodiments of the present invention have been described above with reference to the accompanying drawings. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of the present invention without departing from the spirit and scope of the claims. All of these forms are within the protection scope of the present invention.

Claims

1. A method for testing memory leaks, characterized in that, The method includes: Input an error-missing instruction into memory; the error-missing instruction includes: a first error-missing frequency; the first error-missing frequency is the number of correctable errors that are missed within a unit of time. Read the memory's error-free execution parameters; the error-free execution parameters include: a second error-free frequency; the second error-free frequency is the number of correctable errors that are missed during actual memory operation per unit time. The memory error test passes when the first error frequency and the second error frequency are equal. The language of the first error frequency is a first language, which is different from machine language; the error execution parameters for reading the memory include: Read the machine language error execution parameters from the memory; the machine language error execution parameters include: the second error frequency of the machine language; Before the memory error test passes when the first error frequency and the second error frequency are equal, the method further includes: The second error frequency of the machine language is converted into the second error frequency of the first language; The condition that the memory error test passes when the first error frequency and the second error frequency are equal includes: The memory error test passes when the first error frequency of the first language is equal to the second error frequency of the first language.

2. The memory error testing method according to claim 1, characterized in that, If the second error frequency of the first language is a decimal, and if the first error frequency of the first language is equal to the second error frequency of the first language, before the memory error test passes, the method further includes: The second error frequency of the first language is rounded down to obtain the integer second error frequency of the first language; The condition that the memory error test passes when the first error frequency of the first language is equal to the second error frequency of the first language includes: The memory error test passes when the first error frequency of the first language and the second error frequency of the integer in the first language are equal.

3. The memory error testing method according to claim 1, characterized in that, At least one of the memory settings is in the server, and the step of inputting the error instruction into the memory includes: inputting the error instruction into all memory locations in the server; The error execution parameters for reading the memory include: Read at least one of the memory-related error execution parameters from the server; The condition that the memory error test passes when the first error frequency and the second error frequency are equal includes: For the same memory, if the first error frequency and the second error frequency are equal, the error test of the memory passes.

4. The memory error testing method according to claim 3, characterized in that, The server includes: at least one central processing unit, the central processing unit corresponding to at least one memory; the step of reading the error execution parameters of at least one memory in the server includes: Read the error execution parameters of at least one memory of at least one of the central processing units in the server; The condition that the memory error test passes when the first error frequency and the second error frequency are equal for the same memory includes: For the same memory in the same central processing unit, the memory passes the error test when the first error frequency and the second error frequency are equal.

5. The memory error testing method according to any one of claims 1 to 4, characterized in that, The step of inputting error-related instructions into memory includes: In the interface of the basic input / output system, the error instruction is input into the memory.

6. The memory error testing method according to claim 1, characterized in that, The step of converting the second error frequency of the machine language into the second error frequency of the first language includes: The second error frequency of the machine language is converted into the second error frequency of the first language through a register.

7. A memory error testing device, characterized in that, include: The input module is used to input error-prone instructions into memory; The error omission instruction includes: a first error omission frequency; the first error omission frequency is the number of correctable errors that are missed within a unit of time. An execution parameter reading module is used to read the memory's error-free execution parameters; the error-free execution parameters include: a second error-free frequency; the second error-free frequency is the number of correctable errors that are missed during actual memory operation per unit time. The testing module is used to ensure that the memory error test passes when the first error frequency and the second error frequency are equal. The language of the first error frequency is a first language, which is different from the machine language; the execution parameter reading module includes: an execution parameter first reading submodule, used to read the machine language error execution parameters in the memory; the machine language error execution parameters include: a second error frequency of the machine language; The device further includes: A conversion module is used to convert the second error frequency of the machine language into the second error frequency of the first language; The testing module includes: The first test submodule is used to ensure that the memory error test passes when the first error frequency of the first language and the second error frequency of the first language are equal.

8. An electronic device, characterized in that, include: A processor, a memory, and a computer program stored in the memory and executable on the processor, wherein the computer program, when executed by the processor, implements the steps of the memory leak test method as described in any one of claims 1-6.

9. A readable storage medium, characterized in that, A computer program is stored on the readable storage medium, which, when executed by a processor, implements the steps of the memory leak test method as described in any one of claims 1-6.

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