Display panel and display device

Abstract

The application discloses a display panel and a display device, the first shift register and the second shift register of the display panel are both single-edge driven, the first shift register provides a light-emitting control signal, the second shift register provides a first control signal, the first shift register is electrically connected with a light-emitting control signal line through a first connecting line, and the connecting point of the first connecting line and the light-emitting control signal line is located in a middle area of a display area, and / or the second shift register is electrically connected with a first scanning signal line through a second connecting line, and the connecting point of the second connecting line and the first scanning signal line is located in the middle area, so that the application reduces the load difference of gate driving between different column pixels and improves display performance.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more specifically, to a display panel and a display device. Background Technology

[0002] Currently, display technology has permeated all aspects of people's daily lives, and correspondingly, more and more materials and technologies are being used in displays. Display panels, as a crucial component of display devices, are used to realize the display function. Today, the mainstream display panels are mainly liquid crystal displays (LCDs) and organic light-emitting diode (OLED) displays.

[0003] Organic light-emitting diodes (OLEDs), as current-driven light-emitting devices, are increasingly used in high-performance displays. OLED displays possess numerous superior characteristics, including self-emissiveness, wide viewing angle, fast response speed, high contrast, wide color gamut, low power consumption, thin panel, rich colors, flexible display capability, and wide operating temperature range. Therefore, they are hailed as the next-generation "star" flat panel display technology. An OLED display panel includes an anode and a cathode, as well as a hole transport layer, an organic light-emitting layer, and an electron transport layer disposed between the anode and cathode. The anode provides hole injection, and the cathode provides electron injection. Driven by an external voltage, holes and electrons injected from the cathode and anode recombine in the organic light-emitting layer, forming electron-hole pairs (i.e., excitons) at bound energy levels. Excitons radiate de-excitation, emitting photons and producing visible light.

[0004] In the existing technology, the driving circuit of organic light-emitting display panels usually adopts 7T1C (T is transistor, C is storage capacitor), 8T1C, 16T1C, etc., but there is a problem of uneven pixel column display.

[0005] Therefore, there is an urgent need to provide a display panel and display device that can improve the unevenness of pixel column display. Summary of the Invention

[0006] In view of this, the present invention provides a display panel and a display device for improving the problem of uneven pixel column display.

[0007] On one hand, the present invention provides a display panel, comprising: a display area and a non-display area at least partially surrounding the display area, the display area comprising a plurality of pixel rows, each pixel row comprising a plurality of pixel circuits, and the non-display area comprising a first non-display area and a second non-display area disposed opposite to each other along a first direction, wherein...

[0008] The first non-display area includes multiple cascaded first shift registers, and the second non-display area includes multiple cascaded second shift registers. The first shift registers provide light emission control signals to the pixel circuit, and the second shift registers provide first control signals to the pixel circuit.

[0009] The display area includes a central area, a first area and a second area adjacent to the central area, and the central area is located between the first area and the second area along the first direction;

[0010] The display panel further includes light emission control signal lines and first scan signal lines extending in a first direction and arranged in a second direction, wherein the light emission control signal lines and the first scan signal lines are electrically connected to the pixel circuit.

[0011] The display panel further includes a first connecting line, one end of which is electrically connected to the first shift register, and the other end of which is electrically connected to the light emission control signal line. The connection point between the first connecting line and the light emission control signal line is located in the middle area.

[0012] And / or, the display panel further includes a second connecting line, one end of which is electrically connected to the second shift register, and the other end of the first connecting line is electrically connected to the first scan signal line, with the connection point between the second connecting line and the first scan signal line located in the intermediate area.

[0013] On the other hand, this aspect also provides a display device including the aforementioned display panel.

[0014] Compared with the prior art, the display panel and display device provided by the present invention achieve at least the following beneficial effects:

[0015] The display panel of this invention includes a first non-display area and a second non-display area disposed opposite to each other along a first direction. Both the first shift register providing light emission control signals to the pixel circuits and the second shift register providing first control signals to the pixel circuits are single-sided areas. The first shift register is located in the first non-display area, and the second shift register is located in the second non-display area. In related technologies, since both the first and second shift registers are single-sided driven, the light emission control signal line connected to the first shift register is loaded with an entire row of pixels. Similarly, the first scan signal line connected to the second shift register is loaded with the same row of pixels. Due to the resistive load generated by the pixel circuits themselves, the light emission control signal received by pixel circuits farther from the first shift register gradually decreases, becoming lower than the light emission control signal received by pixel circuits closer to the first shift register. Similarly, the first control signal received by pixel circuits farther from the second shift register gradually decreases, becoming lower than the first control signal received by pixel circuits closer to the second shift register, resulting in uneven pixel display across different pixel columns. In this invention, along the first direction, the display area includes a central area and a first area and a second area located on both sides of the central area. A first connecting line can be provided on the display panel. One end of the first connecting line is electrically connected to a first shift register, and the other end of the first connecting line is connected to a light emission control signal line. The light emission control signal line is not directly electrically connected to the first shift register, but is electrically connected to the first shift register through the first connecting line. The connection point between the first connecting line and the light emission control signal line is located in the central area. That is, the access point of the light emission control signal provided by the first shift register is not located in the first non-display area but in the central area of ​​the display area. In this way, after the light emission control signal is accessed from the connection point between the first connecting line and the light emission control signal line, it is transmitted to the left and right sides of the connection point through the light emission control signal line, which to a certain extent improves the problem of uneven display caused by the weakening of the light emission control signal due to the pixel circuit load. Similarly, a second connection line can also be set on the display panel. One end of the second connection line is electrically connected to the second shift register, and the other end of the second connection line is connected to the first scan signal line. The first scan signal line is not directly electrically connected to the second shift register, but is electrically connected to the second shift register through the second connection line. The connection point between the second connection line and the first scan signal line is located in the middle area. That is, the access point of the first control signal provided by the second shift register is not located in the second non-display area, but in the middle area of ​​the display area. In this way, after the first control signal is accessed from the connection point between the second connection line and the first scan signal line, it is transmitted to the left and right sides of the connection point through the first scan signal line, which improves the display unevenness caused by the weakening of the first control signal due to the pixel circuit load to a certain extent.

[0016] Of course, any product implementing this invention does not necessarily need to achieve all of the technical effects described above at the same time.

[0017] Other features and advantages of the invention will become clear from the following detailed description of exemplary embodiments of the invention with reference to the accompanying drawings. Attached Figure Description

[0018] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments of the invention and, together with their description, serve to explain the principles of the invention.

[0019] Figure 1 This is a schematic diagram of the planar structure of a display panel in related technologies;

[0020] Figure 2 This is a schematic diagram of a planar structure of a display panel provided by the present invention;

[0021] Figure 3 This is a schematic diagram of a planar structure of another display panel provided by the present invention;

[0022] Figure 4 This is a schematic diagram of a planar structure of another display panel provided by the present invention;

[0023] Figure 5 This is a circuit diagram of a pixel circuit provided by the present invention;

[0024] Figure 6 This is a schematic diagram of a planar structure of another display panel provided by the present invention;

[0025] Figure 7 This is a schematic diagram of a planar structure of another display panel provided by the present invention;

[0026] Figure 8 This is a schematic diagram of a planar structure of another display panel provided by the present invention;

[0027] Figure 9 This is a schematic diagram of a planar structure of another display panel provided by the present invention;

[0028] Figure 10 This is a schematic diagram of a planar structure of another display panel provided by the present invention;

[0029] Figure 11 This is a schematic diagram of a planar structure of another display panel provided by the present invention;

[0030] Figure 12 yes Figure 2 A cross-sectional view along line A-A' in the middle;

[0031] Figure 13 This is a schematic diagram of a planar structure of another display panel provided by the present invention;

[0032] Figure 14yes Figure 13 A cross-sectional view of B-B';

[0033] Figure 15 This is a schematic diagram of a planar structure of another display panel provided by the present invention;

[0034] Figure 16 yes Figure 15 A cross-sectional view of C-C';

[0035] Figure 17 This is a schematic diagram of the planar structure of a display device provided in an embodiment of the present invention. Detailed Implementation

[0036] Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of the invention.

[0037] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit the invention or its application or use.

[0038] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0039] In all the examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values.

[0040] It should be noted that similar labels and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0041] In view of the problem of uneven pixel display in the display panels of related technologies, the inventors conducted the following research on related technologies, referring to... Figure 1 , Figure 1 This is a schematic diagram of the planar structure of a display panel in related technologies. Figure 1The display panel 000 includes a display area AA' and a non-display area BB' surrounding the display area AA'. The display area AA' includes a pixel P', and the pixel P' has a pixel circuit Q' along the first direction X. The non-display area BB' includes a first non-display area BB1' and a second non-display area BB2' disposed opposite to each other. The first non-display area BB1' has a first shift register 021, which provides an emission control signal Emit to the pixel circuit Q'. The emission control signal line 050 is directly electrically connected to the first shift register 021. The second non-display area BB2' has a second shift register 022, which provides an emission control signal Emit to the pixel circuit Q'. A control signal S1 is provided. The first scan signal line 030 is directly electrically connected to the second shift register 022. A third shift register 023 is also present in the first non-display area BB1' and the second non-display area BB2'. The third shift register 023 provides the second control signal S2 to the pixel circuit Q'. Both the first shift register 021 and the second shift register 022 are single-sided driven. Each light-emitting control signal line 050 carries one row of pixel circuits Q', and each first scan signal line 030 also carries one row of pixel circuits Q'. Because the pixel circuit Q' itself has a certain resistive load, the light-emitting control signal Emit and the first control signal S1 will inevitably be weakened. Figure 1 Pixel P1' is closer to the first shift register 021, while pixel P2' is farther from the first shift register 021. Pixel P2' is closer to the second shift register 022, while pixel P1' is farther from the second shift register 022. Therefore, the light emission control signal Emit received by pixel P1' will be greater than the light emission control signal Emit received by pixel P2', and the first control signal S1 received by pixel P2' will be greater than the light emission control signal S1 received by pixel P1'. This causes the problem of uneven display between pixels P1' and P2'.

[0042] In view of this, the present invention provides a display panel and a display device to improve the above-mentioned problems. Specific embodiments of the display panel will be described in detail below.

[0043] Reference Figures 2 to 5 , Figure 2 This is a schematic diagram of a planar structure of a display panel provided by the present invention. Figure 3 This is a schematic diagram of a planar structure of another display panel provided by the present invention. Figure 4 This is a schematic diagram of a planar structure of another display panel provided by the present invention. Figure 5 This is a circuit diagram of a pixel circuit provided by the present invention. Figures 2 to 4The display panel 1000 includes: a display area AA and a non-display area BB that at least partially surrounds the display area AA. The display area AA includes a plurality of pixel rows 1, each pixel row 1 including a plurality of pixel circuits Q. The non-display area BB includes a first non-display area BB1 and a second non-display area BB2 disposed opposite to each other along a first direction X. The first non-display area BB1 includes a plurality of cascaded first shift registers 21, and the second non-display area BB2 includes a plurality of cascaded second shift registers 22. The first shift registers 21 provide light emission control signals to the pixel circuits Q, and the second shift registers 22 provide first control signals to the pixel circuits Q. The display area AA includes a middle area 11, a first area 12 and a second area 13 adjacent to the middle area 11. Along the first direction X, the middle area 11 is located between the first area 12 and the second area 13. The display panel 1000 also includes a light emission control signal line 50 extending along a first direction X and arranged in a second direction Y, and a first scan line signal line 30, both of which are electrically connected to the pixel circuit Q; the display panel 1000 also includes a first connecting line 60, one end of which is electrically connected to a first shift register 21, and the other end of which is electrically connected to the light emission control signal line 50, with the connection point between the first connecting line 60 and the light emission control signal line 50 located in the intermediate area 11; and / or, the display panel 1000 also includes a second connecting line 70, one end of which is electrically connected to a second shift register 22, and the other end of which is electrically connected to the first scan line signal line 30, with the connection point between the second connecting line 70 and the first scan line signal line 30 located in the intermediate area 11.

[0044] Specifically, Figures 2 to 4 The display panel 1000 includes a display area AA and a non-display area BB surrounding the display area AA. Only the case where the non-display area BB completely surrounds the display area AA is shown; however, the non-display area BB can also partially surround the display area AA, such as in a waterdrop screen, but this is not specifically limited here. Along the first direction X, the non-display area BB includes a first non-display area BB1 and a second non-display area BB2, i.e., a left border and a right border, respectively. Along the second direction Y, the non-display area BB also includes a top border and a bottom border (not shown in the figure), which are also relatively positioned. The bottom border typically houses a driver chip (not shown in the figure), which provides signals for display. The display panel 1000 also includes data lines (not shown in the figure) arranged along the first direction X and extending in the second direction Y, which transmit data signals to the pixel circuits Q.

[0045] Figures 2 to 4In the display area AA, there are a middle area 11, a first area 12 and a second area 13 adjacent to the middle area 11. Along the first direction X, the middle area 11 is located between the first area 12 and the second area 13. Here, the middle area 11 refers to the middle area 11 domain located in the display area AA along the first direction X. The length of the middle area 11 in the first direction X is not specifically limited here. Of course, the length of the first area 12 and the length of the second area 13 in the first direction X are not specifically limited here.

[0046] The first shift register 21 is located in the first non-display area BB1, meaning it is driven on one side. This configuration reduces the width of the first non-display area BB1 in the first direction X, achieving a narrow bezel. The first shift register 21 provides the light emission control signal to the pixel circuit Q. Similarly, the second shift register 22 is located in the second non-display area BB2, meaning it is driven on one side. This configuration reduces the width of the second non-display area BB2 in the first direction X, achieving a narrow bezel. The second shift register 22 provides the first control signal to the pixel circuit Q. The positions of the first shift register 21 and the second shift register 22 are not specifically limited, as long as they are located on opposite sides of the non-display area BB. For example, the first shift register 21 can be located on the left bezel and the second shift register 22 on the right bezel, or vice versa.

[0047] Figures 2 to 4 The diagram also shows a third shift register 23, which is located in both the first non-display area BB1 and the second non-display area BB2. That is, the third shift register 23 is driven by both sides and can provide a second control signal for the pixel circuit Q.

[0048] Each pixel P in the display area AA of the display panel 1000 includes a pixel circuit Q, which can be referred to as... Figure 5The pixel circuit Q can be a 7T1C, including: a first transistor M1, whose control terminal is electrically connected to the first control signal input terminal S1, whose first terminal is electrically connected to the reference voltage signal input terminal Vref, and whose second terminal is electrically connected to the first node N1; a second transistor M2, whose control terminal is electrically connected to the first control signal input terminal S1, whose first terminal is electrically connected to the first node N1, and whose second terminal is electrically connected to the second terminal of the driving transistor M and the first terminal of the fifth transistor M5; a third transistor M3, whose control terminal is electrically connected to the light emission signal input terminal, whose first terminal is electrically connected to the first power supply signal terminal PVDD, and whose second terminal is electrically connected to the first terminal of the driving transistor M; a fourth transistor M4, whose control terminal is electrically connected to the second control signal input terminal S2, whose first terminal is electrically connected to the data signal input terminal Vdata, and whose second terminal is electrically connected to the first terminal of the driving transistor M; and a driving transistor M... The control terminal of the driving transistor M is electrically connected to the first node N1, and the first terminal of the driving transistor M is electrically connected to the second terminal of the third transistor M3 and the second terminal of the fourth transistor M4; the control terminal of the fifth transistor M5 is electrically connected to the light-emitting signal input terminal Emit, the first terminal of the fifth transistor M5 is electrically connected to the second terminal of the driving transistor M and the second terminal of the second transistor M2, and the second terminal of the fifth transistor M5 is electrically connected to the anode of the light-emitting element O; the control terminal of the sixth transistor M6 is electrically connected to the second control signal input terminal S2, the first terminal of the sixth transistor M6 is electrically connected to the reference voltage signal input terminal Vref, and the second terminal of the sixth transistor M6 is electrically connected to the first terminal of the light-emitting element O; the first terminal of the light-emitting element O is electrically connected to the second terminal of the fifth transistor M5 and the second terminal of the sixth transistor M6, and the second terminal of the light-emitting element O is electrically connected to the second power supply signal terminal PVEE; the first terminal of the storage capacitor Cst is electrically connected to the first power supply signal terminal PVDD, and the second terminal of the storage capacitor Cst is electrically connected to the first node N1. Figure 5 The light-emitting signal input terminal Emit in the middle and Figures 2 to 4 The light emission control signal line 50 is electrically connected, the first control signal input terminal S1 is electrically connected to the first scan line signal line 30, and the second control signal input terminal S2 is electrically connected to the second scan signal line 40.

[0049] Figure 2 The display panel 1000 also includes a first connection line 60. One end of the first connection line 60 is electrically connected to the first shift register 21, and the other end of the first connection line 60 is electrically connected to the light emission control signal line 50. For example, the connection point between the first connection line 60 and the light emission control signal line 50 is located in the middle area 11.

[0050] Figure 3 The display panel 1000 also includes a second connection line 70. One end of the second connection line 70 is electrically connected to the second shift register 22, and the other end of the first connection line 60 is electrically connected to the first scan line signal line 30. For example, the connection point between the second connection line 70 and the first scan line signal line 30 is located in the middle area 11.

[0051] Figure 4 The display panel 1000 also includes a first connecting line 60, one end of which is electrically connected to the first shift register 21, and the other end of which is electrically connected to the light emission control signal line 50. The connection point between the first connecting line 60 and the light emission control signal line 50 is located in the middle area 11. The display panel 1000 also includes a second connecting line 70, one end of which is electrically connected to the second shift register 22, and the other end of which is electrically connected to the first scan line signal line 30. The connection point between the second connecting line 70 and the first scan line signal line 30 is located in the middle area 11.

[0052] Compared with the prior art, the display panel 1000 of the present invention has at least the following beneficial effects:

[0053] The display panel 1000 of the present invention includes a first non-display area BB1 and a second non-display area BB2 disposed opposite to each other along a first direction X. The first shift register 21, which provides a light emission control signal for the pixel circuit Q, and the second shift register 22, which provides a first control signal for the pixel circuit Q, are both single-sided areas. The first shift register 21 is located in the first non-display area BB1, and the second shift register 22 is located in the second non-display area BB2. In related technologies, since both the first shift register 21 and the second shift register 22 are driven on one side, the light emission control signal line 50 connected to the first shift register 21 is loaded with a whole row of pixel row 1, and similarly, the first scan line signal line 30 connected to the second shift register 22 is loaded with the same row of pixel row 1. Since the pixel circuit Q itself generates a certain resistive load, the light emission control signal received by the pixel circuit Q that is farther away from the first shift register 21 will gradually decrease and be lower than the light emission control signal received by the pixel circuit Q that is closer to the first shift register 21. Similarly, the first control signal received by the pixel circuit Q that is farther away from the second shift register 22 will gradually decrease and be lower than the first control signal received by the pixel circuit Q that is closer to the second shift register 22, resulting in uneven pixel display in different pixel columns. In this invention, along the first direction X, the display area AA includes a middle area 11, and a first area 12 and a second area 13 located on both sides of the middle area 11. A first connecting line 60 can be provided on the display panel 1000. One end of the first connecting line 60 is electrically connected to the first shift register 21, and the other end of the first connecting line 60 is connected to the light emission control signal line 50. The light emission control signal line 50 is not directly electrically connected to the first shift register 21, but is electrically connected to the first shift register 21 through the first connecting line 60. The connection point between the first connecting line 60 and the light emission control signal line 50 is located in the middle area 11. That is, the access point of the light emission control signal provided by the first shift register 21 is not located in the first non-display area BB1, but in the middle area 11 of the display area AA. In this way, after the light emission control signal is accessed from the connection point between the first connecting line 60 and the light emission control signal line 50, it is transmitted to the left and right sides of the connection point through the light emission control signal line 50, which to a certain extent improves the problem of uneven display caused by the weakening of the light emission control signal due to the Q load of the pixel circuit.Similarly, a second connection line 70 can also be provided on the display panel 1000. One end of the second connection line 70 is electrically connected to the second shift register 22, and the other end of the second connection line 70 is connected to the first scan line signal line 30. The first scan line signal line 30 is not directly electrically connected to the second shift register 22, but is electrically connected to the second shift register 22 through the second connection line 70. The connection point between the second connection line 70 and the first scan line signal line 30 is located in the middle area 11. That is, the access point of the first control signal provided by the second shift register 22 is not located in the second non-display area BB2, but in the middle area 11 of the display area AA. In this way, after the first control signal is accessed from the connection point between the second connection line 70 and the first scan line signal line 30, it is transmitted to the left and right sides of the connection point through the first scan line signal line 30, which to a certain extent improves the problem of uneven display caused by the weakening of the first control signal due to the Q load of the pixel circuit.

[0054] In some alternative embodiments, reference continues to be made to... Figures 2 to 4 The first connection line 60 includes a first sub-connection line 601 and a second sub-connection line 602. One end of the first sub-connection line 601 is electrically connected to the first shift register 21, and the other end is electrically connected to the second sub-connection line 602. The second sub-connection line 602 is located in the middle area 11, and the other end of the second sub-connection line 602 is electrically connected to the light emission control signal line 50.

[0055] And / or, the second connection line 70 includes a third sub-connection line 701 and a fourth sub-connection line 702. One end of the third sub-connection line 701 is electrically connected to the second shift register 22, and the other end is electrically connected to the fourth connection line. The fourth sub-connection line 702 is located in the intermediate area 11, and the other end of the fourth sub-connection line 702 is electrically connected to the first scan line signal line 30.

[0056] Figure 2In the first connection line 60, there are a first sub-connection line 601 and a second sub-connection line 602. The first sub-connection line 601 extends along a first direction X, and the second sub-connection line 602 extends along a second direction Y. The first sub-connection line 601 and the second sub-connection line 602 can be an integral structure. One end of the first sub-connection line 601 is electrically connected to the first shift register 21, and the other end is electrically connected to the second sub-connection line 602. The second sub-connection line 602 is located in the intermediate area 11. The other end of the second sub-connection line 602 is electrically connected to the light emission control signal line 50. The light emission control signal line 50 is not directly electrically connected to the first shift register 21, but is connected through the first sub-connection line 601. The connecting line 601 and the second sub-connecting line 602 are electrically connected to the first shift register 21. The second sub-connecting line 602 is located in the middle area 11 and is electrically connected to the light emission control signal line 50. That is, the access point of the light emission control signal provided by the first shift register 21 is not located in the first non-display area BB1 but in the middle area 11 of the display area AA. In this way, after the light emission control signal is accessed from the connection point where the second sub-connecting line 602 is electrically connected to the light emission control signal line 50, it is transmitted to the left and right sides of the connection point via the light emission control signal line 50, which improves the problem of uneven display caused by the weakening of the light emission control signal due to the Q load of the pixel circuit to a certain extent.

[0057] Figure 4 In the second connection line 70, there are a third sub-connection line 701 and a fourth sub-connection line 702. The third sub-connection line 701 extends along the first direction X, and the fourth sub-connection line 702 extends along the second direction Y. The third sub-connection line 701 and the fourth sub-connection line 702 can be an integral structure. One end of the third sub-connection line 701 is electrically connected to the second shift register 22, and the other end is electrically connected to the fourth sub-connection line 702. The fourth sub-connection line 702 is located in the intermediate area 11, and the other end of the fourth sub-connection line 702 is electrically connected to the first scan line signal line 30. The first scan line signal line 30 is not directly electrically connected to the second shift register 22, but is connected through the third sub-connection line 701 and the fourth sub-connection line 702. Sub-connection line 702 is electrically connected to the second shift register 22. The fourth sub-connection line 702 is located in the middle area 11. The connection point of the fourth sub-connection line 702 electrically connected to the first scan line signal line 30 is located in the middle area 11. That is, the access point of the first control signal provided by the second shift register 22 is not located in the second non-display area BB2, but in the middle area 11 of the display area AA. In this way, after the first control signal is accessed from the connection point of the fourth sub-connection line 702 electrically connected to the first scan line signal line 30, it is transmitted to the left and right sides of the connection point via the first scan line signal line 30, which improves the display unevenness problem caused by the weakening of the first control signal due to the Q load of the pixel circuit to a certain extent.

[0058] for Figure 5 An embodiment in which both a first connecting line 60 and a second connecting line 70 are provided will not be described in detail here. Figure 5Because both the first connecting line 60 and the second connecting line 70 are set simultaneously, the effect of improving uneven display is better.

[0059] In some alternative embodiments, refer to Figures 6 to 8 , Figure 6 This is a schematic diagram of a planar structure of another display panel provided by the present invention. Figure 7 This is a schematic diagram of a planar structure of another display panel provided by the present invention. Figure 8 This is a schematic diagram of a planar structure of another display panel provided by the present invention.

[0060] Figure 6 In the first sub-connection line 601, the first sub-connection line 602 is located between adjacent pixel rows 1, and the second sub-connection line 602 is electrically connected to two adjacent light emission control signal lines 50 along the second direction Y. In this way, the first connection line 60 can be electrically connected to the light emission control signal lines 50 of the two adjacent pixel rows 1 at the same time, thereby reducing the number of first connection lines 60. On the one hand, this can reduce the number of traces in the display panel 1000, and on the other hand, it can also reduce costs.

[0061] Figure 7 In the middle, the third sub-connection line 701 is located between adjacent pixel rows 1, and the fourth sub-connection line 702 is electrically connected to the two adjacent first scan line signal lines 30 along the second direction Y. In this way, the second connection line 70 can be electrically connected to the first scan line signal lines 30 of the two adjacent pixel rows 1 at the same time, thereby reducing the number of second connection lines 70. On the one hand, it can reduce the number of traces in the display panel 1000, and on the other hand, it can reduce the cost.

[0062] Figure 8 In this configuration, the first sub-connection line 601 is located between adjacent pixel rows 1, the second sub-connection line 602 is electrically connected to two adjacent light emission control signal lines 50 along the second direction Y, the third sub-connection line 701 is located between adjacent pixel rows 1, and the fourth sub-connection line 702 is electrically connected to two adjacent first scan line signal lines 30 along the second direction Y. This reduces the number of first connection lines 60 and second connection lines 70, decreases the number of traces within the display panel 1000, and also reduces costs.

[0063] In some alternative embodiments, reference continues to be made to... Figure 4 The length of the first sub-connector 601 is a, the length of the third sub-connector 701 is b, the distance between the first shift register 21 and the second shift register 22 is c, and the sum of a and b is not greater than c.

[0064] Specifically, in this embodiment, the display panel 1000 is simultaneously provided with a first connecting line 60 and a second connecting line 70. The first sub-connecting line 601 is electrically connected to the first shift register 21 with a length of 'a', and the third sub-connecting line is electrically connected to the second shift register 22 with a length of 'b'. The distance between the first shift register 21 and the second shift register 22 is 'c'. If a + b > c, then the first sub-connecting line 601 and the third sub-connecting line 701 will overlap for a certain distance. On the one hand, the lengths of the first sub-connecting line 601 and the third sub-connecting line 701 are relatively long, so the resistance of the first sub-connecting line 601 itself increases with the increase in length, and the resistance of the third sub-connecting line 701 itself also increases with the increase in length. Thus, the resistances of the first connecting line 60 and the second connecting line 70 are relatively large, and the load is also increased. On the other hand, in the second direction Y, the overlap of the first sub-connecting line 601 and the third sub-connecting line 701 will cause signal coupling, affecting the display. In this embodiment, the sum of a and b is not greater than c, which can minimize the length of the first sub-connection line 601 and the third sub-connection line 701, reduce the resistance of the first sub-connection line 601 and the third sub-connection line 701, and at the same time prevent signal coupling between the first sub-connection line 601 and the third sub-connection line 701 from affecting the display.

[0065] In some alternative embodiments, reference continues to be made to... Figure 4 a = 1 / 2c, or b = 1 / 2c.

[0066] In this embodiment, a = 1 / 2c, b = 1 / 2c, and a + b = c. This minimizes the length of the first sub-connecting line 601 and the third sub-connecting line 701, reducing their resistances and preventing signal coupling between them from affecting the display. Furthermore, the second sub-connecting line 602 has the same number of pixels on both sides of its connection point with the light-emitting control signal line 50, meaning they have the same load. This ensures symmetrical pixel display on both sides of the connection point.

[0067] In some alternative embodiments, refer to Figure 9 , Figure 9 This is a schematic diagram of the planar structure of another display panel provided by the present invention, where a = 1 / 4c and b = 1 / 4c.

[0068] In this embodiment, a = 1 / 4c, b = 1 / 4c, a + b = 1 / 2c < c. This can minimize the length of the first sub-connection line 601 and the third sub-connection line 701, reduce the resistance of the first sub-connection line 601 and the third sub-connection line 701, and at the same time prevent signal coupling between the first sub-connection line 601 and the third sub-connection line 701 from affecting the display.

[0069] In some alternative embodiments, reference continues to be made to... Figure 9 a = 1 / 3c, b = 1 / 3c.

[0070] In this embodiment, a = 1 / 3c, b = 1 / 3c, a + b = 2 / 3c < c. This can shorten the length of the first sub-connection line 601 and the third sub-connection line 701 as much as possible, reduce the resistance of the first sub-connection line 601 and the third sub-connection line 701, and at the same time avoid signal coupling between the first sub-connection line 601 and the third sub-connection line 701 from affecting the display.

[0071] In some alternative embodiments, refer to Figure 10 , Figure 10 This is a schematic diagram of a planar structure of another display panel provided by the present invention. The number of second sub-connecting lines 602 is at least 2-5, and the second sub-connecting lines 602 are evenly distributed in the middle area 11 along the first direction X.

[0072] Figure 10 This example uses three second sub-connecting lines 602 as an example. Of course, the number of second sub-connecting lines 602 can also be two, four, or five. The multiple sub-connecting lines can be evenly distributed, that is, the spacing between adjacent second sub-connecting lines 602 is equal. It can be understood that the second sub-connecting lines are electrically connected to the first sub-connecting line 601 and the light-emitting control signal line 50, respectively. When there are 2-5 second sub-connecting lines, it is equivalent to multiple second sub-connecting lines 602 being connected in parallel. The resistance of multiple second sub-connecting lines 602 connected in parallel is less than the resistance of a single second sub-connecting line 602. Of course, too many second sub-connecting lines 602 will also increase material costs, and too many second sub-connecting lines 602 within the display panel 1000 will also increase the complexity of the manufacturing process.

[0073] In some alternative embodiments, refer to Figure 11 , Figure 11 This is a schematic diagram of a planar structure of another display panel provided by the present invention. The number of fourth sub-connecting lines 702 is 2-5, and the fourth sub-connecting lines 702 are evenly distributed in the middle area 11 along the first direction X.

[0074] Figure 11This example uses four fourth sub-connecting lines 702 as an example. Of course, the number of fourth sub-connecting lines 702 can also be two, three, or five. The selected multiple fourth sub-connecting lines 702 are evenly distributed, that is, the spacing between adjacent fourth sub-connecting lines 702 is equal. It can be understood that the fourth sub-connecting lines 702 are electrically connected to the third sub-connecting line 701 and the first scan line signal line 30, respectively. When there are 2-5 fourth sub-connecting lines 702, it is equivalent to multiple fourth sub-connecting lines 702 being connected in parallel. The resistance of multiple fourth sub-connecting lines 702 connected in parallel is less than the resistance of a single fourth sub-connecting line 702. Of course, too many fourth sub-connecting lines 702 will also increase material costs, and too many fourth sub-connecting lines 702 within the display panel 1000 will also increase the complexity of the manufacturing process.

[0075] In some alternative embodiments, reference continues to be made to... Figure 5 The pixel circuit Q includes a driving transistor M, a first transistor M1 and a second transistor M2 connected to the gate of the driving transistor M. When the first transistor M1 is turned on, the gate of the driving transistor M is reset. When the second transistor M2 is turned on, the gate of the driving transistor M is threshold compensated. The first transistor M1 and the second transistor M2 are oxide thin film transistors. The first scan line signal line 30 is electrically connected to the first transistor M1 and the second transistor M2.

[0076] Specifically, the first transistor M1 has its control terminal electrically connected to the first control signal input terminal S1, its first terminal electrically connected to the reference voltage signal input terminal Vref, and its second terminal electrically connected to the first node N1. The first transistor M1 is turned on under the control of the first control signal input terminal S1, and the reference voltage signal input at the reference voltage signal input terminal Vref is written into the first node N1, resetting the gate of the driving transistor M. The second transistor M2 has its control terminal electrically connected to the first control signal input terminal S1, its first terminal electrically connected to the first node N1, and its second terminal electrically connected to the second terminal of the driving transistor M. The second transistor M2 is turned on under the control of the first control signal input terminal S1, and the data signal input at the data signal input terminal Vdata is written into the first node N1 through the driving transistor M and the second transistor M2, performing threshold compensation on the first node N1, which is equivalent to threshold compensation on the gate of the driving transistor M.

[0077] It is understandable that when the light-emitting element O emits light, the gate potential of the driving transistor M, i.e., the potential of the first node N1, needs to remain stable to ensure the light-emitting duration of the light-emitting element O. If leakage current occurs in the transistor electrically connected to the first node N1, the potential of the first node N1 will decrease, affecting the light-emitting duration of the light-emitting element O. The material of the oxide semiconductor layer 1203 in the oxide thin film transistor can be IGZO (indium gallium zinc oxide), etc. Thin film transistors (TFTs) based on oxide semiconductors (especially indium gallium zinc oxide InGaZnO) have the advantages of smaller off-state current and higher electron mobility. Therefore, setting the first transistor and the second transistor as oxide transistors can reduce the leakage current of the first node, maintain the potential of the first node, prolong the light-emitting duration of the light-emitting element O, and improve the light-emitting performance.

[0078] In some alternative embodiments, refer to Figure 12 , Figure 12 yes Figure 2 A cross-sectional view along line A-A' shows that the display panel 1000 includes a substrate 1201, a first metal layer 1202 located on one side of the substrate 1201, an oxide semiconductor layer 1203 located on the side of the first metal layer 1202 away from the substrate 1201, a second metal layer 1204 located on the side of the oxide semiconductor layer 1203 away from the substrate 1201, and a third metal layer 1205 located on the side of the second metal layer 1204 away from the substrate 1201. The gates of the first transistor M1 and the second transistor M2 are on the same layer as the first metal layer 1202 and the second metal layer 1204, and the gate of the driving transistor M is on the same layer as the third metal layer 1205.

[0079] Specifically, the first transistor M1 and the second transistor M2 in this invention are oxide thin-film transistors. When fabricating the display panel 1000, compared to the display panel 1000 in related technologies, a first metal layer 1202 and a second metal layer 1204 are added to the film layer configuration. The first metal layer 1202 is located on the side of the oxide semiconductor layer 1203 closest to the substrate 1201, and the second metal layer 1204 is located on the side of the oxide semiconductor layer 1203 away from the substrate 1201. The first metal layer 1202 and the second metal layer 1204 simultaneously form a double gate with the oxide semiconductor layer 1203. Figure 12The diagram shows a display panel comprising a first metal layer 1202, a second metal layer 1204, and a third metal layer 1205. Insulating layers 1208 are provided between the first metal layer 1202 and the oxide semiconductor layer 1203, and between the oxide semiconductor layer 1203 and the second metal layer 1204. The first transistor M1 and the second transistor M2 have the advantages of lower off-state current and higher electron mobility. The gates of the first transistor M1 and the second transistor M2 are on the same layer as the first metal layer 1202 and the second metal layer 1204. The first transistor M1 and the second transistor M2 also have source and drain electrodes. The source and drain electrodes of the first transistor M1 and the second transistor M2 are on the same layer as the fourth metal layer 1206. Optionally, the fourth metal layer 1206 is located on the side of the third metal layer 1205 away from the substrate 1201. Figure 12 The gate of the driving transistor M is on the same layer as the third metal layer 1205. The third metal layer 1205 is located on the side of the second metal layer 1204 away from the substrate 1201. The source and drain of the driving transistor M can also be located on the fourth metal layer 1206. The figure also shows that the semiconductor layer 1207 (which can be a low-temperature polysilicon active layer) of the driving transistor M is on the same layer as the oxide semiconductor layer 1203. Of course, the semiconductor layer 1207 and the oxide semiconductor layer 1203 of the driving transistor M are not on the same layer, which is not specifically limited here.

[0080] The display panel 1000 of the present invention is LTPO (Low Temperature Polycrystalline Oxide), which combines the advantages of LTPS (Low Temperature Polycrystalline Silicon Semiconductor) and oxide semiconductor technologies, and has the advantages of low production cost, higher charge mobility, high stability and scalability.

[0081] In some alternative embodiments, reference continues to be made to... Figure 12 The first sub-connecting line 601 and the second sub-connecting line 602 are on the same layer as the third metal layer 1205, and the light-emitting control signal line 50 is on the same layer as the third metal layer 1205.

[0082] The third sub-connecting line 701 and the fourth sub-connecting line 702 are on the same layer as the first metal layer 1202, and the first scan line signal line 30 is on the same layer as the first metal layer 1202.

[0083] Figure 12 The diagram schematically shows that the light emission control signal line 50 is on the same layer as the third metal layer 1205, the first sub-connection line 601 and the second sub-connection line 602 are on the same layer as the third metal layer 1205, the third sub-connection line 701 and the fourth sub-connection line 702 are electrically connected to the first metal layer 1202, and the first scan line signal line 30 is on the same layer as the first metal layer 1202.

[0084] Understandably, since the light-emitting control signal line 50 is on the same layer as the third metal layer 1205, if the first sub-connecting line 601 and the second sub-connecting line 602 are also placed on the third metal layer 1205, then the first sub-connecting line 601 and the second sub-connecting line 602 can be manufactured in the same process as the light-emitting control signal line 50. Moreover, since the second sub-connecting line 602 is on the same layer as the third metal layer 1205, there is no need to replace the wires or drill holes at the connection between the second sub-connecting line 602 and the light-emitting control signal line 50, which simplifies the manufacturing process.

[0085] Similarly, since the first scan line signal line 30 is on the same layer as the first metal layer 1202, if the third sub-connection line 701 and the fourth sub-connection line 702 are also located on the first metal layer 1202, then the third sub-connection line 701 and the fourth sub-connection line 702 can be manufactured in the same process as the first scan line signal line 30. Moreover, since the fourth sub-connection line 702 is on the same layer as the first metal layer 1202, there is no need to replace the line and drill holes at the connection between the fourth sub-connection line 702 and the first scan line signal line 30, which simplifies the manufacturing process.

[0086] In some alternative embodiments, reference continues to be made to... Figure 12 The materials of the first metal layer 1202, the second metal layer 1204, and the third metal layer 1205 all include molybdenum.

[0087] It is understood that the materials of the first metal layer 1202, the second metal layer 1204, and the third metal layer 1205 are usually molybdenum. In this embodiment, the materials of the first connecting line 60 and the second connecting line 70 can also be molybdenum. No other materials are needed. The materials are readily available and more widely used. The fact that the first connecting line 60 and the second connecting line 70 are made of the same material as the first metal layer 1202, the second metal layer 1204, and the third metal layer 1205 can simplify the manufacturing process.

[0088] In some alternative embodiments, refer to Figure 13 , Figure 14 , Figure 15 and Figure 16 , Figure 13 This is a schematic diagram of a planar structure of another display panel provided by the present invention. Figure 14 yes Figure 13 A cross-sectional view of B-B'. Figure 15 This is a schematic diagram of a planar structure of another display panel provided by the present invention. Figure 16 yes Figure 15 A cross-sectional view of C-C'. Figure 13 and Figure 15Some data lines 80 are omitted; only a portion of the data lines 80 connected to the data connection line 900 is shown. This is to clearly illustrate the film layer relationship between the first metal layer 1202, the second metal layer 1204, the third metal layer 1205, and the fourth metal layer 1206. Figure 14 and Figure 16 The diagram also shows the structure of the first transistor (second transistor) and the driving transistor.

[0089] The display panel 1000 of this embodiment also includes data lines 80 extending along the second direction Y and arranged in the first direction X, as well as fan-out traces 800 located on one side of the display area AA and data connection lines 900 located in the display area AA. The data connection lines 900 connect the fan-out traces 800 and the data lines 80. The display panel 1000 also includes a fourth metal layer 1206 located on the side of the third metal layer 1205 away from the substrate 1201 and a fifth metal layer 1209 located on the side of the fourth metal layer 1206 away from the substrate 1201. The source and drain of the driving transistors are on the same layer as the fourth metal layer 1206, and at least a portion of the data connection lines 900 are on the same layer as the fifth metal layer 1209. The data connection lines 900 are at least partially disposed on the same layer as the first sub-connection line 601 and / or the second sub-connection line 602. And / or the data connection lines 900 are at least partially disposed on the same layer as the third sub-connection line 701 and / or the fourth sub-connection line 702.

[0090] It should be noted that as users' demands for the performance of the display panel 1000 have increased, narrow bezel technology has gradually emerged in the display panel 1000. The bottom bezel of the display panel 1000 has also been further compressed. As for the fan-out traces 800, since the fan-out traces 800 connect the driver chip and the data line 80, there are a relatively large number of fan-out traces 800. The fan-out traces 800 need to have a certain angle to arrange enough fan-out traces 800 between the driver chip and the display area AA. Thus, the fan-out traces 800 occupy a relatively large space in the second direction Y. In order to compress the bottom bezel, FIAA (Fanout in AA) was introduced. This method places a portion of the data connection lines 900 connecting the fan-out traces 800 and the data line 80 in the display area AA, reducing the number of fan-out traces 800 in the bottom bezel, thereby further compressing the bottom bezel.

[0091] like Figure 14As shown, the source and drain of the driving transistor are on the same layer as the fourth metal layer 1206, and at least part of the data connection line 900 is on the same layer as the fifth metal layer 1209. That is, part of the data connection line 900 runs on the fifth metal layer 1209. The fifth metal layer 1209 is an additional metal layer added to the display panel 1000. By setting at least part of the data connection line 900 on the same layer as the first sub-connection line 601 and / or the second sub-connection line 602, that is, the first sub-connection line 601 and / or the second sub-connection line 602 are set on the fifth metal layer 1209, on the one hand, there are fewer traces on the fifth metal layer 1209. The ample space allows for easy fabrication of the first sub-connector 601 and / or the second sub-connector 602. Furthermore, the material of the fifth metal layer 1209 includes titanium aluminum titanium, which has a resistance that is one-tenth that of molybdenum. Placing the first sub-connector 601 and / or the second sub-connector 602 in the fifth metal layer 1209 can also reduce the resistive load of the first connecting line 60 itself. Placing the first sub-connector 601 and / or the second sub-connector 602 in the fifth metal layer 1209 is particularly suitable for large-size display panels 1000, as it can significantly reduce the resistance of the first connecting line 60.

[0092] Since the first sub-connector 601 extends along the first direction X and the second sub-connector 602 extends along the second direction Y, the data connection 900 includes both the portion extending along the first direction X and the portion extending along the second direction Y. Therefore, it is necessary to avoid short circuits between the data connection 900 and the first sub-connector 601 or the second sub-connector 602. Figure 15 The following example illustrates the situation using the case where data connection lines 900 are all located in the fifth metal layer 1209, while the first sub-connection line 601 is located in the fourth metal layer 1206 and the second sub-connection line 602 is located in the fifth metal layer 1209.

[0093] like Figure 16As shown, the source and drain of the driving transistor are on the same layer as the fourth metal layer 1206, and at least a portion of the data connection lines 900 are on the same layer as the fifth metal layer 1209. That is, some of the data connection lines 900 run on the fifth metal layer 1209. The fifth metal layer 1209 is an additional metal layer added to the display panel 1000. By setting at least a portion of the data connection lines 900 on the same layer as the third sub-connection line 701 and / or the fourth sub-connection line 702, that is, the third sub-connection line 701 and / or the fourth sub-connection line 702 are set on the fifth metal layer 1209, on the one hand, there are fewer traces on the fifth metal layer 1209. The ample space allows for easy fabrication of the third sub-connector 701 and / or the fourth sub-connector 702. Furthermore, the material of the fifth metal layer 1209 includes titanium aluminum titanium, which has a resistance that is one-tenth that of molybdenum. Placing the third sub-connector 701 and / or the fourth sub-connector 702 in the fifth metal layer 1209 can also reduce the resistive load of the second connection line 70 itself. Placing the third sub-connector 701 and / or the fourth sub-connector 702 in the fifth metal layer 1209 is particularly suitable for large-size display panels 1000, as it can significantly reduce the resistance of the second connection line 70.

[0094] Since the third sub-connector 701 extends along the first direction X and the fourth sub-connector 702 extends along the second direction Y, the data connection 900 includes both the portion extending along the first direction X and the portion extending along the second direction Y. Therefore, it is necessary to avoid short circuits between the data connection 900 and the third sub-connector 701 or the fourth sub-connector 702. Figure 15 The following example illustrates the situation where data connection lines 900 are all located in the fifth metal layer 1209, while the third sub-connection line 701 is located in the fourth metal layer 1206 and the fourth sub-connection line 702 is located in the fifth metal layer 1209.

[0095] In some alternative embodiments, reference continues to be made to... Figures 13 to 16 , Figure 13 and Figure 15 The diagram shows a data connection line 900 including a first data connection line 901 and a second data connection line 902 connected to each other. The first data connection line 901 extends along a first direction X, and the second data connection line 902 extends along a second direction Y.

[0096] Figure 14 In the middle, the first data connection line 901 is on the same layer as the first sub-connection line 601, and the second data connection line 902 is on the same layer as the second sub-connection line 602; Figure 16 In the middle, the first data connection line 901 is on the same layer as the third sub-connection line 701, and the second data connection line 902 is on the same layer as the fourth sub-connection line 702.

[0097] Of course, the first data connection line 901 can be on the same layer as the first sub-connection line 601, the second data connection line 902 can be on the same layer as the second sub-connection line 602, and the first data connection line 901 can be on the same layer as the third sub-connection line 701, and the second data connection line 902 can be on the same layer as the fourth sub-connection line 702. No specific restrictions are made here.

[0098] It is understandable that the first sub-connection line 601 and the first data connection line 901 both extend along the first direction X, and the second sub-connection line 602 and the second data connection line 902 both extend along the second direction Y. It is more convenient to manufacture the first data connection line 901 and the first sub-connection line 601 to be on the same layer, and the second data connection line 902 and the second sub-connection line 602 to be on the same layer.

[0099] Similarly, the third sub-connecting line 701 and the first data connecting line 901 both extend along the first direction X, and the fourth sub-connecting line 702 and the second data connecting line 902 both extend along the second direction Y. It is more convenient to manufacture the first data connecting line 901 and the third sub-connecting line 701 to be on the same layer, and the second data connecting line 902 and the fourth sub-connecting line 702 to be on the same layer.

[0100] In some alternative embodiments, reference continues to be made to... Figure 13 and Figure 15 The second sub-connecting line 602 is electrically connected to the light emission control signal line 50 through a via; the fourth sub-connecting line 702 is electrically connected to the first scan line signal line 30 through a via.

[0101] like Figure 13 As shown, the second data connection line 902 is on the same layer as the first sub-connection line 601, and the second sub-connection line 602 is on the same layer as the first data connection line 901. The first data line 80 can be disposed on the fourth metal layer 1206 or the fifth metal layer 1209, so the second sub-connection line 602 can also be disposed on the fourth metal layer 1206 or the fifth metal layer 1209. The second sub-connection line 602 can be electrically connected to the light-emitting control signal line 50 through vias; similarly, as Figure 15 As shown, the fourth sub-connection line 702 is on the same layer as the first data connection line 901, and the third sub-connection line 701 is on the same layer as the second data connection line 902. The first data line 80 can be disposed on the fourth metal layer 1206 or the fifth metal layer 1209, so the fourth sub-connection line 702 can also be disposed on the fourth metal layer 1206 or the fifth metal layer 1209. The fourth sub-connection line 702 can be electrically connected to the first scan line signal line 30 through a via.

[0102] In some alternative embodiments, please refer to Figure 17 , Figure 17This is a schematic diagram of a planar structure of a display device provided in an embodiment of the present invention. The display device 2000 provided in this embodiment includes the display panel 1000 provided in the above embodiment. Figure 17 This embodiment uses a mobile phone as an example to illustrate the display device 2000. It is understood that the display device 2000 provided in this embodiment can be any other display device 2000 with display functions, such as a computer, television, or vehicle-mounted display device; this invention does not impose specific limitations on this. The display device 2000 provided in this embodiment has the beneficial effects of the display panel 1000 provided in this embodiment. For details, please refer to the specific descriptions of the display panel 1000 in the above embodiments; these will not be repeated here.

[0103] As can be seen from the above embodiments, the display panel and display device provided by the present invention achieve at least the following beneficial effects:

[0104] The display panel of this invention includes a first non-display area and a second non-display area disposed opposite to each other along a first direction. Both the first shift register providing light emission control signals to the pixel circuits and the second shift register providing first control signals to the pixel circuits are single-sided areas. The first shift register is located in the first non-display area, and the second shift register is located in the second non-display area. In related technologies, since both the first and second shift registers are single-sided driven, the light emission control signal line connected to the first shift register is loaded with an entire row of pixels. Similarly, the first scan signal line connected to the second shift register is loaded with the same row of pixels. Due to the resistive load generated by the pixel circuits themselves, the light emission control signal received by pixel circuits farther from the first shift register gradually decreases, becoming lower than the light emission control signal received by pixel circuits closer to the first shift register. Similarly, the first control signal received by pixel circuits farther from the second shift register gradually decreases, becoming lower than the first control signal received by pixel circuits closer to the second shift register, resulting in uneven pixel display across different pixel columns. In this invention, along the first direction, the display area includes a central area and a first area and a second area located on both sides of the central area. A first connecting line can be provided on the display panel. One end of the first connecting line is electrically connected to a first shift register, and the other end of the first connecting line is connected to a light emission control signal line. The light emission control signal line is not directly electrically connected to the first shift register, but is electrically connected to the first shift register through the first connecting line. The connection point between the first connecting line and the light emission control signal line is located in the central area. That is, the access point of the light emission control signal provided by the first shift register is not located in the first non-display area but in the central area of ​​the display area. In this way, after the light emission control signal is accessed from the connection point between the first connecting line and the light emission control signal line, it is transmitted to the left and right sides of the connection point through the light emission control signal line, which to a certain extent improves the problem of uneven display caused by the weakening of the light emission control signal due to the pixel circuit load. Similarly, a second connection line can also be set on the display panel. One end of the second connection line is electrically connected to the second shift register, and the other end of the second connection line is connected to the first scan signal line. The first scan signal line is not directly electrically connected to the second shift register, but is electrically connected to the second shift register through the second connection line. The connection point between the second connection line and the first scan signal line is located in the middle area. That is, the access point of the first control signal provided by the second shift register is not located in the second non-display area, but in the middle area of ​​the display area. In this way, after the first control signal is accessed from the connection point between the second connection line and the first scan signal line, it is transmitted to the left and right sides of the connection point through the first scan signal line, which improves the display unevenness caused by the weakening of the first control signal due to the pixel circuit load to a certain extent.

[0105] While specific embodiments of the invention have been described in detail by way of examples, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of the invention. Those skilled in the art should understand that modifications can be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.

Claims

1. A display panel, characterized in that, include: A display area and a non-display area at least partially surrounding the display area, the display area comprising a plurality of pixel rows, each pixel row comprising a plurality of pixel circuits, the non-display area comprising a first non-display area and a second non-display area disposed opposite to each other along a first direction, wherein... The first non-display area includes multiple cascaded first shift registers, and the second non-display area includes multiple cascaded second shift registers. The first shift registers provide light emission control signals to the pixel circuit, and the second shift registers provide first control signals to the pixel circuit. The display area includes a central area, a first area and a second area adjacent to the central area, and the central area is located between the first area and the second area along the first direction; The display panel further includes light emission control signal lines and first scan signal lines extending in a first direction and arranged in a second direction, wherein the light emission control signal lines and the first scan signal lines are electrically connected to the pixel circuit. The display panel further includes a first connecting line, one end of which is electrically connected to the first shift register, and the other end of which is electrically connected to the light emission control signal line. The connection point between the first connecting line and the light emission control signal line is located in the middle area. And / or, the display panel further includes a second connecting line, one end of which is electrically connected to the second shift register, and the other end of which is electrically connected to the first scan signal line. The connection point between the second connecting line and the first scan signal line is located in the intermediate area.

2. The display panel according to claim 1, characterized in that, The first connection line includes a first sub-connection line and a second sub-connection line. One end of the first sub-connection line is electrically connected to the first shift register, and the other end is electrically connected to the second sub-connection line. The second sub-connection line is located in the intermediate area, and the other end of the second sub-connection line is electrically connected to the light emission control signal line. And / or, the second connection line includes a third sub-connection line and a fourth sub-connection line, one end of the third sub-connection line is electrically connected to the second shift register, the other end of the third sub-connection line is electrically connected to the fourth sub-connection line, the fourth sub-connection line is located in the intermediate region, and the other end of the fourth sub-connection line is electrically connected to the first scan signal line.

3. The display panel according to claim 2, characterized in that, The first sub-connection line is located between adjacent pixel rows, and the second sub-connection line is electrically connected to two adjacent light emission control signal lines along the second direction; And / or, the third sub-connection line is located between adjacent pixel rows, and the fourth sub-connection line is electrically connected to two adjacent first scan signal lines along the second direction.

4. The display panel according to claim 2, characterized in that, The length of the first sub-connector is a, the length of the third sub-connector is b, the spacing between the first shift register and the second shift register is c, and the sum of a and b is not greater than c.

5. The display panel according to claim 4, characterized in that, a = 1 / 2c, b = 1 / 2c.

6. The display panel according to claim 4, characterized in that, a = 1 / 4c, b = 1 / 4c.

7. The display panel according to claim 4, characterized in that, a = 1 / 3c, b = 1 / 3c.

8. The display panel according to claim 2, characterized in that, The number of the second sub-connecting lines is 2-5, and the second sub-connecting lines are evenly distributed in the middle area along the first direction.

9. The display panel according to claim 2, characterized in that, The number of the fourth sub-connecting lines is 2-5, and the fourth sub-connecting lines are evenly distributed in the middle area along the first direction.

10. The display panel according to claim 2, characterized in that, The pixel circuit includes a driving transistor, a first transistor and a second transistor connected to the gate of the driving transistor. When the first transistor is turned on, it resets the gate of the driving transistor. When the second transistor is turned on, it performs threshold compensation on the gate of the driving transistor. The first transistor and the second transistor are oxide thin film transistors. The first scan signal line is electrically connected to the first transistor and the second transistor.

11. The display panel according to claim 10, characterized in that, The device includes a substrate, a first metal layer located on one side of the substrate, an oxide semiconductor layer located on the side of the first metal layer away from the substrate, a second metal layer located on the side of the oxide semiconductor layer away from the substrate, and a third metal layer located on the side of the second metal layer away from the substrate. The gates of the first transistor and the second transistor are on the same layer as the first metal layer and the second metal layer, and the gate of the driving transistor is on the same layer as the third metal layer.

12. The display panel according to claim 11, characterized in that, The first sub-connecting line and the second sub-connecting line are on the same layer as the third metal layer, and the light emission control signal line is on the same layer as the third metal layer; The third sub-connection line and the fourth sub-connection line are on the same layer as the first metal layer or the second metal layer, and the first scan signal line is on the same layer as the first metal layer.

13. The display panel according to claim 12, characterized in that, The materials of the first metal layer, the second metal layer, and the third metal layer all include molybdenum.

14. The display panel according to claim 11, characterized in that, The display panel also includes data lines extending along the second direction and arranged in the first direction, as well as fan-out routing lines located on one side of the display area and data connection lines located in the display area, wherein the data connection lines connect the fan-out routing lines and the data lines; The display panel further includes a fourth metal layer located on the side of the third metal layer away from the substrate, and a fifth metal layer located on the side of the fourth metal layer away from the substrate. The material of the fifth metal layer includes titanium aluminum titanium. The source and drain of the driving transistor are on the same layer as the fourth metal layer, and at least a portion of the data connection lines are on the same layer as the fifth metal layer. The data connection line is at least partially disposed on the same layer as the first sub-connection line and / or the second sub-connection line; and / or the data connection line is at least partially disposed on the same layer as the third sub-connection line and / or the fourth sub-connection line.

15. The display panel according to claim 14, characterized in that, The data connection line includes a first data connection line and a second data connection line connected to each other, the first data connection line extending along the first direction and the second data connection line extending along the second direction; The first data connection line is on the same layer as the first sub-connection line, and the second data connection line is on the same layer as the second sub-connection line; And / or, the first data connection line is on the same layer as the third sub-connection line, and the second data connection line is on the same layer as the fourth sub-connection line.

16. The display panel according to claim 15, characterized in that, The second sub-connecting line is electrically connected to the light-emitting control signal line through a via; The fourth sub-connection line is electrically connected to the first scan signal line via a via.

17. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 16.

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