Memory system, memory controller

Abstract

An embodiment of the present application provides a memory system, a memory controller, and a semiconductor storage device capable of improving data reliability. A memory system 1 of an embodiment includes a semiconductor storage device 20 and a memory controller 10. The semiconductor storage device 20 includes a memory cell array 27 including a memory cell MC and a temperature counter 31 that changes a speed of updating a count value CV based on a temperature of the memory cell array 27. The memory controller 10 is configured to acquire the count value CV from the semiconductor storage device 20 and reserve a refresh operation for the memory cell MC in a case where an accumulated value of the count value CV from writing data to the memory cell MC to the acquisition of the count value CV exceeds a predetermined value 18.

Description

[0001] Related applications

[0002] This application enjoys priority based on Japanese Patent Application No. 2021-106100 (filed on June 25, 2021). This application incorporates the entire contents of the said basic application by reference. Technical Field

[0003] One embodiment of the present invention relates to a memory system, a memory controller, and a semiconductor memory device. Background Technology

[0004] A memory system is known that includes NAND (Not-AND) flash memory as a semiconductor storage device and a memory controller for controlling the semiconductor storage device. Summary of the Invention

[0005] One embodiment of the present invention provides a memory system, a memory controller, and a semiconductor memory device that can improve data reliability.

[0006] One embodiment of the memory system includes: a semiconductor memory device and a memory controller, the semiconductor memory device comprising: a memory cell array including memory cells; and a temperature counter that changes the rate at which a count value is updated based on the temperature of the memory cell array; the memory controller is configured to obtain a count value from the semiconductor memory device, and to schedule a refresh operation for the memory cell if the accumulated count value from the time data is written to the memory cell until the count value is obtained exceeds a predetermined value. Attached Figure Description

[0007] Figure 1 This is a block diagram of the memory system according to the first embodiment.

[0008] Figure 2 This is a block diagram illustrating an example of the configuration of a memory chip within a semiconductor memory device included in the memory system of the first embodiment.

[0009] Figure 3 This is a circuit diagram of the memory cell array within the memory chip included in the memory system of the first embodiment.

[0010] Figure 4 This is a block diagram illustrating an example of the configuration of a temperature counter within a memory chip included in the memory system of the first embodiment.

[0011] Figure 5 This is a diagram illustrating the count value of the temperature counter included in the memory system of the first embodiment.

[0012] Figure 6 This is a conceptual diagram of the cumulative count table included in the memory system of the first embodiment.

[0013] Figure 7 This is a flowchart illustrating the refresh reservation control operation of the memory controller included in the memory system of the first embodiment.

[0014] Figure 8 This diagram illustrates the refresh reservation control operation of the memory controller included in the memory system of the first embodiment.

[0015] Figure 9 This is a flowchart illustrating the write operation of the memory controller included in the memory system of the first embodiment.

[0016] Figure 10 This is a flowchart illustrating the erase operation of the memory controller included in the memory system of the first embodiment.

[0017] Figure 11 This is a flowchart illustrating the refresh control operation of the memory controller included in the memory system of the first embodiment.

[0018] Figure 12 This is a block diagram illustrating an example of the configuration of a memory chip within a semiconductor memory device included in the memory system of the second embodiment.

[0019] Figure 13 This is a block diagram illustrating an example of the configuration of a temperature counter within a memory chip included in the memory system of the second embodiment.

[0020] Figure 14 This is a conceptual diagram of the addition value table included in the memory system of the second embodiment. Detailed Implementation

[0021] Hereinafter, embodiments will be described with reference to the accompanying drawings. Throughout the description, common reference numerals will be used for common parts.

[0022] [1] First Embodiment

[0023] The memory system of the first embodiment will be described. Hereinafter, an example of a memory system including NAND flash memory will be described as a semiconductor memory device.

[0024] [1-1] Composition

[0025] [1-1-1] Overall Structure of the Memory System

[0026] use Figure 1 The overall configuration of the memory system in this embodiment will be described. Figure 1 This is a block diagram of the memory system in this embodiment.

[0027] The memory system 1 includes a memory controller 10 and a NAND flash memory 20. The memory system 1 is controlled by a host device 2. The memory system 1 processes requests received from the host device 2. The memory system 1 is, for example, a storage device such as an SSD (solid-state drive), a USB (Universal Serial Bus) memory, an MMC (Multi-Media Card), or a memory card. The host device 2 is, for example, a digital camera or a personal computer.

[0028] The memory controller 10 receives request signals from the host device 2 via the host bus. The type of host bus depends on the application used to the memory system 1. If the memory system 1 is an SSD, a serial interface such as SAS (Serial Attached SCSI, Small Computer System Interface), SATA (Serial ATA, Advanced Technology Attachment), or UFS (Universal Flash Storage) can be used as the host bus. If the memory system 1 is a USB memory, USB can be used as the host bus. If the memory system 1 is an MMC, an eMMC (Embedded Multi Media Card) interface can be used as the host bus. If the memory system 1 is a memory card, an interface suitable for the memory card can be used as the host bus.

[0029] The memory controller 10 controls the NAND flash memory 20 via the NAND bus based on the request signal received from the host device 2. The NAND bus transmits and receives signals according to the NAND interface.

[0030] The memory controller 10 includes a host interface circuit 11, a processor (CPU: Central Processing Unit) 12, a buffer memory 13, an ECC (Error Checking and Correcting) circuit 14, a NAND interface circuit 15, and RAM (Random Access Memory) 16.

[0031] The host interface circuit 11 is connected to the host device 2 via the host bus. The host interface circuit 11 is responsible for communication between the memory controller 10 and the host device 2.

[0032] Processor 12 controls the overall operation of memory controller 10 by loading a program stored in ROM (Read-Only Memory) (not shown) within memory controller 10. For example, when processor 12 receives a write request from host device 2, it controls a write operation based on the request. The same applies to read and erase operations. Additionally, processor 12 performs refresh operations, refresh reservation control operations, and refresh control operations. A refresh operation includes, for example, writing data written to a storage area in NAND flash memory 20 to a new storage area after performing error correction processing, and reducing the number of errors (error bits) in the data when reading the data. A refresh reservation control operation is an operation that controls the reservation of refresh operations. A refresh control operation is an operation that controls the execution of refresh operations.

[0033] The buffer memory 13 is, for example, SRAM (Static Random Access Memory). The buffer memory 13 temporarily stores data read by the memory controller 10 from the NAND flash memory 20, or write data received by the memory controller 10 from the host device 2, etc.

[0034] ECC circuit 14 performs error detection and correction processing related to the data stored in NAND flash memory 20. Specifically, during data writing, ECC circuit 14 generates an error correction code and provides it to the written data. During data reading, ECC circuit 14 decodes the error correction code and detects the presence of error bits. When an error bit is detected, ECC circuit 14 identifies the error position of the error bit and corrects the error.

[0035] NAND interface circuit 15 is connected to NAND flash memory 20 via NAND bus. NAND interface circuit 15 is responsible for communication between memory controller 10 and NAND flash memory 20. For example, NAND interface circuit 15 controls the transmission of data, instructions, and addresses between memory controller 10 and NAND flash memory 20.

[0036] RAM 16 is, for example, SRAM. RAM 16 is used as the working area of ​​processor 12. RAM 16 stores firmware or various management information used to manage NAND flash memory 20. RAM 16 stores a cumulative count table 17, a cumulative count threshold 18, and the previous count value 19 as information used, for example, for refresh reservation control actions.

[0037] Cumulative count table 17 is a table storing cumulative count values. The count values ​​correspond to the temperature history of the NAND flash memory 20. The cumulative count value represents the accumulated (incremental) count value from the time data is written to the object storage area within the NAND flash memory 20 until the count value is obtained by the memory controller 10. Details regarding the cumulative count table 17 will be described later. The cumulative count threshold 18 is a threshold used to determine whether to schedule a refresh operation by comparing it with the cumulative count values ​​in the cumulative count table 17. The previous count value 19 is the count value previously obtained by the memory controller 10.

[0038] Furthermore, the cumulative count table 17, the cumulative count threshold 18, and the previous count value 19 are stored in, for example, any block BLK in the NAND flash memory 20. The cumulative count table 17, the cumulative count threshold 18, and the previous count value 19 are loaded from the NAND flash memory 20 into the RAM 16, for example, immediately after power-on. In addition, the cumulative count table 17, the cumulative count threshold 18, and the previous count value 19 are updated, for example, during a refresh reservation control operation.

[0039] The NAND flash memory 20 non-volatilely stores data received from the memory controller 10. The NAND flash memory 20 outputs read data to the memory controller 10. The NAND flash memory 20 contains multiple memory chips 21 (21-0 to 21-N, where N is an integer greater than or equal to 1). Each memory chip 21-0 to 21-N is independently controlled by the memory controller 10. Alternatively, the NAND flash memory 20 may contain only one memory chip 21.

[0040] [1-1-2] Composition of memory chip 21

[0041] use Figure 2 The configuration of the memory chip (hereinafter referred to as "chip") 21 within the NAND flash memory 20 will be described. Figure 2 This is a block diagram illustrating an example of the configuration of chip 21-0 within the NAND flash memory 20 included in the memory system 1 of this embodiment. Furthermore, since chips 21-1 to 21-N have the same configuration as chip 21-0, their description is omitted.

[0042] Chip 21-0 includes, for example, input / output circuit 22, register group 23, logic control circuit 24, sequencer 25, voltage generation circuit 26, memory cell array 27, line decoder module 28, sensing amplifier module 29, temperature sensor 30, and temperature counter 31.

[0043] The input / output circuit 22 transmits and receives, for example, 8-bit wide input / output signals I / O0 to I / O7 with the memory controller 10. The input / output signals I / O include, for example, data DAT, status STS, address ADD, and instruction CMD. The input / output circuit 22 also transmits and receives data DAT with the sense amplifier module 29.

[0044] Register set 23 contains a status register 23A, an address register 23B, and an instruction register 23C. Status register 23A stores the status STS. Address register 23B stores the address ADD. Instruction register 23C stores the instruction CMD.

[0045] For example, the status STS is updated based on the action status of the sequencer 25. The status STS is transferred from the status register 23A to the input / output circuit 22 based on commands from the memory controller 10, and then output to the memory controller 10. The address ADD is transferred from the input / output circuit 22 to the address register 23B. The address ADD contains, for example, chip address, block address, page address, and column address. The instruction CMD is transferred from the input / output circuit 22 to the instruction register 23C. The instruction CMD contains, for example, commands related to various actions of chip 21-0.

[0046] The logic control circuit 24 controls each of the input / output circuits 22 and the sequencer 25 based on control signals received from the memory controller 10. Examples of such control signals include the chip start signal CEn, the instruction latch start signal CLE, the address latch start signal ALE, the write start signal WEn, the read start signal REen, and the write protection signal WPn. Additionally, the logic control circuit 24 notifies the memory controller 10 of control signals received from the sequencer 25. Examples of such control signals include, for example, the ready / busy signal RBn.

[0047] The chip start signal CEn is used to start chip 21-0. The instruction latch start signal CLE is used to notify the input / output circuit 22 that the received input / output signal I / O is the instruction CMD. The address latch start signal ALE is used to notify the input / output circuit 22 that the received input / output signal I / O is the address ADD. The write start signal WEn is used to command the input / output circuit 22 to input the input / output signal I / O. The read start signal REn is used to command the input / output circuit 22 to output the input / output signal I / O. The write protection signal WPn is used to set chip 21-0 to a protected state when the power is switched on or off.

[0048] The Ready / Busy signal RBn is used to notify the memory controller 10 chip 21-0 whether it is in a ready or busy state. Furthermore, in this specification, "ready state" indicates that chip 21-0 is capable of receiving commands from the memory controller 10. On the other hand, "busy state" indicates that chip 21-0 is unable to process commands from the memory controller 10.

[0049] The sequencer 25 controls the overall operation of the control chip 21-0. For example, the sequencer 25 performs read, write, and erase operations based on the instruction CMD stored in the instruction register 23C and the address ADD stored in the address register 23B. Additionally, the sequencer 25 controls the temperature sensor 30 and the temperature counter 31. For example, the sequencer 25 stores the voltage value based on the temperature obtained from the temperature sensor 30 or the count value obtained from the temperature counter 31 in the status register 23A as a status STS, and outputs it to the memory controller 10 via the input / output circuit 22. Alternatively, the voltage value or count value based on the temperature may not be used as a status STS, but rather as information other than a status STS, and is output to the memory controller 10.

[0050] The voltage generation circuit 26 generates the voltage used for read, write, and erase operations. The voltage generation circuit 26 supplies the generated voltage to the memory cell array 27, the row decoder module 28, and the sense amplifier module 29.

[0051] The memory cell array 27 contains multiple blocks BLK0 to BLKi (where i is an integer greater than or equal to 1). A block BLK is a collection of multiple memory cell transistors (hereinafter sometimes referred to as "memory cells"), used, for example, as a unit for erasing data. Each memory cell transistor is associated with one bit line and one word line.

[0052] The line decoder module 28 selects a block BLK based on the block address. The line decoder module 28 transmits the voltage supplied from the voltage generation circuit 26 to the word lines, etc., within the selected block BLK.

[0053] During the read operation, the sensing amplifier module 29 reads data from the memory cell array 27 and transmits the read data to the input / output circuit 22. During the write operation, the sensing amplifier module 29 applies a specific voltage to the bit line based on the data received from the input / output circuit 22.

[0054] Temperature sensor 30 measures, for example, the temperature of memory cell array 27. Temperature sensor 30 supplies a voltage based on the measured temperature to sequencer 25 and temperature counter 31. Furthermore, temperature sensor 30 may not directly measure the temperature of memory cell array 27. For example, temperature sensor 30 may also measure the temperature of locations outside memory cell array 27 within chip 21-0.

[0055] Temperature counter 31 changes the incrementing count (count value update) period (speed) based on the voltage supplied from temperature sensor 30. For example, temperature counter 31 increases the incrementing count speed as the voltage supplied from temperature sensor 30 increases. Temperature counter 31 sends the count value to sequencer 25. Details regarding the operation of temperature counter 31 will be described later.

[0056] [1-1-3] Circuit configuration of memory cell array 27

[0057] use Figure 3 The circuit configuration of the memory cell array 27 within chip 21 will be explained. Figure 3 This is a circuit diagram of the memory cell array 27 within the chip 21 included in the memory system 1 of this embodiment. Figure 3 Retrieving one block BLK from the plurality of blocks BLK contained in the memory cell array 27 represents an example of the circuit configuration of the memory cell array 27. The other block BLKs also have... Figure 3 The structure shown.

[0058] Block BLK contains, for example, four string cells SU0 to SU3. Each string cell SU contains multiple NAND strings NS associated with bit lines BL0 to BLm (where m is an integer greater than or equal to 1). Each NAND string NS contains, for example, memory cell transistors MC0 to MC15, and select transistors ST1 and ST2. The memory cell transistor MC contains a control gate and a charge storage layer, storing data non-volatilely. Each of the select transistors ST1 and ST2 is used to select the string cell SU during various operations.

[0059] In each NAND string NS, memory cell transistors MC0 to MC15 are connected in series. The drain of selector transistor ST1 is connected to the bit line BL that establishes the association. The source of selector transistor ST1 is connected to one end of the series-connected memory cell transistors MC0 to MC15. The drain of selector transistor ST2 is connected to the other end of the series-connected memory cell transistors MC0 to MC15. The source of selector transistor ST2 is connected to the source line SL.

[0060] Within the same memory block (BLK), the control gates of memory cell transistors MC0 to MC15 are all connected to word lines WL0 to WL15. The gates of each selection transistor ST1 within serial cells SU0 to SU3 are all connected to selection gate lines SGD0 to SGD3. The gates of all selection transistors ST2 within the same BLK are all connected to selection gate line SGS.

[0061] In the circuit configuration of the memory cell array 27 described above, the bit line BL is shared, for example, by NAND strings NS in each string cell SU that are assigned the same column address. The source line SL is shared, for example, among multiple blocks BLK.

[0062] A collection of multiple memory cell transistors (MCs) connected to a common word line (WL) within a single string cell (SU) is called a cell group (CU). The storage capacity of a cell group (CU), containing memory cell transistors (MCs) that each store 1 bit of data, is defined, for example, as "1 page of data". A cell group (CU) can have a storage capacity of 2 pages or more, depending on the number of bits of data stored by the memory cell transistors (MCs).

[0063] Furthermore, the circuit configuration of the memory cell array 27 is not limited to the configuration described above. For example, the number of string cells SU contained in each BLK, or the number of memory cell transistors MC and selection transistors ST1 and ST2 contained in each NAND string NS, can be arbitrary.

[0064] [1-1-4] Composition of temperature counter 31

[0065] use Figure 4 The configuration of the temperature counter 31 inside chip 21 will be explained. Figure 4 This is a block diagram illustrating an example of the configuration of the temperature counter 31 within the chip 21 included in the memory system 1 of this embodiment.

[0066] Temperature counter 31 includes, for example, a VCO (Voltage Controlled Oscillator) 32 and a counter 33.

[0067] Temperature sensor 30 supplies a temperature-based voltage Vtmp to sequencer 25 and VCO 32. VCO 32 controls the oscillation frequency of signal Sigvc based on the voltage Vtmp supplied from temperature sensor 30. For example, as voltage Vtmp increases, the oscillation frequency of signal Sigvc increases. VCO 32 sends signal Sigvc to counter 33.

[0068] Counter 33 increments the count value CV based on the period of the signal Sigvc received from VCO 32. Counter 33 then sends the count value CV to sequencer 25.

[0069] Hereinafter, the count value CV of the temperature counter 31 will be described using Figure 5 . Figure 5 FIG. is a diagram for explaining the count value CV of the temperature counter 31 included in the memory system 1 of the present embodiment.

[0070] At time t1, if a power supply voltage is supplied to the temperature counter 31, the counter 33 sets the count value CV to 0. The chip temperature Tc is Tc1.

[0071] When the chip temperature Tc is Tc1, the temperature sensor 30 supplies a voltage Vtmp1 based on the chip temperature Tc1 to the VCO 32. The VCO 32 sends a signal Sigvc based on the voltage Vtmp1 supplied from the temperature sensor 30 to the counter 33. For example, if the frequency of the signal Sigvc at this time is set to f1, the period of the signal Sigvc is 1 / f1. The counter 33 receives the signal Sigvc from the VCO 32. After a period of 1 / f1 has elapsed from time 1, that is, at time t2, the counter 33 increments the count value CV from 0 to 1. After a period of 1 / f1 has elapsed from time t2, that is, at time t3, the counter 33 increments the count value CV from 1 to 2.

[0072] At time t3, the chip temperature Tc rises from Tc1 to Tc2. When the chip temperature Tc is Tc2, the temperature sensor 30 supplies a voltage Vtmp2 based on the chip temperature Tc2 to the VCO 32. The VCO 32 sends a signal Sigvc based on the voltage Vtmp2 supplied from the temperature sensor 30 to the counter 33. For example, if the frequency of the signal Sigvc at this time is set to f2, then the relationship f1 < f2 holds. In this case, the period of the signal Sigvc is 1 / f2. The period 1 / f2 is shorter than the period 1 / f1. The counter 33 receives the signal Sigvc from the VCO 32. After a period of 1 / f2 has elapsed from time t3, that is, at time t4, the counter 33 increments the count value CV from 2 to 3. After a period of 1 / f2 has elapsed from time t4, that is, at time t5, the counter 33 increments the count value CV from 3 to 4.

[0073] At time t5, the chip temperature Tc starts to drop from Tc2 to Tc1. When the chip temperature Tc is between Tc2 and Tc3 which is higher than Tc1, the temperature sensor 30 supplies a voltage Vtmp based on the chip temperature Tc to the VCO 32. The VCO 32 sends a signal Sigvc based on the voltage Vtmp supplied from the temperature sensor 30 to the counter 33. For example, if the frequency of the signal Sigvc at this time is set to f3, then the relationship is f1 < f3 < f2. In this case, the period of the signal Sigvc is 1 / f3. The period 1 / f3 is shorter than the period 1 / f1 and longer than the period 1 / f2. The counter 33 receives the signal Sigvc from the VCO 32. After passing the period 1 / f3 from time t5, that is, at time t6, the counter 33 increments the count value CV from 4 to 5.

[0074] At time t6, the chip temperature Tc becomes Tc3. When the chip temperature Tc is between Tc3 and Tc1, the temperature sensor 30 supplies a voltage Vtmp based on the chip temperature Tc to the VCO 32. The VCO 32 sends a signal Sigvc based on the voltage Vtmp supplied from the temperature sensor 30 to the counter 33. For example, if the frequency of the signal Sigvc at this time is set to f4, then the relationship is f1 < f4 < f3. In this case, the period of the signal Sigvc becomes 1 / f4. The period 1 / f4 is shorter than the period 1 / f1 and longer than the period 1 / f3. The counter 33 receives the signal Sigvc from the VCO 32. After passing the period 1 / f4 from time t6, that is, at time t7, the counter 33 increments the count value CV from 5 to 6.

[0075] At time t7, the chip temperature Tc becomes Tc1. Similar to the period from time t1 to time t2, after passing the period 1 / f1 from time t7, that is, at time t8, the counter 33 increments the count value CV from 6 to 7. <​​​​​​​​​​​​​​The cumulative count table 17 stores the cumulative count value and the written flag for each word line WL. The cumulative count value represents the accumulated count value from the time data is written to the memory cell connected to the corresponding word line WL until the count value is obtained by the memory controller 10. For example, the initial value of the cumulative count value is set to -1. The written flag is a flag indicating whether data has been written to the memory cell connected to the corresponding word line WL. For example, when data is being written to the memory cell connected to the corresponding word line WL, the written flag is True. On the other hand, when no data is being written to the memory cell connected to the corresponding word line WL, the written flag is False. The initial value of the written flag is set to False. Furthermore, the cumulative count table 17 may also store the cumulative count value and the written flag in units of multiple word lines or per block BLK, rather than per word line WL.

[0080] Table 17 has multiple cumulative count values ​​(in Figure 6 (In this example, there are 16 entries.) Each entry contains a word line number, a cumulative count value, and a written flag. The word line number and... Figure 3 The character lines WL0 to WL15 correspond to each other.

[0081] If no data has been written to the memory cell connected to the corresponding word line WL, or if the memory cell connected to the corresponding word line WL has been erased, the accumulated count value is set to -1. If the memory cell connected to the corresponding word line WL has been erased, the written flag is set to false.

[0082] When data is being written to the memory cell connected to the corresponding word line WL, or when a refresh operation has been performed on the memory cell connected to the corresponding word line WL, the cumulative count value is set to 0.

[0083] When refreshing the reservation control action, for entries that have been written and marked as true, for example, the cumulative count value is added to the difference between the previous count value 19 and the count value CV that can be obtained from the temperature counter 31.

[0084] For example, in Figure 6In the example, data is being written to memory cells connected to word lines WL0 to WL10, numbered 0 to 10. For word lines 0 to 10, the write flag is true. For word lines 0, 4, and 9, the cumulative count is 2000. For word lines 1 and 6, the cumulative count is 2355. For word lines 2 and 7, the cumulative count is 4336. For word lines 3 and 8, the cumulative count is 2111. For word lines 5 and 10, the cumulative count is 335669. On the other hand, data is not being written to memory cells connected to word lines 11 to 15. For word lines 11 to 15, the write flag is false. For word lines 11 to 15, the cumulative count is -1.

[0085] [1-2] Operation of memory controller 10

[0086] In the memory system 1 of this embodiment, the actions performed by the memory controller 10 include refresh reservation control action, write action, read action, erase action, and refresh control action.

[0087] The following explains the refresh reservation control action, write action, erase action, and refresh control action.

[0088] [1-2-1] Refresh reservation control action

[0089] use Figure 7 This section explains the actions involved in refreshing the reservation control mechanism. Figure 7 This is a flowchart illustrating the refresh reservation control operation of the memory controller 10 included in the memory system 1 of this embodiment.

[0090] At predetermined time intervals (e.g., once a day), the memory controller 10 obtains the count value CV from the temperature counter 31 (S10).

[0091] After obtaining the count value CV, the memory controller 10 calculates the difference between the obtained count value CV and the previous count value 19 (S11).

[0092] After calculating the difference between the obtained count value CV and the previous count value 19, the memory controller 10 updates the previous count value 19 to the count value CV obtained by S10 (S12).

[0093] After updating the previous count value 19, the memory controller 10 selects word line WL (S13). In other words, the memory controller 10 selects any word line number in the cumulative count value table 17. Hereinafter, the selected word line WL will be referred to as word line WLsel.

[0094] After selecting word line WLsel, memory controller 10 determines whether the written flag corresponding to word line WLsel in cumulative count table 17 is true (S14).

[0095] If the corresponding written flag is determined to be true (S14_YES), the memory controller 10 adds the difference between the cumulative value CV calculated by S11 and the previous count value 19 to the cumulative count value corresponding to the word line WLsel in the cumulative count value table 17 (S15).

[0096] After adding the difference between the count value CV and the previous cumulative value 19 to the corresponding cumulative count value, the memory controller 10 determines whether the cumulative count value corresponding to the word line WLsel in the cumulative count value table 17 exceeds the cumulative count threshold 18 (S16).

[0097] If it is determined that the corresponding cumulative count value exceeds the cumulative count threshold 18 (S16_Yes), the memory controller 10 schedules a refresh operation (S17).

[0098] After the scheduled refresh action, the memory controller 10 determines whether all word lines WL have been selected (S18).

[0099] If it is determined that all word lines WL have been selected (S18_Yes), the memory controller 10 ends the refresh reservation control action.

[0100] On the other hand, if it is determined that not all word lines WL are selected (S18_No), the memory controller 10 executes S13.

[0101] If the corresponding written flag is determined to be false (S14_No) and the corresponding cumulative count value is determined not to exceed the cumulative count threshold 18 (S16_No), the memory controller 10 executes S18.

[0102] Thus, the memory controller 10 executes S13 to S17 (repeated) in units of entries in the cumulative count table 17. For example, in the case of multiple word lines or in the case of defining entries in the cumulative count table 17 according to each block BLK, S13 to S17 are executed in units of multiple word lines WL or blocks.

[0103] The following uses Figure 8 A specific example of refreshing the reservation control operation is explained. Figure 8 This diagram illustrates the refresh reservation control operation of the memory controller 10 included in the memory system 1 of this embodiment. Furthermore, in Figure 8 To simplify the explanation, six entries in the cumulative count table 17 are shown.

[0104] The table on the left shows the cumulative count value table 17 before the refresh reservation control action. Furthermore, the cumulative count threshold 18 is set to 340000. The previous count value 19 is set to 100000. Because data has been written to the memory cells connected to word lines WL0 and WL4, the cumulative count values ​​corresponding to word line numbers 0 and 4 change from -1 to 0. Data is being written to the memory cells connected to word lines WL1 to WL3 and WL5. The cumulative count value corresponding to word line number 1 is 355. The cumulative count value corresponding to word line number 2 is 2336. The cumulative count value corresponding to word line number 3 is 111. The cumulative count value corresponding to word line number 5 is 333669. The written flag corresponding to word lines 0 to 5 is true. The table on the center shows the cumulative count value table 17 after the refresh reservation control action. The table on the right shows the cumulative count value table 17 after a certain period has elapsed since the refresh reservation control action began, and after the next refresh reservation control action.

[0105] In the refresh reservation control action, perform the following actions.

[0106] The memory controller 10 obtains the count value CV(102000) from the temperature counter 31. Figure 7 (S10).

[0107] The memory controller 10 calculates the difference (2000) between the acquired count value CV (102000) and the previous count value CV (100000). Figure 7 (S11).

[0108] After calculating the difference between the count value CV and the previous count value 19, the memory controller 10 updates the previous count value 19 to the value obtained from the previous count value CV. Figure 7 The count value CV(102000) obtained by S10 ( Figure 7 (S12).

[0109] The memory controller 10 adds the cumulative count value to each entry marked as true written in the cumulative count value table 17. Figure 7 The difference between the count value CV calculated by S11 and the previous count value 19 (2000)( Figure 7 (S15). The cumulative count value corresponding to word line numbers 0 and 4 changes from 0 to 2000. The cumulative count value corresponding to word line number 1 changes from 355 to 2355. The cumulative count value corresponding to word line number 2 changes from 2336 to 4336. The cumulative count value corresponding to word line number 3 changes from 111 to 2111. The cumulative count value corresponding to word line number 5 changes from 333669 to 335669.

[0110] The memory controller 10 determines whether the cumulative count value exceeds the cumulative count threshold 18 (340000) for each entry in the cumulative count value table 17 corresponding to word line numbers 0 to 5. Figure 7 (S16). The cumulative count value corresponding to word line numbers 0 to 5 does not exceed the cumulative count threshold 18 (340000). Therefore, the memory controller 10 does not schedule a refresh operation.

[0111] In the next refresh reservation control action, perform the following actions.

[0112] The memory controller 10 obtains the count value CV(112000) from the temperature counter 31. Figure 7 (S10).

[0113] The memory controller 10 calculates the difference (10000) between the acquired count value CV (112000) and the previous count value CV (102000). Figure 7 (S11).

[0114] After calculating the difference between the count value CV and the previous count value 19, the memory controller 10 updates the previous count value 19 to the value obtained from the previous count value CV. Figure 7 The count value CV obtained by S10 is 112000 ( Figure 7 (S12).

[0115] The memory controller 10 adds the cumulative count value to each entry marked as true written in the cumulative count value table 17. Figure 7 The difference between the count value CV calculated by S11 and the previous count value 19 (10000)( Figure 7 (S15). The cumulative count value corresponding to word line numbers 0 and 4 changes from 2000 to 12000. The cumulative count value corresponding to word line number 1 changes from 2355 to 12355. The cumulative count value corresponding to word line number 2 changes from 4336 to 14336. The cumulative count value corresponding to word line number 3 changes from 2111 to 12111. The cumulative count value corresponding to word line number 5 changes from 335669 to 345669.

[0116] The memory controller 10 determines whether the cumulative count value exceeds the cumulative count threshold 18 (340000) for each entry in the cumulative count value table 17 corresponding to word line numbers 0 to 5. Figure 7 (S16). The cumulative count value corresponding to word line numbers 0 to 4 does not exceed the cumulative count threshold (340000). However, the cumulative count value (345669) corresponding to word line number 5 exceeds the cumulative count threshold (340000). Therefore, the memory controller 10 schedules a refresh operation for the memory cell connected to word line WL5.

[0117] [1-2-2] Write action

[0118] use Figure 9 The writing action is described below. Figure 9 This is a flowchart illustrating the write operation of the memory controller 10 included in the memory system 1 of this embodiment.

[0119] If a write request is received from the host device 2, the memory controller 10 commands the NAND flash memory 20 to write data (S20).

[0120] If the NAND flash memory 20 completes the data writing, the memory controller 10 sets the cumulative count value corresponding to the word line WLsel in the cumulative count value table 17 to 0 (clear) (S21). In addition, the memory controller 10 sets the written flag corresponding to the word line WLsel in the cumulative count value table 17 to true (S22).

[0121] [1-2-3] Erasure action

[0122] use Figure 10 The erasure action is explained. Figure 10 This is a flowchart illustrating the erase operation of the memory controller 10 included in the memory system 1 of this embodiment.

[0123] The memory controller 10 commands the NAND flash memory 20 to erase the data (S30).

[0124] If the NAND flash memory 20 completes the data erasure, the memory controller 10 sets the cumulative count value corresponding to the word line WLsel in the cumulative count value table 17 to -1 (initialization) (S31). In addition, the memory controller 10 sets the written flag corresponding to the word line WLsel in the cumulative count value table 17 to false (S32).

[0125] [1-2-4] Refresh control actions

[0126] use Figure 11 This section explains the refresh control actions. Figure 11 This is a flowchart illustrating the refresh control operation of the memory controller 10 included in the memory system 1 of this embodiment.

[0127] The memory controller 10 checks whether to schedule a refresh operation at predetermined time intervals (S40).

[0128] If the scheduled refresh action is confirmed (S40_Yes), the memory controller 10 performs the refresh action (S41).

[0129] If the refresh operation is completed, the memory controller 10 sets the cumulative count value corresponding to the word line WLsel in the cumulative count value table 17 to 0 (clear) (S42).

[0130] On the other hand, if it is confirmed that no refresh action has been scheduled (S40_No), the memory controller 10 ends the refresh control action.

[0131] [1-3] Effects

[0132] In this embodiment, the NAND flash memory 20 includes a temperature counter 31. The temperature counter 31 changes its incrementing count period (speed) based on the voltage supplied from the temperature sensor 30. The count value CV of the temperature counter 31 corresponds to the temperature history of the chip 21. The memory controller 10 stores a cumulative count value table 17. The memory controller 10 obtains the count value CV from the temperature counter 31 at predetermined time intervals. Based on the obtained count value CV, the memory controller 10 updates the cumulative count value in the cumulative count value table 17. The memory controller 10 schedules a refresh operation if the updated cumulative count value exceeds a cumulative count threshold 18.

[0133] Thus, according to this embodiment, the memory controller 10 can grasp the temperature history of the chip 21 through the count value CV. That is, the memory controller 10 can obtain the temperature history of the chip 21 during periods when the temperature is not monitored. Therefore, since the memory controller 10 can monitor the temperature of the chip 21 less frequently, low power consumption can be achieved. In addition, because the time spent on monitoring is reduced, the processing power of the memory controller 10 can be improved.

[0134] Furthermore, according to this embodiment, since the memory controller 10 reflects the temperature history of the chip 21 during periods of non-monitoring and schedules refresh operations, erroneous reads caused by retention can be suppressed. Therefore, data reliability can be improved.

[0135] [2] Second Embodiment

[0136] The second embodiment will be described. The memory system 1 of this embodiment differs from the first embodiment in the configuration of the chip 21 and the temperature counter 31. The operation of the memory controller 10 is the same as in the first embodiment. Hereinafter, the description will focus on the differences from the first embodiment.

[0137] [2-1] Composition of chip 21

[0138] use Figure 12 The configuration of the chip 21 within the NAND flash memory 20 will be explained. Figure 12This is a block diagram illustrating an example of the configuration of chip 21-0 within the NAND flash memory 20 included in the memory system 1 of this embodiment. Furthermore, since chips 21-1 to 21-N have the same configuration as chip 21-0, their description is omitted.

[0139] Chip 21-0 also includes an A / D (Analog / Digital) converter 34. The other configurations of chip 21-0 are the same as in the first embodiment.

[0140] The A / D converter 34 performs A / D conversion on the voltage supplied from the temperature sensor 30. The A / D converter 34 sends the converted value to the sequencer 25 and the temperature counter 31.

[0141] [2-2] Composition of temperature counter 31

[0142] use Figure 13 The configuration of the temperature counter 31 inside chip 21 will be explained. Figure 13 This is a block diagram illustrating an example of the configuration of the temperature counter 31 within the chip 21 included in the memory system 1 of this embodiment.

[0143] Temperature counter 31 changes the increment (count value update) based on the value received from A / D converter 34. For example, temperature counter 31 increments the count by one increment as the value received from A / D converter 34 increases. Temperature counter 31 includes, for example, an adder circuit 35, an adder 36, and a register 37.

[0144] Temperature sensor 30 supplies a temperature-based voltage Vtmp to sequencer 25 and A / D converter 34. A / D converter 34 performs A / D conversion on the voltage Vtmp supplied from temperature sensor 30 and sends the converted value as the temperature code TEMPCODE to sequencer 25 and adder conversion circuit 35.

[0145] The adder value conversion circuit 35 receives the temperature code TEMPCODE from the A / D converter 34 at predetermined time intervals (e.g., once per second). The adder value conversion circuit 35 retrieves the adder value table 38 stored in the NAND flash memory 20. The adder value table 38 is a table storing adder values. The adder value is the number of increments corresponding to the temperature code TEMPCODE. Details about the adder value table 38 will be described later. Based on the adder value table 38, the adder value conversion circuit 35 converts the received temperature code TEMPCODE into an adder value adv. The adder value conversion circuit 35 sends the adder value adv to the adder 36.

[0146] Adder 36 receives the addition value adv from adder value conversion circuit 35. Adder 36 receives the value rgv stored in register 37. Adder 36 adds the addition value adv received from adder value conversion circuit 35 to the value rgv received from register 37. Adder 36 sends the addition result (value rtv) to register 37.

[0147] Register 37 stores the value rtv received from adder 36 as the value rgv. Register 37 sends the stored value rgv to adder 36. Register 37 also sends the stored value rgv as the count value CV to sequencer 25.

[0148] [2-3] Addition Value Table 38

[0149] use Figure 14 The addition value table 38 is explained. Figure 14 This is a conceptual diagram of the addition value table 38 included in the memory system 1 of this embodiment.

[0150] The addition value table 38 stores the addition value according to each temperature code TEMPCODE.

[0151] Addition value table 38 has multiple (in Figure 14 (In this example, there are 11 entries.) Each entry contains a temperature code TEMPCODE and an addition value. The temperature code TEMPCODE is a value corresponding to a temperature. Furthermore, the addition value table 38 is stored, for example, in any block BLK of the NAND flash memory 20. The addition value table 38 is loaded from the NAND flash memory 20 into RAM (not shown), for example, immediately after power-on.

[0152] For example, in Figure 14 In the example case, the value of the temperature code TEMPCODE is represented by the temperature [degrees] of chip 21. That is to say, in Figure 14 In this model, an additive value is defined every 10 degrees from 20 degrees to 120 degrees. The additive value corresponding to 20 degrees, 30 degrees, 40 degrees, and 50 degrees is 1. The additive value corresponding to 60 degrees is 2. The additive value corresponding to 70 degrees is 4. The additive value corresponding to 80 degrees is 8. The additive value corresponding to 90 degrees is 16. The additive value corresponding to 100 degrees is 32. The additive value corresponding to 110 degrees is 128. The additive value corresponding to 120 degrees is 256. Furthermore, the additive values ​​corresponding to the temperature of chip 21 are not limited to this.

[0153] When the temperature of chip 21 is below 60 degrees, the addition value conversion circuit 35 converts the temperature code TEMPCODE into an addition value (1). Adder 36 adds the addition value (1) received from the addition value conversion circuit 35 to the value stored in register 37.

[0154] When the temperature of chip 21 is above 60 degrees but below 70 degrees, the addition value conversion circuit 35 converts the temperature code TEMPCODE into an addition value (2). Adder 36 adds the addition value (2) received from the addition value conversion circuit 35 to the value stored in register 37.

[0155] When the temperature of chip 21 is above 70 degrees but below 80 degrees, the addition value conversion circuit 35 converts the temperature code TEMPCODE into an addition value (4). Adder 36 adds the addition value (4) received from the addition value conversion circuit 35 to the value stored in register 37.

[0156] When the temperature of chip 21 is above 80 degrees but below 90 degrees, the addition value conversion circuit 35 converts the temperature code TEMPCODE into an addition value (8). Adder 36 adds the addition value (8) received from the addition value conversion circuit 35 to the value stored in register 37.

[0157] When the temperature of chip 21 is above 90 degrees but below 100 degrees, the adder-value conversion circuit 35 converts the temperature code TEMPCODE into an addend value (16). Adder 36 adds the addend value (16) received from the adder-value conversion circuit 35 to the value stored in register 37.

[0158] When the temperature of chip 21 is above 100 degrees but below 110 degrees, the addition value conversion circuit 35 converts the temperature code TEMPCODE into an addition value (32). Adder 36 adds the addition value (32) received from the addition value conversion circuit 35 to the value stored in register 37.

[0159] When the temperature of chip 21 is above 110 degrees but below 120 degrees, the adder-value conversion circuit 35 converts the temperature code TEMPCODE into an addend value (128). Adder 36 adds the addend value (128) received from the adder-value conversion circuit 35 to the value stored in register 37.

[0160] When the temperature of chip 21 is above 120 degrees, the adder-value conversion circuit 35 converts the temperature code TEMPCODE into an addend value (256). Adder 36 adds the addend value (256) received from the adder-value conversion circuit 35 to the value stored in register 37.

[0161] Thus, the increment of temperature counter 31 in one increment is as follows: the lower the chip temperature, the smaller the increment; the higher the chip temperature, the larger the increment. In other words, the lower the chip temperature, the slower the increment; and the higher the chip temperature, the faster the increment.

[0162] [2-4] Effects

[0163] According to the configuration of this embodiment, the same effect as the first embodiment can be achieved.

[0164] [3] Examples of variations, etc.

[0165] As described above, the memory system of the embodiment includes: a semiconductor memory device (20) and a memory controller (10), the semiconductor memory device (20) including: a memory cell array (27) including memory cells (MC); and a temperature counter (31) that changes the rate at which the update count value (CV) is changed based on the temperature of the memory cell array; the memory controller (10) is configured to obtain the count value from the semiconductor memory device and, if the accumulated count value from writing data to the memory cell to obtaining the count value exceeds a predetermined value (18), schedule a refresh operation for the memory cell.

[0166] Furthermore, the implementation method is not limited to the described method and various variations are possible.

[0167] Furthermore, the processing order of the flowcharts described in the embodiments can be changed as much as possible. For example, in the refresh reservation control action, the update of the previous count value 19 (S12) can be performed after determining whether all word lines WL have been selected (S18). In the write action, updating the accumulated count value to 0 (S21) and updating the written flag to true (S22) can be in the reverse order. In the erase action, updating the accumulated count value to -1 (S31) and updating the completed flag to false (S32) can also be in the reverse order.

[0168] While several embodiments of the present invention have been described, these embodiments are provided as examples and are not intended to limit the scope of the invention. The novel embodiments can be implemented in various other ways, with various omissions, substitutions, and modifications possible without departing from the spirit of the invention. The embodiments or variations thereof are included within the scope or spirit of the invention, as well as within the scope of the invention as described in the claims and its equivalents.

[0169] [Explanation of Symbols]

[0170] 1: Memory System

[0171] 2: Host equipment

[0172] 10: Memory controller

[0173] 11: Host Interface Circuit

[0174] 12: Processor

[0175] 13: Buffer memory

[0176] 14: ECC circuit

[0177] 15: NAND Interface Circuit

[0178] 16: RAM

[0179] 17: Cumulative Count Table

[0180] 18: Cumulative count threshold

[0181] 19: Previous count value

[0182] 20: NAND flash memory

[0183] 21-0~21-N: Memory chips

[0184] 22: Input / output circuit

[0185] 23: Register Set

[0186] 24: Logic control circuit

[0187] 25:Serializer

[0188] 26: Voltage generation circuit

[0189] 27: Memory Cell Array

[0190] 28: Line decoder module

[0191] 29: Sensing Amplifier Module

[0192] 30: Temperature sensor

[0193] 31: Temperature counter

[0194] 32:VCO

[0195] 33: Counter

[0196] 34: A / D Converter

[0197] 35: Addition value conversion circuit

[0198] 36: Adder

[0199] 37: Register

[0200] 38: Addition Value Table.

Claims

1. A memory system comprising a semiconductor memory device and a memory controller, and The semiconductor memory device includes: Memory cell array, comprising memory cells; and A temperature counter that updates its count value based on the temperature of the memory cell array. The memory controller is configured as follows: The count value is obtained from the semiconductor memory device. If the accumulated value of the count value from the time data is written to the memory cell until the count value is obtained exceeds a predetermined value, a refresh operation is scheduled for the memory cell.

2. The memory system of claim 1, wherein the temperature counter is updated based on the temperature change period.

3. The memory system according to claim 2, wherein the update cycle is longer at lower temperatures and shorter at higher temperatures.

4. The memory system of claim 1, wherein the temperature counter is updated based on the amount of one temperature change.

5. The memory system of claim 4, wherein the amount of update is less at lower temperatures and more at higher temperatures.

6. The memory system according to any one of claims 1 to 5, wherein, when data has been written to the memory cell, the memory controller clears the accumulated value of the counter value corresponding to the memory cell.

7. The memory system according to any one of claims 1 to 5, wherein the memory controller performs a refresh operation on the memory cell when the refresh operation has been scheduled for the memory cell.

8. The memory system of claim 7, wherein, when the refresh operation has been performed on the memory cell, the memory controller clears the accumulated value of the count value corresponding to the memory cell.

9. A memory controller, configured as follows: From a semiconductor memory device having an array of memory cells containing memory cells, obtain a count value based on the temperature of the memory cell array. If the accumulated value of the count value from the time data is written to the memory cell until the count value is obtained exceeds a predetermined value, a refresh operation is scheduled for the memory cell.

10. The memory controller according to claim 9, further configured to clear the accumulated value of the count value corresponding to the memory cell when data has been written to the memory cell.

11. The memory controller according to claim 9 or 10, further configured to perform a refresh operation on the memory cell when the refresh operation has been scheduled for the memory cell.

12. The memory controller according to claim 11, further configured to clear the accumulated value of the count value corresponding to the memory cell when the refresh operation has been performed on the memory cell.

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