Over-allocation components for memory management

Abstract

This disclosure relates to an over-allocation component for memory management. One method includes: designating a first set of memory cells in a memory array for write burst mode operations by the over-allocation component; designating a second set of memory cells in the memory array for non-write burst mode operations; identifying that a request to perform a specific non-write burst operation exceeds the number of memory cells available in the second set of memory cells for the non-write burst mode write operation; designating a portion of the first set of memory cells as a static single-level cell (SLC) block for the non-write burst mode write operation by the over-allocation component in response to the request; and writing data associated with the specific non-write burst write operation to the static SLC block.

Description

Technical Field

[0001] Embodiments of this disclosure generally relate to memory subsystems, and more specifically, to over-allocation components for memory management. Background Technology

[0002] The memory subsystem may include one or more memory devices for storing data. For example, the memory devices may be non-volatile memory devices and volatile memory devices. Generally, a host system may utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the Invention

[0003] On one hand, this disclosure provides a method for managing over-allocated memory, comprising: designating a first group of memory cells in a memory array for write burst mode operations by an over-allocation component; designating a second group of memory cells in the memory array for non-write burst mode operations; identifying that a request to perform a specific non-write burst operation exceeds the number of memory cells available for the second group of memory cells for the non-write burst mode write operation; designating a portion of the first group of memory cells as a static single-level cell (SLC) block for the non-write burst mode write operation by the over-allocation component in response to the request; and writing data associated with the specific non-write burst write operation into the static SLC block.

[0004] On the other hand, this disclosure provides an apparatus for over-allocation memory management, comprising: a memory array; and an over-allocation component coupled to the memory array and configured to: designate a set of memory cells of the memory array for over-allocation; designate a first portion of the set of memory cells as an idle write burst block, wherein the first portion includes a dynamic single-level cell (SLC) block and a static SLC block; designate a second portion of the set of memory cells as an idle non-write burst block, wherein the second portion includes a dynamic SLC block; designate a static SLC block from the first portion to the second portion to be used as an idle non-write burst block; perform a non-write burst operation using the designated static SLC block; and when the non-write burst write operation exceeds the static SLC block, open a third portion of the memory array as an idle non-write burst block.

[0005] In another aspect, this disclosure provides a system for over-allocation memory management, comprising: a plurality of memory components arranged to form a stackable cross-grid array of interleaved NAND memory cells; and a processing means coupled to the plurality of memory components, the processing means being configured to perform operations including: designating a set of memory cells of the NAND memory cells for over-allocation; designating a first portion of the set of memory cells as an idle write burst block, wherein the first portion comprises a static single-level cell (SLC) block; identifying a second portion of the set of memory cells as a data write burst block having data stored from a write burst write operation; and designating a third portion of the set of memory cells as an idle non-... Write a burst block, wherein the third portion comprises a dynamic SLC block; identify a fourth portion of the group memory cells as a data non-write burst block having data stored from a non-write burst write operation; designate a static SLC block from the first portion to the third portion to be used as an idle non-write burst block; perform a non-write burst write operation using the designated static SLC block to store data associated with the non-write burst write operation; when the non-write burst write operation is performed, identify the static SLC block as a portion of the fourth portion; and designate the static SLC block as a portion of the first portion in response to the execution of a media management operation involving the removal of the data associated with the non-write burst write operation. Attached Figure Description

[0006] Figure 1 This describes an example computing system including a memory subsystem according to some embodiments of the present disclosure.

[0007] Figure 2 This is a flowchart corresponding to a method for managing over-allocation memory according to some embodiments of the present disclosure.

[0008] Figure 3 This is a flowchart corresponding to a method for managing over-allocation memory according to some embodiments of the present disclosure.

[0009] Figure 4 Examples of memory management involving over-allocated memory blocks for a set of memory cells, according to some embodiments of this disclosure, are described.

[0010] Figure 5 Examples of memory management involving over-allocated memory blocks for a set of memory cells, according to some embodiments of this disclosure, are described.

[0011] Figure 6 Examples of memory management involving over-allocated memory blocks for a set of memory cells, according to some embodiments of this disclosure, are described.

[0012] Figure 7 This is a block diagram of an example computer system in which embodiments of this disclosure may be operated. Detailed Implementation

[0013] This disclosure relates to over-allocation memory management in a memory subsystem, and more particularly to a memory subsystem including over-allocation memory management components. The memory subsystem may be a storage system, a storage device, a memory module, or a combination thereof. An example of a memory subsystem is a storage system, such as a solid-state drive (SSD). The following describes... Figure 1 Examples of storage devices and memory modules are described elsewhere. Generally, a host system may utilize a memory subsystem comprising one or more components, such as a memory device for storing data. The host system can provide data to be stored in the memory subsystem and can request data to be retrieved from the memory subsystem.

[0014] Memory devices can be non-volatile memory devices. An example of a non-volatile memory device is a NAND flash memory device (also known as flash memory). The following section combines... Figure 1 Other examples of non-volatile memory devices are described below. A non-volatile memory device is a package of one or more dies. Each die may consist of one or more planes. Planes may be divided into logic units (LUNs). For some types of non-volatile memory devices (e.g., NAND devices), each plane consists of a set of physical blocks. Each block consists of a set of pages. Each page consists of a set of memory cells (“cells”). A cell is an electronic circuit that stores information. The term “block” below refers to a unit of memory device used to store data and may contain a group of memory cells, a group of word lines, a word line, or individual memory cells. For some memory devices, a block (hereinafter also referred to as a “memory block”) is the smallest erasable area. Pages cannot be erased individually; only the entire block can be erased.

[0015] Each memory device may contain one or more arrays of memory cells. Depending on the cell type, a cell may store one or more bits of binary information and has various logic states related to the number of bits stored. Logic states may be represented by binary values ​​such as "0" and "1" or combinations of such values. Various types of cells exist, such as single-level cells (SLC), multi-level cells (MLC), three-level cells (TLC), and four-level cells (QLC). For example, an SLC may store one bit of information and have two logic states.

[0016] Some NAND memory devices employ a floating gate architecture, where memory access is controlled based on a relative voltage change between the bit line and the word line. Other examples of NAND memory devices may employ an alternative gate architecture that may include the use of a word line layout, which allows charge corresponding to data values ​​to be trapped within the memory cell based on the properties of the materials used to construct the word lines.

[0017] During operation, the memory subsystem may perform write burst operations, read burst operations, and / or other types of burst operations. Similarly, the memory subsystem may perform non-write burst operations, non-read burst operations, and / or other types of non-burst operations. As used herein, a "write burst operation" generally refers to a write operation performed by a number of transactions less than the amount of data being written. In some embodiments, a write burst operation may be characterized by a number of write commands being executed in parallel that is greater than the average number of write commands. For example, a write burst operation may not utilize a separate transaction for each piece of data being written. In some instances, a write burst operation may involve writing to a cache line that only specifies the start address of the cache line. During the execution of a write burst operation, the memory subsystem may operate in a transient performance state (e.g., burst operation mode) that is shorter in duration than a steady-state performance state (e.g., normal operation mode) and characterized by higher performance than the steady-state performance state. In contrast, a "non-write burst operation" may involve writing a transaction for each piece of data on a cache line. For example, a non-write burst operation may involve using a transaction for each cache line, compared to a write burst operation that may utilize a single transaction for multiple cache lines. In some embodiments, non-write burst operations include operations performed when the memory subsystem is operating in a steady-state performance state.

[0018] In some embodiments, the host may request a write burst operation on a single-level cell (SLC) block until the write burst buffer is full. In these embodiments, the host may not request a non-write burst operation on the SLC block. In some instances, a four-level cell (QLC) may be forced to support asynchronous power loss (APL) using either SLC or TLC. As used herein, "asynchronous power loss" may refer to power loss without prior power-off notification. For example, asynchronous power loss may include unexpected power loss and / or power loss when the memory subsystem is unable to perform a final operation in response to a power-off notification. In some embodiments, the memory subsystem may include a first portion designated for user data and a second portion designated for over-allocation.

[0019] As used herein, "over-allocation portion" and variations thereof generally refer to a portion of a memory subsystem that may contain memory cells allocated by the memory subsystem controller (e.g., not by the host) for use during media management operations, such as discarded item collection and / or wear leveling operations. By reserving a specific number of free memory blocks in the over-allocation portion of the memory subsystem, write operations involving the over-allocation portion can be performed without waiting for memory blocks not allocated to the over-allocation portion to be erased. This allows for improved efficiency of the memory subsystem compared to a method in which the host has access to all memory blocks of the memory subsystem. That is, an over-allocation portion may refer to a certain number of memory cells used for over-allocation operations. In some instances, the over-allocation portion may contain memory cells designated as dynamic blocks and memory cells designated as static blocks. As used herein, "static memory cell" or "static block" generally refers to a memory cell that is fixed in size once allocated. As used herein, "dynamic memory cell" or "dynamic block" generally refers to a memory cell that can be allocated to multiple different sizes and is reassigned to different sizes once allocated. In some embodiments, static memory cells may have relatively higher endurance than dynamic memory cells. For example, static SLCs may have relatively higher endurance than dynamic SLCs. In this example, the endurance of a static SLC is 10 to 50 times that of a dynamic SLC. However, in some embodiments, SLC blocks cannot be used as QLC blocks, and therefore, using static SLC blocks may affect the over-allocation and limiting block functionality of the memory subsystem.

[0020] In some embodiments, a host or host device may utilize a Universal Flash Memory (UFS) system to increase the reliability of the memory subsystem. As used herein, “Universal Flash Memory System” generally refers to a storage specification protocol that can be utilized by the memory subsystem. In some instances, the UFS system may include instructions to perform write burst operations using the SLC of the memory subsystem. In some embodiments, even under 100% logical saturation, the memory subsystem may allocate or designate a certain percentage (e.g., 0.25%, etc.) of the device capacity as a write burst. As used herein, the term “logical saturation” generally refers to a certain amount or percentage of memory resources that are being used or storing data at a given time. In this way, static SLC blocks and / or dynamic SLC blocks may not be fully utilized or may be over-allocated, which can degrade overall system performance.

[0021] This disclosure addresses the above and other shortcomings by specifying or allocating static and dynamic SLC blocks between a non-write burst free block pool and a write burst free block pool. As used herein, a "free block pool" may contain memory cells that are writable or to which data is not currently written. In this way, the free block pool can be used by the host for write burst operations and / or non-write burst operations. In some embodiments, the excess allocation portion of the memory subsystem may be specified as multiple portions. For example, the excess allocation portion of the memory subsystem may include a write burst free portion, a non-write burst free portion, a write burst data portion, and / or a non-write burst data portion. By specifying and reassigning memory cells between different portions, static and dynamic SLCs can be utilized more efficiently and the overall performance of the memory subsystem can be improved.

[0022] Figure 1 This description describes an example computing system 100 including a memory subsystem 110 according to some embodiments of the present disclosure. The memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination thereof.

[0023] The memory subsystem 110 may be a memory device, a memory module, or a hybrid of a memory device and a memory module. Examples of memory devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0024] The computing system 100 may be a computing device, such as a desktop computer, laptop computer, server, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other vehicle), Internet of Things (IoT) enabled device, embedded computer (e.g., device included in a vehicle, industrial equipment or networked business device), or the computing device including memory and processing device.

[0025] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1This describes an example of a host system 120 coupled to a memory subsystem 110. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without an intermediate component), whether wired or wireless, including, for example, electrical, optical, magnetic and similar connections.

[0026] Host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an SSD controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). Host system 120, for example, uses memory subsystem 110 to write data to and read data from memory subsystem 110.

[0027] Host system 120 may be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include (but are not limited to) Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect Fast (PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Small Computer System Interface (SCSI), Double Data Rate (DDR) memory bus, Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM slot interfaces supporting Double Data Rate (DDR)), Open NAND Flash Interface (ONFI), Double Data Rate (DDR), Low Power Double Data Rate (LPDDR), or any other interface. The physical host interface can be used to transfer data between host system 120 and memory subsystem 110. Host system 120 may further utilize an NVM Fast (NVMe) interface to access components (e.g., memory device 130) when memory subsystem 110 is coupled to host system 120 via a PCIe interface. The physical host interface provides an interface for transmitting control, address, data and other signals between the memory subsystem 110 and the host system 120. Figure 1 The memory subsystem 110 is described as an example. Generally, the host system 120 can access multiple memory subsystems via the same communication connection, multiple individual communication connections, and / or combinations of communication connections.

[0028] Memory devices 130 and 140 may include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be (but are not limited to) random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0029] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND flash memory and in-place write memory, such as three-dimensional crosspoint (“3D crosspoint”) memory devices, which are crosspoint arrays of non-volatile memory cells. The crosspoint array of non-volatile memory can be combined with a stackable cross-grid data access array to perform bit storage based on changes in volume resistance. Furthermore, unlike many flash-based memories, crosspoint non-volatile memory can perform in-place write operations, where non-volatile memory cells can be programmed without prior erasing of the non-volatile memory cells. NAND flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0030] Each of the memory devices 130 and 140 may include one or more arrays of memory cells. One type of memory cell (e.g., a single-level cell (SLC)) may store one bit per cell. Other types of memory cells (e.g., multi-level cell (MLC), three-level cell (TLC), four-level cell (QLC), and five-level cell (PLC)) may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, or any combination thereof. In some embodiments, a particular memory device may include SLC portions and MLC portions, TLC portions, QLC portions, or PLC portions of memory cells. The memory cells of the memory device 130 may be grouped into pages that can refer to logical units of the memory device used for storing data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0031] Although a three-dimensional cross-point array of non-volatile memory cells and a non-volatile memory component of NAND flash memory (e.g., 2D NAND, 3D NAND) are described, memory device 130 may be based on any other type of non-volatile memory or storage device, such as, for example, read-only memory (ROM), phase-change memory (PCM), self-select memory, other chalcogenide-based memory, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0032] The memory subsystem controller 115 (or, for simplicity, controller 115) can communicate with the memory device 130 to perform operations such as reading data, writing data, or erasing data at the memory device 130, and other such operations. The memory subsystem controller 115 may include hardware such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0033] The memory subsystem controller 115 may be a processor 117 (e.g., a processing device) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logical flows, and routines for controlling the operation of the memory subsystem 110 (including handling communication between the memory subsystem 110 and the host system 120).

[0034] In some embodiments, local memory 119 may include memory registers storing memory pointers, fetched data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although Figure 1 The instance memory subsystem 110 in the present disclosure has been described as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0035] Generally, the memory subsystem controller 115 can receive commands or operations from the host system 120 and can translate these commands or operations into instructions or appropriate commands to achieve the desired access to memory devices 130 and / or 140. The memory subsystem controller 115 may be responsible for other operations, such as wear leveling operations, discard item collection operations, error detection and error correction code (ECC) operations, encryption operations, caching operations, and address translation between logical addresses (e.g., logical block addresses, namespaces) and physical addresses (e.g., physical block addresses, physical media addresses) associated with memory device 130. The memory subsystem controller 115 may further include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system into command instructions to access memory devices 130 and / or 140, and translate responses associated with memory devices 130 and / or 140 into information for the host system 120.

[0036] The memory subsystem 110 may also include additional circuitry or components not described. In some embodiments, the memory subsystem 110 may include caches or buffers (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) capable of receiving addresses from the memory subsystem controller 115 and decoding the addresses to access the memory devices 130 and / or 140.

[0037] In some embodiments, memory device 130 includes a local media controller 135, which operates in conjunction with a memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory device 130 is a managed memory device, which is a native memory device combined with a local controller (e.g., local controller 135) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0038] Memory subsystem 110 may include over-allocation memory management component 113. Although in Figure 1While not shown in the diagrams to avoid confusion, the over-allocation memory management component 113 may include various circuitry to facilitate the allocation of memory cells for write burst operations and non-write burst operations. In some embodiments, the over-allocation memory management component 113 may include dedicated circuitry in the form of an ASIC, FPGA, state machine, and / or other logic circuitry, which may allow the over-allocation memory management component 113 to orchestrate and / or execute operations to selectively perform media management operations on memory devices 130 and / or 140.

[0039] In some embodiments, the memory subsystem controller 115 includes at least a portion of the over-allocation memory management component 113. For example, the memory subsystem controller 115 may include a processor 117 (processing means) configured to execute instructions stored in local memory 119 for performing the operations described herein. In some embodiments, the over-allocation memory management component 113 is part of the memory subsystem 110, an application program, or an operating system.

[0040] In a non-limiting example, the device (e.g., computing system 100) may include an over-allocated memory management component 113. The over-allocated memory management component 113 may reside on a memory subsystem 110. As used herein, the term "resides on" means something physically located on a particular component. For example, the over-allocated memory management component 113 "residing" on memory subsystem 110 means that the hardware circuitry including the over-allocated memory management component 113 is physically located on memory subsystem 110. The term "resides on" may be used interchangeably with other terms herein, such as "deployed on" or "located on".

[0041] In some embodiments, the over-allocation memory management component 113 may be configured to designate a portion of the memory array for storing user data and to designate different portions of the memory array for over-allocation. In this way, the group of memory cells can be designated to perform over-allocation on the memory array. In some embodiments, the over-allocation memory management component 113 may cause one or more operations involving the group of memory cells to be performed, which may allow data to be erased from at least one portion of the memory array without interrupting the operation of the memory array and / or the memory subsystem.

[0042] In some embodiments, the over-allocation memory management component 113 may be configured to designate a first portion of the group of memory cells as a free write burst block. In these embodiments, the first portion may include dynamic single-level cell (SLC) blocks and static SLC blocks. In some embodiments, a free write burst block may be an open or unoccupied memory cell that will be used by the host or host system for a write burst operation. That is, circuitry residing on the memory subsystem may select memory cells from the first portion of the group of memory cells for a write burst write operation in response to signaling received from the host. In some instances, the first portion of the group of memory cells may include both dynamic SLC blocks and static SLC blocks. The number of free dynamic SLC blocks and static SLC blocks may change as data is written into blocks within the first portion of the group of memory cells and / or as data is erased from memory cells designated as data write burst blocks. In this way, the number of free dynamic SLC blocks and free static SLC blocks designated as the first portion of the group of memory cells can be monitored.

[0043] In some embodiments, the over-allocation memory management component 113 may be configured to designate a second portion of the group of memory cells as an idle non-write burst block. In these embodiments, the second portion may include a dynamic SLC block. The idle non-write burst block may be a memory cell designated for use by the host to perform a non-write burst write operation. That is, the memory subsystem may utilize the second portion of the group of memory cells to perform a non-write burst write operation in response to signaling received from the host.

[0044] In some embodiments, a designated second portion of the group memory cell may not contain any free static SLC blocks. As described herein, a particular protocol may not require non-write burst blocks to be written to static SLC blocks, and therefore, the original designation of the second portion of the group memory cell for free non-write burst blocks may not contain any free static SLC blocks. As used herein, the original designation of the second portion of the group memory cell may generally refer to an initial designation or a designation specific to a particular host protocol. Some prior methods may use these types of original designations for the second portion of the group memory cell because static SLC blocks are not required for non-write burst operations.

[0045] In some embodiments, the over-allocation memory management component 113 may be configured to designate static SLC blocks from a first portion to a second portion that will be used as idle non-write burst blocks. As described herein, the second portion may not contain any static SLC blocks because the host may not use static SLC blocks for non-write burst operations, as described above. In some embodiments, the over-allocation memory management component 113 may designate static SLC blocks to the second portion when write requests involving non-write burst blocks from the second portion exceed the number of available memory cells. Previous methods may require opening new blocks within the over-allocation portion, opening new blocks within the user area portion, and / or slowing down the execution of the memory subsystem to accommodate the requests. In contrast, this disclosure designates static SLC blocks from the first portion to the second portion to allow requests to be completed without opening additional blocks or negatively impacting the performance of the memory array.

[0046] In some embodiments, the over-allocation memory management component 113 can be configured to perform non-write burst operations using a designated static SLC block. Once the static SLC block is specified in the second part, the over-allocation memory management component 113 can be configured to perform non-write burst operations using the static SLC block. In this way, the data within the static SLC block can include non-write burst operation data. Furthermore, once non-write burst operation data is written to the static SLC block, the static SLC block can be designated as a non-write burst data block or a data block occupied by non-write burst operation data.

[0047] In some embodiments, the over-allocation memory management component 113 may be configured to open a third portion of the memory array as an idle non-write burst block when non-write burst write operations exceed the number of memory cells in a static SLC block. In some instances, a designated static SLC block may be exceeded or occupied by non-write burst write operations. If this occurs, the over-allocation memory management component 113 may open the third portion of the memory array and designate the third portion of the memory array as an idle non-write burst block. In some embodiments, additional static SLC blocks from the first portion may be designated to the second portion. In some embodiments, the over-allocation memory management component 113 may be configured to determine when there are no additional static SLC blocks from the first portion that would be designated to the second portion before opening the third portion of the memory array. In this way, opening the third portion can be avoided for a period of time, as opening the third portion can remove memory cells from the user data area and / or degrade performance. In some embodiments, it may not be necessary to open the third portion when the static SLC blocks from the first portion contain the number that allows all non-write burst requests.

[0048] In some embodiments, the over-allocation memory management component 113 may be configured to designate static SLC blocks from the second portion back to the first portion after performing a media management operation on the memory array. In some embodiments, the media management operation may be a discard item collection operation that can erase non-write burst operation data from the static SLC block. In this way, when a static SLC block is designated back to the first portion, it can be designated back to an idle write burst block. In these embodiments, the over-allocation memory management component 113 may be configured to designate dynamic SLC blocks from the first portion to the second portion in response to designating static SLC blocks back to the first portion.

[0049] In some embodiments, the over-allocation memory management component 113 may designate a dynamic SLC block from a first portion to a second portion to allow the second portion to contain a specific number of memory cells required to store a particular non-write burst operation. That is, once a static SLC block is free or not occupied by non-write burst operation data, the over-allocation memory management component 113 may determine the count or number of memory cells utilized by a particular non-write burst operation and, based on the count or number of memory cells, designate a dynamic SLC block from the first portion to the second portion when the static SLC block is designated back to the first portion.

[0050] In some embodiments, the over-allocation memory management component 113 may be configured to designate idle dynamic SLC blocks from the write burst data pool to the second portion in response to the execution of a write burst refresh operation. For example, the write burst data pool may contain memory cells occupied by write burst operation data. In this example, a write burst refresh operation may be performed to erase the write burst operation data from the dynamic SLC blocks designated to the write burst data pool. In this example, dynamic SLC blocks previously designated as idle write burst blocks may be designated as idle non-write burst blocks to increase the count of memory cells within the second portion.

[0051] In some embodiments, the over-allocation memory management component 113 may be configured to determine when the first portion does not contain dynamic SLC blocks and to prevent static SLC blocks assigned to idle non-write burst blocks from being designated as obsolete item collection source blocks. As described herein, some protocols may require static SLC blocks for write burst operations. Therefore, in some embodiments, static SLC blocks assigned to idle non-write burst blocks may be prevented from becoming designated obsolete item collection source blocks to allow static SLC blocks to be assigned back to the first portion or the idle write burst block.

[0052] Figure 2This is a flowchart corresponding to a method 220 for over-allocation memory management according to some embodiments of the present disclosure. Method 220 may be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 220 is performed by… Figure 1 The over-allocated memory management component 113 performs the process. Although shown in a specific sequence or order, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0053] As described herein, a memory array may include designated user area portions for storing data and designated excess allocation portions for removing data through various memory management operations. In some instances, the excess allocation portion of the memory array may be divided into multiple designated portions. For example, the excess allocation portion may include a first portion containing free memory cells (e.g., free memory blocks) to be used for write burst operations, a second portion containing free memory cells (e.g., free memory blocks) to be used for non-write burst operations, a third portion including occupied memory cells containing data from write burst operations, and / or a fourth portion including occupied memory cells containing data from non-write burst operations. Method 220 may be used to designate and redesignate (and / or allocate and reallocate) different memory cells within the excess allocation portion of the memory array to improve the utilization efficiency of both static SLC and dynamic SLC within the excess allocation portion.

[0054] At operation 221, a first set of memory cells in the memory array may be designated for write burst-mode operations. In some embodiments, the first set of memory cells includes free memory cells for writing data associated with the write burst-mode operations. In some embodiments, the memory array may include QLC, MLC, TLC, and / or SLC residing on a mobile device. For example, the memory array may include memory cells residing in a mobile phone, smartphone, wearable device, or tablet computer. As used herein, the term "mobile computing device" generally refers to a handheld computing device with a slate or tablet form factor. Generally, a slate form factor may include a display between approximately 3 inches and 5.2 inches (diagonally measured), while a tablet form factor may include a display between approximately 5.2 inches and 7 inches (diagonally measured). However, instances of "mobile computing device" are not limited thereto, and in some embodiments, "mobile computing device" may refer to IoT devices and other types of edge computing devices. In some instances, the first set of memory cells may be designated to an over-allocated portion of the memory array. That is, the first set of memory cells may be designated for write burst-mode operations within an over-allocated portion of the memory array. In this manner, the first set of memory cells can be written in response to commands and / or signaling received by the memory subsystem from the host (e.g., host system 120, etc.), the commands and / or signaling being processed by the memory subsystem (e.g., over-allocation component 113 and / or memory subsystem controller 115) and asserted by the circuitry residing on the memory subsystem according to the write burst operation described herein.

[0055] At operation 222, a second set of memory cells in the memory array can be designated for non-write burst mode operations. In some instances, the second set of memory cells includes free memory cells for writing data associated with non-write burst mode operations. In some embodiments, the second set of memory cells can be assigned to an over-allocation portion of the memory array. In some embodiments, both the first and second set of memory cells can be assigned to an over-allocation portion of the memory array. In this way, the first set of memory cells can be used by the memory subsystem (e.g., over-allocation memory management component 113 and / or memory subsystem controller 115) to perform write burst operations, and the second set of memory cells can be used by the memory subsystem to perform non-write burst operations.

[0056] At operation 223, a request to perform a specific non-write burst operation (e.g., one or more commands, one or more signals, etc.) can be identified, exceeding the number of memory cells available for the second set of memory cells for the non-write burst mode write operation. In some embodiments, memory access may exceed a specified number of memory cells allocated to the second set of memory cells in response to a write request from the host system (e.g., host system 120) processed by the memory subsystem. Therefore, method 220 may include operations for identifying when a specific request for a non-write burst operation exists that exceeds a specified number of memory cells from the second set of memory cells. In some prior methods, new blocks of memory cells or new numbers of memory cells may be made available and designated as non-write burst mode cells or as a portion of the second set of memory cells. In these prior methods, additional memory cells may be designated away from the user data area of ​​the memory array, which can reduce the resources available to users of the computing system.

[0057] At operation 224, a portion of the first set of memory cells may be designated as a Static Single-Level Cell (SLC) block for non-write burst mode write operations in response to a request. In some embodiments, method 220 may designate a portion of the first set of memory cells to a second set of memory cells, rather than designating a portion of the user data region of the memory array. In these embodiments, method 220 may include operations for designating a portion of the first set of memory cells as a static SLC block for use in the second set of memory cells. In this manner, non-write burst operation commands and / or signaling from the host (e.g., host system 120, etc.), processed by the memory subsystem, and asserted by circuitry residing on the memory subsystem are executed on the static SLC block initially designated for write burst operations within the first set of memory cells.

[0058] At operation 225, data associated with a specific non-write burst write operation can be written to a static SLC block. As described herein, method 220 may include operations for performing a non-write burst write operation on a static SLC block initially assigned to a first portion of the memory cells. In this way, additional memory cells from the user data region or user-allocated region of the memory array can maintain a specific number of memory cells (e.g., may contain at least a threshold number of free or open memory blocks), which can provide better performance compared to utilizing additional memory cells from the user data region.

[0059] In some embodiments, method 220 may include operations for performing media management operations involving data written to the memory array. In some embodiments, the media management operation may include obsolete item collection. As used herein, "obsolete item collection" generally refers to a media management operation that attempts to remove data that is no longer in use or can no longer be used. In some embodiments, obsolete item collection may include a foreground obsolete item collection operation. As used herein, "foreground obsolete item collection" generally refers to an obsolete item collection operation of data that is visible to a user or host. Method 220 may include operations for reassigning static SLC blocks back to a first set of memory cells for write burst mode operations when data associated with a particular non-burst write operation is erased during the execution of the media management operation. In this way, static SLC blocks can be reassigned back to the first set of memory cells for the execution of subsequent write burst operations.

[0060] In some embodiments, method 220 may include operations for assigning a dynamic SLC block from the first set of memory cells to a second set of memory cells when a static SLC block is assigned to a first set of memory cells. In some embodiments, the first set of memory cells may not contain any free static SLC blocks that can be assigned to the second set of memory cells. Therefore, a dynamic SLC block can be assigned from the first set of memory cells to the second set of memory cells. In these embodiments, method 220 may include operations for recording a count when a dynamic SLC block is not available from the first set of memory cells. The count may be stored as... Figure 1 The integers (e.g., binary, floating-point, or other integers) are located in the hardware associated with the over-allocation memory management component 113, local memory 119, and / or any other components of the memory subsystem 110 described herein. In some embodiments, the count may be stored in firmware executable by the hardware components of the memory subsystem. Furthermore, in these embodiments, method 220 may include operations to prevent the write burst buffer size from increasing in response to the record count.

[0061] In some embodiments, method 220 may include operations for reducing a count when a dynamic SLC block is unavailable from a first set of memory cells. In some embodiments, reducing the count may generally refer to reducing the amount of data that can be stored in a particular set of memory cells. In these embodiments, method 220 may include operations for releasing a dynamic SLC block from a write burst data block pool to a second set of memory cells and reducing the count in response to releasing the dynamic SLC block from the write burst data block pool. In some embodiments, the first set of memory cells may include a first set of free memory cells, and the second set of memory cells may include a second set of free memory cells.

[0062] In these embodiments, the third set of memory cells assigned to the write burst data block pool may be memory cells with write data (e.g., memory cells "occupied" by data). For example, the write burst data block pool may contain a set of memory cells including data written using write burst operations. In these embodiments, after a media management operation, dynamic SLC blocks from the write burst data block pool may be released (e.g., reallocated to different types of memory blocks and / or erased so that the blocks can be written), such as a discarded item collection operation or a similar operation of erasing and / or folding data stored in dynamic SLC blocks. In this way, memory cells that previously stored data from write burst operations can be allocated to a set of free cells to store non-write burst data from non-write burst operations. In these embodiments, memory cells may be assigned to a fourth set of memory cells including memory cells occupied by data written using non-write burst write operations. For example, the fourth set of memory cells may be referred to as a non-write burst data pool.

[0063] Figure 3 This is a flowchart corresponding to a method 330 for over-allocation memory management according to some embodiments of the present disclosure. Method 330 may be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 330 is performed by… Figure 1 The over-allocated memory management component 113 performs the process. Although shown in a specific sequence or order, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0064] As described herein, the over-allocation memory management component can be used to specify and reassign different memory cells within an over-allocation portion of a memory array to improve the utilization efficiency of both static SLC and dynamic SLC within the over-allocation portion. At operation 331, a group of memory cells of a NAND memory array can be specified for over-allocation. As described herein, the processor can specify a portion of the NAND memory array for over-allocation.

[0065] At operation 332, a first portion of the group of memory cells may be designated as an idle write burst block. In some embodiments, the first portion comprises a static single-level cell (SLC) block. As described herein, an idle write burst block may comprise unoccupied or open memory cells that can be designated for write burst operations. The first portion may comprise a static SLC block because some protocols may require write burst operations to be performed on or using a static SLC block. In some embodiments, the first portion may also comprise a dynamic SLC block, such that the first portion comprises a combination of static and dynamic SLC blocks.

[0066] At operation 333, the second portion of the group memory cell can be identified as a data write burst block having data stored from a write burst write operation. In some embodiments, method 330 may include operations for designating the second portion of the group memory cell as a data write burst block. In some embodiments, a data write burst block or write burst data block may be an occupied memory cell or a memory cell having data stored from a write burst operation. That is, a data write burst block can be designated as a data write burst block when data from a write burst operation is written to a data block. For example, a write burst operation may store write burst data to a specific free write burst block from the first portion, and the specific free write burst block may be designated as a data write burst block.

[0067] In operation 334, a third portion of the group memory cell can be designated as an idle non-write burst block. In some embodiments, the third portion may contain dynamic SLC blocks. As described herein, some protocols may not require the use of static SLC blocks or the performance of non-write burst operations on static SLC blocks. In these embodiments, the third portion of the group memory cell may not contain any static SLC blocks. Therefore, the third portion of the group memory cell may contain only dynamic SLC blocks. In some embodiments, an idle non-write burst block may contain memory cells that are not occupied or have no data. Because the third portion of the group memory cell is designated as an idle non-write burst block, the third portion of the group memory cell can be used by the host to perform non-write burst operations on the third portion of the group memory cell.

[0068] At operation 335, the fourth portion of the group memory cell can be identified as a data non-write burst block having data stored from a non-write burst write operation. In these embodiments, the data non-write burst block can be an occupied memory cell that has been used to store data from a non-write burst operation. Therefore, when an idle non-write burst block from the third portion is used to write data using a non-write burst operation, the idle non-write burst block can be designated as a portion of the fourth portion of the group memory cell.

[0069] At operation 336, a static SLC block from the first portion can be designated to a third portion that will be used as an idle non-write burst block. In some embodiments, the static SLC block from the first portion is an idle static SLC block. In this way, when a static SLC block from the first portion is designated to the third portion, the static SLC block may not contain data or may be occupied by data. In some instances, designating a static SLC block from the first portion to the third portion may include providing the host with an indication that the static SLC block will be used to store data associated with a non-write burst operation. In this way, the host can access the static SLC block in a manner similar to that of a dynamic SLC block within the third portion to perform a non-write burst operation on the static SLC block.

[0070] At operation 337, a non-write burst write operation can be performed by storing data associated with the non-write burst write operation using a designated static SLC block. As described herein, the memory subsystem can access the designated static SLC block in response to signaling received from the host or host system, similar to accessing a dynamic SLC block from a third part, and perform a non-write burst write operation on the designated static SLC block. In this manner, data associated with the non-write burst write operation can be stored on the designated static SLC block.

[0071] At operation 338, when a non-write burst write operation is performed, a static SLC block can be identified as part of the fourth portion. As described herein, a static SLC block can be identified as storing non-write burst data from a non-write burst write operation. In this way, method 330 can designate a static SLC block as part of the fourth portion. In some embodiments, the number of dynamic SLC blocks and static SLC blocks within the fourth portion can be monitored to ensure that static SLC blocks are reassigned to the first portion so that write burst operations requiring the use of static SLCs can access free static SLC blocks. In some instances, a count within the fourth portion can be monitored or registered to determine whether additional dynamic SLC blocks are designated to the third portion as free dynamic SLC blocks for non-write burst operations.

[0072] At operation 339, a static SLC block can be designated as part of the first part in response to the execution of a media management operation involving the removal of data associated with a non-write burst write operation. As described herein, a static SLC block can be designated to the first part when data associated with a non-write burst write operation is removed or erased from a static SLC block. Typically, blocks from the fourth part are designated to the third part to allow non-write burst write operations to be performed on the erased block; however, write burst write operations within the first part may require static SLC blocks. In some instances, dynamic SLC blocks from the first part can be designated to the third part when a static SLC block is designated back to the first part. In this way, a larger number of static SLC blocks can remain in the first part, where write burst operations may require static SLC blocks.

[0073] In some embodiments, method 330 may include operations for determining when a first portion does not contain dynamic SLC blocks and preventing static SLC blocks from being assigned from the first portion to a third portion that will be used as free non-write burst blocks. In some instances, the first portion may need to contain static SLC blocks when no additional dynamic SLC blocks exist within it. In this way, the number of dynamic and static SLC blocks assigned to the first portion can be monitored to ensure that static SLC blocks are not assigned to the third portion when the first portion does not contain additional dynamic SLC blocks. For example, in some embodiments, method 330 may include operations for recording a count of situations where it is determined that no dynamic SLC blocks are available in the first portion and releasing dynamic SLC blocks from the second portion to the third portion. In this way, dynamic SLC blocks with erased data from the second portion can be assigned to the third portion instead of being reassigned back to the first portion. This allows the third portion to continue to provide free memory cells for non-write burst write operations without impacting performance or opening up additional blocks for free non-write burst blocks.

[0074] In some embodiments, method 330 may include operations to reduce a data count in response to releasing a dynamic SLC block from the second portion. In some instances, reducing the data count may include performing memory management operations to erase data stored in a particular SLC block. For example, data stored in a dynamic SLC block from the second portion may be erased to allow the dynamic SLC block from the second portion to be assigned to either the first or third portion based on a count associated with the first portion and / or a count associated with the third portion. In this way, SLC blocks can be dynamically assigned or allocated to provide improved performance and reduce the number of memory cells assigned within an over-allocated portion of the memory array.

[0075] Figure 4This describes an example of over-allocation memory management for a group of memory cells 440 according to some embodiments of the present disclosure. Figure 4 A set of memory cells 440 is described, which can be divided into a user data area portion 441 and an over-allocation portion, wherein the over-allocation portion includes a dynamic over-allocation portion 442 and a static over-allocation portion 443.

[0076] As described herein, the excess allocation portion can be divided into a write burst operation portion 444 and a non-write burst operation portion 445. That is, a write burst write operation can be performed using memory cells within the write burst operation portion 444, and a non-write burst write operation can be performed using memory cells within the non-write burst operation portion 445. For example, the memory subsystem can perform a write burst write operation on memory cells within the write burst operation portion 445 in response to a signaling received from the host, and the host can perform a non-write burst write operation on memory cells within the non-write burst operation portion 445.

[0077] Figure 4 The first operation 448 is described below. In some embodiments, the first operation 448 may be performed by the over-allocation memory management component 113 as described herein. In some embodiments, the first operation 448 may include designating a static SLC block 446-1 from the write burst operation portion 444 to the non-write burst operation portion 445 as a static SLC block 446-2, as illustrated by the first arrow 447. In this manner, the static SLC block 446-1, previously designated as a portion of the write burst operation portion 444, is now designated as SLC block 446-2 as a portion of the non-write burst operation portion 445. In this manner, SLC block 446-2 can be used to store data associated with non-write burst write operations. When a non-write burst write operation writes data to SLC block 446-2, SLC block 446-2 can be designated as non-write burst data.

[0078] Figure 4 The second operation 449 is described below. In some embodiments, the second operation 449 may be performed by the over-allocation memory management component 113. In some embodiments, the second operation 449 may include designating the static SLC block 446-2 from the non-write burst operation portion 445 to the write burst operation portion 444, as illustrated by the second arrow 450. In the second operation 449, non-write burst data stored at the static SLC block 446-2 may be erased or removed by memory management operations (e.g., discarded item collection, folding, etc.). When the static SLC block 446-2 is designated from a data block to a free block, the static SLC block 446-2 may be designated from the non-write burst operation portion 445 to the write burst operation portion 444, as illustrated by the second arrow 450.

[0079] Figure 5 This section describes examples of over-allocation memory management for a group of memory units 551 according to some embodiments of the present disclosure. In some embodiments, the group of memory units 551 may be memory units designated for over-allocation. Figure 5 This describes the over-allocation operation as described herein. In some embodiments, the over-allocation operation may include dividing or designating the group of memory units 551 into multiple portions. For example, memory units 551 may be divided into a write burst data pool 552, a write burst free pool 553, a non-write burst data pool 554, and / or a non-write burst free pool 555.

[0080] As described herein, write burst data pool 552 may include memory cells containing occupied memory cells or memory cells containing stored data associated with a write burst operation. Additionally, write burst free pool 553 may include memory cells that are not occupied or do not contain data. Write burst free pool 553 may include memory cells designated for storing data associated with a write burst operation. Furthermore, non-write burst data pool 554 may include memory cells containing occupied or stored data associated with non-write burst operations. Moreover, non-write burst free pool 555 may include memory cells that are not occupied or do not contain data. Non-write burst free pool 555 may be designated for storing data associated with non-write burst operations.

[0081] Figure 5 The over-allocation operation involves, as illustrated by arrow 557, designating static SLC 556-1 from non-write burst data pool 554 to write burst free pool 553 as static SLC 556-2. In this operation, data stored by static SLC 556-1 within non-write burst data pool 554 can be erased via memory management operations, such as a discarded item collection operation. When data from static SLC 556-1 is erased, the processor can designate SLC 556-1 as SLC 556-2 within write burst free pool 553.

[0082] As described herein, assigning static SLC 556-2 to write burst free pool 553 results in dynamic SLC 558-1 being assigned from write burst free pool 553 to non-write burst data pool 554 to be assigned as SLC 558-2, as illustrated by arrow 559. In this manner, a memory cell assigned from non-write burst data pool 554 results in an additional memory cell being assigned to non-write burst free pool 555.

[0083] Figure 6This section describes examples of over-allocation memory management for a group of memory units 660 according to some embodiments of the present disclosure. In some embodiments, the group of memory units 660 may be memory units designated for over-allocation. Figure 6 This describes the over-allocation operation as described herein. In some embodiments, the over-allocation operation may include dividing or designating the group of memory units 660 into multiple portions. For example, memory units 660 may be divided into a write burst data pool 661, a write burst free pool 662, non-write burst data pools 663-1, and / or a non-write burst free pool 664.

[0084] As described herein, write burst data pool 661 may include memory cells containing occupied memory cells or memory cells containing stored data associated with a write burst operation. Additionally, write burst free pool 662 may include memory cells that are not occupied or do not contain data. Write burst free pool 662 may include memory cells designated for storing data associated with a write burst operation. Furthermore, non-write burst data pool 663-1 may include memory cells containing occupied or stored data associated with non-write burst operations. Moreover, non-write burst free pool 664 may include memory cells that are not occupied or do not contain data. Non-write burst free pool 664 may be designated for storing data associated with non-write burst operations.

[0085] Figure 6 The over-allocation operation involves determining that the non-write burst data pool 663-1 has fallen below a threshold of free non-write burst memory cells. As described herein, a new non-write burst data pool 663-2 can be opened to accommodate additional non-write burst requests from the host or host system. In some instances, when data from a dynamic SLC is erased or removed via memory management operations, the over-allocation operation may also include, or alternatively, assigning the dynamic SLC from the write burst data pool 661 to the non-write burst free pool 664. For example, data from dynamic SLC 665-1 may be erased or removed. In this example, dynamic SLC 665-1 may be assigned as 665-2 within the non-write burst free pool 664, instead of being assigned back to the write burst free pool 662. In this way, when non-write burst data operations exceed the non-write burst data pool 663-1, additional dynamic SLCs can be provided to the non-write burst free pool 664.

[0086] Figure 7 This is a block diagram of an example computer system 700 in which embodiments of this disclosure may operate. For example, Figure 7An example machine illustrating computer system 700 is described, within which a set of instructions is executable to cause said machine to perform any or more of the methods discussed herein. In some embodiments, computer system 700 may correspond to a host system (e.g., Figure 1 The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110), or may be used to perform controller operations (e.g., execute an operating system to perform operations corresponding to...). Figure 1 (Operation of the over-allocated memory management component 113). In an alternative embodiment, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The computer may operate as a server or client machine in a client-server network environment, as a peer-to-peer machine in a peer-to-peer (or distributed) network environment, or as a server or client machine in a cloud computing infrastructure or environment.

[0087] The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network device, server, network router, switch, or bridge, or any machine capable of executing a set of instructions (sequentially or otherwise) specifying actions to be taken by said machine. Furthermore, while a single machine is described, the term "machine" should also be considered to include any collection of machines that individually or collectively execute a set (or more) of instructions to perform any or more of the methods discussed herein.

[0088] The example computer system 700 includes a processing device 702, a main memory 704 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 706 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 718, which communicate with each other via a bus 730.

[0089] Processing device 702 represents one or more general-purpose processing devices, such as microprocessors, central processing units, or the like. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a processor implementing a combination of instruction sets. Processing device 702 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, or the like. Processing device 702 is configured to execute instructions 726 for performing the operations and steps discussed herein. Computer system 700 may further include a network interface device 708 for communication via network 720.

[0090] Data storage system 718 may include machine-readable storage medium 724 (also called computer-readable medium) on which one or more sets of instructions 726 or software embodying any or more of the methods or functions described herein are stored. During execution of instructions 726 by computer system 700, instructions 726 may also reside wholly or at least partially in main memory 704 and / or processing device 702, which also constitute machine-readable storage medium. Machine-readable storage medium 724, data storage system 718, and / or main memory 704 may correspond to... Figure 1 The memory subsystem 110.

[0091] In one embodiment, instruction 726 includes instructions for implementing a corresponding over-allocation memory management component (e.g., Figure 1 The machine-readable storage medium 724 is shown as a single medium in the exemplary embodiment, but the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions for machine execution and causing the machine to perform any or more of the methods of this disclosure. Therefore, the term "machine-readable storage medium" should be considered to include (but is not limited to) solid-state memory, optical media, and magnetic media.

[0092] Certain portions of the foregoing detailed description have been presented based on algorithms and symbolic representations of operations on data bits within computer memory. These algorithmic descriptions and representations are the most effective way for those skilled in the art of data processing to communicate the essence of their work to others skilled in the art. Algorithms herein are generally considered to be self-consistent sequences of operations that lead to desired results. These operations are those requiring physical manipulation of physical quantities. Typically, but not necessarily, these quantities take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. It has proven convenient to sometimes refer to these signals as bits, values, elements, symbols, characters, items, numbers, or similar terms, primarily for general reasons.

[0093] However, it should be remembered that all these and similar terms should be associated with appropriate physical quantities and are merely convenient labels applied to those quantities. This disclosure may relate to the operation and processes of a computer system or similar electronic computing device that manipulates and transforms data representing physical (electronic) quantities in the registers and memories of the computer system into physical quantities similarly represented in the computer system's memory or registers or other such information storage systems.

[0094] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specifically configured for its intended purpose, or it may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. This computer program may be stored in a computer-readable storage medium, such as (but not limited to) any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0095] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with the programs taught herein, or it may prove convenient to construct more specialized devices to perform the methods. The structures of various such systems will appear as described below. Furthermore, this disclosure is described without reference to any particular programming language. It will be understood that the teachings of this disclosure as described herein can be implemented using various programming languages.

[0096] This disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, the instructions being usable to program a computer system (or other electronic device) to perform processes according to this disclosure. The machine-readable medium includes any mechanism for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, the machine-readable (e.g., computer-readable) medium includes machine-readable (e.g., computer-readable) storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory devices, etc.

[0097] In the foregoing description, embodiments of the present disclosure have been described with reference to specific examples. It will be apparent that various modifications can be made to the present disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be considered illustrative rather than limiting.

Claims

1. A method (220) for managing excess allocation memory, comprising: The first set of memory cells (440) of the memory array is designated by the over-allocation component (113) for writing burst mode operations (444); The second group of memory cells (440) of the memory array is designated for non-write burst mode operation (445); The number of requests to perform a specific non-write burst operation exceeds the number of memory cells available for the second set of memory cells to perform the non-write burst mode operation (445). In response to the request, the over-allocation component (113) designates a portion of the first group of memory cells (440) as static single-level cell (SLC) blocks (446-1, 446-2) for the non-write burst mode operation; The data associated with the specific non-write burst operation is written to the static SLC block (446-1, 446-2); When the static SLC block is assigned to the first group of memory cells, the dynamic SLC block is assigned from the first group of memory cells to the second group of memory cells; Record the count when a dynamic SLC block cannot be obtained from the first group of memory cells; and Prevent the write burst buffer size from increasing in response to the recorded count.

2. The method according to claim 1, further comprising: Perform media management operations involving data written to the memory array; and When the data associated with the specific non-write burst operation is erased during the execution of the media management operation, the static SLC block is assigned back to the first set of memory cells used for the write burst mode operation.

3. The method of claim 1, further comprising reducing the count when a dynamic SLC block cannot be obtained from the first set of memory cells.

4. The method of claim 1, further comprising: Release the dynamic SLC blocks from the write burst data block pool (552, 661) to the second set of memory cells; and The count is reduced in response to releasing the dynamic SLC block from the write burst data block pool.

5. The method of claim 1, wherein the first set of memory cells includes free memory cells for writing data associated with the write burst mode operation, and the second set of memory cells includes free memory cells for writing data associated with the non-write burst mode operation.

6. A device for managing excess allocation memory, comprising: Memory array; and An over-allocation component (113), coupled to the memory array and configured to: A set of memory cells in the memory array is designated for over-allocation; The first portion of the group of memory cells is designated as an idle write burst block (553, 662), wherein the first portion includes a dynamic single-level cell (SLC) block (665-1) and a static SLC block (446-1, 446-2). The second portion of the group memory cell is designated as an idle non-write burst block (555, 664), wherein the second portion contains a dynamic SLC block (665-1); The static SLC block is designated from the first part to the second part, which will be used as an idle non-write burst block (555, 664); Perform a non-write burst operation using the specified static SLC blocks (446-1, 446-2); When the non-write burst operation exceeds the static SLC blocks (446-1, 446-2), the third portion of the memory array is opened as an idle non-write burst block (555, 664); and In response to the execution of a write burst refresh operation, an idle dynamic SLC block is assigned from the write burst data pool (552) to the second part.

7. The device of claim 6, wherein the second portion contains only dynamic SLC blocks before the static SLC block is designated from the first portion to the second portion.

8. The device of claim 6, wherein the over-allocation component is configured to designate the static SLC block from the second portion back to the first portion after performing a media management operation on the memory array.

9. The device of claim 8, wherein the over-allocation component is configured to assign a dynamic SLC block from the first portion to the second portion in response to assigning the static SLC block back to the first portion.

10. The device of claim 6, wherein the device is a smartphone and the memory array includes a number of four-level cells (QLCs) configured to use SLCs or three-level cells (TLCs) within the memory array to support asynchronous power loss (APL).

11. The device of claim 6, wherein the over-rationing component is configured to: Determine when the first part does not contain dynamic SLC blocks; and Prevent the static SLC block assigned to the idle non-write burst block from being designated as a discarded item collection source block.

12. A system (100, 700) for managing excess allocation memory, comprising: Multiple memory components arranged to form a stackable cross-grid array of interleaved NAND memory cells; and Processing devices (113, 117, 702), coupled to the plurality of memory components (704, 718), are configured to perform operations including the following: A set of memory cells of the NAND memory cell is designated for over-allocation; The first portion of the group of memory cells is designated as an idle write burst block (553, 662), wherein the first portion includes a static single-level cell (SLC) block (446-1, 446-2); The second portion of the group memory cell is identified as a data write burst block (552, 661) having data stored from the write burst write operation; The third portion of the group memory cell is designated as an idle non-write burst block (555, 664), wherein the third portion contains a dynamic SLC block (665-1); The fourth portion of the group memory cell is identified as a data non-write burst block (554, 663-1, 663-2) having data stored from non-write burst write operations; The static SLC blocks (446-1, 446-2) are designated from the first part to the third part, which will be used as idle non-write burst blocks (555, 664); A non-write burst write operation is performed using the specified static SLC blocks (446-1, 446-2) to store the data associated with the non-write burst write operation; When the non-write burst write operation is performed, the static SLC blocks (446-1, 446-2) are identified as part of the fourth part; In response to the execution of a media management operation involving the removal of the data associated with the non-write burst write operation, the static SLC block (446-1, 446-2) is designated as a portion of the first part; and Record the count of cases where it is determined that no dynamic SLC block is available in the first part.

13. The system of claim 12, wherein the media management operation is a front-end abandoned item collection operation.

14. The system of claim 13, wherein the processing device is configured to perform operations including: Determine when the first part does not contain dynamic SLC blocks; and Prevent the static SLC block from being designated from the first portion to the third portion, which will be used as an idle non-write burst block (555, 664).

15. The system of claim 12, wherein the processing means is configured to perform an operation including releasing a dynamic SLC block from the second portion to the third portion.

16. The system of claim 15, wherein the processing means is configured to perform an operation including reducing the data count in response to releasing the dynamic SLC block from the second portion.

17. The system of claim 12, wherein at least a portion of the NAND memory cell includes a four-level cell residing on a mobile phone or wearable device.

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