Voltage supply circuit, memory and method of operating a memory

Abstract

This disclosure provides a voltage supply circuit, a memory, and a method for operating the memory, relating to the field of memory technology. The voltage supply circuit includes: a first charge pump; a second charge pump; a first voltage terminal; a second voltage terminal; a first driving module for providing a first clock driving signal configuring a first target voltage; and a second driving module for providing a second clock driving signal configuring a second target voltage. In a first stage, the output terminals of both the first and second charge pumps are connected to the first voltage terminal, and the first and second charge pumps are connected in parallel to charge a first load to the first target voltage. In a second stage, the output terminal of the second charge pump is disconnected from the first voltage terminal and connected to the second voltage terminal, and the second charge pump charges a second load to the second target voltage. The technical solution of this disclosure can shorten the setup time of the first target voltage, thereby improving the read / write efficiency of the memory powered by this voltage supply circuit.

Description

Technical Field

[0001] This disclosure relates to the field of memory technology, and in particular to a power supply circuit, a memory, and a method of operating the memory. Background Technology

[0002] Flash memory is a commonly used data and program storage device. Flash memory requires boost voltage during programming and erasing operations, and this boost operation is achieved through a dedicated charge pump.

[0003] Specifically, when performing read, write, and erase operations, Flash memory uses the output voltage of the charge pump. Therefore, the speed at which the voltage is built up is closely related to the read and write speed that the Flash memory can achieve. In order to achieve a faster read and write frequency and save the time of read, write, and erase operations, it is necessary to shorten the build-up time of the charge pump output voltage.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] The purpose of this disclosure is to provide a power supply circuit, a memory, and a method for operating the memory, which at least partially overcomes the problem of slow read / write frequencies of memory in related technologies.

[0006] Other features and advantages of this disclosure will become apparent from the following detailed description, or may be learned in part from practice of this disclosure.

[0007] According to one aspect of this disclosure, a voltage supply circuit is provided, comprising: a first charge pump; a second charge pump; a first voltage terminal; a second voltage terminal; a first driving module for providing a first clock driving signal configuring a first target voltage; and a second driving module for providing a second clock driving signal configuring a second target voltage; wherein, in a first stage, the output terminals of both the first charge pump and the second charge pump are connected to the first voltage terminal, and the first charge pump and the second charge pump are connected in parallel to charge a first load to the first target voltage; in a second stage, the output terminal of the second charge pump is disconnected from the first voltage terminal and connected to the second voltage terminal, and the second charge pump charges a second load to the second target voltage.

[0008] In one embodiment of this disclosure, a selection switch is further included, the selection switch including a first terminal, a second terminal and a third terminal, the first terminal being connected to the first driving module, the third terminal being connected to the second driving module, and the second terminal being connected to the clock signal input terminal of the second charge pump, wherein, in the first stage, the selection switch is configured to be turned on between the first terminal and the second terminal, and in the second stage, the selection switch is configured to be turned on between the second terminal and the third terminal.

[0009] In one embodiment of this disclosure, it further includes: a first switch and a second switch, wherein the first switch is connected between the output terminal of the second charge pump and a first voltage terminal, and the second switch is connected between the output terminal of the second charge pump and the second voltage terminal.

[0010] In one embodiment of this disclosure, the device further includes a third switch, a fourth switch, and a fifth switch, wherein the fifth switch is connected between the output terminal of the second charge pump and a common node, the fourth switch is connected between the common node and the second voltage terminal, and the third switch is connected between the common node and the first voltage terminal. In a first stage, the fifth switch and the third switch are turned on, and the fourth switch is turned off; in a second stage, the fifth switch and the fourth switch are turned on, and the third switch is turned off.

[0011] In one embodiment of this disclosure, after the second stage, the fifth switch is turned off, the third and fourth switches are turned on, and the charge on the second load is transferred to the first load.

[0012] In one embodiment of this disclosure, the first load is a word line, and the second load is the control terminal of a switch on a bit line.

[0013] In one embodiment of this disclosure, the first driving module includes: a first comparator, a first input terminal of which is used to receive a first feedback voltage proportional to the voltage of the first voltage terminal, and a second input terminal of which is used to receive a first reference voltage; and a first clock generator, one end of which is connected to the output terminal of the first comparator, and the other end of which is connected to the clock signal input terminal of the first charge pump, wherein when the first feedback voltage is less than the first reference voltage, the first comparator outputs an activation signal to the first clock generator, and the first clock generator outputs the first clock driving signal to the first charge pump based on the activation signal.

[0014] In one embodiment of this disclosure, the second driving module includes: a second comparator, a first input terminal of which is used to receive a second feedback voltage proportional to the voltage of the second voltage terminal, and a second input terminal of which is used to receive a second reference voltage; and a second clock generator, one end of which is connected to the output terminal of the second comparator, and the other end of which is connected to the clock signal input terminal of the second charge pump, wherein when the second feedback voltage is less than the second reference voltage, the second comparator outputs an activation signal to the second clock generator, and the second clock generator outputs the second clock driving signal to the second charge pump based on the activation signal.

[0015] According to another aspect of this disclosure, a memory is provided, comprising: a memory cell array; word lines; bit lines; and a power supply circuit as described in any of the above technical solutions.

[0016] In one embodiment of this disclosure, it further includes: a sense amplifier; and a bit line switch disposed between the bit line and the sense amplifier, wherein the first voltage terminal is connected to the word line and the second voltage terminal is connected to the control terminal of the bit line switch.

[0017] According to another aspect of this disclosure, a method for operating a memory is provided, comprising: in a first stage, connecting the output terminal of a first charge pump and the output terminal of a second charge pump to a first voltage terminal, and a first driving module outputting a first clock driving signal to the first charge pump and the second charge pump connected in parallel to boost the voltage at the first voltage terminal; in a second stage, disconnecting the output terminal of the second charge pump from the first voltage terminal and connecting it to a second voltage terminal, and a second driving module outputting a second clock driving signal to the second charge pump to boost the voltage at the second voltage terminal.

[0018] The voltage supply circuit scheme provided by the embodiments of this disclosure multiplexes the original first charge pump that generates the first target voltage and the second charge pump that generates the second target voltage in the first stage, that is, the stage of generating the first target voltage. In other words, in the first stage, the first charge pump and the second charge pump are connected in parallel so that the output voltage of the first voltage terminal can quickly reach the first target voltage. Compared with the method of only using the first charge pump to make the voltage value of the first voltage terminal reach the first target voltage, the establishment time of the first target voltage can be shortened, which is beneficial to improving the read and write efficiency of the memory powered by the voltage supply circuit.

[0019] Furthermore, after the first voltage terminal reaches the first target voltage, the second charge pump is reconfigured to connect to the second voltage terminal so that the second voltage terminal outputs the second target voltage, thereby realizing the switching of the second charge pump from participating in establishing the first target voltage to establishing the second target voltage, thus ensuring the smooth execution of read and write operations on the memory.

[0020] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0021] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0022] Figure 1 A schematic block diagram of the memory in an embodiment of this disclosure is shown; Figure 2 A schematic diagram of the structure of the memory cell array in an embodiment of this disclosure is shown; Figure 3 This diagram shows a structural schematic of a voltage supply circuit according to an embodiment of the present disclosure; Figure 4 This diagram illustrates the structure of another voltage supply circuit in an embodiment of the present disclosure. Figure 5 This diagram shows a structural schematic of another voltage supply circuit according to an embodiment of the present disclosure. Figure 6 A schematic diagram showing a comparison of the voltage curves output by the voltage supply circuit in the related art and the voltage supply circuit in the embodiments of this disclosure is provided. Figure 7 This diagram illustrates a programming operation that uses a power supply circuit to perform incremental step pulses in an embodiment of this disclosure. Figure 8 This diagram illustrates a flash memory recovery operation performed using a power supply circuit in an embodiment of this disclosure. Figure 9 A flowchart illustrating an operation method of a memory according to an embodiment of this disclosure is shown.

[0023] in, Figures 1 to 8 The annotations in the accompanying drawings are explained as follows: 10 memory, 100 memory cell array, 102 controller, 104 word line decoder, 106 readout circuit, 108 bit line decoder, 110 power supply circuit, 20 memory cells, 302 seventh switch, 304 eighth switch, 306 bit line switch, 402 first charge pump, 404 second charge pump, OUT1 first output terminal, OUT2 first output terminal, 406 selection switch, 408 first clock generator, 410 first comparator, 412 second clock generator, 414 second comparator, S1 first switch, S2 second switch, S3 third switch, S4 fourth switch, S5 fifth switch, S6 sixth switch, Cload1 first load capacitor, Cload2 second load capacitor. Detailed Implementation

[0024] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0025] Furthermore, the accompanying drawings are merely illustrative of this disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0026] like Figure 1 As shown, memory 10 is electrically connected to an electronic device. Memory 10 can be an internal or external storage device of the electronic device. Memory 10 can be volatile or non-volatile memory. Volatile memory requires power to maintain data, and includes, for example, random access memory (RAM), dynamic random access memory (DRAM), and synchronous dynamic random access memory (SDRAM). Non-volatile memory can retain stored data even when power is off, and includes, for example, NAND flash memory, NOR flash memory, electrically erasable programmable ROM (EEPROM), phase-change random access memory (PCRAM), resistive random access memory (RRAM), and magnetoresistive random access memory (MRAM).

[0027] Specifically, the memory 10 includes a memory cell array 100, a controller 102, a word line decoder 104, a readout circuit 106, a bit line encoder 108, and a voltage supply circuit 110. The readout circuit 106 includes multiple sense amplifiers (SAs). The voltage supply circuit 110 is also known as an on-chip high-voltage generator. The memory cell array includes multiple blocks.

[0028] The following description uses NOR flash memory as an example to illustrate the voltage supply circuit 110 used in the NOR flash memory of this disclosure.

[0029] Figure 2 This is a schematic diagram of a block of a NOR flash memory cell array.

[0030] like Figure 2 As shown, a block of memory cell array comprises multiple memory cells, such as 20 memory cells arranged in 64 rows and n columns, with each row corresponding to a word line (WL). A memory cell is, for example, a transistor with a floating gate. The transistor includes a substrate, a source, a drain, and a control gate. The transistor has a programmed state and an erased state (unprogrammed state). A transistor in the programmed state has more electrons in its floating gate than a transistor in the erased state. The threshold voltage of a transistor in the programmed state is higher than the threshold voltage of a transistor in the erased state. A transistor in the programmed state stores "0", and a transistor in the erased state stores "1".

[0031] Furthermore, a bit represents the smallest unit of information stored in a computer, while a word represents the basic unit of data transfer and processing within the computer. The control gate of a transistor is connected to the word line, the drain of a transistor is connected to the bit line, and the source of a transistor is grounded or connected to the source line. The control gates of memory cells in the same row are connected to the same word line, and the drains of memory cells in the same column are connected to the same bit line. Bit lines are connected between sense amplifiers via switches, and bit lines are also connected to the voltage supply circuit via switches.

[0032] Typical operations of memory 10 include read operations, programming operations (also known as write operations), erase operations, and various verification operations.

[0033] During a read operation (or verification operation), the voltage supply circuit 110 provides a read voltage (or verification voltage) to the target word line, and the voltage provided by the voltage supply circuit 110 turns on the switch between the bit line and the sense amplifier. During an erase operation, the erase voltage provided by the voltage supply circuit 110 is provided to the substrate of the block. During a programming operation, the programming voltage provided by the voltage supply circuit 110 is applied to the target word line, and the programming enable voltage provided by the voltage supply circuit 110 is selectively provided to bit lines BL1-BLn.

[0034] like Figure 2 As shown, the storage matrix in flash memory is composed of multiple storage cells arranged in a row. Each storage cell 20 contains several storage elements, each storing one bit of binary code (0 or 1). Several storage cells together form a "word" (i.e., one information unit). The address decoder has n address input lines and 2n decoding output lines. Each decoding output line Wi is called a "word line," corresponding to a "word" in the storage matrix. Therefore, whenever a set of input addresses is given, only one output word line is selected by the decoder. This word line can find a corresponding "word" in the storage matrix and send the m bits of information from the word to the output buffer. Each data output line that reads information is also called a "bit line."

[0035] In related technologies, a first charge pump generates a first target voltage V1, which is applied to the word line through a switch. A second charge pump generates a second target voltage V2, which controls the switch that transmits voltage in the direction of the bit line. Since a separate charge pump is used to generate the corresponding voltages V1 and V2, when the load capacitance of the first voltage V1 and the second voltage V2 is large, the time for the voltage to build up and stabilize will be relatively long, which will affect the read and write speed of the memory.

[0036] like Figure 4 As shown, a voltage supply circuit according to an embodiment of the present disclosure includes: a first charge pump 402, a second charge pump 404, a first voltage terminal OUT1, a second voltage terminal OUT2, a first driving module, and a second driving module.

[0037] The first driving module is used to provide a first clock driving signal for configuring a first target voltage, and the second driving module is used to provide a second clock driving signal for configuring a second target voltage.

[0038] The first driving module outputs a first clock signal to drive the first charge pump 402 to output voltage, and the second driving module outputs a second clock signal to drive the second charge pump 404 to output voltage.

[0039] In NOR flash memory applications, the first target voltage is the gate voltage of the memory cell connected to the word line, which is the voltage supplied to the word line. The second target voltage is the drain voltage of the memory cell connected to the bit line, which is the voltage supplied to the bit line.

[0040] Specifically, when a high level is applied to the word line, the control memory cell and the bit line are connected. The bit line is used to read or write the saved state of the memory cell. Whether it is a read operation or a write operation for flash memory, the word line needs to output a high level. Therefore, in order to ensure read and write operations, the power supply process is divided into at least a first stage and a second stage, based on the strategy of first powering the word line to reach the first target voltage, that is, completing the charging operation first, and then powering the bit line, that is, performing the programming operation.

[0041] In the first stage, the output terminals of the first charge pump 402 and the second charge pump 404 are both connected to the first voltage terminal OUT1, and the first charge pump 402 and the second charge pump 404 are connected in parallel to charge the first load to the first target voltage.

[0042] Specifically, the first stage refers to the stage in which the voltage value of the first voltage terminal OUT1 reaches the first target voltage, and the first load is the memory cell connected to the word line.

[0043] In the second stage, the output terminal of the second charge pump 404 is disconnected from the first voltage terminal OUT1 and connected to the second voltage terminal OUT2, and the second charge pump 404 charges the second load to the second target voltage.

[0044] Specifically, the second stage refers to the stage in which the voltage value of the second voltage terminal OUT2 reaches the second target voltage, and the second load is the memory cell connected to the bit line.

[0045] In one embodiment of this disclosure, the first load is a word line and the second load is the control terminal of a bit line switch.

[0046] like Figure 3 As shown, the voltage supply circuit 110 is provided with a first voltage terminal for outputting a first target voltage V1 and a second voltage terminal for outputting a second target voltage V2. A seventh switch 302 is provided between the second voltage terminal and the word line WL. An eighth switch 304 is also provided between the second voltage terminal and the control terminal of the bit line switch 306. The seventh switch 302 and the eighth switch 304 can be power transistors capable of withstanding high voltage.

[0047] In addition, the first charge pump 402 and the second charge pump 404 can specifically be Dickson charge pumps.

[0048] In this embodiment, the original first charge pump 402, which generates the first target voltage, and the second charge pump 404, which generates the second target voltage, are multiplexed in the first stage, i.e., the stage of generating the first target voltage. In other words, in the first stage, the first charge pump 402 and the second charge pump 404 are connected in parallel so that the output voltage of the first voltage terminal OUT1 can quickly reach the first target voltage. Compared with the method of using only the first charge pump 402 to make the voltage value of the first voltage terminal OUT1 reach the first target voltage, the establishment time of the first target voltage can be shortened, which is beneficial to improving the read and write efficiency of the memory powered by this voltage supply circuit.

[0049] Furthermore, after the first voltage terminal OUT1 reaches the first target voltage, the second charge pump 404 is reconfigured to be connected to the second voltage terminal OUT2 so that the second voltage terminal OUT2 outputs the second target voltage, thereby realizing the switching of the second charge pump 404 from participating in establishing the first target voltage to establishing the second target voltage, thus ensuring the smooth execution of read and write operations on the memory.

[0050] like Figure 4 and Figure 5 As shown, in one embodiment of this disclosure, it further includes: a selection switch 406, which includes a first terminal A, a second terminal B and a third terminal C. The first terminal A is connected to the first driving module, the third terminal C is connected to the second driving module, and the second terminal B is connected to the clock signal input terminal of the second charge pump 404.

[0051] In the first stage, the first switch S1 selector switch 406 is configured to be connected between the first terminal A and the second terminal B, and in the second stage, the selector switch 406 is configured to be connected between the second terminal B and the third terminal C.

[0052] Specifically, the selector switch 406 can be a switching element such as a transistor or a MOSFET.

[0053] One implementation of the selector switch 406 is to receive a feedback signal from the first output terminal and, when the voltage value of the first output terminal is detected to have reached the first target voltage based on the feedback signal, perform a switching operation between different connection terminals.

[0054] Another way to implement the selector switch 406 is to determine the switching time based on experience. When the conduction time between the first terminal A and the second terminal B reaches the preset time, it is considered that the voltage value of the first output terminal has risen to the first target voltage. At this time, the switching operation between different connection terminals can be performed.

[0055] In this embodiment, by setting a selection switch 406, the switching of the selection switch 406 can be used to switch from the first driving module driving the first charge pump 402 and the second charge pump 404 simultaneously to the first driving module driving the first charge pump 402 and the second driving module driving the second charge pump 404. This achieves a reliable switch from establishing the first target voltage to establishing the second target voltage. After quickly reaching the first target voltage, the second voltage terminal OUT2 connected to the output terminal of the second voltage pump is quickly brought to the second target voltage based on the driving of the second voltage pump by the second driving module. This achieves a rapid switch from the first target voltage to the second target voltage.

[0056] Furthermore, those skilled in the art will understand that after the output terminal of the second charge pump 404 is disconnected from the first voltage terminal OUT1 and connected to the second voltage terminal OUT2, the first charge pump 402 continues to maintain the first voltage terminal OUT1 outputting the first target voltage.

[0057] In one embodiment of this disclosure, the device further includes a first switch S1 and a second switch S2, wherein the first switch S1 is connected between the output terminal of the second charge pump 404 and the first voltage terminal OUT1, and the second switch S2 is connected between the output terminal of the second charge pump 404 and the second voltage terminal OUT2.

[0058] like Figure 4 As shown, as one implementation of switching the output terminal of the second charge pump 404 between the first voltage terminal OUT1 and the second voltage terminal OUT2, by setting the first switch S1 and the second switch S2 to be closed alternately, when the first switch S1 is closed, the selector switch 406 is set to connect the first terminal and the second terminal accordingly, and when the second switch S2 is closed, the selector switch 406 is set to connect the first terminal and the third terminal accordingly, thereby realizing the alternating establishment of the first target voltage and the second target voltage. In the process of establishing the first target voltage, since the first charge pump 402 and the second charge pump 404 participate simultaneously, the time consumed in establishing the voltage can be shortened.

[0059] Those skilled in the art will understand that the first switch S1 and the second switch S2 can also be replaced by simply setting up a single switch with a single-pole double-throw function.

[0060] like Figure 5As shown, in one embodiment of this disclosure, it further includes: a third switch S3, a fourth switch S4, and a fifth switch S5, wherein the fifth switch S5 is connected between the output terminal of the second charge pump 404 and the common node, the fourth switch S4 is connected between the common node and the second voltage terminal OUT2, and the third switch S3 is connected between the common node and the first voltage terminal OUT1. In a first stage, the fifth switch S5 and the third switch S3 are turned on, and the fourth switch S4 is turned off; in a second stage, the fifth switch S5 and the fourth switch S4 are turned on, and the third switch S3 is turned off.

[0061] Among them, the common node is the common connection point of the third switch, the fourth switch and the fifth switch.

[0062] like Figure 5 As shown, the voltage supply circuit also includes a first load capacitor Cload1 and a second load capacitor Cload2. The first load capacitor Cload1 is set at the first voltage terminal OUT1, and the second load capacitor Cload2 is set at the second voltage terminal OUT2, so as to accumulate charge in the first load capacitor Cload1 and the second load capacitor Cload2 while outputting the corresponding target voltage to the word line and bit line.

[0063] Furthermore, in one embodiment of this disclosure, after the second stage, the fifth switch S5 is turned off, the third switch S3 and the fourth switch S4 are turned on, and the charge on the second load is transferred to the first load.

[0064] like Figure 5 As shown, as another implementation of the switching of the output terminal of the second charge pump 404 between the first voltage terminal OUT1 and the second voltage terminal OUT2, the switches involved in the switching control include a third switch, a fourth switch, and a fifth switch. The third switch S3 and the fifth switch S5 are turned on, and the fourth switch S4 is turned off. The first charge pump 402 and the second charge pump 404 are connected in parallel to charge the first load of the first voltage terminal OUT1. When the first target voltage V1 is reached, the fourth switch S4, the fifth switch S5, and the sixth switch S6 are turned on, and the third switch S3 is turned off. The second charge pump 404 charges the second load of the second voltage terminal OUT2. When the second target voltage V2 is reached, the third switch S3 and the fourth switch S4 are turned on, and the fifth switch S5 and the sixth switch S6 are turned off. The charge on the second load capacitor Cload2 is transferred to the first load capacitor Cload1. Then, the third switch S3 and the fifth switch S5 are turned on, and the fourth switch S4 is turned off. The first charge pump 402 and the second charge pump 404 are connected in parallel to charge the first load of the first voltage terminal OUT1, reaching the third target voltage V3.

[0065] In this embodiment, when the fifth switch is closed, the switching between the open and closed states of the third and fourth switches enables the conversion between two working states: the first charge pump 402 and the second charge pump 404 are connected in parallel and multiplexed, and the first charge pump 402 and the second charge pump 404 are powered separately. This allows for a rapid increase in word line voltage and bit line voltage, thereby improving read and write efficiency.

[0066] Furthermore, by setting a first load capacitor at the first voltage terminal OUT1 and a second load capacitor at the second terminal, charge is accumulated on the load capacitors while outputting voltage signals to the word lines and bit lines. When the voltage value output by the second charge pump 404 reaches the second target voltage, the third and fourth switches are turned on, and the fifth and sixth switches are turned off, thereby realizing charge sharing between the first and second load capacitors. When it is necessary to set the voltage of the first target voltage to a larger value, that is, when the output of the first voltage terminal OUT1 needs to be boosted, the boosting time can be shortened.

[0067] like Figure 6 As shown, the solid line represents the curve of the charge pump voltage output by the first charge pump in the related art, and the dashed line represents the curve of the charge pump voltage output by the voltage supply circuit used in the embodiments of this disclosure.

[0068] like Figure 5 and Figure 6 As shown, during the initial setup phase of the charge pump, the third switch S3 and the fifth switch S5 are turned on, and the fourth switch S4 is turned off. The first charge pump 1 and the second charge pump 2 are connected in parallel to charge the first load at the first voltage terminal OUT1. Compared with the time required to establish the first target voltage V1 in related technologies, this saves the setup time t2-t1. After the voltage at the first output terminal reaches V1, the fourth switch S4, the fifth switch S5, and the sixth switch S6 are turned on, and the third switch S3 is turned off. The second charge pump 404 charges the second load at the second voltage terminal OUT2. At this time, the first charge pump is used to maintain the V1 voltage, and the second charge pump is used to make the voltage at the second voltage terminal reach the second target voltage V2. During this process, It can perform read and write operations on the flash cell in the memory. At time t3, if the first voltage terminal OUT1 needs to output a larger third target voltage V3, at time t3, the third switch S3 and the fourth switch S4 are turned on, and the fifth switch S5 and the sixth switch S6 are turned off. The charge on the load capacitor Cload2 is transferred to the load capacitor Cload1 to achieve charge sharing. Then, the third switch S3 and the fifth switch S5 are turned on, and the fourth switch S4 is turned off. The first charge pump 402 and the second charge pump pump 2 are connected in parallel to charge the first load of the first voltage terminal OUT1 to reach the third target voltage V3. Compared with the voltage establishment time in related technologies, the time t5-t4 is saved.

[0069] like Figure 4 and Figure 5 As shown, in one embodiment of this disclosure, the first driving module includes a first comparator 410 and a first clock generator 408.

[0070] The first input terminal of the first comparator 410 is used to receive a first feedback voltage VFB1 that is proportional to the voltage of the first voltage terminal, and the second input terminal of the first comparator 410 is used to receive a first reference voltage VREF1. One end of the first clock generator 408 is connected to the output terminal of the first comparator 410, and the other end of the first clock generator 408 is connected to the clock signal input terminal of the first charge pump. When the first feedback voltage VFB1 is less than the first reference voltage VREF1, the first comparator 410 outputs an activation signal to the first clock generator 408, and the first clock generator 408 outputs a first clock drive signal to the first charge pump based on the activation signal.

[0071] The first feedback voltage VFB1 is proportional to the voltage at the first voltage terminal, and the first reference voltage VREF1 is proportional to the first target voltage.

[0072] like Figure 4 and Figure 5 As shown, in one embodiment of this disclosure, the second driving module includes a second clock generator 412.

[0073] The second comparator 414 has a first input terminal for receiving a second feedback voltage VFB2 proportional to the voltage of the second voltage terminal, and a second input terminal for receiving a second reference voltage VREF2. One end of the second clock generator 412 is connected to the output terminal of the second comparator 414, and the other end of the second clock generator 412 is connected to the clock signal input terminal of the second charge pump. When the second feedback voltage VFB2 is less than the second reference voltage VREF2, the second comparator 414 outputs an activation signal to the second clock generator 412, and the second clock generator 412 outputs a second clock drive signal to the second charge pump based on the activation signal.

[0074] The second feedback voltage VFB2 is proportional to the voltage at the second voltage terminal, and the second reference voltage VREF2 is proportional to the second target voltage.

[0075] In this embodiment, when the output voltage of the first charge pump reaches the first target voltage, the first comparator stops outputting the activation signal to the first clock generator, causing the first clock generator to stop outputting the first clock signal. When the first comparator detects that the output voltage of the first charge pump has dropped below the first target voltage, it outputs the first clock signal to the first charge pump again, causing the output voltage of the first charge pump to rise again. The comparator is also continuously operating during the setup process.

[0076] The output voltage regulation process of the second charge pump is similar to that of the first charge pump, and will not be described in detail here.

[0077] Specifically, the incremental step pulse program (ISSP) method is typically used to perform programming operations.

[0078] In one specific scenario of applying the voltage supply circuit of this disclosure to a memory, the voltage supply circuit further includes at least a third charge pump that provides an erase voltage and a fourth charge pump that provides a bit line voltage, and the programming process may include a charging phase, a programming phase and a programming verification phase.

[0079] Combination Figure 7 and Figure 2 As shown, during the charging phase, the first voltage terminal is connected to the selected word line, such as word line WL1. The selected word line is charged by the first charge pump and the second charge pump connected in parallel, and the programming pulse Vpgm1 is applied to the selected word line.

[0080] During the programming phase, the second charge pump disconnects from the first voltage terminal and establishes a connection with the second voltage terminal. The second voltage terminal is connected to the control terminal of the bit line switch between the bit line and the fourth charge pump. The second charge pump provides the turn-on voltage to the control terminal of the bit line switch, while the fourth charge pump provides the programming enable voltage to the bit line.

[0081] During the programming verification phase, the second charge pump is disconnected from the second voltage terminal and connected to the first voltage terminal. The selected word line is charged by the parallel connection of the first and second charge pumps, and the verification voltage Vver is applied to the selected word line. Afterward, the second charge pump is disconnected from the first voltage terminal and connected to the second voltage terminal, which is then connected to the control terminal of the bit line switch between the bit line and SA.

[0082] If the programming verification fails, the first and second charge pumps connected in parallel apply the programming pulse Vpgm2 to the selected word line.

[0083] Optionally, use Figure 5During the circuit operation, after verification, the third switch S3 and the fourth switch S4 are turned on, and the fifth switch S5 and the sixth switch S6 are turned off. The charge on the control terminal of the bit line switch between the bit line and SA is transferred to the selected word line. Then, the first charge pump and the second charge pump connected in parallel charge the selected word line until the voltage of the selected word line rises to Vpgm2.

[0084] Furthermore, according to the ISPP method, the programming voltage Vpgm can be increased incrementally by Vp during the repeated programming cycles.

[0085] In each programming cycle, whenever a programming voltage Vpgmi (i=1, 2, ..., N) is applied, verification is performed using a verification voltage Vver.

[0086] like Figure 8 As shown, in another specific scenario where the power supply circuit of this disclosure is applied to a memory, a recovery operation of NOR flash memory is performed.

[0087] Specifically, the memory cell includes an erase state and a programmable state. Because the memory cell does not have ideal data retention capabilities, over time, electrons in the floating gate of the programmed memory cell (which stores 0) will leak back to the substrate, causing a decrease in the threshold voltage and resulting in a 0→1 error. Therefore, verification and recovery are required at appropriate times.

[0088] During the verification operation, the first charge pump and the second charge pump are connected in parallel to charge the selected word line to the first verification voltage V81. Then the second charge pump is disconnected from the first voltage terminal and connected to the second voltage terminal. The second charge pump provides the turn-on voltage for the switch between the bit line and SA.

[0089] Then, the first charge pump and the second charge pump are connected in parallel again to charge the selected word line to the second verification voltage V82. After that, the second charge pump is disconnected from the first voltage terminal and connected to the second voltage terminal. The second charge pump provides the turn-on voltage for the switch between the bit line and SA.

[0090] The first verification voltage V81 is close to the voltage applied to the selected word line during the read operation, and the second verification voltage V82 is slightly less than the lower limit of the threshold voltage range corresponding to the programming state. The memory cell with the threshold voltage between the first verification voltage V81 and the second verification voltage V82 is the memory cell to be recovered, and then the memory cell to be recovered is used for storage operation.

[0091] A memory according to an embodiment of the present disclosure includes: a memory cell array; word lines; bit lines; and a power supply circuit as shown in any of the above embodiments.

[0092] In one embodiment of this disclosure, it further includes: a sense amplifier; and a third switch disposed between the bit line and the sense amplifier, wherein a first voltage terminal is connected to the word line and a second voltage terminal is connected to the control terminal of the switch on the bit line.

[0093] like Figure 9 As shown, a method for operating a memory according to an embodiment of the present disclosure includes: In step S902, in the first stage, the output terminal of the first charge pump and the output terminal of the second charge pump are connected to the first voltage terminal, and the first driving module outputs a first clock driving signal to the first charge pump and the second charge pump connected in parallel, so as to boost the voltage of the first voltage terminal.

[0094] In step S904, in the second stage, the output terminal of the second charge pump is disconnected from the first voltage terminal and connected to the second voltage terminal. The second drive module outputs a second clock drive signal to the second charge pump to boost the voltage at the second voltage terminal.

[0095] In this embodiment, by setting a selection switch and a switching switch between the first voltage terminal and the second voltage terminal, the first driving module is controlled to simultaneously output a first clock driving signal to the first charge pump and the second charge pump, and the output terminals of the first charge pump and the second charge pump are both connected to the first voltage terminal, so that the first charge pump and the second charge pump are connected in parallel in the first stage, so that the output charges of the first charge pump and the second charge pump are both concentrated at the first voltage terminal, thereby making the output voltage of the first voltage terminal quickly reach the first target voltage. Compared with the method of making the voltage value of the first voltage terminal reach the first target voltage only through the first charge pump, the establishment time of the first target voltage can be shortened, which is beneficial to improving the read and write efficiency of the memory powered by this voltage supply circuit.

[0096] Furthermore, after the first voltage terminal reaches the first target voltage, the second charge pump is reconfigured to connect to the second voltage terminal so that the second voltage terminal outputs the second target voltage, thereby realizing the switching of the second charge pump from participating in establishing the first target voltage to establishing the second target voltage, thus ensuring the smooth execution of read and write operations on the memory.

[0097] In one embodiment of this disclosure, when the output voltage required at the first voltage terminal rises from a first target voltage to a second target voltage, in response to the boost signal of the word line voltage, the third and fourth switches are controlled to turn on, and the fifth and sixth switches are turned off, so that the charge on the load capacitor Cload2 is transferred to the load capacitor Cload1. Then, the third and fifth switches are controlled to turn on, and the fourth switch is turned off. The first charge pump and the second charge pump are connected in parallel to charge the first load at the first voltage terminal to reach the third target voltage V3.

[0098] The voltage supply circuit and memory provided in this disclosure multiplex the original first charge pump that generates a first target voltage and the second charge pump that generates a second target voltage in the first stage, i.e., the stage of generating the first target voltage. That is, in the first stage, the first charge pump and the second charge pump are connected in parallel, so that the output voltage of the first voltage terminal quickly reaches the first target voltage. Compared with the method of using only the first charge pump to reach the first target voltage, the establishment time of the first target voltage can be shortened, thereby improving the read and write efficiency of the memory powered by this voltage supply circuit. Furthermore, after the first voltage terminal reaches the first target voltage, the second charge pump is reconfigured to be connected to the second voltage terminal so that the second voltage terminal outputs the second target voltage, thereby realizing the switching of the second charge pump from participating in the establishment of the first target voltage to establishing the second target voltage, thus ensuring the smooth execution of read and write operations on the memory.

[0099] In this application, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance; the term "multiple" refers to two or more unless otherwise expressly defined. The terms "install," "connect," "link," and "fix" should be interpreted broadly. For example, "connect" can mean a fixed connection, a detachable connection, or an integral connection; "link" can mean a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0100] In the description of this application, it should be understood that the terms "upper", "lower", "left", "right", "front", "rear", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or unit referred to must have a specific orientation or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0101] In the description of this specification, the terms "one embodiment," "some embodiments," "specific embodiment," etc., refer to a specific feature, structure, material, or characteristic described in connection with that embodiment or example, which is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0102] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

[0103] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A voltage supply circuit, characterized in that, include: First charge pump; Second charge pump; First voltage terminal; Second voltage terminal; The first driving module is used to provide a first clock driving signal for configuring the first target voltage; as well as The second drive module is used to provide a second clock drive signal for configuring the second target voltage; The selection switch includes a first terminal, a second terminal, and a third terminal. The first terminal is connected to the first driving module, the third terminal is connected to the second driving module, and the second terminal is connected to the clock signal input terminal of the second charge pump. In the first stage, the selection switch is configured to be connected between the first terminal and the second terminal, the output terminals of the first charge pump and the second charge pump are both connected to the first voltage terminal, and the first charge pump and the second charge pump are connected in parallel to charge the first load to the first target voltage. In the second stage, the selection switch is configured to be connected between the second terminal and the third terminal, the output terminal of the second charge pump is disconnected from the first voltage terminal and connected to the second voltage terminal, the second charge pump charges the second load to the second target voltage, the first load is the word line, and the second load is the control terminal of the switch on the bit line.

2. The voltage supply circuit according to claim 1, characterized in that, Also includes: A first switch and a second switch, wherein the first switch is connected between the output terminal of the second charge pump and the first voltage terminal, and the second switch is connected between the output terminal of the second charge pump and the second voltage terminal.

3. The voltage supply circuit according to claim 1, characterized in that, Also includes: The third, fourth, and fifth switches are configured such that the fifth switch is connected between the output terminal of the second charge pump and the common node, the fourth switch is connected between the common node and the second voltage terminal, and the third switch is connected between the common node and the first voltage terminal. In the first stage, the fifth and third switches are turned on, and the fourth switch is turned off. In the second stage, the fifth switch and the fourth switch are turned on, and the third switch is turned off.

4. The voltage supply circuit according to claim 3, characterized in that, After the second stage, the fifth switch is turned off, the third and fourth switches are turned on, and the charge on the second load is transferred to the first load.

5. The voltage supply circuit according to any one of claims 1-4, characterized in that, The first driving module includes: A first comparator, wherein a first input terminal of the first comparator is used to receive a first feedback voltage proportional to the voltage at the first voltage terminal, and a second input terminal of the first comparator is used to receive a first reference voltage; and A first clock generator, one end of which is connected to the output of the first comparator, and the other end of which is connected to the clock signal input of the first charge pump. When the first feedback voltage is less than the first reference voltage, the first comparator outputs an activation signal to the first clock generator, and the first clock generator outputs the first clock drive signal to the first charge pump based on the activation signal.

6. The voltage supply circuit according to any one of claims 1-4, characterized in that, The second drive module includes: A second comparator, wherein a first input terminal of the second comparator is used to receive a second feedback voltage proportional to the voltage at the second voltage terminal, and a second input terminal of the second comparator is used to receive a second reference voltage; and A second clock generator has one end connected to the output of the second comparator and the other end connected to the clock signal input of the second charge pump. Specifically, when the second feedback voltage is less than the second reference voltage, the second comparator outputs an activation signal to the second clock generator, and the second clock generator outputs the second clock drive signal to the second charge pump based on the activation signal.

7. A memory, characterized in that, include: Storage cell array; Word lines; Bit line; as well as The voltage supply circuit as described in any one of claims 1 to 6.

8. The memory according to claim 7, characterized in that, Also includes: Readout amplifier; And a bit line switch disposed between the bit line and the readout amplifier, wherein the first voltage terminal is connected to the word line and the second voltage terminal is connected to the control terminal of the bit line switch.

9. A method for operating a memory, characterized in that, The memory is the memory according to claim 7, comprising: In the first stage, the configuration selection switch is configured to enable conduction between the first terminal and the second terminal, the output terminal of the first charge pump and the output terminal of the second charge pump are connected to the first voltage terminal, and the first drive module outputs a first clock drive signal to the parallel first charge pump and the second charge pump to boost the first voltage terminal. In the second stage, the selection switch is configured to enable conduction between the second terminal and the third terminal. The output terminal of the second charge pump is disconnected from the first voltage terminal and connected to the second voltage terminal. The second drive module outputs a second clock drive signal to the second charge pump to boost the second voltage terminal. The first voltage terminal charges the first load, and the second voltage terminal charges the second load. The first load is a word line, and the second load is the control terminal of the switch on the bit line.

Images