Non-volatile memory device, memory system, and read method

Abstract

The present disclosure relates to a non-volatile memory device, a memory system, and a read method. Disclosed is a non-volatile memory device, a memory system including the same, and a read method of the memory system, wherein the non-volatile memory device includes: a first storage in which a base offset level for a read retry operation is stored; a second storage in which an additional offset level for the read retry operation is stored; and a voltage generator adapted to adjust a read voltage by using the base offset level and further by selectively using the additional offset level according to a read operation when the read retry operation is performed.

Description

Technical Field

[0001] Various embodiments of this disclosure relate to semiconductor design technology, and more particularly, to non-volatile memory devices, memory systems including thereof, and methods for reading said memory systems. Background Technology

[0002] Semiconductor memory devices can be divided into volatile memory devices such as DRAM and non-volatile memory devices such as flash memory. Volatile memory devices lose the data stored in them when power is off, while non-volatile memory devices retain the data stored in them even when power is off. In particular, flash memory has advantages such as high programming speed, low power consumption, and large data storage capacity, and is therefore widely used as a storage medium in computer systems and the like.

[0003] Flash memory includes an array of memory cells for storing data. The array of memory cells includes multiple memory blocks, each of which includes multiple pages, and each page includes multiple memory cells. Flash memory with this configuration performs erase operations on a block-by-block basis and write or read operations on a page-by-page basis. Summary of the Invention

[0004] Various embodiments of this disclosure relate to a non-volatile memory device that supports normal read operations and cache read operations, a memory system including the non-volatile memory device, and a method for reading the memory system.

[0005] According to embodiments of this disclosure, a non-volatile memory device may include: a first memory storing a base offset level for a read retry operation; a second memory storing an additional offset level for a read retry operation; and a voltage generator adapted to adjust a read voltage by using the base offset level and further by selectively using the additional offset level according to the read operation when performing the read retry operation.

[0006] A read operation can be a normal read operation or a cache read operation.

[0007] When the read operation is a normal read operation, the voltage generator can use the base offset level, and when the read operation is a cache read operation, the voltage generator can use both the base offset level and the additional offset level.

[0008] According to embodiments of this disclosure, a memory system may include: a control device adapted to generate command signals and address signals to control a read operation, determine whether the read operation has failed based on read data, and generate a read failure flag signal as a result of the determination; and a non-volatile memory device adapted to perform the read operation using a read voltage having a default level based on the command signals and the address signals, generate the read data according to the read operation, and adjust the read voltage by using different offset levels according to the read operation when retrying the read operation based on the read failure flag signal.

[0009] A read operation can be a normal read operation or a cache read operation.

[0010] When the read operation is a normal read operation, the non-volatile memory device can adjust the read voltage by using a base offset level, and when the read operation is a cache read operation, the read voltage can be adjusted by using a base offset level and an additional offset level.

[0011] According to embodiments of this disclosure, a method for reading a memory system may include the following steps: performing a read operation using a read voltage having a default level; determining whether the read operation has failed; when the read operation has failed and is a cache read operation, applying a base offset level and an additional offset level to the read voltage; and retrying the read operation using the read voltage.

[0012] The reading method may further include the following steps: when the reading operation has failed and it is a normal reading operation, the base offset level is applied to the reading voltage.

[0013] The steps for retrying a read operation may include performing a normal read operation as a retry of the read operation.

[0014] The reading method may also include the following steps: repeatedly applying the step and retrying the step by adjusting the base offset level while fixing the additional offset level.

[0015] According to embodiments of the present disclosure, a memory device may include: a memory cell array configured to store data therein; and control circuitry configured to perform a read retry operation on the memory cell array by adjusting a read voltage by a predetermined amount, wherein the predetermined amount is configured by a variable first amount when the read retry operation is caused by a normal read operation, and by both a first amount and a fixed second amount when the read retry operation is caused by a cache read operation. Attached Figure Description

[0016] Figure 1This is a block diagram illustrating a memory system according to an embodiment of the present disclosure.

[0017] Figure 2 This illustrates an embodiment according to the present disclosure. Figure 1 The block diagram shown is of a non-volatile memory device.

[0018] Figure 3 This illustrates an embodiment according to the present disclosure. Figure 2 The circuit diagram shows an example of a memory cell array.

[0019] Figure 4 This is a diagram that briefly illustrates a normal read operation according to an embodiment of the present disclosure.

[0020] Figure 5 This is a diagram that briefly illustrates a cache read operation according to an embodiment of the present disclosure.

[0021] Figure 6 This illustrates an embodiment according to the present disclosure. Figure 1 The flowchart shown is for the read operation of the memory system. Detailed Implementation

[0022] Various embodiments of this disclosure are described below with reference to the accompanying drawings in order to provide a detailed description of the disclosure so that those skilled in the art to which this disclosure pertain can readily implement its technical spirit.

[0023] It should be understood that when an element is referred to as "connected to" or "coupled to" another element, the element may be directly connected to or coupled to that other element, or electrically connected to or coupled to that other element in the case of one or more elements interposed therebetween. Furthermore, it should be understood that the terms "comprising," "including," "having," and "containing" as used in this specification do not exclude the presence of one or more other elements, but may further include or have one or more other elements, unless otherwise stated. Throughout the description of this specification, some components are described in the singular, but this disclosure is not limited thereto, and it should be understood that components may be formed in the plural.

[0024] Figure 1 This is a block diagram illustrating a memory system according to an embodiment of the present disclosure.

[0025] Reference Figure 1 The memory system may include a control device 100 and a non-volatile memory device 200.

[0026] The control device 100 can generate a command signal CMD and an address signal ADDR to control the read operation. The control device 100 can determine whether the read operation has failed based on the read data RDATA, and generate a read failure flag signal RFF corresponding to the determination result. For example, the control device 100 can determine whether the read operation has failed by using an error correction code (ECC).

[0027] The non-volatile memory device 200 can perform a read operation based on the command signal CMD using a read voltage RV with a default level, and generate read data RDATA according to the read operation. The non-volatile memory device 200 can retry the read operation based on the read failure flag signal RFF. In particular, when retrying the read operation, the non-volatile memory device 200 can adjust the read voltage RV according to the read operation by using either the basic offset level OL1 or both the basic offset level OL1 and the additional offset level OL2.

[0028] A read operation can be either a normal read operation or a cache read operation. The following describes normal read operations and cache read operations in detail (see [reference]). Figure 4 and 5 ).

[0029] Figure 2 This illustrates an embodiment according to the present disclosure. Figure 1 The block diagram of the non-volatile memory device 200 shown in the figure.

[0030] Reference Figure 2 The non-volatile memory device 200 may include control logic circuitry 210, voltage generator 220, first memory 230, second memory 240, decoder 250, memory cell array 260, page buffer 270, and data input / output circuitry 280.

[0031] The control logic circuit 210 can generate a voltage control signal VC and a row address signal RADD based on the command signal CMD, the address signal ADDR, and the read failure flag signal RFF.

[0032] When a read operation is performed, voltage generator 220 can generate a read voltage RV with a default level. When a read operation is retried (hereinafter referred to as a "read retry operation"), voltage generator 220 can adjust the read voltage RV based on a basic adjustment table or based on both a basic adjustment table and an additional adjustment table, depending on the read operation. For example, voltage generator 220 can adjust the read voltage RV based on the basic adjustment table when the read operation is a normal read operation, and adjust the read voltage RV based on both the basic adjustment table and the additional adjustment table when the read operation is a cache read operation.

[0033] The first memory 230 can store a base adjustment table. The base adjustment table can indicate a base offset level OL1 based on the number of read retry operations performed. The base offset level OL1 can have a positive or negative value. In the base adjustment table, the base offset level OL1 can be gradually changed according to the number of read retry operations.

[0034] The second memory 240 may store an additional adjustment table. The additional adjustment table may indicate a single additional offset level OL2 based on the read retry operation. The additional offset level OL2 may have a positive or negative value. In the additional adjustment table, the additional offset level OL2 may be fixed and independent of the number of retries in the read retry operation.

[0035] Decoder 250 can apply a read voltage RV to memory cell array 260 according to the row address signal RADD. For example, the read voltage RV can have a default level during a read operation and a different level during a read retry operation, i.e., an adjusted level. The adjusted level can be the sum of the default level and the base offset level OL1, or the sum of the default level, the base offset level OL1, and the additional offset level OL2.

[0036] Memory cell array 260 may include memory cells. Memory cell array 260 is connected to decoder 250 via row line RL and to page buffer 270 via bit line BL. Row line RL may include drain select line DSL, word lines WL1 to WL16, source select line SSL, and source line SL, which will be described below. Read voltage RV can be applied via word lines selected from word lines WL1 to WL16.

[0037] During a read operation, page buffer 270 can receive data from the memory cell of the selected page via bit line BL and output data to data input / output circuit 280 via data line DL. Page buffer 270 may include main buffer MB and cache buffer CB.

[0038] The data input / output circuit 280 can output read data RDATA to the control device 100 based on the data input to the data input / output circuit 280 via the data line DL.

[0039] Figure 3 This illustrates an embodiment according to the present disclosure. Figure 2 The circuit diagram of an example of the memory cell array 260 shown is shown.

[0040] Reference Figure 3The source select line SSL, word lines WL1 to WL16, and drain select line DSL, arranged in parallel to each other, can be connected to the memory cell array 260. For example, word lines WL1 to WL16 can be arranged in parallel to each other between the source select line SSL and the drain select line DSL.

[0041] More specifically, the memory cell array 260 may include strings connected between the first bit line BL1 to the nth bit line BLn and the source line SL. The first bit line BL1 to the nth bit line BLn may be individually connected to each string, and the source line SL may be collectively connected to each string. Since the strings may have the same configuration, the string ST connected to the first bit line BL1 is described in detail representatively.

[0042] A string ST may include a source selection transistor SST, memory cells F1 to F16, and a drain selection transistor DST connected in series between the source line SL and the first bit line BL1. A string ST may include at least one source selection transistor SST and at least one drain selection transistor DST, and may include more memory cells than the memory cells F1 to F16 shown in the figure.

[0043] The source of the source select transistor SST can be connected to the source line SL, and the drain of the drain select transistor DST can be connected to the first bit line BL1. Memory cells F1 to F16 can be connected in series between the source select transistor SST and the drain select transistor DST. The gates of the source select transistors included in different strings can be connected to the source select line SSL, the gates of the drain select transistors included in different strings can be connected to the drain select line DSL, and the gates of the memory cells F1 to F16 included in different strings can be connected to multiple word lines WL1 to WL16. A group of memory cells in different strings that are connected to the same word line can be called a physical page (PPG). Therefore, the memory cell array 260 can include as many physical pages as the number of word lines WL1 to WL16.

[0044] In the following text, see references Figures 4 to 6 The operation of a memory system according to an embodiment having the above configuration is described.

[0045] Figure 4 This is a diagram that briefly illustrates a normal read operation according to an embodiment of the present disclosure.

[0046] Reference Figure 4The control device 100 can generate a command signal CMD and an address signal ADDR corresponding to a normal read operation, and transmit the generated signals to the non-volatile memory device 200 (①). The non-volatile memory device 200 can read data DATA corresponding to a normal read operation from the memory cell array 260 based on the command signal CMD and the address signal ADDR, and store the data DATA in the main buffer MB (②). The data stored in the main buffer MB can be transferred to the cache buffer CB (③). When the data transferred to the cache buffer CB is transferred to the data input / output circuit 280, the data input / output circuit 280 can output the read data RDATA to the control device 100 (④).

[0047] A normal read operation may include a series of processes that read data DATA from memory cell array 260 in response to a command CMD and output read data RDATA corresponding to data DATA to control device 100.

[0048] Figure 5 This is a diagram that briefly illustrates a cache read operation according to an embodiment of the present disclosure.

[0049] Reference Figure 5 The control device 100 can generate a first command signal CMD and a first address signal ADDR (①) corresponding to a cache read operation. The non-volatile memory device 200 can read the first data DATA1 corresponding to the cache read operation from the memory cell array 260 based on the first command signal CMD and the first address signal ADDR, and store the first data DATA1 in the main buffer MB (②). When the first data stored in the main buffer MB is transferred to the cache buffer CB (③), the first cache read operation of the cache read operation can be fully executed.

[0050] Subsequently, the control device 100 can generate a second command signal CMD and a second address signal ADDR corresponding to the cache read operation (④). The non-volatile memory device 200 can read the second data DATA2 corresponding to the cache read operation from the memory cell array 260 based on the second command signal CMD and the second address signal ADDR, and store the second data DATA2 in the main buffer MB (⑤). At the same time, the first data stored in the cache buffer CB can be output to the control device 100 as read data RDATA through the data input / output circuit 280 (⑤). Subsequently, the second data stored in the main buffer MB can be stored in the cache buffer CB (⑥), and although not shown in the figure, the second data stored in the cache buffer CB can be output to the control device 100 as read data RDATA through the data input / output circuit 280.

[0051] A cache read operation may include a series of processes in response to a current command signal, reading current data (i.e., DATA2) from the memory cell array 260 and simultaneously outputting previous data (i.e., DATA1) corresponding to a previous command signal to the control device 100. Therefore, a cache read operation can achieve higher read performance than a normal read operation. On the other hand, while a cache read operation is efficient when command signals CMD associated with read operations are generated consecutively, it may be less efficient than a normal read operation when command signals CMD associated with read operations and command signals CMD associated with write operations are generated alternately. In short, this is because the previous data (i.e., DATA1) stored in the cache buffer CB is output to the control device 100, and the current data (i.e., DATA2) read from the memory cell array 260 is stored in the cache buffer CB. Therefore, when the current command signal generated by the control device 100 is not related to a read operation, a separate command signal must be generated before generating the current command signal to output the previous data (e.g., DATA1) stored in the cache buffer CB.

[0052] although Figure 5An example is shown in which, when a first cache read operation corresponding to the first command signal CMD and the first address signal ADDR is fully executed, the control device 100 generates the second command signal CMD and the second address signal ADDR, and transmits the generated signals to the non-volatile memory device 200. However, this disclosure is not limited to this, and the timing at which the control device 100 generates the second command signal CMD and the second address signal ADDR can be designed in various ways. For example, the control device 100 may generate the second command signal CMD and the second address signal ADDR at the time when the first data DATA1 is transferred from the main buffer MB to the cache buffer CB. Alternatively, the control device 100 may generate the second command signal CMD and the second address signal ADDR before the first data DATA1 is transferred from the main buffer MB to the cache buffer CB.

[0053] Figure 6 This illustrates an embodiment according to the present disclosure. Figure 1 The flowchart shows the reading method of the memory system.

[0054] First, the read method of the memory system according to the normal read operation is described.

[0055] Reference Figure 6 The control device 100 can generate a command signal CMD and an address signal ADDR corresponding to a normal read operation.

[0056] In operation S101, the non-volatile memory device 200 can generate a read voltage RV with a default level based on the command signal CMD and the address signal ADDR. In operation S103, the non-volatile memory device 200 can determine whether the current read operation is a normal read operation based on the command signal CMD and the address signal ADDR, and execute the normal read operation in operation S105. In operation S107, the non-volatile memory device 200 can output the read data RDATA corresponding to the normal read operation to the control device 100.

[0057] In operation S109, the control device 100 can determine whether a normal read operation has failed based on the read data RDATA, and generate a read failure flag signal RFF corresponding to the determination result. For example, the control device 100 can determine whether a normal read operation has failed by using an error correction code ECC.

[0058] Based on the read failure flag signal RFF, the non-volatile memory device 200 can retry a normal read operation when it fails. For example, in operation S111, the non-volatile memory device 200 can determine that the current read operation is a normal read operation and adjust the read voltage RV by using the base offset level OL1. In this case, the read voltage RV can have a sum level of the default level and the base offset level OL1. In operation S105, when a read retry operation is performed, the non-volatile memory device 200 can additionally perform a normal read operation.

[0059] When a normal read operation is performed, depending on whether the normal read operation has failed, the above operations S105, S107, S109, and S111 can be repeated at least once. For example, when operations S105, S107, S109, and S111 are repeated at least twice, the base offset level OL1 can be gradually increased or decreased. Since the base offset level OL1 based on the number of read retry operations is stored in the base adjustment table, the base offset level OL1 can be determined based on the base adjustment table.

[0060] Next, the read method of the memory system based on cache read operations is described.

[0061] Continue to refer to Figure 6 The control device 100 can generate a command signal CMD and an address signal ADDR corresponding to a cache read operation.

[0062] In operation S101, the non-volatile memory device 200 can generate a read voltage RV with a default level based on the command signal CMD and the address signal ADDR. In operation S103, the non-volatile memory device 200 can determine that the current read operation is a cache read operation based on the command signal CMD and the address signal ADDR, and execute the cache read operation in operation S113. In operation S115, the non-volatile memory device 200 can output the read data RDATA corresponding to the cache read operation to the control device 100.

[0063] In operation S117, the control device 100 can determine whether the cache read operation has failed based on the read data RDATA, and generate a read failure flag signal RFF corresponding to the determination result. For example, the control device 100 can determine whether the read operation has failed by using error correction code (ECC).

[0064] The non-volatile memory device 200 can retry a read operation based on a read failure flag signal RFF. For example, in operation S119, the non-volatile memory device 200 can determine that the current read operation is a cache read operation and adjust the read voltage RV by using a base offset level OL1 and an additional offset level OL2. In this case, the read voltage RV can have a default level, a sum of the base offset level OL1 and the additional offset level OL2. A cache read operation can be more susceptible to noise than a normal read operation by outputting data (e.g., DATA1) and simultaneously reading data (e.g., DATA2). For example, noise caused by ground bouncing may affect the data to be read (e.g., DATA2) because ground bouncing occurs when data (e.g., DATA1) is output and the source line SL and the ground power supply terminal are connected to each other when data (e.g., DATA2) is read. The additional offset level OL2 can be an offset level used to correct for this noise. In operation S121, the non-volatile memory device 200 can perform a normal read operation as a read retry operation based on the adjusted read voltage RV.

[0065] When a cache read operation is performed, the aforementioned operations S115, S117, S119, and S121 may be repeated at least once depending on whether the cache read operation has failed (i.e., whether a read retry operation has been performed). For example, when operations S115, S117, S119, and S121 are repeated at least twice, the base offset level OL1 may gradually increase or decrease, and the additional offset level OL2 may be fixed, i.e., remain unchanged. Since the base offset level OL1, based on the number of read retry operations performed, is stored in the base adjustment table, and the additional offset level OL2 is stored in the additional adjustment table, the base offset level OL1 can be determined based on the base adjustment table, and the additional offset level OL2 can be determined based on the additional adjustment table.

[0066] According to this embodiment, when performing a read retry operation based on a read failure, an offset level suitable for the cache read operation can be applied, and when performing a cache read operation, the base offset level used for normal read operations can be shared. Therefore, the capacity of the second memory can be reduced.

[0067] According to embodiments of this disclosure, the operational reliability of cache read operations can be improved, and the resource consumption of cache read operations can be minimized.

[0068] While this disclosure has been shown and described with reference to specific embodiments, the disclosed embodiments are provided for descriptive purposes and are not intended to be limiting. Furthermore, it should be noted that, as those skilled in the art will recognize from this disclosure, it can be implemented in various ways by substitutions, alterations, and modifications falling within the scope of the appended claims. Additionally, embodiments can be combined to form other embodiments.

[0069] Cross-references to related applications

[0070] This application claims priority to Korean Patent Application No. 10-2021-0082501, filed on June 24, 2021, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A non-volatile memory device, the non-volatile memory device comprising: A first storage device stores a base adjustment table indicating the base offset level. The second storage contains an additional adjustment table indicating the additional offset level; as well as A voltage generator is adapted to adjust the read voltage during a read retry operation by using the base offset level based on the base adjustment table according to a first read operation, or by using the base offset level and the additional offset level based on the base adjustment table and the additional adjustment table according to a second read operation.

2. The non-volatile memory device according to claim 1, wherein, The first read operation is a normal read operation, and the second read operation is a cache read operation.

3. The non-volatile memory device according to claim 1, wherein, The voltage generator uses the base offset level when the first read operation is a normal read operation, and uses both the base offset level and the additional offset level when the second read operation is a cache read operation.

4. The non-volatile memory device according to claim 1, further comprising: A memory cell array, the memory cell array comprising memory cells; as well as A decoder adapted to apply the read voltage to the memory cell array.

5. A memory system, the memory system comprising: Control device, the control device being adapted to: Generate command and address signals to control the first or second read operation. Based on the read data, determine whether the first read operation or the second read operation has failed, and A read failure flag signal is generated as the result of the determination. as well as A non-volatile memory device, said non-volatile memory device being adapted to: Based on the command signal and the address signal, the first read operation or the second read operation is performed using a read voltage with a default level. The read data is generated according to the first read operation or the second read operation, and When retrying the first read operation based on the read failure flag signal and the basic adjustment table, the read voltage is adjusted by using the basic offset level, or when retrying the second read operation based on the read failure flag signal, the basic adjustment table, and the additional adjustment table, the read voltage is adjusted by using the basic offset level and the additional offset level.

6. The memory system according to claim 5, wherein, The first read operation is a normal read operation, and the second read operation is a cache read operation.

7. The memory system according to claim 5, wherein, The basic adjustment table is shared when the first read operation or the second read operation is performed.

8. The memory system according to claim 5, wherein, The non-volatile memory device includes: A first storage device stores a base adjustment table that indicates the base offset level; A second storage device, wherein the additional adjustment table indicating the additional offset level is stored; and A voltage generator adapted to adjust the read voltage during a read retry operation by using the base offset level and further by selectively using the additional offset level according to the first read operation or the second read operation.

9. The memory system according to claim 8, wherein, The first read operation is a normal read operation, and the second read operation is a cache read operation.

10. The memory system according to claim 8, wherein, The voltage generator uses the base offset level when the first read operation is a normal read operation, and uses both the base offset level and the additional offset level when the second read operation is a cache read operation.

11. The memory system of claim 8, wherein the non-volatile memory device further comprises: A memory cell array, the memory cell array comprising memory cells; as well as A decoder adapted to apply the read voltage to the memory cell array.

12. A method for reading from a memory system, the method comprising the following steps: Perform the read operation using a read voltage with a default level; Determine whether the read operation has failed; When the read operation fails and the read operation is a cache read operation, a base offset level and an additional offset level are applied to the read voltage based on a base adjustment table for normal read operations and an additional adjustment table for cache read operations. as well as Retry the read operation using the read voltage.

13. The reading method according to claim 12, further comprising the following steps: When the read operation has failed and the read operation is a normal read operation, the base offset level is applied to the read voltage based on the base adjustment table.

14. The reading method according to claim 12, wherein, The steps for retrying the read operation include the following: performing a normal read operation as a step to retry the read operation.

15. The reading method according to claim 12, further comprising the following steps: The steps of applying and retrying are repeated by adjusting the base offset level while keeping the additional offset level fixed.

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