GaAs planar doped barrier diode and its fabrication method

Abstract

This invention relates to the field of diode technology and provides a GaAs planar doped barrier diode and its fabrication method. The method includes: epitaxially growing a first electrode contact layer, a first diffusion barrier layer, a first undoped layer, a p-type charge layer, a doped layer, a second undoped layer, a second diffusion barrier layer, an upper contact transition layer, and a second electrode contact layer layer layer on a semi-insulating substrate; placing the epitaxial wafer obtained after epitaxial growth into an annealing furnace, applying a preset forward voltage, and performing annealing treatment in a nitrogen atmosphere. This invention can prevent Si atoms from diffusing into the undoped layer and causing device failure, and prevent the doping concentration of the p-type material dopant element C from being passivated by H ions in the MOCVD reaction chamber.

Description

Technical Field

[0001] This invention belongs to the field of diode technology, and particularly relates to a GaAs planar doped barrier diode and its fabrication method. Background Technology

[0002] GaAs planar doped barrier diodes (PDBs) were first reported in 1980 by American scientists BJ Malik et al. They are majority carrier rectifiers with an n / i / p / i / n doping structure, where the p-layer is relatively thin and can be completely depleted at 0V, forming a triangular barrier distribution. The barrier height is proportional to the surface charge density of the p-layer, and the thickness of the two i-layers determines the shape of the barrier. Due to their low barrier height and structural asymmetry, GaAs planar doped barrier diodes are widely used in microwave and millimeter-wave detectors, detectors, and mixers.

[0003] However, actual material growth is often more difficult. In order to reduce ohmic contact resistance, the two sides of the material structure are designed as highly Si-doped N-type materials. When the doping concentration is high, Si atoms can easily diffuse into the undoped layer in the middle, causing device failure. The C doping element in the P-type material in the middle layer of the material structure is easily passivated by H ions in the MOCVD reaction chamber during epitaxial growth, which reduces its doping concentration and affects device performance.

[0004] In summary, all existing publicly available technologies have problems that can easily cause device failure and affect device performance. To address these issues, it is necessary to design and optimize the material structure and process. Summary of the Invention

[0005] In view of this, the present invention provides a GaAs planar doped barrier diode and its fabrication method, which can prevent Si atoms from diffusing into the undoped layer and causing device failure, and prevent the doping concentration of the doping element C in the P-type material from being passivated by H ions in the MOCVD reaction chamber.

[0006] The first aspect of this invention provides a method for fabricating a GaAs planar doped barrier diode, comprising: epitaxially growing a first electrode contact layer, a first diffusion barrier layer, a first undoped layer, a p-type charge layer, a doped layer, a second undoped layer, a second diffusion barrier layer, an upper contact transition layer, and a second electrode contact layer on a semi-insulating substrate; placing the epitaxial wafer obtained after epitaxial growth into an annealing furnace, applying a preset forward voltage, and performing annealing treatment in a nitrogen atmosphere.

[0007] Based on the first aspect, in some embodiments, the semi-insulating substrate is a 4-inch semi-insulating GaAs material with a crystal plane deflection angle of 0 degrees and a substrate thickness of 600um-650um.

[0008] Based on the first aspect, in some embodiments, the first electrode contact layer is a highly doped N-type GaAs material with a thickness of 0.8-1 μm, the doping element is Si, and the doping concentration is 4*10⁻⁶. 18 cm -3 Up to 6*10 18 cm -3 ;

[0009] The second electrode contact layer is made of highly doped N-type In. x Ga 1-x As material, doped with Si, with an In composition of 0.3-0.5, a thickness of 0.05-0.15 μm, and a doping concentration of 5*10⁻⁶. 18 cm -3 Up to 2*10 19 cm -3 .

[0010] Based on the first aspect, in some embodiments, the first diffusion barrier layer is made of N-type doped GaAs material, with Si as the dopant element, a thickness of 0.05µm-0.1µm, and a doping concentration of 3*10⁻⁶. 17 cm -3 Up to 5*10 17 cm -3 ;

[0011] The second diffusion barrier layer is made of N-type doped GaAs material, with Si as the dopant element, a thickness of 0.05µm-0.1µm, and a doping concentration of 5*10⁻⁶. 17 cm -3 Up to 8*10 17 cm -3 .

[0012] Based on the first aspect, in some embodiments, the first undoped layer is made of undoped type i GaAs material with a thickness of 0.3µm-0.5µm and an intrinsic concentration of less than 10. 15 cm -3 ;

[0013] The second undoped layer is made of undoped type i-GaAs material with a thickness of 5-10 nm and an intrinsic concentration of less than 10. 15 cm -3 .

[0014] Based on the first aspect, in some embodiments, the p-type charge layer is made of p-type doped GaAs material, with C as the dopant element, a thickness of 8nm-12nm, and a doping concentration of 10* 18 cm -3 Up to 3*10 18 cm -3 .

[0015] Based on the first aspect, in some embodiments, the doped layer is made of N-type GaAs material, with a thickness of 1nm-2nm and a concentration of 8e. 17 cm -3 -1e 18 cm -3 .

[0016] Based on the first aspect, in some embodiments, the upper contact transition layer is made of highly doped N-type GaAs material, with Si as the dopant element, a thickness of 0.2µm-0.4µm, and a doping concentration of 4*10⁻⁶. 18 cm -3 Up to 6e*10 18 cm -3 .

[0017] Based on the first aspect, in some embodiments, the annealing conditions are: annealing temperature of 500℃-600℃ and annealing time of 2min-5min.

[0018] A second aspect of the present invention provides a GaAs planar doped barrier diode, comprising: a semi-insulating substrate; a first electrode contact layer formed on the semi-insulating substrate; a first diffusion barrier layer formed on the first electrode contact layer; a first undoped layer formed on the first diffusion barrier layer; a p-type charge layer formed on the first undoped layer; a doped layer formed on the p-type charge layer; a second undoped layer formed on the doped layer; a second diffusion barrier layer formed on the second undoped layer; an upper contact transition layer formed on the upper contact transition layer; and a second electrode contact layer formed on the upper contact transition layer.

[0019] The advantages of this invention compared to the prior art are:

[0020] This invention involves epitaxially growing a first electrode contact layer, a first diffusion barrier layer, a first undoped layer, a p-type charge layer, a doped layer, a second undoped layer, a second diffusion barrier layer, an upper contact transition layer, and a second electrode contact layer on a semi-insulating substrate. The resulting epitaxial wafer is then placed in an annealing furnace under a preset forward voltage and annealed in a nitrogen atmosphere. This process prevents Si atoms from diffusing into the undoped layer and causing device failure, and also prevents the C dopant in the p-type material from being passivated by H ions in the MOCVD reaction chamber, thus preventing a decrease in the C doping concentration. The fabricated GaAs planar doped barrier diode was used as a chip in a directional detector to test its detection sensitivity. The measured sensitivity reached an advanced level in China, significantly optimizing device performance compared to traditional fabrication methods. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a flowchart illustrating the implementation of a GaAs planar doped barrier diode fabrication method provided in an embodiment of the present invention.

[0023] Figure 2 This is a schematic diagram of the electric field distribution of a GaAs planar doped barrier diode provided in an embodiment of the present invention;

[0024] Figure 3 This is an electrochemical CV test curve of C concentration for epitaxial wafers subjected to electro-annealing and conventional non-electro-annealing, provided in an embodiment of the present invention.

[0025] Figure 4 This is an IV test curve of the GaAs planar doped barrier diode provided in an embodiment of the present invention;

[0026] Figure 5 This is a test curve of the detection sensitivity of the directional detector provided in an embodiment of the present invention;

[0027] Figure 6 This is a schematic diagram of the structure of the GaAs planar doped barrier diode provided in an embodiment of the present invention;

[0028] Figure 7 This is a SIMS test curve of Si concentration with and without a diffusion barrier layer for a GaAs planar doped barrier diode provided in an embodiment of the present invention. Detailed Implementation

[0029] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of the invention. However, those skilled in the art will understand that the invention can be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods are omitted so as not to obscure the description of the invention with unnecessary detail.

[0030] Throughout the description of this patent, for the purpose of facilitating or simplifying the description of the invention, terms such as "upper," "lower," "left," and "right" that indicate orientation or positional relationship should be understood as being based on the orientation or positional relationship shown in the accompanying drawings, rather than indicating or implying the specific orientation, specific orientational structure, and operating sequence that the referred part or accessory must actually have, and therefore should not be construed as a limitation of the invention.

[0031] Furthermore, terms such as "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying their relative importance, nor should they be construed as indicating or implying the number of technical features indicated. In the description of this invention, "a plurality of" means three or more, unless otherwise explicitly specified.

[0032] To make the objectives, technical solutions, and advantages of the present invention clearer, specific embodiments will be described below in conjunction with the accompanying drawings.

[0033] GaAs planar doped barrier diodes have a positive temperature coefficient, resulting in better temperature stability than Schottky diodes. They also have a lower noise figure, leading to higher voltage sensitivity and dynamic range in microwave and millimeter-wave detection applications. Detection sensitivity is a crucial performance indicator for directional detectors. Reducing the turn-on voltage of GaAs planar doped barrier diodes can effectively improve the detection sensitivity of directional detectors. Achieving a lower turn-on voltage requires optimized material structure design to reduce barrier height and ohmic contact resistance. The inventors discovered that to reduce ohmic contact resistance, the two sides of the material structure are designed as highly Si-doped N-type materials. However, at high doping concentrations, Si atoms easily diffuse into the undoped middle layer, causing device failure. Furthermore, the C dopant element in the middle P-type material layer is easily passivated by H ions in the MOCVD reaction chamber during epitaxial growth, reducing its doping concentration and affecting device performance.

[0034] To address the aforementioned issues, this application provides a GaAs planar doped barrier diode and its fabrication method. The method involves epitaxially growing a first electrode contact layer, a first diffusion barrier layer, a first undoped layer, a p-type charge layer, a doped layer, a second undoped layer, a second diffusion barrier layer, an upper contact transition layer, and a second electrode contact layer layer layer on a semi-insulating substrate. The resulting epitaxial wafer is then annealed. This process prevents Si atoms from diffusing into the undoped layer and causing device failure, and also prevents the doping concentration of the p-type material dopant element C from being passivated by H ions in the MOCVD reaction chamber.

[0035] The following detailed description, in conjunction with the accompanying drawings, illustrates the above-mentioned GaAs planar doped barrier diode and its fabrication method.

[0036] See Figure 1 The diagram illustrates a flowchart of a GaAs planar doped barrier diode fabrication method provided by an embodiment of the present invention, detailed below:

[0037] Step 101: Epitaxially grow the first electrode contact layer, the first diffusion barrier layer, the first undoped layer, the p-type charge layer, the doped layer, the second undoped layer, the second diffusion barrier layer, the upper contact transition layer, and the second electrode contact layer layer layer by layer on the semi-insulating substrate.

[0038] In this step, GaAs planar doped barrier diode material layers are grown on a semi-insulating substrate. The semi-insulating substrate is used to isolate the device and prevent short-circuit effects between devices.

[0039] In one embodiment, layer-by-layer epitaxial growth was performed on a GaAs semi-insulating substrate using metal-organic chemical vapor deposition (MOCVD). The semi-insulating substrate can be a 4-inch semi-insulating GaAs material with a 0-degree offset and a thickness of 600-650 μm.

[0040] In one embodiment, the first electrode contact layer can be made of highly doped N-type GaAs material with a thickness of 0.8µm-1µm, and the doping element is Si with a doping concentration of 4*10⁻⁶. 18 cm -3 Up to 6*10 18 cm -3 .

[0041] In one embodiment, the material of the second electrode contact layer can be highly doped N-type In. x Ga 1-x As material, doped with Si, with an In composition of 0.3-0.5, a thickness of 0.05-0.15 μm, and a doping concentration of 5*10⁻⁶. 18 cm -3 Up to 2*10 19 cm -3 Among them, InGaAs has a narrower band gap, which can effectively reduce ohmic contact resistance.

[0042] In one embodiment, the first diffusion barrier layer can be made of N-type doped GaAs material, with Si as the dopant element, a thickness of 0.05µm-0.1µm, and a doping concentration of 3*10⁻⁶. 17 cm -3 Up to 5*10 17 cm -3 The second diffusion barrier layer can be made of N-type doped GaAs, with Si as the dopant element, a thickness of 0.05µm-0.1µm, and a doping concentration of 5*10⁻⁶. 17 cm -3 Up to 8*10 17 cm -3The first diffusion barrier layer can effectively prevent Si from diffusing from the first electrode contact layer to the first undoped layer; the second diffusion barrier layer can effectively prevent Si from diffusing from the second electrode contact layer to the second undoped layer.

[0043] In one embodiment, the p-type charge layer is made of p-type doped GaAs material, with C as the dopant element, a thickness of 8nm-12nm, and a doping concentration of 1*10⁻⁶. 18 cm -3 Up to 3*10 18 cm -3 The p-type charge layer is used to control the potential barrier of the diode by utilizing the surface charge density.

[0044] In one embodiment, the first undoped layer can be made of undoped type i GaAs material with a thickness of 0.3-0.5 μm and an intrinsic concentration of less than 1*10. 15 cm -3 The second undoped layer can be made of undoped type i GaAs material, with a thickness of 5-10 nm and an intrinsic concentration of less than 1*10⁻⁶. 15 cm -3 Since the thickness of the undoped layer directly affects the electric field strength, the thinner the layer, the greater the electric field strength. Therefore, two undoped layers with significantly different thicknesses create an asymmetric electric field distribution on both sides of the p-type charge layer (e.g., ...). Figure 2 E1 is less than E2, meaning E1 is the electric field strength of the second undoped layer and E2 is the electric field strength of the first undoped layer. Most of the electric field falls on the second undoped layer, which greatly reduces the potential barrier of the diode.

[0045] Step 102: Anneal the epitaxial wafer obtained after epitaxial growth.

[0046] In one embodiment, the epitaxial wafer obtained after epitaxial growth is placed in an annealing furnace, a preset positive voltage is applied, and annealing is performed in a nitrogen atmosphere at a temperature of 500°C-600°C for 2-5 minutes. By applying a positive voltage, the internal electric field of the material is counteracted, allowing hydrogen ions to rapidly diffuse to the outside of the material, thereby fully activating the C dopant element in the p-type charge layer. Figure 3 Electrochemical CV test curves of C concentration for electro-annealing and conventional non-electro-annealing show that the C concentration of electro-annealing is basically consistent with the design value and is significantly higher than that of non-electro-annealing, indicating that electro-annealing can completely activate the C element in the p layer.

[0047] In one embodiment, an annealed epitaxial wafer is fabricated into a chip for testing the IV test curves of a GaAs planar doped barrier diode (see [reference]). Figure 4Its turn-on voltage at 10uA decreased to 0.06V. When applied to a directional detector, the detection sensitivity was tested. Under conditions of 0dBm input power and a frequency range of 10MHz to 26.5GHz, the detection sensitivity of the GaAs planar doped barrier diode was 30-35mV / mW (see...). Figure 5 It has reached the advanced level in China.

[0048] The aforementioned method for fabricating GaAs planar doped barrier diodes involves epitaxially growing a first electrode contact layer, a first diffusion barrier layer, a first undoped layer, a p-type charge layer, a doped layer, a second undoped layer, a second diffusion barrier layer, an upper contact transition layer, and a second electrode contact layer layer layer on a semi-insulating substrate. The resulting epitaxial wafer is then annealed. This process prevents Si atoms from diffusing into the undoped layer and causing device failure, and also prevents the C dopant in the p-type material from being passivated by H ions in the MOCVD reaction chamber, thus reducing the C doping concentration. The resulting GaAs planar doped barrier diode was fabricated into a chip and applied to a directional detector for sensitivity testing. The measured sensitivity reached an advanced level in China, significantly optimizing device performance compared to traditional fabrication methods.

[0049] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0050] To make the technical problems to be solved, the technical solutions, and the beneficial effects of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present invention and are not intended to limit the present invention.

[0051] The following are device embodiments of the present invention. For details not described in detail, please refer to the corresponding method embodiments described above.

[0052] Figure 6 A schematic diagram of a GaAs planar doped barrier diode device according to an embodiment of the present invention is shown. For ease of explanation, only the parts related to the embodiment of the present invention are shown, and are described in detail below:

[0053] The aforementioned GaAs planar doped barrier diode includes a semi-insulating substrate 601 and a multilayer structure. The multilayer structure is formed on the semi-insulating substrate 601 and, from bottom to top, includes a first electrode contact layer 602, a first diffusion barrier layer 603, a first undoped layer 604, a p-type charge layer 605, a doped layer 606, a second undoped layer 607, a second diffusion barrier layer 608, an upper contact transition layer 609, and a second electrode contact layer 610.

[0054] Wherein, the first electrode contact layer 602 is an N+ contact layer; the first diffusion barrier layer 603 is an N- diffusion barrier layer; the first undoped layer 604 is a lower undoped layer; the doped layer 606 is a δ-doped layer; the second undoped layer 607 is an upper undoped layer; the second barrier diffusion layer 608 is an N- diffusion barrier layer; and the second electrode contact layer 610 is an N+ contact layer.

[0055] The first undoped layer 604 and the second undoped layer 607 are made of undoped i-type GaAs material. The thickness of the first undoped layer 604 is 0.3-0.5 μm, and the thickness of the second undoped layer 607 is 5-10 nm. The thicknesses of the two layers are different, forming an asymmetric structure. This structure creates an asymmetric electric field distribution, thereby significantly reducing the potential barrier of the diode.

[0056] See Figure 2 , Figure 2 This is a schematic diagram of the electric field distribution of a GaAs planar doped barrier diode in an embodiment of the present invention. The GaAs planar doped barrier diode with this structure forms an asymmetric electric field distribution, with most of the electric field falling on the thinner second undoped layer 607, thus significantly reducing the diode's barrier.

[0057] The first diffusion barrier layer 603 is an N-type doped GaAs material with Si as the dopant element, a thickness of 0.05-0.1 μm, and a doping concentration of 3*10⁻⁶. 17 cm -3 Up to 5*10 17 cm -3 The second diffusion barrier layer 608 is an N-type doped GaAs material with Si as the dopant element, a thickness of 0.05-0.1 μm, and a doping concentration of 5*10⁻⁶. 17 cm -3 Up to 8*10 17 cm -3 Its function is to reduce the concentration gradient and block the diffusion of Si in the outer contact layer.

[0058] See Figure 7 The figure shows the SIMS test curves of Si concentration with and without a diffusion barrier layer in the GaAs planar doped barrier diode in this embodiment of the invention. It can be seen from the figure that, in the range of 0.8-1.6 μm, at the same thickness value, the Si concentration tail with the diffusion barrier layer is significantly smaller than that without the diffusion barrier layer, indicating that inserting a diffusion barrier layer can effectively prevent Si from diffusing into the undoped layer.

[0059] The surface layer is the second electrode contact layer 610, which is a highly doped N-type In. x Ga 1-xAs material, doped with Si, with an In composition x of 0.3-0.5, a thickness of 0.05-0.15 μm, and a doping concentration of 5*10⁻⁶. 18 cm -3 Up to 2*10 19 cm -3 Highly doped and narrow bandgap In x Ga 1-x As materials are beneficial for achieving good ohmic contact and reducing series resistance.

[0060] The aforementioned GaAs planar doped barrier diode, which epitaxially grows a first electrode contact layer 602, a first diffusion barrier layer 603, a first undoped layer 604, a p-type charge layer 605, a doped layer 606, a second undoped layer 607, a second diffusion barrier layer 608, an upper contact transition layer 609, and a second electrode contact layer 610 on a semi-insulating substrate 601, can prevent Si atoms from diffusing into the undoped layer and causing device failure, and can also prevent the doping concentration of the p-type material dopant element C from being passivated by H ions in the MOCVD reaction chamber, thus reducing the doping concentration of the dopant element C, and has good performance.

[0061] In one embodiment, the GaAs planar doped barrier diode has a doping structure type of n+ / n- / i / p / δ / i / n- / n+.

[0062] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A method for fabricating a GaAs planar doped barrier diode, characterized in that, include: A first electrode contact layer, a first diffusion barrier layer, a first undoped layer, a p-type charge layer, a doped layer, a second undoped layer, a second diffusion barrier layer, an upper contact transition layer, and a second electrode contact layer are epitaxially grown layer by layer on a semi-insulating substrate. The first diffusion barrier layer is used to prevent Si from the first electrode contact layer from diffusing into the first undoped layer. The second diffusion barrier layer is used to prevent Si from the second electrode contact layer from diffusing into the second undoped layer. The thickness of the first undoped layer is 0.3 μm-0.5 μm, and the thickness of the second undoped layer is 5 nm-10 nm. An asymmetric electric field distribution is formed on both sides of the p-type charge layer. The epitaxial wafer obtained after epitaxial growth is placed in an annealing furnace and subjected to a preset positive voltage, and then annealed in a nitrogen atmosphere.

2. The method for fabricating a GaAs planar doped barrier diode as described in claim 1, characterized in that, The semi-insulating substrate is a 4-inch semi-insulating GaAs material with a crystal plane deflection angle of 0 degrees and a substrate thickness of 600um-650um.

3. The method for fabricating a GaAs planar doped barrier diode as described in claim 1, characterized in that, The first electrode contact layer is made of highly doped N-type GaAs material, with a thickness of 0.8µm-1µm, and the doping element is Si with a doping concentration of 4. 10 18 cm -3 up to 6 10 18 cm -3 ; The second electrode contact layer is made of highly doped N-type In. x Ga 1-x As material, doped with Si, In composition x is 0.3-0.5, thickness is 0.05um-0.15um, doping concentration is 5. 10 18 cm -3 to 2 10 19 cm -3 .

4. The method for fabricating a GaAs planar doped barrier diode as described in claim 1, characterized in that, The first diffusion barrier layer is made of N-type doped GaAs material, with Si as the dopant element, a thickness of 0.05µm-0.1µm, and a doping concentration of 3. 10 17 cm -3 up to 5 10 17 cm -3 ; The second diffusion barrier layer is made of N-type doped GaAs material, with Si as the dopant element, a thickness of 0.05µm-0.1µm, and a doping concentration of 5. 10 17 cm -3 up to 8 10 17 cm -3 .

5. The method for fabricating a GaAs planar doped barrier diode as described in claim 1, characterized in that, The first undoped layer is made of undoped type i GaAs material with an intrinsic concentration of less than 10. 15 cm -3 ; The second undoped layer is made of undoped type i GaAs material with an intrinsic concentration of less than 10. 15 cm -3 .

6. The method for fabricating a GaAs planar doped barrier diode as described in claim 1, characterized in that, The p-type charge layer is made of p-type doped GaAs material, with C as the dopant element, a thickness of 8 nm-12 nm, and a doping concentration of 10. 18 cm -3 up to 3 10 18 cm -3 .

7. The method for fabricating a GaAs planar doped barrier diode as described in claim 1, characterized in that, The doped layer is made of N-type GaAs material, with a thickness of 1nm-2nm and a concentration of 8. 10 17 cm -3 -10 18 cm -3 .

8. The method for fabricating a GaAs planar doped barrier diode as described in claim 1, characterized in that, The upper contact transition layer is made of highly doped N-type GaAs material, with Si as the dopant element, a thickness of 0.2µm-0.4µm, and a doping concentration of 4. 10 18 cm -3 up to 6 10 18 cm -3 .

9. The method for fabricating a GaAs planar doped barrier diode as described in claim 1, characterized in that, The annealing conditions are as follows: annealing temperature is 500℃-600℃, and annealing time is 2min-5min.

10. A GaAs planar doped barrier diode, characterized in that, include: Semi-insulating substrate; A first electrode contact layer is formed on the semi-insulating substrate; A first diffusion barrier layer is formed on the first electrode contact layer; A first undoped layer is formed on the first diffusion barrier layer; A p-type charge layer is formed on the first undoped layer; A doped layer is formed on the p-type charge layer; A second undoped layer is formed on the doped layer; the thickness of the first undoped layer is 0.3um-0.5um, and the thickness of the second undoped layer is 5nm-10nm, forming an asymmetric electric field distribution on both sides of the p-type charge layer; A second diffusion barrier layer is formed on the second undoped layer; An upper contact transition layer is formed on the upper contact transition layer; The second electrode contact layer is formed on the upper contact transition layer; The first diffusion barrier layer is used to prevent Si from diffusing from the first electrode contact layer to the first undoped layer; the second diffusion barrier layer is used to prevent Si from diffusing from the second electrode contact layer to the second undoped layer.

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