Methods for forming semiconductor structures
By epitaxially growing a second fin material layer with its top higher than the first fin in a semiconductor structure and forming an isolation wall at the junction, the problem of insufficient performance of fin field-effect transistors under reduced feature size is solved, and the channel mobility and stability are improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2021-06-24
- Publication Date
- 2026-04-03
AI Technical Summary
In the prior art, as the density and integration of semiconductor devices increase, the gate size of planar transistors is shortened, which weakens the channel current control capability and causes short-channel effect, affecting the electrical performance of semiconductor devices. The performance of fin field-effect transistors is difficult to improve as the feature size is further reduced.
During the semiconductor structure formation process, a second fin material layer is epitaxially grown on the substrate, with its top being higher than the first fin material layer, and an isolation wall is formed at the junction to avoid the growth of a poor-quality film layer. Fin patterning is performed to ensure the effective fin height and improve performance.
By increasing the height of the second fin material layer and forming an isolation wall at the junction, the fins are ensured to have sufficient height and mass, thereby improving the performance of the semiconductor structure, especially the channel mobility and negative bias temperature instability of fin field-effect transistors.
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Figure CN115527942B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a method for forming a semiconductor structure. Background Technology
[0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are evolving towards higher component density and higher integration. Transistors, as one of the basic semiconductor devices, are currently widely used. Therefore, as the density and integration of semiconductor devices increase, the gate size of planar transistors is becoming shorter and shorter. The ability of traditional planar transistors to control channel current weakens, resulting in short-channel effects, which increase leakage current and ultimately affect the electrical performance of semiconductor devices.
[0003] To better adapt to the shrinking feature size, semiconductor processes have gradually transitioned from planar MOSFETs to three-dimensional transistors with higher efficiency, such as FinFETs. However, with further reductions in feature size, it is difficult to further improve the performance of FinFETs. Summary of the Invention
[0004] The problem addressed by the embodiments of the present invention is to provide a method for forming a semiconductor structure, thereby improving the performance of the semiconductor structure.
[0005] To address the aforementioned problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a first device region for forming a first transistor and a second device region adjacent to the first device region for forming a second transistor, wherein a first fin material layer is further formed on the substrate in the first device region, and a hard mask layer is further formed on the first fin material layer; epitaxially growing a second fin material layer on the substrate of the second device region, wherein the top of the second fin material layer is higher than the top of the first fin material layer; removing the hard mask layer after forming the second fin material layer; epitaxially growing a third fin material layer on the first fin material layer after removing the hard mask layer, wherein the material of the third fin material layer is the same as the material of the first fin material layer; performing fin patterning processing, patterning the first fin material layer and the third fin material layer into a first fin protruding from the substrate of the first device region, and patterning the second fin material layer into a second fin protruding from the substrate of the second device region.
[0006] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:
[0007] In the formation method provided by this embodiment of the invention, a second fin material layer is epitaxially grown on the substrate of the second device region, and the top of the second fin material layer is higher than the top of the first fin material layer. Since the second fin material layer is obtained through epitaxial growth, a relatively thick epitaxially poor quality film layer is usually formed at the interface between the second fin material layer and the substrate. This poor quality film layer is difficult to serve as an effective fin for use as a channel in a semiconductor structure. In this embodiment of the invention, the height of the second fin material layer is moderately increased, which is beneficial to maintain sufficient height after fin patterning. Furthermore, in this embodiment of the invention, the first device region and the second device region are adjacent. At the junction of the first device region and the second device region, when the second fin material layer is epitaxially grown on the sidewall of the first fin material layer, a thicker epitaxial film layer with poor quality is easily formed at the junction of the first fin material layer and the second fin material layer. Thus, after fin patterning, when the formed second fin is close to the junction of the first device region and the second device region, the second fin can still have a sufficiently high effective fin, thereby improving the performance of the semiconductor structure.
[0008] In an alternative embodiment, an isolation wall is formed on the sidewall of the second fin material layer at the boundary between the first device region and the second device region. The isolation wall prevents the epitaxial growth of the third fin material layer on the sidewall of the second fin material layer, thereby avoiding the growth of a thicker, lower-quality film layer on the sidewall of the second fin material layer as much as possible. This facilitates the formation of a higher-quality third fin material layer, thereby improving the quality of the first fin and thus enhancing the performance of the semiconductor structure. Attached Figure Description
[0009] Figures 1 to 5 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.
[0010] Figures 6 to 15 This is a schematic diagram of the structure corresponding to each step in one embodiment of the method for forming a semiconductor structure of the present invention;
[0011] Figures 16 to 19 This is a schematic diagram of the structure corresponding to each step in another embodiment of the method for forming the semiconductor structure of the present invention. Detailed Implementation
[0012] The performance of semiconductor structures still needs improvement. This paper analyzes the reasons why the performance of semiconductor structures still needs improvement, using one semiconductor structure formation method as an example.
[0013] Figures 1 to 5 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.
[0014] refer to Figure 1 A substrate 10 is provided, the substrate 10 including a first device region 10B for forming a first transistor and a second device region 10A for forming a second transistor and adjacent to the first device region 10B. In the first device region 10B, a first fin material layer 21 is also formed on the substrate 10, and a hard mask layer 15 is also formed on the first fin material layer 21.
[0015] refer to Figure 2 Using the hard mask layer 15 as a mask, a buffer layer 24 is epitaxially grown on the substrate 10 of the second device region 10A; a second fin material layer 22 is epitaxially grown on the buffer layer 24, wherein the material of the buffer layer 24 is Si. 1-x M x The material of the second fin material layer 22 is Si. 1-y M y And x is less than y, where M represents a non-silicon element.
[0016] When the second fin material layer 22 is epitaxially grown on the substrate 10, a thicker epitaxial layer with poor quality is easily formed at the junction of the substrate 10 and the second fin material layer 22. The poor quality film layer is difficult to serve as an effective fin to provide a channel for the semiconductor structure.
[0017] Because the concentration gradient between the M element concentration in the second fin material layer 22 and the M element concentration in the substrate 10 is large, the buffer layer 24 is used to alleviate this large concentration gradient. Therefore, the M element concentration in the buffer layer 24 needs to be lower than the M element concentration in the second fin material layer 22. Consequently, the epitaxial quality of the buffer layer 24 is also poor, and after subsequent fin patterning processing, the buffer layer 24 cannot be used as an effective fin. The effective fin is used to provide channels for the semiconductor structure.
[0018] refer to Figure 3 Using the top of the first fin material layer 21 as the etching stop layer, the second fin material layer 22 and the hard mask layer 15 are planarized, the hard mask layer 15 is removed, and the remaining second fin material layer 22 is flush with the top of the first fin material layer 21.
[0019] refer to Figure 4 The fins are then patterned, with the first fin material layer 21 patterned as the first fin 31, and the second fin material layer 22 and the buffer layer 24 patterned as the second fin 32.
[0020] refer to Figure 5An isolation layer 16 is formed on the substrate 10, the isolation layer 16 covering part of the sidewalls of the first fin 31 and the second fin 32, and the top of the isolation layer 16 is higher than or flush with the top of the buffer layer 24.
[0021] Because the buffer layer 24 is relatively thick, the effective fin height in the second fin 32 is correspondingly smaller, making it difficult for the second fin 32 to have a sufficiently high effective fin. Furthermore, since the first device region 10B and the second device region 10A are adjacent, at the boundary between the first device region 10B and the second device region 10A, when the second fin material layer 22 is also epitaxially grown on the sidewall of the first fin material layer 21, a thicker epitaxial layer with poor quality is easily formed at the boundary between the first fin material layer 21 and the second fin material layer 22. At the same time, the buffer layer 24 is also epitaxially grown on the sidewall of the first fin material layer 21. Therefore, after fin patterning, when the formed second fin 32 is close to the boundary between the first device region 10B and the second device region 10A, it is even more difficult for the second fin 32 to have a sufficiently high effective fin, thereby affecting the performance of the semiconductor structure.
[0022] To address the aforementioned technical problem, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a first device region for forming a first transistor and a second device region adjacent to the first device region for forming a second transistor, wherein a first fin material layer is further formed on the substrate in the first device region, and a hard mask layer is further formed on the first fin material layer; epitaxially growing a second fin material layer on the substrate of the second device region, wherein the top of the second fin material layer is higher than the top of the first fin material layer; removing the hard mask layer after forming the second fin material layer; epitaxially growing a third fin material layer on the first fin material layer after removing the hard mask layer, wherein the material of the third fin material layer is the same as the material of the first fin material layer; and performing fin patterning processing, patterning the first fin material layer and the third fin material layer into a first fin protruding from the substrate of the first device region, and patterning the second fin material layer into a second fin protruding from the substrate of the second device region.
[0023] In the formation method provided by this embodiment of the invention, a second fin material layer is epitaxially grown on the substrate of the second device region, and the top of the second fin material layer is higher than the top of the first fin material layer. Since the second fin material layer is obtained through epitaxial growth, a relatively thick epitaxially poor quality film layer is usually formed at the interface between the second fin material layer and the substrate. This poor quality film layer is difficult to serve as an effective fin for use as a channel in a semiconductor structure. In this embodiment of the invention, the height of the second fin material layer is moderately increased, which is beneficial to maintain sufficient height after fin patterning. Furthermore, in this embodiment of the invention, the first device region and the second device region are adjacent. At the junction of the first device region and the second device region, when the second fin material layer is epitaxially grown on the sidewall of the first fin material layer, a thicker epitaxial film layer with poor quality is easily formed at the junction of the first fin material layer and the second fin material layer. Thus, after fin patterning, when the formed second fin is close to the junction of the first device region and the second device region, the second fin can still have a sufficiently high effective fin, thereby improving the performance of the semiconductor structure.
[0024] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
[0025] Figures 6 to 15 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.
[0026] Reference Figures 6 to 8 A substrate 100 is provided, the substrate 100 including a first device region 100B for forming a first transistor and a second device region 100A for forming a second transistor and adjacent to the first device region 100B. In the first device region 100B, a first fin material layer 210 (e.g., ...) is also formed on the substrate 100. Figure 8 As shown), a hard mask layer 150 is also formed on the first fin material layer 210.
[0027] The substrate 100 provides the basis for the process operation of forming the semiconductor structure. The semiconductor structure includes a finned field-effect transistor.
[0028] In this embodiment, the substrate 100 is made of silicon. In other embodiments, the substrate may also be made of germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide, or other materials. The substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates. The substrate 101 may be made of a material suitable for process requirements or easy to integrate.
[0029] In this embodiment, the substrate 100 includes a first device region 100B for forming a first transistor and a second device region 100A for forming a second transistor. The first transistor and the second transistor have different channel conductivity types, including N-type and P-type. As an example, the first transistor is an NMOS transistor and the second transistor is a PMOS transistor. In other embodiments, the first transistor and the second transistor may have the same channel conductivity type.
[0030] In this embodiment, the channel materials of the first transistor and the second transistor are different. By using different channel materials, the respective performance requirements of the first transistor and the second transistor are met.
[0031] In this embodiment, taking a fin field-effect transistor as an example, a first fin material layer 210 is also formed on the substrate 100 in the first device region 100B.
[0032] In this embodiment, the material of the first fin material layer 210 includes silicon, germanium, silicon germanide, or group III-V semiconductor materials.
[0033] In this embodiment, the first fin material layer 210 and the substrate 100 are integrally formed. In other embodiments, the first fin material layer may also be a semiconductor layer epitaxially grown on the substrate, thereby achieving precise control over the height of the first fin material layer.
[0034] In this embodiment, the material of the first fin material layer 210 is the same as the material of the substrate 100, and the material of the first fin material layer 210 is silicon. In other embodiments, the material of the first fin material layer may be different from the material of the substrate to meet the material requirements of the first fin material layer.
[0035] The hard mask layer 150 is used to protect the top of the first fin material layer 210 during the subsequent formation of the second fin material layer. Moreover, during the subsequent epitaxial growth of the second fin material layer, the barrier effect of the hard mask layer 150 helps to prevent the second fin material layer from epitaxially growing on the top of the first fin material layer 210.
[0036] In this embodiment, the hard mask layer 150 is made of one or more of silicon oxide and silicon nitride, meaning the hard mask layer 150 can be a single-layer structure or a multilayer structure. As an example, the hard mask layer 150 is made of silicon nitride, meaning the hard mask layer 150 is a single-layer structure.
[0037] Specifically, refer to Figure 6Before forming the first fin material layer 210 and the hard mask layer 150, the method further includes: forming a first initial fin material layer 110 covering the first device region 100B and the second device region 100A on the substrate 100, and a hard mask material layer 120 is also formed on the first initial fin material layer 110.
[0038] The first initial fin material layer 110 is used to form the first fin material layer 210, and the hard mask material layer 120 is used to form the hard mask layer 150.
[0039] In this embodiment, the material of the first initial fin material layer 110 is silicon, which is used to directly form the first fin material layer 210; the material of the hard mask material layer 120 is silicon nitride, which is used to directly form the hard mask layer 150.
[0040] In this embodiment, the first initial fin material layer 110 and the substrate 100 are an integral structure.
[0041] In this embodiment, the step of forming the hard mask layer 150 includes: forming a pattern transfer layer 180 on the hard mask material layer 120, the pattern transfer layer 180 having an opening 181 exposing the second device region 100A.
[0042] The pattern transfer layer 180 is used to transfer patterns to form a hard mask layer 150 that exposes the second device region 100A.
[0043] The pattern transfer layer 180 includes a planarization layer 130, an anti-reflective coating 140 on the planarization layer 310, and a photoresist layer 170 on the anti-reflective coating 140.
[0044] In this embodiment, the planarization layer 130 is made of spin-on carbon (SOC). Spin-on carbon is formed by a spin coating process, which has a low processing cost; moreover, by using spin-on carbon, the flatness of the top surface of the planarization layer 130 can be improved.
[0045] In this embodiment, the anti-reflective coating 140 is made of Si-ARC (silicon-containing anti-reflective coating) material.
[0046] refer to Figure 7 Using the pattern transfer layer 180 as a mask, the hard mask material layer 120 located in the second device region 100A is removed, and the hard mask material layer 120 located in the first device region 100B is retained as the hard mask layer 150.
[0047] Specifically, using the photoresist layer 170 as a mask, the anti-reflective coating 140 and planarization layer 130 located in the second device region 100A are removed, exposing the hard mask material layer 120 located in the second device region 100A; the exposed hard mask material layer 120 of the second device region 100A is removed, and the hard mask material layer 120 located in the first device region 100B is retained as the hard mask layer 150.
[0048] In this embodiment, after forming the hard mask layer 150, the method further includes: removing the remaining planarization layer 130, anti-reflection coating 140, and photoresist layer 170.
[0049] refer to Figure 8 The step of forming the first fin material layer 210 includes: using the hard mask layer 150 as a mask, etching the first initial fin material layer 110 of the second device region 100A.
[0050] Using the hard mask layer 150 as a mask, the first initial fin material layer 110 located in the first device region 100B is protected, and it is beneficial to improve the accuracy of pattern transfer.
[0051] Reference Figure 9 and Figure 10 A second fin material layer 220 is epitaxially grown on the substrate 100 of the second device region 100A, and the top of the second fin material layer 220 is higher than the top of the first fin material layer 210.
[0052] The second fin material layer 220 is used for the subsequent formation of the second fin.
[0053] Since the second fin material layer 220 is obtained through epitaxial growth, a relatively thick epitaxial layer with poor quality is usually formed at the interface between the second fin material layer 220 and the substrate 100. This poor-quality film layer is difficult to use as an effective fin for a channel in a semiconductor structure. In this embodiment of the invention, the height of the second fin material layer 220 is moderately increased, which helps to maintain a sufficiently high effective fin after fin patterning. Furthermore, in this embodiment of the invention, the first device region 100B and the second device region 100A are adjacent. At the junction of device region 100B and device region 100A, when the second fin material layer 220 is also epitaxially grown on the sidewall of the first fin material layer 210, a thicker epitaxial layer with poor quality is easily formed at the junction of the first fin material layer 210 and the second fin material layer 220. Therefore, after fin patterning, when the formed second fin is close to the junction of the first device region 100B and device region 100A, the second fin can still have a sufficiently high effective fin, thereby improving the performance of the semiconductor structure.
[0054] In this embodiment, the first device region 100B is adjacent to the second device region 100A, and the sidewall of the first fin material layer 210 is exposed at the junction of the first device region 100B and the second device region 100A. Therefore, during the epitaxial growth of the second fin material layer 220 on the substrate 100 of the second device region 100A, the second fin material layer 220 is also epitaxially grown on the sidewall of the first fin material layer 210.
[0055] Therefore, at the junction of the first fin material layer 210 and the second fin material layer 220, a thicker epitaxial layer with poor quality is also easily formed. Thus, after the fin patterning process, when the formed second fin is close to the junction of the first device region 100B and the second device region 100A, the second fin can still have a sufficiently high effective fin, thereby improving the performance of the semiconductor structure.
[0056] In this embodiment, the material of the second fin material layer 220 in the step of forming the second fin material layer 220 includes silicon germanide, silicon carbide or silicon phosphide.
[0057] As an example, the material of the second fin material layer 220 is Si. 1-y M y The element M represents a non-silicon element. A non-silicon element refers to any element other than silicon.
[0058] Specifically, the M element includes Ge, C, or P, so that the formed second fin material layer 220 can serve as a channel.
[0059] In this embodiment, the material of the second fin material layer 220 is silicon germanide.
[0060] In this embodiment, in the step of epitaxially growing the second fin material layer 220, the second fin material layer 220 is made of a different material than the first fin material layer 210, and the second fin material layer 220 is made of a different material than the substrate 100.
[0061] In this embodiment, the second fin material layer 220 and the first fin material layer 210 are made of different materials, thereby satisfying the respective performance requirements of the first transistor and the second transistor. Moreover, in order to select a fin material that meets the performance requirements of the second transistor, the second fin material layer 220 and the substrate 100 are made of different materials.
[0062] If the material of the second fin material layer 220 is different from that of the substrate 100, a thicker epitaxial layer with poor quality is easily formed at the junction of the second fin material layer 220 and the substrate 100. If the material of the second fin material layer 220 is different from that of the first fin material layer 210, a thicker epitaxial layer with poor quality is easily formed at the junction of the second fin material layer 220 and the first fin material layer 210. At the same time, this makes the materials of the subsequently formed first fin and second fin different, thereby meeting the respective performance requirements of the first transistor and the second transistor.
[0063] Specifically, the material of the first fin material layer 210 is silicon, and the material of the second fin material layer 220 is silicon germanide. Therefore, the material of the subsequently formed first fin is silicon, and the material of the subsequently formed second fin is silicon germanide. In this embodiment, the first transistor is an NMOS transistor, and the second transistor is a PMOS transistor. By using silicon germanide for the channel of the PMOS transistor, the channel mobility of the PMOS transistor is improved. Simultaneously, this helps to improve the negative bias temperature instability (NBTI) problem of the PMOS transistor, thereby improving the performance of the PMOS transistor.
[0064] refer to Figure 9 Before epitaxially growing the second fin material layer 220, the method further includes: epitaxially growing a buffer layer 240 on the substrate 100 of the second device region 100A, wherein the material of the buffer layer 240 is Si. 1-x M x .
[0065] The buffer layer 240 is used for epitaxial growth of the second fin material layer 220.
[0066] In this embodiment, the first device region 100B is adjacent to the second device region 100A, and the sidewall of the first fin material layer 210 is exposed at the junction of the first device region 100B and the second device region 100A. Therefore, the buffer layer 240 is also epitaxially grown on the sidewall of the first fin material layer 210.
[0067] In this embodiment, a second fin material layer 220 is epitaxially grown on the buffer layer 240, and the material of the buffer layer 240 is Si. 1-x M x The material of the second fin material layer 220 is Si. 1-y M y Where x is less than y.
[0068] Because the concentration gradient between the M element concentration in the second fin material layer 220 and the M element concentration in the substrate 100 is large, the buffer layer 240 is used to alleviate this large concentration gradient. Therefore, the M element concentration in the buffer layer 240 needs to be lower than the M element concentration in the second fin material layer 220. Consequently, the epitaxial quality of the buffer layer 240 is also poor, and after subsequent fin patterning, the buffer layer 240 cannot be used as an effective fin. In this embodiment, even though the buffer layer 240 is epitaxially grown before the second fin material layer 220, by moderately increasing the height of the second fin material layer 220, it is beneficial to still have an effective fin with sufficient height to provide a channel for the semiconductor structure after fin patterning.
[0069] It should be noted that x should not be too large or too small. If x is too large, the concentration difference between the M element in the buffer layer 240 and the M element in the substrate 100 will be too large, making it difficult to form the buffer layer 240; if x is too small, the concentration difference between the M element in the buffer layer 240 and the M element in the second fin material layer 220 will be too large, making it difficult to form the second fin material layer 220. Therefore, in this embodiment, the material Si of the buffer layer 240 is... 1-x M x In this context, x ranges from 0.05 to 0.3.
[0070] It should also be noted that y should not be too large or too small. If y is too large, the concentration of element M in the second fin material layer 220 will differ too much from the concentration of element M in the buffer layer 240, making it difficult to form the second fin material layer 220. If y is too small, the concentration of element M in the second fin material layer 220 will be too small. Element M plays a significant role in improving the electron mobility of the second transistor, so a low concentration of element M will make it difficult to improve the electron mobility of the second transistor, affecting its performance. Therefore, in this embodiment, the material Si of the second fin material layer 220... 1-y M y In this context, y ranges from 0.2 to 0.8.
[0071] Continue to refer to Figure 9 In this embodiment, the step of forming the second fin material layer 220 includes: epitaxially growing a second initial fin material layer 250 on the substrate 100 of the second device region 100A, wherein the top of the second initial fin material layer 250 is higher than the top of the hard mask layer 150.
[0072] If the top of the second initial fin material layer 250 is higher than the top of the hard mask layer 150, a second fin material layer 220 with a larger height can be formed, so that the second fin formed subsequently has an effective fin with sufficient height.
[0073] Furthermore, the second initial fin material layer 250 is subsequently planarized to the target height. Compared to directly forming the second fin material layer to the target height, in this embodiment, forming a higher second initial fin material layer 250 and then planarizing it to the target height can result in a second fin material layer 220 with higher top surface flatness and more accurate height dimensions.
[0074] In other embodiments, the top of the second initial fin material layer may also be lower than the top of the hard mask layer.
[0075] refer to Figure 10 The step of forming the second fin material layer 220 further includes: using the top of the hard mask layer 150 as the stop position, planarizing the second initial fin material layer 250, and retaining the remaining second initial fin material layer 250 as the second fin material layer 220.
[0076] Using the top of the hard mask layer 150 as the stopping position, while forming a second fin material layer 220 of sufficient height, it is beneficial to make the height dimension accuracy of the formed second fin material layer 220 higher, the top surface flatness of the second fin material layer 220 higher, and the hard mask layer 150 also protects the first fin material layer 210 during the process of flattening the second fin material layer 220.
[0077] In this embodiment, the planarization process includes a chemical mechanical polishing process.
[0078] The chemical mechanical polishing process combines the advantages of chemical polishing and mechanical polishing, which can ensure efficient removal of the second fin material layer 220 above the hard mask layer 150 and obtain a better surface.
[0079] In other embodiments, the planarization process may be omitted depending on process requirements (e.g., the thickness requirement of the second fin material layer 220).
[0080] It should be noted that in other embodiments, the second fin material layer can be formed at different heights according to different process requirements. After the second initial fin material layer is planarized, the top surface of the second fin material layer can be higher than the top surface of the hard mask layer or lower than the top surface of the hard mask layer.
[0081] It should be noted that the dimension d of the second fin material layer 220 being higher than the first fin material layer 210 should not be too large or too small. If the dimension d of the second fin material layer 220 being higher than the first fin material layer 210 is too large, the subsequent formation of an excessively tall second fin will easily lead to unnecessary process waste; if the dimension d of the second fin material layer 220 being higher than the first fin material layer 210 is too small, the subsequent formation of an excessively short second fin will make it difficult to meet the process requirements for the height of the second effective fin used as a channel in the second fin, affecting the performance of the semiconductor structure. Therefore, the dimension d of the second fin material layer 220 being higher than the first fin material layer 210 is between 20 nm and 200 nm.
[0082] refer to Figure 11 After forming the second fin material layer 220, the hard mask layer 150 is removed.
[0083] Specifically, after planarizing the second fin material layer 220, the hard mask layer 150 is removed.
[0084] Remove the hard mask layer 150 to prepare for the subsequent formation of the third fin material layer.
[0085] In this embodiment, the hard mask layer 150 is removed using a wet etching process.
[0086] The wet etching process has a relatively low cost and simple operation steps, and can achieve a large etching selectivity, which helps to reduce damage to the first fin material layer 210 and the second fin material layer 220 during the removal of the hard mask layer 150.
[0087] Furthermore, by removing the hard mask layer 150, preparation is made for the subsequent epitaxial growth of the third fin material layer on the first fin material layer 210, thereby making the top of the first fin subsequently formed in the first device region flush with the top of the second fin formed in the second device region.
[0088] Reference Figure 12 and Figure 13 After removing the hard mask layer 150, a third fin material layer 230 is epitaxially grown on the first fin material layer 210. The material of the third fin material layer 230 is the same as that of the first fin material layer 210.
[0089] The third fin material layer 230 is used to form the first fin together with the first fin material layer 210.
[0090] Therefore, the material of the third fin material layer 230 is the same as the material of the first fin material layer 210.
[0091] Moreover, the material of the third fin material layer 230 is the same as that of the first fin material layer 210, which is beneficial to improving the film quality of the third fin material layer 230 at the interface between the third fin material layer 230 and the first fin material layer 210.
[0092] In this embodiment, the material of the third fin material layer 230 in the step of forming the third fin material layer 230 includes silicon, germanium, silicon germanide, or group III-V semiconductor materials. In this embodiment, the material of the third fin material layer 230 is silicon.
[0093] Specifically, refer to Figure 12 In the step of epitaxially growing a third fin material layer 230 on the first fin material layer 210, the third fin material layer 230 is also epitaxially grown on the top of the second fin material layer 220.
[0094] The top surface of the second fin material layer 220 is exposed in the epitaxial growth process. Therefore, the third fin material layer 230 is also epitaxially grown on the second fin material layer 220. Furthermore, the third fin material layer 230 is subsequently planarized to the target height. Compared to directly forming the third fin material layer to the target height, this embodiment can obtain a third fin material layer 230 with higher top surface flatness and more accurate height dimensions.
[0095] refer to Figure 13 Before the subsequent fin patterning process, the method further includes: using the top surface of the second fin material layer 220 as the stop position, the third fin material layer 230 is planarized to expose the top surface of the second fin material layer 220. After planarization, the remaining third fin material layer 230 is flush with the top of the second fin material layer 220.
[0096] Using the top surface of the second fin material layer 220 as the stopping position, the third fin material layer 230 is planarized. This helps to ensure that the height dimension of the formed third fin material layer 230 is highly accurate. After planarization, the remaining third fin material layer 230 is flush with the top of the second fin material layer 220, providing a process platform with high flatness for subsequent fin patterning.
[0097] In this embodiment, the planarization process includes a chemical mechanical polishing process.
[0098] The chemical mechanical polishing process combines the advantages of chemical polishing and mechanical polishing, which can ensure efficient removal of the third fin material layer 230 above the second fin material layer 220 and obtain a better surface.
[0099] refer to Figure 14 The fins are patterned by patterning the first fin material layer 210 and the third fin material layer 230 into a first fin 310 protruding from the substrate 100 of the first device region 100B, and the second fin material layer 220 into a second fin 320 protruding from the substrate 100 of the second device region 100A.
[0100] The first fin 310 is used to provide a channel for the first transistor, and the second fin 320 is used to provide a channel for the second transistor.
[0101] In this embodiment, a dry etching process is used for fin patterning.
[0102] The dry etching process is an anisotropic etching process with directional etching, which is beneficial for forming a first fin 310 and a second fin 320 with better sidewall quality. At the same time, the dry etching process can better control the process parameters, so that the parameters of the fin patterning process can be controlled more precisely.
[0103] Accordingly, the first fin 310 is made of silicon, and the second fin 320 is made of silicon germanide. Specifically, the first transistor is a PMOS transistor, and the second transistor is an NMOS transistor. By using silicon germanide for the channel of the PMOS transistor, the channel mobility of the PMOS transistor is improved. At the same time, it is beneficial to improve the negative bias temperature instability problem of the PMOS transistor, thereby improving the performance of the PMOS transistor.
[0104] In this embodiment, the step of performing the fin patterning process further includes: patterning the buffer layer 240, and patterning the second fin material layer 220 and the buffer layer 240 into a second fin 320 protruding from the substrate 100 of the second device region 100A.
[0105] The buffer layer 240 in the second fin 320 will subsequently be covered by the isolation layer and will not be used as an effective fin of the second fin 320.
[0106] refer to Figure 15 After performing the fin patterning process, the method further includes: forming an isolation layer 160 on the substrate 100, the isolation layer 160 covering part of the sidewalls of the first fin 310 and the second fin 320, and the top of the isolation layer 160 being higher than or flush with the top of the buffer layer 240 in the second fin 320.
[0107] The isolation layer 160 serves as a shallow trench isolation (STI) structure to isolate adjacent transistors. In this embodiment, the top of the isolation layer 160 is higher than or flush with the top of the buffer layer 240 in the second fin 320, so that the transistors only use the portions of the first fin 310 and the second fin 320 that are higher than the top of the isolation layer 160 as channels.
[0108] In this embodiment, the portions of the first fin 310 and the second fin 320 exposed above the isolation layer 160 are considered effective fins. That is, the portions of the first fin 310 and the second fin 320 exposed above the isolation layer 160 are used to be covered by the gate structure. Therefore, depending on actual needs, the top of the isolation layer 160 is higher than or flush with the top of the buffer layer 240 in the second fin 320. As an example, Figure 15 The top of the isolation layer 160 is shown above the top of the buffer layer 240 in the second fin 320, in order to reduce the possibility of the buffer layer 240 being exposed.
[0109] It should be noted that a gate structure spanning the first fin 310 and the second fin 320 will subsequently be formed on the isolation layer 160. The description of these subsequent steps will not be repeated here.
[0110] Figures 16 to 19 This is a schematic diagram of the structure corresponding to each step in another embodiment of the method for forming the semiconductor structure of the present invention.
[0111] The similarities between this embodiment and the previous embodiment will not be repeated here. The difference between this embodiment and the previous embodiment is that an isolation wall 411 is formed between the second fin material layer 241 and the first fin material layer 211 at the junction of the first device region 101B and the second device region 101A.
[0112] Reference Figure 16 and Figure 17 After removing the hard mask layer and before forming the third fin material layer, the method further includes: forming an isolation wall 411 on the sidewall of the second fin material layer 221 at the junction of the first device region 101B and the second device region 101A.
[0113] The isolation wall 411 blocks the epitaxial growth of the third fin material layer on the sidewall of the second fin material layer 221, thus avoiding the growth of a thick, low-quality film layer on the sidewall of the second fin material layer 221 as much as possible. This allows the first fin material layer 211 to be used as the epitaxial growth base during the epitaxial growth of the third fin material layer, which is conducive to forming a high-quality third fin material layer and correspondingly improving the quality of the first fin, thereby improving the performance of the semiconductor structure.
[0114] In this embodiment, in the step of forming the isolation wall 411, the material of the isolation wall 411 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbon oxynitride. The material of the isolation wall 411 is an insulating material, which can play a good isolation role and is conducive to preventing epitaxial growth on the isolation wall 411.
[0115] Specifically, refer to Figure 16 The step of forming the isolation wall 411 includes: forming an isolation wall material layer 401 covering the top and sidewalls of the second fin material layer 221 and the top of the first fin material layer 211.
[0116] The isolation wall material layer 401 is used to form the isolation wall 411.
[0117] In this embodiment, the isolation wall material layer 401 is formed by atomic layer deposition.
[0118] The isolation wall material layer 401 formed by atomic layer deposition has good thickness uniformity and good step coverage capability, which enables the isolation wall material layer 401 to cover the top and sidewalls of the second fin material layer 221 and the top of the first fin material layer 211 in a good conformal manner, and improves the thickness uniformity of the isolation wall material layer 401, thereby improving the protective effect on the second fin material layer 221.
[0119] In this embodiment, the material of the isolation material layer 401 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbon oxynitride, and is used to directly form the isolation wall 411.
[0120] refer to Figure 17 Remove the isolation wall material layer 401 located on the top of the second fin material layer 221 and the top of the first fin material layer 211, and retain the isolation wall material layer 401 located on the side wall of the second fin material layer 221 as the isolation wall 411.
[0121] Remove the isolation wall material layer 401 located on top of the second fin material layer 221 and the first fin material layer 211 to expose the top of the second fin material layer 221 and the top of the first fin material layer 211, in preparation for the subsequent formation of the third fin material layer.
[0122] In this embodiment, in the step of forming the isolation wall 411, a dry etching process is used to remove the isolation wall material layer 401 located on the top of the second fin material layer 221 and the top of the first fin material layer 211.
[0123] The dry etching process has the characteristics of anisotropic etching. Therefore, by selecting the dry etching process, it is beneficial to reduce the damage to the formed isolation wall 411. At the same time, the dry etching is more directional, which is beneficial to improve the morphological quality and dimensional accuracy of the isolation wall 411.
[0124] Reference Figure 18 and Figure 19 During the formation of the third fin material layer 231, the third fin material layer 231 covers the side wall of the isolation wall 411 facing away from the second fin material layer 221.
[0125] The third fin material layer 231 covers the sidewall of the isolation wall 411 facing away from the second fin material layer 221. During the epitaxial growth of the third fin material layer 231, the isolation wall 411 blocks the epitaxial growth of the third fin material layer 231 on the sidewall of the second fin material layer 221, thus avoiding the growth of a thicker, lower-quality film layer on the sidewall of the second fin material layer 221 as much as possible. This is beneficial for forming a higher-quality third fin material layer 231, thereby improving the quality of the first fin and thus improving the performance of the semiconductor structure.
[0126] Specifically, refer to Figure 18 In the step of epitaxially growing a third fin material layer 231 on the first fin material layer 211, the third fin material layer 231 is also epitaxially grown on the top of the second fin material layer 221.
[0127] Therefore, in this embodiment, a thicker, lower-quality film layer is easily formed between the top of the second fin material layer 221 and the third fin material layer 231. However, the third fin material layer 231 located on top of the second fin material layer 221 will be removed subsequently to avoid affecting the semiconductor structure as much as possible.
[0128] refer to Figure 19 Before the subsequent fin patterning process, the method further includes: using the top surface of the second fin material layer 221 as the stop position, performing planarization on the third fin material layer 231 to expose the top surface of the second fin material layer 221, and after planarization, the remaining third fin material layer 231 is flush with the top of the second fin material layer 221.
[0129] Using the top surface of the second fin material layer 221 as the stopping position, the third fin material layer 231 is planarized to remove the thicker, lower-quality film layer between the top of the second fin material layer 221 and the third fin material layer 231, forming a higher-quality third fin material layer 231. Using the top surface of the second fin material layer 221 as the stopping position helps ensure high accuracy in the height dimensions of the formed third fin material layer 231. Furthermore, after planarization, the remaining third fin material layer 231 is flush with the top of the second fin material layer 221, providing a high-flatness process platform for subsequent fin patterning.
[0130] In this embodiment, the planarization process includes a chemical mechanical polishing process.
[0131] The chemical mechanical polishing process combines the advantages of chemical polishing and mechanical polishing, which can ensure efficient removal of the third fin material layer 231 that is higher than the second fin material layer 221 and obtain a better surface.
[0132] It should be noted that the isolation wall 411 is located at the junction of the first device region 101B and the second device region 101A. During the subsequent fin patterning process, the isolation layer 411 will be removed. Therefore, the formation of the isolation wall 411 has little impact on the performance of the semiconductor structure.
[0133] For a detailed description of the formation method described in this embodiment, please refer to the corresponding descriptions in the foregoing embodiments, which will not be repeated here.
[0134] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.
Claims
1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including a first device region for forming a first transistor and a second device region adjacent to the first device region for forming a second transistor, wherein a first fin material layer is further formed on the substrate in the first device region, and a hard mask layer is further formed on the first fin material layer. A second fin material layer is epitaxially grown on the substrate of the second device region, wherein the top of the second fin material layer is higher than the top of the first fin material layer; After forming the second fin material layer, the hard mask layer is removed; After removing the hard mask layer, a third fin material layer is epitaxially grown on the first fin material layer, wherein the material of the third fin material layer is the same as that of the first fin material layer. The fins are patterned by patterning the first fin material layer and the third fin material layer into a first fin protruding from the substrate of the first device region, and the second fin material layer into a second fin protruding from the substrate of the second device region.
2. The method for forming a semiconductor structure as described in claim 1, characterized in that, During the epitaxial growth of the second fin material layer on the substrate of the second device region, the second fin material layer is also epitaxially grown on the sidewall of the first fin material layer.
3. The method for forming a semiconductor structure as described in claim 1, characterized in that, Before epitaxially growing the second fin material layer, the method further includes: epitaxially growing a buffer layer on the substrate of the second device region, wherein the buffer layer is made of Si. 1- x M x Where M represents a non-silicon element; The second fin material layer is epitaxially grown on the buffer layer, and the material of the second fin material layer is Si. 1-y M y Where x is less than y; The step of performing the fin patterning process further includes: patterning the buffer layer, and patterning the second fin material layer and the buffer layer into a second fin protruding from the substrate of the second device region.
4. The method for forming a semiconductor structure as described in claim 3, characterized in that, The buffer layer is also epitaxially grown on the sidewall of the first fin material layer.
5. The method for forming a semiconductor structure as described in claim 1, characterized in that, After removing the hard mask layer and before forming the third fin material layer, the method further includes: forming an isolation wall on the sidewall of the second fin material layer at the junction of the first device region and the second device region; During the formation of the third fin material layer, the third fin material layer covers the sidewall of the isolation wall facing away from the second fin material layer.
6. The method for forming a semiconductor structure as described in claim 5, characterized in that, The step of forming the isolation wall includes: forming an isolation wall material layer covering the top and sidewalls of the second fin material layer and the top of the first fin material layer; Remove the isolation wall material layer located on top of the second fin material layer and on top of the first fin material layer, and retain the isolation wall material layer located on the side wall of the second fin material layer as an isolation wall.
7. The method for forming a semiconductor structure as described in claim 1, characterized in that, The step of forming the second fin material layer includes: epitaxially growing a second initial fin material layer on a substrate of the second device region, wherein the top of the second initial fin material layer is higher than the top of the hard mask layer; Using the top of the hard mask layer as the stop position, the second initial fin material layer is planarized, and the remaining second initial fin material layer is retained as the second fin material layer.
8. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of epitaxially growing a third fin material layer on the first fin material layer, the third fin material layer is also epitaxially grown on top of the second fin material layer; Before performing fin patterning, the process further includes: using the top surface of the second fin material layer as the stop position, flattening the third fin material layer to expose the top surface of the second fin material layer, and after flattening, the remaining third fin material layer is flush with the top of the second fin material layer.
9. The method for forming a semiconductor structure as described in claim 7 or 8, characterized in that, The planarization process includes chemical mechanical polishing.
10. The method for forming a semiconductor structure as described in claim 1, characterized in that, Before forming the first fin material layer and the hard mask layer, the method further includes: forming a first initial fin material layer covering the first device region and the second device region on the substrate, wherein a hard mask material layer is also formed on the first initial fin material layer; The step of forming the hard mask layer includes: forming a pattern transfer layer on the hard mask material layer, the pattern transfer layer having an opening that exposes the second device region; Using the pattern transfer layer as a mask, the hard mask material layer located in the second device region is removed, while the hard mask material layer located in the first device region is retained as the hard mask layer. The step of forming the first fin material layer includes: using the hard mask layer as a mask, etching the first initial fin material layer of the second device region.
11. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of epitaxially growing the second fin material layer, the material of the second fin material layer is different from that of the first fin material layer, and the material of the second fin material layer is different from that of the substrate.
12. The method for forming a semiconductor structure as described in claim 6, characterized in that, In the step of forming the isolation wall material layer, the isolation wall material layer is formed using an atomic layer deposition process.
13. The method for forming a semiconductor structure as described in claim 6, characterized in that, In the step of forming the isolation wall, a dry etching process is used to remove the isolation wall material layer located on top of the second fin material layer and on top of the first fin material layer.
14. The method for forming a semiconductor structure as described in claim 1, characterized in that, The second fin material layer is 20 nm to 200 nm larger than the first fin material layer.
15. The method for forming a semiconductor structure as described in claim 5, characterized in that, In the step of forming the isolation wall, the material of the isolation wall includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbon oxynitride.
16. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of forming the first fin material layer, the material of the first fin material layer includes silicon, germanium, silicon germanide, or a group III-V semiconductor material; in the step of forming the second fin material layer, the material of the second fin material layer includes silicon germanide, silicon carbide, or silicon phosphide; in the step of forming the third fin material layer, the material of the third fin material layer includes silicon, germanium, silicon germanide, or a group III-V semiconductor material.
17. The method for forming a semiconductor structure as described in claim 3, characterized in that, The M includes elements Ge, C, or P.
18. The method for forming a semiconductor structure as described in claim 3, characterized in that, The material of the buffer layer is Si. 1-x M x In the figure, x is 0.05 to 0.3, and the material of the second fin layer is Si. 1-y M y In this context, y ranges from 0.2 to 0.
8.
19. The method for forming a semiconductor structure as described in claim 3, characterized in that, After performing the fin patterning process, the method further includes: forming an isolation layer on the substrate, the isolation layer covering a portion of the sidewalls of the first fin and the second fin, the top of the isolation layer being higher than or flush with the top of the buffer layer in the second fin.
20. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of providing the substrate, the first transistor and the second transistor have different channel conductivity types.
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