ESD protection devices, protection circuits and their fabrication methods

Abstract

This invention provides an ESD protection device, protection circuit, and fabrication method. The ESD protection device includes: a semiconductor substrate, an SCR structure with an NMOS transistor formed on the semiconductor substrate, a coupling structure, and a trigger structure; wherein, one end of the coupling structure is connected to the positive terminal of the SCR structure, and the other end is connected to the negative terminal of the SCR structure, and the coupling voltage output is connected to the gate of the NMOS transistor in the SCR structure; one end of the trigger structure is connected to the positive terminal of the SCR structure, and the other end is connected to the base of a parasitic NPN transistor in the SCR structure. The ESD protection device, protection circuit, and fabrication method provided by this invention solve the problem of excessively high trigger voltage in existing ESD protection devices.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuit technology, and in particular to an ESD protection device, protection circuit, and preparation method. Background Technology

[0002] Electrostatic discharge (ESD) protection is a crucial aspect of integrated circuit (IC) design. As process nodes shrink and high-voltage applications operate at higher voltages, the ESD requirements for ICs become increasingly stringent. Currently, thyristors (SCRs) are widely used in ICs due to their strong ESD discharge capacity and low parasitic capacitance. Figure 1 The diagram shows a traditional SCR structure. When a positive ESD pulse is applied to the positive terminal, the reverse PN junction of the N-well and P-well forms a leakage current. As the positive voltage increases, the leakage current gradually increases. When the leakage current reaches a certain value, the base-emitter (P-well-negative terminal) of the parasitic NPN transistor T2 formed by the N-well-P-well-N+ (negative terminal) becomes forward biased. T2 conducts, forming a current from the N-well to the negative terminal (N+). This current causes the emitter-base (positive terminal-N-well) of the parasitic PNP transistor T1 to also become forward biased, and T1 conducts accordingly, thus forming a positive feedback effect and creating a low-resistance PNPN path from the positive terminal to the negative terminal. In other words, the thyristor is turned on, thereby discharging the ESD current and protecting other protected circuits.

[0003] However, the trigger (turn-on) voltage of a conventional thyristor (SCR) is determined by the reverse breakdown voltage of the N-well-P-well. Since the doping concentration of the well is very low, this voltage is usually very high. Therefore, one of the major weaknesses that limits the widespread application of conventional thyristors is that their trigger voltage is too high. An excessively high trigger voltage will cause the SCR to not turn on completely, and the protected device will be burned out.

[0004] Therefore, finding more effective electrostatic protection devices or structures has become a technical problem that we urgently need to solve. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide an ESD protection device, protection circuit and preparation method to solve the problem of excessively high trigger voltage of ESD protection devices in the prior art.

[0006] To achieve the above and other related objectives, the present invention provides an ESD protection device, the ESD protection device comprising:

[0007] A semiconductor substrate, and an SCR structure with an NMOS transistor, a coupling structure, and a trigger structure formed on the semiconductor substrate; wherein,

[0008] One end of the coupling structure is connected to the positive terminal of the SCR structure, and the other end is connected to the negative terminal of the SCR structure. The coupling voltage output is connected to the gate of the NMOS transistor in the SCR structure. One end of the trigger structure is connected to the positive terminal of the SCR structure, and the other end is connected to the base of the parasitic NPN transistor in the SCR structure.

[0009] Specifically, when there is a positive ESD pulse at the positive terminal of the SCR structure, the gate voltage of the NMOS transistor in the SCR structure is pulled up through the coupling structure.

[0010] Optionally, the SCR structure includes:

[0011] A well layer is formed above the semiconductor substrate and includes an N-well region and an adjacent P-well region.

[0012] A doped layer is formed above the well region layer, and from left to right includes: a first N-type doped region, a first P-type doped region, a second N-type doped region, a third N-type doped region, a second P-type doped region, and a third P-type doped region. The second N-type doped region is located above the boundary between the N-well region and the P-well region, and a channel region is formed between the second N-type doped region and the third N-type doped region.

[0013] A gate is formed above the channel region, and the second N-type doped region, the third N-type doped region, the channel region and the gate together constitute an NMOS transistor;

[0014] The first N-type doped region is connected to the first P-type doped region and leads out the positive electrode of the SCR structure; the third N-type doped region is connected to the third P-type doped region and leads out the negative electrode of the SCR structure.

[0015] In this configuration, a parasitic PNP transistor and an N-well parasitic resistor are formed in the N-well region, and a parasitic NPN transistor and a P-well parasitic resistor are formed in the P-well region. The base of the parasitic PNP transistor is connected to the first N-type doped region through the N-well parasitic resistor, the emitter is connected to the first P-type doped region, and the collector is connected to the base of the parasitic NPN transistor. The base of the parasitic NPN transistor is connected to the second P-type doped region and to the third P-type doped region through the P-well parasitic resistor. The emitter is connected to the third N-type doped region, and the collector is connected to the base of the parasitic PNP transistor.

[0016] Optionally, the SCR structure further includes: shallow trench isolation, formed at least between the first N-type doped region and the first P-type doped region, between the first P-type doped region and the second N-type doped region, between the third N-type doped region and the second P-type doped region, and between the second P-type doped region and the third P-type doped region.

[0017] Optionally, the coupling structure includes a diode and a resistor, wherein the cathode of the diode is connected to the anode of the SCR structure, the anode is connected to the gate of the NMOS transistor in the SCR structure, and the diode is connected to the cathode of the SCR structure through the resistor.

[0018] Optionally, the triggering structure includes: N diodes connected in series, the anodes of the series diodes being connected to the positive terminal of the SCR structure, and the cathodes being connected to the base of the parasitic NPN transistor in the SCR structure; wherein, N is a positive integer greater than or equal to 1.

[0019] Optionally, the sum of the forward voltages of the N series-connected diodes is not less than the voltage difference between the positive and negative terminals of the SCR structure.

[0020] The present invention also provides an ESD protection circuit, the circuit comprising: at least one ESD protection device as described in any of the preceding claims, connected between the positive and negative terminals of the ESD protection circuit; when the number of the ESD protection devices is greater than or equal to two, the plurality of the ESD protection devices are connected in series.

[0021] This invention also provides a method for fabricating an ESD protection device, the method comprising:

[0022] 1) A semiconductor substrate is provided, the semiconductor substrate comprising: a first region, a second region and a third region;

[0023] 2) An SCR structure with an NMOS transistor is formed in the first region, a coupling structure is formed in the second region, and a trigger structure is formed in the third region;

[0024] In this configuration, one end of the coupling structure is connected to the positive terminal of the SCR structure, and the other end is connected to the negative terminal of the SCR structure. The coupling voltage output is connected to the gate of the NMOS transistor in the SCR structure. One end of the trigger structure is connected to the positive terminal of the SCR structure, and the other end is connected to the base of the parasitic NPN transistor in the SCR structure.

[0025] Optionally, the methods for forming the SCR structure, coupling structure, and triggering structure in 2) include:

[0026] 2.1) An N-well region and an adjacent P-well region are formed in the first region, an N-well region is formed in the second region, and N N-well regions and (N-1) P-well regions are formed in the third region, with the P-well regions located between adjacent N-well regions;

[0027] 2.2) From left to right, a first N-type doped region, a first P-type doped region, a second N-type doped region, a third N-type doped region, a second P-type doped region, and a third P-type doped region are formed in the N-well region and P-well region of the first region. An N-type doped region and a P-type doped region are formed in the N-well region of the second region. A P-type doped region and an N-type doped region are formed in the N-well region of the third region. The second N-type doped region is located above the boundary between the N-well region and the P-well region, and a channel region is formed between the second N-type doped region and the third N-type doped region.

[0028] 2.3) A gate is formed above the channel region of the first region, and a resistor is formed above the non-N-well region of the second region;

[0029] 2.4) A metal wiring is formed above the structure formed in 2.3) to electrically connect the coupling structure, the trigger structure, and the SCR structure. Simultaneously, the first N-type doped region is connected to the first P-type doped region and the positive electrode of the SCR structure is led out. The third N-type doped region is connected to the third P-type doped region and the negative electrode of the SCR structure is led out.

[0030] Optionally, the method further includes the step of forming shallow trench isolation, wherein the shallow trench isolation is formed at least between adjacent doped regions.

[0031] As described above, the ESD protection device, protection circuit, and fabrication method of the present invention have the following beneficial effects: The ESD protection device of the present invention includes an SCR structure, a trigger structure, and a coupling structure. When there is a positive ESD pulse at the positive terminal of the SCR structure, the coupling structure pulls up the gate of the NMOS transistor in the SCR structure, causing it to conduct and form a MOS discharge path. At the same time, the trigger structure triggers the parasitic NPN transistor in the SCR structure to conduct, thereby triggering the parasitic PNP transistor in the SCR structure to conduct, forming a PNPN discharge path, thus realizing a dual-trigger SCR protection mechanism. Since the coupling structure pulls up the gate voltage of the NMOS transistor, the trigger voltage of the discharge ESD pulse is significantly reduced. Moreover, the ESD protection device of the present invention maintains its advantage of strong protection capability per unit area. Attached Figure Description

[0032] Figure 1 The diagram shows a conventional SCR structure in the prior art.

[0033] Figure 2 The diagram shown is a structural schematic of the ESD protection device of the present invention.

[0034] Figure 3 The image shown is a top view of the ESD protection device of the present invention.

[0035] Figure 4The diagram shown is a cross-sectional view of the diode in the coupling structure of this invention.

[0036] Figure 5 The diagram shown is a cross-sectional view of the series diode in the trigger structure of this invention.

[0037] Figure 6 The diagram shown is a schematic of the ESD protection circuit of the present invention.

[0038] Component designation explanation

[0039] 1 Semiconductor substrate

[0040] 11 First District

[0041] 12 Second Region

[0042] 13 Third Region

[0043] 2 SCR Structure

[0044] 21 gate

[0045] 22-well layer

[0046] 221, 31, 41 N-well regions

[0047] 222, 42 P-well regions

[0048] 23 Doped layer

[0049] 231 First N-type doped region

[0050] 232 First P-type doped region

[0051] 233 Second N-type doped region

[0052] 234 Third N-type doped region

[0053] 235 Second P-type doped region

[0054] 236 Third P-type doped region

[0055] 227 Ditch Area

[0056] 24, 34, 45 Shallow trench isolation

[0057] 3. Coupled Structure

[0058] 32, 44 N-type doped regions

[0059] 33, 43 P-type doped regions

[0060] 4. Triggering Structure

[0061] R1 resistor

[0062] Diodes D1, D2, D3, and D4

[0063] T1 PNP pipe

[0064] T2 NPN tube Detailed Implementation

[0065] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification.

[0066] Please see Figures 1 to 6 It should be understood that the structures, proportions, sizes, etc., illustrated in the accompanying drawings are merely for illustrative purposes to aid those skilled in the art and to facilitate understanding and reading. They are not intended to limit the scope of the invention and therefore have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effectiveness and purpose of the invention, should still fall within the scope of the technical content disclosed in this invention. Furthermore, the terms such as "upper," "lower," "left," "right," "middle," and "one" used in this specification are merely for clarity and not intended to limit the scope of the invention. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of the invention's implementation.

[0067] like Figure 2 As shown, this embodiment provides an ESD protection device, which includes: a semiconductor substrate 1, an SCR structure 2 with an NMOS transistor, a coupling structure 3, and a trigger structure 4 formed on the semiconductor substrate 1; wherein,

[0068] One end of the coupling structure 3 is connected to the positive terminal of the SCR structure 2, and the other end is connected to the negative terminal of the SCR structure 2. The coupling voltage output is connected to the gate 21 of the NMOS transistor in the SCR structure 2. One end of the trigger structure 4 is connected to the positive terminal of the SCR structure 2, and the other end is connected to the base of the parasitic NPN transistor T2 in the SCR structure 2.

[0069] When there is a positive ESD pulse at the positive terminal of the SCR structure 2, the voltage of the gate 21 of the NMOS transistor in the SCR structure 2 is pulled up by the coupling structure 3, so that it is turned on to form a MOS discharge path; at the same time, the parasitic NPN transistor T2 in the SCR structure 2 is triggered to conduct by the trigger structure 4, which in turn triggers the parasitic PNP transistor T1 in the SCR structure 2 to conduct, forming a PNPN discharge path.

[0070] Specifically, such as Figure 3As shown, the semiconductor substrate 1 includes a first region 11, a second region 12, and a third region 13, and the three regions are arranged adjacent to each other; wherein, the SCR structure 2 with an NMOS transistor is formed in the first region 11, the coupling structure 3 is formed in the second region 12, and the trigger structure 4 is formed in the third region 13. The material of the semiconductor substrate 1 includes, but is not limited to, undoped single-crystal silicon, doped single-crystal silicon, and silicon-on-insulator (SOI).

[0071] Specifically, the SCR structure 2 includes a well layer 22, a doped layer 23, and a gate 21. The well layer 22 is formed above the semiconductor substrate 1 and includes an N-well region 221 and an adjacent P-well region 222. The doped layer 23 is formed above the well layer 22 and, from left to right, includes: a first N-type doped region 231, a first P-type doped region 232, a second N-type doped region 233, a third N-type doped region 234, a second P-type doped region 235, and a third P-type doped region 236. The first N-type doped region 236, the second N-type doped region 233 is located above the boundary between the N-well region 221 and the P-well region 222, and a channel region 237 is formed between the second N-type doped region 233 and the third N-type doped region 234. The gate 21 is formed above the channel region 237. The second N-type doped region 233, the third N-type doped region 234, the channel region 237 and the gate 21 together constitute an NMOS transistor; the first N-type doped region 236... The first P-type doped region 232 is connected to and leads out the positive electrode of the SCR structure 2. The third N-type doped region 234 is connected to and leads out the negative electrode of the SCR structure 2. A parasitic PNP transistor T1 and an N-well parasitic resistor Rnwell are formed in the N-well region 221, and a parasitic NPN transistor T2 and a P-well parasitic resistor Rpwell are formed in the P-well region 222. The base of the parasitic PNP transistor T1 is connected to the N-well parasitic resistor Rnwell. The P-well resistor Rnwell is connected to the first N-type doped region 231, the emitter is connected to the first P-type doped region 232, and the collector is connected to the base of the parasitic NPN transistor T2; the base of the parasitic NPN transistor T2 is connected to the second P-type doped region 235, and is connected to the third P-type doped region 236 through the P-well parasitic resistor Rpwell, the emitter is connected to the third N-type doped region 234, and the collector is connected to the base of the parasitic PNP transistor T1.

[0072] More specifically, the SCR structure further includes a shallow trench isolation 24, wherein the shallow trench isolation 24 is formed at least between the first N-type doped region 231 and the first P-type doped region 232, between the first P-type doped region 232 and the second N-type doped region 233, between the third N-type doped region 234 and the second P-type doped region 235, and between the second P-type doped region 235 and the third P-type doped region 236. Of course, the shallow trench isolation 24 may also be formed outside the first N-type doped region 231 and the third P-type doped region 236.

[0073] Specifically, the coupling structure 3 includes a diode D1 and a resistor R1. The cathode of the diode D1 is connected to the positive terminal of the SCR structure 2, and the anode is connected to the gate 21 of the NMOS transistor in the SCR structure 2. The diode D1 is also connected to the negative terminal of the SCR structure 2 through the resistor R1. When there is a positive ESD pulse at the positive terminal, the diode D1 acts as a capacitor. The diode D1 and the resistor R1 form an RC coupling, and an effective time constant, such as 5ns, can be set through the diode D1 and the resistor R1 to ensure that the gate 21 of the integrated NMOS is coupled to a sufficiently high voltage, so that the NMOS channel region 237 can quickly conduct and discharge part of the ESD current.

[0074] More specifically, such as Figure 4 As shown, in the coupling structure 3, the diode D1 is formed above the semiconductor substrate 1, including an N-well region 31, an N-type doped region 32, a P-type doped region 33, and a shallow trench isolation 34. The N-well region 31 is formed above the semiconductor substrate 1, the N-type doped region 32 and the P-type doped region 33 are formed above the N-well region 31, and the shallow trench isolation 34 is formed between the N-type doped region 32 and the P-type doped region 33. Alternatively, the shallow trench isolation 34 can also be formed outside the N-type doped region 32 and the P-type doped region 33. The resistor R1 is formed above the non-N-well region of the third region 13 and is formed synchronously with the gate 21.

[0075] Specifically, the trigger structure 4 includes N diodes connected in series. The anodes of the series diodes are connected to the positive terminal of the SCR structure 2, and the cathodes are connected to the base of the parasitic NPN transistor T2 in the SCR structure 2; where N is a positive integer greater than or equal to 1. More specifically, the sum of the forward voltages of the N series diodes is not less than the voltage difference between the positive and negative terminals of the SCR structure. The N series diodes can be all silicon diodes, all germanium diodes, or both. Preferably, the N series diodes are of the same type (silicon or germanium diodes). When the diodes are of the same type, the following relationship V is satisfied. D *N≥ΔV,VD The signal represents the forward voltage of the diode, N represents the number of diodes connected in series, and ΔV represents the voltage difference between the positive and negative terminals of the SCR structure. For example, if the voltage difference is 2.5V and the forward voltage of the diode is 0.7V for a silicon diode, then at least four diodes need to be connected in series. In this embodiment, the number of diodes N is 3, namely D2, D3, and D4. When there is a positive ESD pulse at the positive terminal, a current path is formed: positive terminal → series diodes D2-D3-D4 → second P-type doped region 235 → negative terminal. The trigger current flows through this path, causing the base-emitter junction of the parasitic NPN transistor T2 to be forward biased. The parasitic NPN transistor T2 quickly turns on, and its collector current is fed back to the base of the parasitic PNP transistor T1, causing the emitter-base junction of the parasitic PNP transistor T1 to be forward biased. The parasitic PNP transistor T1 turns on, and at this time, a PNPN SCR path is formed, and most of the ESD current is quickly discharged from the SCR.

[0076] More specifically, such as Figure 5 As shown, in the trigger structure 4, the series diode is formed above the semiconductor substrate 1, including an N-well region 41, a P-well region 42, a P-type doped region 43, an N-type doped region 44, and a shallow trench isolation 45. The N-well region 41 and the P-well region 42 are formed above the semiconductor substrate 1, with the P-well region 41 located between adjacent N-well regions 42. The P-type doped region 43 and the N-type doped region 44 are formed above the N-well region 41. The shallow trench isolation 45 is formed at least above the P-well region 42 to isolate the P-type doped region 43 and the N-type doped region 44 between adjacent N-well regions 41. Alternatively, the shallow trench isolation 45 can also be formed outside the series diode. In this embodiment, the number of series diodes N is 3. Therefore, three N-well regions 41 and two P-well regions 42 are formed above the semiconductor substrate 1, and P-type doped regions 43 and N-type doped regions 44 are formed in the three N-well regions 41, respectively.

[0077] Accordingly, such as Figure 6 As shown, this embodiment also provides an ESD protection circuit, which includes at least one ESD protection device as described above, connected between the positive terminal VDD and the negative terminal VSS of the ESD protection circuit; when the number of ESD protection devices is greater than or equal to two, the multiple ESD protection devices are connected in series. By applying the ESD protection device to the ESD protection circuit, the ESD protection capability of the chip can be improved.

[0078] Specifically, such as Figure 6 As shown, the ESD protection circuit further includes: an internal circuit connected between VDD and VSS, a clamping circuit connected in parallel with the internal circuit, and an IO port connected to and led out from the internal circuit.

[0079] Accordingly, this embodiment also provides a method for fabricating an ESD protection device, the method comprising:

[0080] 1) A semiconductor substrate 1 is provided, the semiconductor substrate 1 comprising: a first region 11, a second region 12 and a third region 13;

[0081] 2) An SCR structure 2 with an NMOS transistor is formed in the first region 11, a coupling structure 3 is formed in the second region 12, and a trigger structure 4 is formed in the third region 13;

[0082] In this configuration, one end of the coupling structure 3 is connected to the positive terminal of the SCR structure 2, and the other end is connected to the negative terminal of the SCR structure 2. The coupling voltage output is connected to the gate 21 of the NMOS transistor in the SCR structure. One end of the trigger structure 4 is connected to the positive terminal of the SCR structure 2, and the other end is connected to the base of the parasitic NPN transistor T2 in the SCR structure 2.

[0083] Specifically, the methods for forming the SCR structure 2, coupling structure 3, and triggering structure 4 in step 2) include:

[0084] 2.1) An N-well region 221 and an adjacent P-well region 222 are formed in the first region 11, an N-well region 31 is formed in the second region 12, and N N-well regions and (N-1) P-well regions are formed in the third region 3, wherein the P-well regions are located between adjacent N-well regions.

[0085] 2.2) From left to right, a first N-type doped region 231, a first P-type doped region 232, a second N-type doped region 233, a third N-type doped region 234, a second P-type doped region 235, and a third P-type doped region 236 are formed in the N-well region 221 and P-type doped region 222 of the first region 11; an N-type doped region 321 and a P-type doped region 322 are formed in the N-well region 31 of the second region 12; and a P-type doped region and an N-type doped region are formed in the N-well region of the third region 13. The second N-type doped region 233 is located above the boundary between the N-well region 221 and the P-well region 222, and a channel region 237 is formed between the second N-type doped region 233 and the third N-type doped region 234.

[0086] 2.3) A gate 21 is formed above the channel region 237 of the first region 11, and a resistor R1 is formed above the non-N-well region of the second region 12;

[0087] 2.4) A metal wiring is formed above the structure formed in 2.3) to electrically connect the coupling structure 3, the trigger structure 4 and the SCR structure 2. At the same time, the first N-type doped region 231 is connected to the first P-type doped region 232 and the positive electrode of the SCR structure 2 is led out. The third N-type doped region 234 is connected to the third P-type doped region 236 and the negative electrode of the SCR structure 2 is led out.

[0088] More specifically, in step 2.1), N-type ion implantation is first performed on the semiconductor substrate 1 based on the first mask to form N-well regions in the first region 11, the second region 12, and the third region 13; then, P-type ion implantation is performed on the semiconductor substrate 1 based on the second mask to form P-well regions in the first region 11 and the third region 13. The formation order of the N-well and P-well regions is not limited, and those skilled in the art can choose according to actual conditions. In step 2.2), N-type ion implantation is first performed on the structure obtained in step 2.1) based on the third mask to form N-type doped regions in the first region 11, the second region 12, and the third region 13; then, P-type ion implantation is performed on the structure obtained in step 2.1) based on the fourth mask to form P-type doped regions in the first region 11, the second region 12, and the third region 13. The formation order of the N-type and P-type doped regions is not limited, and those skilled in the art can choose according to actual conditions. In step 2.3), a polysilicon layer is formed on the upper surface of the structure obtained in step 2.2), and then the polysilicon layer is etched based on a fifth mask to form the gate 21 and the resistor R1. In step 2.4), a metal material layer is formed on the upper surface of the structure obtained in step 2.3), and then the metal material layer is etched based on a sixth mask to form metal wiring.

[0089] Specifically, the method further includes the step of forming shallow trench isolation, wherein the shallow trench isolation is formed at least between adjacent doped regions; for the SCR structure 2, the shallow trench isolation 24 is formed at least between the first N-type doped region 231 and the first P-type doped region 232, between the first P-type doped region 232 and the second N-type doped region 233, between the third N-type doped region 234 and the second P-type doped region 235, and between the second P-type doped region 235 and the third P-type doped region 236. Of course, it can also... The shallow trench isolation 34 is formed on the outside of the first N-type doped region 231 and the third P-type doped region 236. For the coupling structure 3, the shallow trench isolation 34 is formed at least between the N-type doped region 32 and the P-type doped region 33, and of course, it can also be formed on the outside of the N-type doped region 32 and the P-type doped region 33. For the trigger structure 4, the shallow trench isolation 45 is formed at least between the P-type doped region 43 and the N-type doped region 44, and of course, it can also be formed on the outside of the N-type doped region 44 and the P-type doped region 43.

[0090] More specifically, the semiconductor substrate 1 is etched using a seventh mask to form shallow trenches, and then the shallow trenches are filled with oxide to form shallow trench isolation; wherein, the step of forming the shallow trench isolation can be performed after step 2.1) and before step 2.2), or after step 2.2) and before step 2.3), which has no impact on this embodiment.

[0091] In summary, the ESD protection device of this invention includes an SCR structure, a trigger structure, and a coupling structure. When a positive ESD pulse is applied to the positive electrode of the SCR structure, the coupling structure pulls up the gate of the NMOS transistor in the SCR structure, causing it to conduct and form a MOS discharge path. Simultaneously, the trigger structure triggers the parasitic NPN transistor T2 in the SCR structure to conduct, which in turn triggers the parasitic PNP transistor T1 in the SCR structure to conduct, forming a PNPN discharge path, thus realizing a dual-trigger SCR protection mechanism. Because the coupling structure raises the gate voltage of the NMOS transistor, the trigger voltage of the ESD discharge pulse is significantly reduced. Moreover, the ESD protection device of this invention maintains its advantage of strong protection capability per unit area. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0092] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. An ESD protection device, characterized in that, The ESD protection device includes: A semiconductor substrate, and an SCR structure with an NMOS transistor, a coupling structure, and a trigger structure formed on the semiconductor substrate; wherein, One end of the coupling structure is connected to the positive terminal of the SCR structure, and the other end is connected to the negative terminal of the SCR structure. The coupling voltage output is connected to the gate of the NMOS transistor in the SCR structure. One end of the trigger structure is connected to the positive terminal of the SCR structure, and the other end is connected to the base of the parasitic NPN transistor in the SCR structure. The coupling structure includes a diode and a resistor. The cathode of the diode is connected to the anode of the SCR structure, and the anode is connected to the gate of the NMOS transistor in the SCR structure. The diode is also connected to the cathode of the SCR structure through the resistor. When there is a positive ESD pulse at the anode of the SCR structure, the coupling structure pulls up the gate voltage of the NMOS transistor in the SCR structure, turning on the NMOS channel and forming a MOS discharge channel. When there is a positive ESD pulse at the anode of the SCR structure, the triggering structure triggers the parasitic NPN transistor in the SCR structure to turn on, which in turn triggers the parasitic PNP transistor in the SCR structure to turn on, forming a PNPN discharge path.

2. The ESD protection device according to claim 1, characterized in that, The SCR structure includes: A well layer is formed above the semiconductor substrate and includes an N-well region and an adjacent P-well region. A doped layer is formed above the well region layer, and from left to right includes: a first N-type doped region, a first P-type doped region, a second N-type doped region, a third N-type doped region, a second P-type doped region, and a third P-type doped region. The second N-type doped region is located above the boundary between the N-well region and the P-well region, and a channel region is formed between the second N-type doped region and the third N-type doped region. A gate is formed above the channel region, and the second N-type doped region, the third N-type doped region, the channel region and the gate together constitute an NMOS transistor; The first N-type doped region is connected to the first P-type doped region and leads out the positive electrode of the SCR structure; the third N-type doped region is connected to the third P-type doped region and leads out the negative electrode of the SCR structure. In this configuration, a parasitic PNP transistor and an N-well parasitic resistor are formed in the N-well region, and a parasitic NPN transistor and a P-well parasitic resistor are formed in the P-well region. The base of the parasitic PNP transistor is connected to the first N-type doped region through the N-well parasitic resistor, the emitter is connected to the first P-type doped region, and the collector is connected to the base of the parasitic NPN transistor. The base of the parasitic NPN transistor is connected to the second P-type doped region and to the third P-type doped region through the P-well parasitic resistor. The emitter is connected to the third N-type doped region, and the collector is connected to the base of the parasitic PNP transistor.

3. The ESD protection device according to claim 2, characterized in that, The SCR structure further includes: shallow trench isolation, formed at least between the first N-type doped region and the first P-type doped region, between the first P-type doped region and the second N-type doped region, between the third N-type doped region and the second P-type doped region, and between the second P-type doped region and the third P-type doped region.

4. The ESD protection device according to claim 1, characterized in that, The triggering structure includes: N diodes connected in series, the anode of the series diodes being connected to the positive terminal of the SCR structure, and the cathode being connected to the base of the parasitic NPN transistor in the SCR structure; wherein, N is a positive integer greater than or equal to 1.

5. The ESD protection device according to claim 4, characterized in that, The sum of the forward voltages of the N series-connected diodes is not less than the voltage difference between the positive and negative terminals of the SCR structure.

6. An ESD protection circuit, characterized in that, The circuit includes: at least one ESD protection device as described in any one of claims 1-5, connected between the positive and negative terminals of the ESD protection circuit; when the number of ESD protection devices is greater than or equal to two, the plurality of ESD protection devices are connected in series.

7. A method for fabricating an ESD protection device, characterized in that, The method for preparing the ESD protection device as described in any one of claims 1-5 includes: 1) A semiconductor substrate is provided, the semiconductor substrate comprising: a first region, a second region and a third region; 2) An SCR structure with an NMOS transistor is formed in the first region, a coupling structure is formed in the second region, and a trigger structure is formed in the third region; In this configuration, one end of the coupling structure is connected to the positive terminal of the SCR structure, and the other end is connected to the negative terminal of the SCR structure. The coupling voltage output is connected to the gate of the NMOS transistor in the SCR structure. One end of the trigger structure is connected to the positive terminal of the SCR structure, and the other end is connected to the base of the parasitic NPN transistor in the SCR structure. The coupling structure includes a diode and a resistor. The cathode of the diode is connected to the positive terminal of the SCR structure, and the anode is connected to the gate of the NMOS transistor in the SCR structure. The diode is also connected to the negative terminal of the SCR structure through the resistor.

8. The method for preparing the ESD protection device according to claim 7, characterized in that, 2) The methods for forming the SCR structure, coupling structure, and triggering structure include: 2.1) An N-well region and an adjacent P-well region are formed in the first region, an N-well region is formed in the second region, and N N-well regions and (N-1) P-well regions are formed in the third region, with the P-well regions located between adjacent N-well regions; 2.2) From left to right, a first N-type doped region, a first P-type doped region, a second N-type doped region, a third N-type doped region, a second P-type doped region, and a third P-type doped region are formed in the N-well region and P-well region of the first region. An N-type doped region and a P-type doped region are formed in the N-well region of the second region. A P-type doped region and an N-type doped region are formed in the N-well region of the third region. The second N-type doped region is located above the boundary between the N-well region and the P-well region, and a channel region is formed between the second N-type doped region and the third N-type doped region. 2.3) A gate is formed above the channel region of the first region, and a resistor is formed above the non-N-well region of the second region; 2.4) A metal wiring is formed above the structure formed in 2.3) to electrically connect the coupling structure, the trigger structure and the SCR structure. At the same time, the first N-type doped region is connected to the first P-type doped region and the positive electrode of the SCR structure is led out. The third N-type doped region is connected to the third P-type doped region and the negative electrode of the SCR structure is led out.

9. The method for preparing the ESD protection device according to claim 8, further comprising: The step of forming shallow trench isolation, wherein the shallow trench isolation is formed at least between adjacent doped regions.

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