A double-wavelength LED epitaxial structure containing V-shaped pits and a preparation method thereof

Abstract

The application provides a LED epitaxial structure containing V-shaped pits and double wavelengths and a preparation method thereof. The LED epitaxial structure comprises a substrate, an N-type gallium nitride layer, a low-temperature gallium nitride layer, a first multi-quantum well layer, a second multi-quantum well layer, a first V-shaped pit and a second V-shaped pit. Two different V-shaped pits change the active light-emitting area from a traditional planar structure to a three-dimensional structure. Two different V-shaped pits can inject into different multi-quantum well layers, so that two different wavelengths of light can be emitted on a single chip. In addition, the quantum barrier layer in the first multi-quantum well layer can provide a high potential barrier to block the recombination of carriers in the first multi-quantum well layer. The In component in the quantum well layer of the first multi-quantum well layer is greater than that in the quantum well layer of the second multi-quantum well layer. Different In components can control the transport path of carriers in different depth V-shaped pits, thereby realizing the uniformity of carrier distribution and solving the problem of uneven mixed light.

Description

Technical Field

[0001] This invention relates to the field of semiconductor optoelectronics, and more specifically, to an LED epitaxial structure with V-shaped pits and dual wavelengths and its fabrication method. Background Technology

[0002] In recent years, LED (Light Emitting Diode) devices have been widely used in lighting, displays, medical devices, and visible light communications due to their advantages such as small size, high efficiency, energy saving, and long lifespan. With technological advancements and improved living standards, people's lighting requirements have shifted from high brightness and high luminous efficacy to more energy-efficient, environmentally friendly, healthy, and intelligent lighting. Since full-spectrum phosphorless lighting can improve the spectral quality of LED lighting and meet these requirements, it has become one of the development trends in LED lighting technology.

[0003] However, multi-chip, multi-color, phosphorless LEDs have problems such as uneven light output due to difficulties in light mixing and high production costs due to complex driving circuits. Therefore, a feasible solution is needed to solve the problem of uneven light mixing when multi-chip, multi-color LEDs are mixed to emit light. Summary of the Invention

[0004] In view of this, to solve the above problems, the present invention provides an LED epitaxial structure with V-shaped craters and a method for fabricating the same, the technical solution of which is as follows:

[0005] An LED epitaxial structure with V-shaped craters and dual wavelengths, the LED epitaxial structure comprising:

[0006] Substrate;

[0007] In a first direction, an N-type gallium nitride layer, a low-temperature gallium nitride layer, a first multiple quantum well layer, and a second multiple quantum well layer are sequentially located on one side of the substrate. The first direction is perpendicular to the substrate and extends from the substrate toward the N-type gallium nitride layer.

[0008] The LED epitaxial structure further includes: a first V-shaped pit and a second V-shaped pit;

[0009] In the first direction, the first V-shaped pit penetrates the first quantum well layer and the second quantum well layer, and extends partially to the low-temperature gallium nitride layer; the second V-shaped pit penetrates the second quantum well layer;

[0010] The first multiple quantum well layer includes a plurality of first stacked film layers sequentially stacked in the first direction;

[0011] The first stacked film layer includes In layers sequentially stacked in the first direction.x Ga (1-x) N quantum well layer, Al y Ga (1-y) N quantum barrier layer and first GaN quantum barrier layer;

[0012] The second multiple quantum well layer includes multiple sets of second stacked film layers sequentially stacked in the first direction;

[0013] The second stacked film layer includes In layers sequentially stacked in the first direction. z Ga (1-z) N-quantum well layer and second GaN quantum barrier layer;

[0014] The In x Ga (1-x) The value of x in the N quantum well layer is greater than that of In. z Ga (1-z) The value of z in the N quantum well layer.

[0015] Preferably, in the above-mentioned LED epitaxial structure with V-shaped pits and dual wavelengths, the first V-shaped pit is an inverted hexagonal pyramidal V-shaped pit, and the second V-shaped pit is an inverted hexagonal pyramidal V-shaped pit.

[0016] Preferably, in the above-mentioned LED epitaxial structure containing V-grooves and dual wavelengths, the LED epitaxial structure further includes:

[0017] A buffer layer, a three-dimensional nucleation layer, and a two-dimensional merging layer are sequentially located on the side of the substrate facing the N-type gallium nitride layer;

[0018] A stress relief layer located between the low-temperature gallium nitride layer and the first multiple quantum well layer;

[0019] The P-type electron blocking layer and the P-type gallium nitride layer are located on the side of the second quantum well layer opposite to the first quantum well layer.

[0020] Preferably, in the above-mentioned LED epitaxial structure with V-shaped pits and dual wavelengths, the P-type electron blocking layer fills the first V-shaped pit and the second V-shaped pit.

[0021] Preferably, in the above-mentioned LED epitaxial structure with V-shaped pits and dual wavelengths, the opening size of the first V-shaped pit ranges from 98nm to 280nm, the depth of the first V-shaped pit in the first direction ranges from 90nm to 200nm, and the density of the first V-shaped pit ranges from 1.5E8 / cm³. 2 -6E8 / cm 2 ;

[0022] The opening size of the second V-shaped pit ranges from 98 nm to 280 nm, the depth of the second V-shaped pit in the first direction ranges from 90 nm to 200 nm, and the density of the second V-shaped pit ranges from 1.5 E8 / cm³. 2 -6E8 / cm 2 .

[0023] Preferably, in the above-mentioned LED epitaxial structure containing V-groove dual wavelengths, the In x Ga (1-x) In the N-quantum well layer, the value of x ranges from 0 to x ≤ 0.5, and the Al y Ga (1-y) In the N quantum barrier layer, the value of y ranges from 0 to 0.5. z Ga (1-z) In the N-quantum well layer, the value of z ranges from 0 to z ≤ 0.5.

[0024] Preferably, in the above-mentioned LED epitaxial structure with V-shaped pits and dual wavelengths, the thickness of the low-temperature gallium nitride layer ranges from 50nm to 400nm, and the In... x Ga (1-x) The thickness of the N quantum well layer ranges from 2nm to 4nm, and the Al y Ga (1-y) The thickness of the N quantum barrier layer ranges from 2nm to 4nm, and the In z Ga (1-z) The thickness of the N quantum well layer ranges from 2nm to 4nm, the thickness of the first GaN quantum barrier layer ranges from 8nm to 15nm, and the thickness of the second GaN quantum barrier layer ranges from 8nm to 15nm.

[0025] Preferably, in the above-mentioned LED epitaxial structure with V-shaped pits and dual wavelengths, the number of periods of the first quantum well layer is in the range of 3-9, and the number of periods of the second quantum well layer is in the range of 3-9.

[0026] A method for fabricating a dual-wavelength LED epitaxial structure containing a V-shaped crater, the method comprising:

[0027] Provide a substrate;

[0028] An N-type gallium nitride layer, a low-temperature gallium nitride layer, a first multiple quantum well layer, and a second multiple quantum well layer are sequentially formed on one side of the substrate.

[0029] The LED epitaxial structure includes a first V-shaped pit and a second V-shaped pit. In a first direction, the first V-shaped pit penetrates the first quantum well layer and the second quantum well layer, and extends partially to the low-temperature gallium nitride layer. The second V-shaped pit penetrates the second quantum well layer. The first direction is perpendicular to the substrate and points from the substrate to the N-type gallium nitride layer.

[0030] The first multiple quantum well layer includes multiple sets of first stacked film layers sequentially stacked in the first direction, and the first stacked film layers include In layers sequentially stacked in the first direction. x Ga (1-x) N quantum well layer, Al y Ga (1-y) N quantum barrier layer and first GaN quantum barrier layer;

[0031] The second multiple quantum well layer includes a plurality of second stacked film layers sequentially stacked in the first direction, and the second stacked film layers include In layers sequentially stacked in the first direction. z Ga (1-z) The N quantum well layer and the second GaN quantum barrier layer, the In x Ga (1-x) The value of x in the N quantum well layer is greater than that of In. z Ga (1-z) The value of z in the N quantum well layer.

[0032] Preferably, in the above-described method for fabricating a dual-wavelength LED epitaxial structure containing a V-shaped pit, before forming the N-type gallium nitride layer, the fabrication method further includes:

[0033] A buffer layer, a three-dimensional nucleation layer, and a two-dimensional merging layer are sequentially formed on the side of the substrate facing the N-type gallium nitride layer.

[0034] Preferably, in the above-described method for fabricating a dual-wavelength LED epitaxial structure containing a V-shaped pit, after forming the low-temperature gallium nitride layer, the fabrication method further includes:

[0035] A stress relief layer is formed on one side of the first multiple quantum well layer on the low-temperature gallium nitride layer.

[0036] Preferably, in the above-described method for fabricating a V-shaped pit dual-wavelength LED epitaxial structure, after forming the second multiple quantum well layer, the fabrication method further includes:

[0037] A P-type electron blocking layer and a P-type gallium nitride layer are sequentially formed on the side of the second quantum well layer away from the first quantum well layer.

[0038] Preferably, in the above-mentioned method for fabricating a dual-wavelength LED epitaxial structure containing a V-shaped pit, the formation of the low-temperature gallium nitride layer includes:

[0039] The low-temperature gallium nitride layer is formed under conditions of 600℃-800℃.

[0040] Compared with the prior art, the beneficial effects achieved by the present invention are as follows:

[0041] This invention provides a dual-wavelength LED epitaxial structure with V-shaped pits and its fabrication method. The LED epitaxial structure includes a substrate, an N-type gallium nitride layer, a low-temperature gallium nitride layer, a first multiple quantum well layer, and a second multiple quantum well layer. The N-type gallium nitride layer has line dislocations. By forming the low-temperature gallium nitride layer, the number of line dislocations increases continuously, thereby forming two different depths of V-shaped pits in at least the first and second multiple quantum well layers. This transforms the active light-emitting region from a traditional planar structure to a three-dimensional structure. Charge carriers can be injected into the first multiple quantum well layer through the first V-shaped pit, and charge carriers can be injected into the second multiple quantum well layer through the second V-shaped pit, thus enabling the emission of two different wavelengths of light on a single chip. Furthermore, the first multiple quantum well layer includes In... x Ga (1-x) N quantum well layer and Al y Ga (1-y) The N-quantum barrier layer, the second multiple quantum well layer includes In z Ga (1-z) N quantum well layer, the Al y Ga (1-y) The N-quantum barrier layer can provide a high barrier to prevent carrier recombination and luminescence in the first multiple quantum well layer, wherein the In x Ga (1-x) The value of x in the N quantum well layer is greater than that of In. z Ga (1-z) The value of z in the N quantum well layer varies. A quantum well layer with a high In composition has a strong hole confinement effect. Different In compositions can control the transport path of charge carriers in V-shaped pits at different depths, thereby achieving uniformity in charge carrier distribution and solving the problem of uneven light mixing. Attached Figure Description

[0042] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0043] Figure 1A schematic diagram of an LED epitaxial structure with V-shaped craters and dual wavelengths provided in an embodiment of the present invention;

[0044] Figure 2 A schematic diagram of another LED epitaxial structure with V-shaped craters and dual wavelengths provided in an embodiment of the present invention;

[0045] Figure 3 This is a schematic flowchart illustrating a method for fabricating a dual-wavelength LED epitaxial structure with a V-shaped crater, as provided in an embodiment of the present invention.

[0046] Figure 4 This is a schematic flowchart illustrating another method for fabricating a dual-wavelength LED epitaxial structure with a V-shaped crater, as provided in an embodiment of the present invention. Detailed Implementation

[0047] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0048] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0049] This invention provides an LED epitaxial structure with V-shaped troughs and dual wavelengths, as referenced. Figure 1 , Figure 1 This is a schematic diagram of a V-groove dual-wavelength LED epitaxial structure provided in an embodiment of the present invention, combined with... Figure 1 The LED epitaxial structure includes:

[0050] Substrate 1; In a first direction A, an N-type gallium nitride layer 2, a low-temperature gallium nitride layer 3, a first quantum well layer 4, and a second quantum well layer 5 are sequentially located on one side of the substrate 1, wherein the first direction A is perpendicular to the substrate 1 and points from the substrate 1 to the N-type gallium nitride layer 2.

[0051] Specifically, in this embodiment of the invention, the substrate 1 includes, but is not limited to, using a Si substrate, a PSS sapphire substrate, or a SiC substrate; the low-temperature gallium nitride layer 3 is located on the side of the N-type gallium nitride layer 2 away from the substrate 1, the first multiple quantum well layer 4 is located on the side of the low-temperature gallium nitride layer 3 away from the N-type gallium nitride layer 2, and the second multiple quantum well layer 5 is located on the side of the first multiple quantum well layer 4 away from the low-temperature gallium nitride layer 3.

[0052] The LED epitaxial structure further includes: a first V-shaped pit 6 and a second V-shaped pit 7; in the first direction A, the first V-shaped pit 6 penetrates the first quantum well layer 4 and the second quantum well layer 5, and extends partially to the low-temperature gallium nitride layer 3; the second V-shaped pit 7 penetrates the second quantum well layer 5.

[0053] Specifically, in this embodiment of the invention, the first V-shaped pit 6 penetrates the first quantum well layer 4 and the second quantum well layer 5, and the first V-shaped pit 6 extends to the low-temperature gallium nitride layer 3 while penetrating the first quantum well layer 4 and the second quantum well layer 5, but the first V-shaped pit 6 does not penetrate the low-temperature gallium nitride layer 3.

[0054] The first multiple quantum well layer 4 includes a plurality of first stacked film layers 41 sequentially stacked in the first direction A; the first stacked film layer 41 includes In layers sequentially stacked in the first direction A. x Ga (1-x) N quantum well layer 411, Al y Ga (1-y) N quantum barrier layer 412 and first GaN quantum barrier layer 413.

[0055] Specifically, in this embodiment of the invention, the first multiple quantum well layer 4 includes N groups of first stacked film layers 41 sequentially stacked in the first direction A; wherein, in the first stacked film layers 41, the Al y Ga (1-y) The N quantum barrier layer 412 is located in the In x Ga (1-x) The N-quantum well layer 411 is located on the side opposite to the substrate 1, and the first GaN quantum barrier layer 413 is located on the Al y Ga (1-y) N quantum barrier layer 412 is away from the In x Ga (1-x) One side of the N-quantum well layer 411.

[0056] The second multiple quantum well layer 5 includes multiple sets of second stacked film layers 51 sequentially stacked in the first direction A; the second stacked film layer 51 includes In layers sequentially stacked in the first direction A. z Ga (1-z) The In x Ga (1-x) In the N quantum well layer 411, the value of x is greater than that of In. z Ga (1-z) The value of z in the N-quantum well layer 511.

[0057] Specifically, in this embodiment of the invention, the second multi-quantum-well layer 5 includes M groups of second stacked film layers 51 sequentially stacked in the first direction A; wherein, in the second stacked film layers 51, the second GaN quantum barrier layer 512 is located in the In z Ga (1-z) The N-quantum well layer 511 is located on the side opposite to the substrate 1.

[0058] As described above, the present invention provides an LED epitaxial structure with dual wavelengths and V-shaped pits. The LED epitaxial structure includes a substrate 1, an N-type gallium nitride layer 2, a low-temperature gallium nitride layer 3, a first multiple quantum well layer 4, a second multiple quantum well layer 5, a first V-shaped pit 6, and a second V-shaped pit 7. The first V-shaped pit 6 penetrates the first multiple quantum well layer 4 and the second multiple quantum well layer 5, and partially extends into the low-temperature gallium nitride layer 3. The second V-shaped pit 7 penetrates the second multiple quantum well layer 5. The two different depths of V-shaped pits transform the active light-emitting region from a traditional planar structure to a three-dimensional structure. Charge carriers can be injected into the first multiple quantum well layer 4 through the first V-shaped pit 6, and into the second multiple quantum well layer 5 through the second V-shaped pit 7, thereby enabling the emission of two different wavelengths of light on a single chip. Furthermore, the first multiple quantum well layer 4 includes In... x Ga (1-x) N quantum well layer 411 and Al y Ga (1-y) N quantum barrier layer 412, the second multiple quantum well layer 5 includes In z Ga (1-z) N quantum well layer 511, the Al y Ga (1-y) The N-quantum barrier layer 412 can provide a high barrier to prevent carrier recombination and luminescence in the first multiple quantum well layer, wherein the In x Ga (1-x) In the N quantum well layer 411, the value of x is greater than that of In. z Ga (1-z) The value of z in the N quantum well layer 511 is important. A quantum well layer with a high In composition has a strong hole confinement effect. Different In compositions can control the transport path of charge carriers in V-shaped pits at different depths, thereby achieving uniformity in charge carrier distribution, solving the problem of uneven light mixing, and optimizing the circuit design.

[0059] Optionally, in another embodiment of the present invention, the first V-shaped pit 6 and the second V-shaped pit 7 in the above-mentioned LED epitaxial structure with V-shaped pits and dual wavelengths are further described in detail below:

[0060] The first V-shaped pit 6 is an inverted hexagonal pyramidal V-shaped pit, and the second V-shaped pit 7 is an inverted hexagonal pyramidal V-shaped pit.

[0061] Specifically, in this embodiment of the invention, the opening region of the inverted hexagonal pyramidal V-shaped pit faces away from the substrate 1, and the tip region of the inverted hexagonal pyramidal V-shaped pit faces the substrate 1; the inverted hexagonal pyramidal V-shaped pit is a three-dimensional carrier structure that can serve as a carrier transport channel. Carriers can be injected into the first multiple quantum well layer 4 through the first V-shaped pit 6, and carriers can be injected into the second multiple quantum well layer 5 through the second V-shaped pit 7.

[0062] The opening size of the first V-shaped pit 6 ranges from 98nm to 280nm, the depth of the first V-shaped pit 6 in the first direction A ranges from 90nm to 200nm, and the density of the first V-shaped pit 6 ranges from 1.5E8 / cm³. 2 -6E8 / cm 2 .

[0063] The opening size of the second V-shaped pit 7 ranges from 98nm to 280nm, the depth of the second V-shaped pit 7 in the first direction A ranges from 90nm to 200nm, and the density of the second V-shaped pit 7 ranges from 1.5E8 / cm³. 2 -6E8 / cm 2 .

[0064] Specifically, in this embodiment of the invention, the opening size of the first V-shaped pit 6 can take any value within the range of 98nm-280nm, for example: the opening size of the first V-shaped pit 6 can be 98nm, 220nm, 280nm, etc.; the opening size of the second V-shaped pit 7 can take any value within the range of 98nm-280nm, for example: the opening size of the second V-shaped pit 7 can be 98nm, 200nm, 280nm, etc.; wherein, the opening sizes of the first V-shaped pit 6 and the second V-shaped pit 7 are not the same, and the opening size of the first V-shaped pit 6 is larger than the opening size of the second V-shaped pit 7.

[0065] The depth of the first V-shaped pit 6 in the first direction A can take any value within the range of 90nm-200nm. For example, the depth of the first V-shaped pit 6 can be 90nm, 175nm, 200nm, etc.; the depth of the second V-shaped pit 7 in the first direction A can take any value within the range of 90nm-200nm. For example, the depth of the second V-shaped pit 7 can be 90nm, 150nm, 200nm, etc.; wherein, the depths of the first V-shaped pit 6 and the second V-shaped pit 7 in the first direction A are not the same, and the depth of the first V-shaped pit 6 is greater than the depth of the second V-shaped pit 7.

[0066] The density of the first V-shaped pit 6 can be 1.5E8 / cm³.2 -6E8 / cm 2 The density can be any value within the range; for example, the density of the first V-shaped pit 6 can be 1.5E8 / cm³. 2 3E8 / cm 2 6E8 / cm 2 etc.; the density of the second V-shaped pit 7 can be 1.5E8 / cm³. 2 -6E8 / cm 2 The density can be any value within the range; for example, the density of the second V-shaped pit 7 can be 1.5E8 / cm³. 2 3E8 / cm 2 6E8 / cm 2 etc.; wherein the densities of the first V-shaped pit 6 and the second V-shaped pit 7 may be the same or different.

[0067] Optionally, in another embodiment of the present invention, the above-mentioned LED epitaxial structure with V-shaped craters and dual wavelengths is further described, referring to... Figure 2 , Figure 2 This is a schematic diagram of another LED epitaxial structure with V-shaped craters and dual wavelengths provided in an embodiment of the present invention, combined with... Figure 2 The LED epitaxial structure further includes:

[0068] A buffer layer 8, a three-dimensional nucleation layer 9, and a two-dimensional merging layer 10 are sequentially located on the side of the substrate 1 facing the N-type gallium nitride layer 2.

[0069] Specifically, in this embodiment of the invention, the buffer layer 8 is an aluminum nitride buffer layer; the three-dimensional nucleation layer 9 is located on the side of the buffer layer 8 away from the substrate 1, and the two-dimensional merging layer 10 is located on the side of the three-dimensional nucleation layer 9 away from the buffer layer 8.

[0070] Stress relief layer 11 located between the low-temperature gallium nitride layer 3 and the first multi-quantum well layer 4.

[0071] Specifically, in this embodiment of the invention, the first V-shaped pit 6 also penetrates the stress relief layer 11. The first V-shaped pit 6 extends to the low-temperature gallium nitride layer 3 after penetrating the first quantum well layer 4, the second quantum well layer 5 and the stress relief layer 11, but the first V-shaped pit 6 does not penetrate the low-temperature gallium nitride layer 3.

[0072] The second quantum well layer 5 has a P-type electron blocking layer 12 and a P-type gallium nitride layer 13 located on the side opposite to the first quantum well layer 4.

[0073] Specifically, in this embodiment of the invention, the P-type electron blocking layer fills the first V-shaped pit and the second V-shaped pit; the P-type gallium nitride layer 13 is located on the side of the P-type electron blocking layer 12 away from the substrate 1; since the effective mass of a hole in the GaN material system is about five times that of an electron, the hole mobility is low and can only be injected into a few quantum wells near the P-type gallium nitride layer 13. It is generally believed that the light emission in a multi-quantum-well LED is mainly in the quantum well region near the P-type gallium nitride. Therefore, setting the second multi-quantum-well layer 5 close to the P-type gallium nitride layer is beneficial for carriers to emit light in the second multi-quantum-well layer 5.

[0074] Optionally, in another embodiment of the present invention, the above-mentioned LED epitaxial structure with V-shaped craters and dual wavelengths is further described in detail below:

[0075] The In x Ga (1-x) In the N-quantum well layer 411, the value of x ranges from 0 to x ≤ 0.5. The Al y Ga (1-y) In the N quantum barrier layer 412, the value of y ranges from 0 to 0.5. z Ga (1-z) In the N-quantum well layer 511, the value of z ranges from 0 to z ≤ 0.5.

[0076] Specifically, in this embodiment of the invention, the In x Ga (1-x) In the N-quantum well layer 411, x can be 0, 0.3, 0.5, etc., and the Al y Ga (1-y) In the N quantum barrier layer 412, y can be 0, 0.3, 0.5, etc., and the In... z Ga (1-z) In the N-quantum well layer 511, z can be 0, 0.3, or 0.5, and the values ​​of x, y, and z can be determined based on the performance of the V-shaped pit dual-wavelength LED epitaxial structure; where In x Ga (1-x) In the N-quantum well layer 411, the value of x is always greater than that of In. z Ga (1-z) The value of z in the N-quantum well layer 511.

[0077] The thickness of the low-temperature gallium nitride layer 3 ranges from 50nm to 400nm, and the In... x Ga (1-x) The thickness of the N quantum well layer 411 ranges from 2 nm to 4 nm, and the Al y Ga (1-y) The thickness of the N quantum barrier layer 412 ranges from 2nm to 4nm, and the In... z Ga(1-z) The thickness of the N quantum well layer 511 ranges from 2nm to 4nm, the thickness of the first GaN quantum barrier layer 413 ranges from 8nm to 15nm, and the thickness of the second GaN quantum barrier layer 512 ranges from 8nm to 15nm.

[0078] Specifically, in this embodiment of the invention, the thickness of the low-temperature gallium nitride layer 3 can take any value within the range of 50nm-400nm, for example: the thickness of the low-temperature gallium nitride layer 3 can be 50nm, 100nm, 250nm, 400nm, etc.; the In x Ga (1-x) The thickness of the N quantum well layer 411 can take any value in the range of 2nm-4nm, for example: the In x Ga (1-x) The thickness of the N quantum well layer 411 can be 2nm, 3nm, 3.5nm, 4nm, etc.; the In z Ga (1-z) The thickness of the N quantum well layer 511 can take any value in the range of 2nm-4nm, for example: the In z Ga (1-z) The thickness of the N-quantum well layer 511 can be 2nm, 3nm, 3.5nm, 4nm, etc.; the thickness of the first GaN quantum barrier layer 413 can take any value in the range of 8nm-15nm, for example: the thickness of the first GaN quantum barrier layer 413 can be 8nm, 10nm, 13.5nm, 15nm, etc.; the thickness of the second GaN quantum barrier layer 512 can take any value in the range of 8nm-15nm, for example: the thickness of the second GaN quantum barrier layer 512 can be 8nm, 10nm, 13.5nm, 15nm, etc.

[0079] The number of periods in the first multiple quantum well layer 4 ranges from 3 to 9, and the number of periods in the second multiple quantum well layer 5 ranges from 3 to 9.

[0080] Specifically, in this embodiment of the invention, the first multiple quantum well layer 4 includes multiple sets of first stacked film layers 41 sequentially stacked in the first direction A, and the number of periods is the number of stacked layers of the first stacked film layers 41; one set of first stacked film layers 41 constitutes one period, and the first multiple quantum well layer 4 of one period includes In layers sequentially stacked in the first direction A. x Ga (1-x) N quantum well layer 411, Al y Ga (1-y) N-quantum barrier layer 412 and first GaN quantum barrier layer 413 Figure 2The first multiple quantum well layer 4 shown includes N sets of first stacked film layers 41 sequentially stacked in the first direction A, where N is the number of periods of the first multiple quantum well layer 4, and the number of periods ranges from 3 to 9.

[0081] For example, if the number of periods of the first multiple quantum well layer 4 is 3, then the first multiple quantum well layer 4 includes In layers sequentially arranged in the first direction A. x Ga (1-x) N quantum well layer 411, Al y Ga (1-y) N-quantum barrier layer 412, first GaN quantum barrier layer 413, In x Ga (1-x) N quantum well layer 411, Al y Ga (1-y) N-quantum barrier layer 412, first GaN quantum barrier layer 413, In x Ga (1-x) N quantum well layer 411, Al y Ga (1-y) N quantum barrier layer 412, first GaN quantum barrier layer 413.

[0082] The second multiple quantum well layer 5 includes multiple sets of second stacked film layers 51 sequentially stacked in the first direction A, and the number of periods is the number of stacked layers of the second stacked film layers 51; one set of second stacked film layers 51 constitutes one period, and the second multiple quantum well layer 5 of one period includes In layers sequentially stacked in the first direction A. z Ga (1-z) N-quantum well layer 511 and second GaN quantum barrier layer 512 Figure 2 The second multiple quantum well layer 5 shown includes M groups of second stacked film layers 51 sequentially stacked in the first direction A, where M is the number of periods of the second multiple quantum well layer 5, and the number of periods ranges from 3 to 9.

[0083] For example, if the number of periods of the second multiple quantum well layer 5 is 3, then the second multiple quantum well layer 5 includes In layers sequentially arranged in the first direction A. z Ga (1-z) N-quantum well layer 511, second GaN quantum barrier layer 512, In z Ga (1-z) N-quantum well layer 511, second GaN quantum barrier layer 512, In z Ga (1-z) N-quantum well layer 511, second GaN quantum barrier layer 512.

[0084] This invention also provides a method for fabricating an LED epitaxial structure containing a V-shaped crater and two wavelengths, as described in the following embodiments. Figure 3 , Figure 3 This is a schematic flowchart illustrating a method for fabricating a dual-wavelength LED epitaxial structure with a V-shaped crater, as provided in an embodiment of the present invention. Figure 3 The preparation method includes:

[0085] S100: Provide a substrate 1.

[0086] Specifically, in step S100, the substrate 1 includes, but is not limited to, a Si substrate, a PSS sapphire substrate, or a SiC substrate.

[0087] S200: An N-type gallium nitride layer 2 and a low-temperature gallium nitride layer 3 are sequentially formed on one side of the substrate 1.

[0088] Specifically, in step S200, the low-temperature gallium nitride layer 3 needs to be formed under a temperature range of 600℃-800℃. For example, the temperature conditions for forming the low-temperature gallium nitride layer 3 can be 600℃, 750℃, 800℃, etc.

[0089] S300: A first multiple quantum well layer 4 and a second multiple quantum well layer 5 are sequentially formed on the side of the low-temperature gallium nitride layer 3 away from the substrate 1.

[0090] The LED epitaxial structure includes a first V-shaped pit 6 and a second V-shaped pit 7. In a first direction A, the first V-shaped pit 6 penetrates the first quantum well layer 4 and the second quantum well layer 5, and extends partially to the low-temperature gallium nitride layer 3. The second V-shaped pit 6 penetrates the second quantum well layer 5. The first direction A is perpendicular to the substrate 1 and points from the substrate 1 to the N-type gallium nitride layer 2.

[0091] Specifically, in step S300, the first V-shaped pit 6 penetrates the first quantum well layer 4 and the second quantum well layer 5, and the first V-shaped pit 6 extends to the low-temperature gallium nitride layer 3 after penetrating the first quantum well layer 4 and the second quantum well layer 5, but the first V-shaped pit 6 does not penetrate the low-temperature gallium nitride layer 3.

[0092] The first multiple quantum well layer 4 includes multiple sets of first stacked film layers 41 sequentially stacked in the first direction A, and the first stacked film layer 41 includes In layers sequentially stacked in the first direction A. x Ga (1-x) N quantum well layer 411, Al y Ga (1-y) N quantum barrier layer 412 and first GaN quantum barrier layer 413.

[0093] The second multiple quantum well layer 5 includes multiple sets of second stacked film layers 51 sequentially stacked in the first direction A, and the second stacked film layers 51 include In layers sequentially stacked in the first direction A. z Ga (1-z) The N quantum well layer 511 and the second GaN quantum barrier layer 512, the In x Ga (1-x) In the N quantum well layer 411, the value of x is greater than that of In. z Ga (1-z) The value of z in the N-quantum well layer 511.

[0094] As described above, this invention provides a method for fabricating a dual-wavelength LED epitaxial structure containing V-shaped pits. The method includes providing a substrate 1, and sequentially forming an N-type gallium nitride layer 2, a low-temperature gallium nitride layer 3, a first multiple quantum well layer 4, and a second multiple quantum well layer 5 on one side of the substrate 1. The N-type gallium nitride layer 2 has line dislocations. By forming the low-temperature gallium nitride layer 3, as the thickness of the low-temperature gallium nitride layer 3 increases, growth stress continuously accumulates in the multiple quantum well layer or near the multiple quantum well layer, thereby... This results in a continuous increase in line dislocations, forming two different depths of V-shaped pits at least in the first quantum well layer 4 and the second quantum well layer 5. The V-shaped pits of different depths are spaced apart to form a V-shaped pit array, transforming the active light-emitting region from a traditional planar structure to a three-dimensional structure. Charge carriers can be injected into the first quantum well layer 4 through the first V-shaped pit 6, and into the second quantum well layer 5 through the second V-shaped pit 7, thus enabling the emission of two different wavelengths of light on a single chip. Furthermore, the first quantum well layer 4 includes In... x Ga (1-x) N quantum well layer 411 and Al y Ga (1-y) N quantum barrier layer 412, the second multiple quantum well layer 5 includes In z Ga (1-z) N quantum well layer 511, the Al y Ga (1-y) The N quantum barrier layer 412 can provide a high barrier to prevent carrier recombination and luminescence in the first multiple quantum well layer 4, wherein the In x Ga (1-x) In the N quantum well layer 411, the value of x is greater than that of In. z Ga (1-z) The value of z in the N quantum well layer 511 is important. A quantum well layer with a high In composition has a strong hole confinement effect. Different In compositions can control the transport path of charge carriers in V-shaped pits at different depths, thereby achieving uniformity in charge carrier distribution, solving the problem of uneven light mixing, and optimizing the circuit design.

[0095] Optionally, in another embodiment of the present invention, the method for fabricating the above-described LED epitaxial structure with V-shaped craters and dual wavelengths is further described, referring to... Figure 4 , Figure 4 A detailed flowchart of a method for fabricating a dual-wavelength LED epitaxial structure with a V-shaped crater provided in this embodiment of the invention is shown below. The fabrication method further includes:

[0096] S400: A buffer layer 8, a three-dimensional nucleation layer 9, and a two-dimensional merging layer 10 are sequentially formed on the side of the substrate facing the N-type gallium nitride layer 2.

[0097] Specifically, step S400 is performed before step S200 to form the N-type gallium nitride layer 2. In step S400, the buffer layer 8 is an aluminum nitride buffer layer. During the formation of the three-dimensional nucleation layer 9, the lattice mismatch between GaN and AlN is used as the driving force. Under a low ammonia atmosphere, a three-dimensional island growth mode is achieved by deposition decomposition. During the formation of the two-dimensional merging layer 10, under a high-temperature high ammonia atmosphere, a lateral growth mode is achieved by diffusion, merging the three-dimensional islands into the GaN plane, thereby reducing the dislocation density.

[0098] S500: A stress relief layer 11 is formed on the side of the low-temperature gallium nitride layer 3 facing the first multiple quantum well layer 4.

[0099] Specifically, step S500 is performed after the formation of the low-temperature gallium nitride layer in step S200. In step S500, the first V-shaped pit 6 also penetrates the stress relief layer 11. The first V-shaped pit 6 extends to the low-temperature gallium nitride layer 3 after penetrating the first quantum well layer 4, the second quantum well layer 5, and the stress relief layer 11, but the first V-shaped pit 6 does not penetrate the low-temperature gallium nitride layer 3. The purpose of forming the stress relief layer 11 is to further open the V-shaped pit and use the relatively low In composition to buffer the stress of the subsequent quantum wells.

[0100] S600: A P-type electron blocking layer 12 and a P-type gallium nitride layer 13 are sequentially formed on the side of the second quantum well layer 5 away from the first quantum well layer 4.

[0101] Specifically, step S600 is performed after the formation of the first V-shaped pit 6 and the second V-shaped pit 7 in step S300. In step S600, the P-type electron blocking layer 12 fills the first V-shaped pit 6 and the second V-shaped pit 7.

[0102] Optionally, this invention illustrates a method for fabricating a V-shaped pit dual-wavelength LED epitaxial structure. This method employs MOCVD (Modular CVD) to fabricate the V-shaped pit dual-wavelength LED epitaxial structure on a Si substrate. Trimethylgallium (TMGa) and triethylgallium (TEGa) are used as Ga sources, ammonia (NH3) as an N source, trimethylindium (TMIn) as an In source, and trimethylaluminum (TMAl) as an Al source. H2 and N2 are used as carrier gases, silane (SiH4) is used as a doping source, magnesium pyrocene (CP2Mg) is used as a P-type doping source, and a graphite disk is used as the carrier disk. The specific implementation process is as follows:

[0103] Step 1: Process the Si substrate.

[0104] Specifically, the Si substrate is hydrogenated for 5 minutes by introducing H2 at a temperature range of 900℃-1150℃. In this embodiment of the invention, the optimal embodiment is to hydrogenate the Si substrate at a high temperature of 1000℃ to remove impurities, scratches, etc. on the substrate surface. An Al layer is pre-deposited on one side of the Si substrate to prevent the Ga element from melting back and corroding the Si substrate.

[0105] Step 2: Form an AlN buffer layer.

[0106] Specifically, the reaction is carried out by introducing NH3 at a temperature range of 600℃-800℃. In this embodiment of the invention, the optimal embodiment is to introduce NH3 at a low temperature of 700℃, which can fix the Al layer on one side of the Si substrate, thereby forming a thin AlN layer. Then, TMAl, SiH4, NH3, H2, and N2 are introduced to grow an AlN buffer layer at a temperature range of 900℃-1150℃. In this embodiment of the invention, the optimal embodiment is to grow the AlN buffer layer at a temperature of 1000℃. The thickness of the AlN buffer layer ranges from 5nm to 50nm, and the molar ratio of Si to Al ranges from 0.05 to 0.5. In this embodiment of the invention, the optimal embodiment is to have an AlN buffer layer thickness of 20nm and a molar ratio of Si to Al of 0.2.

[0107] Step 3: Form a three-dimensional nucleation layer 9.

[0108] Specifically, NH3, H2, and N2 are introduced, and under conditions of a temperature range of 800℃-1000℃, an NH3 composition range of 30%-80%, and a time range of 0.5min-3min, a three-dimensional island growth mode is achieved by using the lattice mismatch between GaN and AlN as the driving force in a low ammonia atmosphere, thereby forming a three-dimensional nucleation layer 9. In the embodiments of the present invention, the formation of the three-dimensional nucleation layer 9 under the conditions of a temperature of 900℃, an NH3 composition of 20%, and a time of 1min is the optimal embodiment.

[0109] Step 4: Form a two-dimensional merged layer 10.

[0110] Specifically, NH3, H2, and N2 are introduced, and under conditions of a temperature range of 900℃-1200℃, an NH3 composition range of 70%-100%, and a time range of 0.5min-3min, in a high-temperature ammonia atmosphere, diffusion is used to achieve a lateral growth mode, merging three-dimensional island-like GaN planes to form the two-dimensional merged layer 10, thereby reducing dislocation density. In this embodiment of the invention, the formation of the two-dimensional merged layer 10 under the conditions of a temperature of 1150℃, an NH3 composition of 80%, and a time of 2min is the optimal embodiment.

[0111] Step 5: Form an N-type gallium nitride layer 2.

[0112] Specifically, TMGa, SiH4, NH3, H2, and N2 are introduced to form the N-type gallium nitride layer 2 at a temperature range of 900℃-1200℃ and a SiH4 concentration of 8E18 / cm3. The thickness of the N-type gallium nitride layer 2 ranges from 1500nm to 2500nm. In this embodiment of the invention, the optimal embodiment is formed at a temperature of 1070℃ with a thickness of 2000nm.

[0113] Step 6: Form a low-temperature gallium nitride layer 3.

[0114] Specifically, by introducing TMGa, NH3, and N2, a low-temperature gallium nitride layer 3 is formed at a temperature range of 600℃-800℃, which can transform dislocation density into V-shaped pits. The thickness of the low-temperature gallium nitride layer 3 ranges from 50nm to 400nm. In this embodiment of the invention, the optimal embodiment is formed at a temperature of 750℃ with a thickness of 100nm.

[0115] Step 7: Form stress relief layer 11.

[0116] Specifically, TEGa, TMI, NH3, H2, and N2 are introduced, and a stress relief layer 11 is formed by growing a 5nm InGaN well layer and a 2nm GaN superlattice barrier layer for 25-35 cycles. The total thickness of the stress relief layer 11 ranges from 150nm to 250nm. In this embodiment, the optimal embodiment is to grow the stress relief layer 11 for 30 cycles with a total thickness of 210nm. The temperature range of the InGaN well layer is 700℃-850℃, and the temperature range of the GaN superlattice barrier layer is 800℃-1000℃. In this embodiment, the optimal embodiment is to have the InGaN well layer at 800℃ and the GaN superlattice barrier layer at 880℃. The purpose is to further open up the V-shaped pit, using the relatively low In composition to buffer the stress of the subsequent quantum well, while the periodic well barrier structure also facilitates current spread.

[0117] Step 8: Form the first multi-quantum well layer 4.

[0118] Specifically, TEGa, TMI, TMAl, SiH4, NH3, H2, and N2 are introduced (to form In). x Ga (1-x) When the N quantum well layer is 411, H2 is not allowed to pass through, Al y Ga (1-y) Si is doped in the N quantum barrier layer 412 and the first GaN quantum barrier layer 413, and In x Ga (1-x) The N quantum well layer 411 has a thickness of 2.5 nm, and Al y Ga (1-y) The total thickness of the N quantum barrier layer 412 and the first GaN quantum barrier layer 413 is 10.5 nm, and the total thickness of the first multi-quantum-well layer 4 ranges from 10 nm to 16 nm; where In x Ga (1-x) The temperature range of the N quantum well layer 411 is 700℃-850℃, Al y Ga (1-y) The temperature of the N quantum barrier layer 412 ranges from 700℃ to 850℃, the Al composition ranges from 0% to 50%, the temperature of the first GaN quantum barrier layer 413 ranges from 800℃ to 1000℃, and the number of well-barrier cycles ranges from 3 to 9.

[0119] In this embodiment of the invention, the total thickness of the first multiple quantum well layer 4 is 13 nm, and In... x Ga (1-x) The temperature of the N quantum well layer 411 is 750℃, Al y Ga (1-y)The optimal embodiment has an N quantum barrier layer 412 temperature of 750°C, an Al composition of 20%, a first GaN quantum barrier layer 413 temperature of 880°C, and a well-barrier period number of 4.

[0120] Step 9: Form the second multiple quantum well layer 5.

[0121] Specifically, TEGa, TMI, SiH4, NH3, H2, and N2 are introduced to grow In. z Ga (1-z) H2 is not allowed in the N-quantum well layer 511, and Si is doped in the second GaN quantum barrier layer 512. z Ga (1-z) The N-quantum well layer 511 is 3 nm thick, the second GaN quantum barrier layer 512 is 11 nm thick, and the total thickness of the second multi-quantum well layer 5 ranges from 10 nm to 16 nm, where In... z Ga (1-z) The temperature of the N quantum well layer 511 ranges from 700℃ to 850℃, the temperature of the second GaN quantum barrier layer 512 ranges from 800℃ to 1000℃, and the number of well / barrier cycles ranges from 3 to 9.

[0122] In this embodiment of the invention, the total thickness of the second multiple quantum well layer 5 is 14 nm, and In... z Ga (1-z) The optimal embodiment has an N quantum well layer 511 temperature of 780°C, a second GaN quantum barrier layer 512 temperature of 880°C, and a well barrier period of 4.

[0123] Step 10: Form a P-type electron blocking layer 12.

[0124] Specifically, the p-type electron blocking layer 12 is a p-type AlGAN electron blocking layer, through which TMAl, TMGa, CP2Mg, NH3, H2, and N2 are introduced, with a temperature range of 850℃-1050℃ and a Mg concentration of 1E19 / cm³. 3 A p-type electron blocking layer 12 is formed under conditions where the Al component ranges from 0% to 50%, and the thickness of the p-type electron blocking layer 12 ranges from 150 nm to 250 nm; in this embodiment of the invention, the conditions are: a temperature of 950 °C and a Mg concentration of 1E19 / cm³. 3 The optimal embodiment is to form a P-type electron blocking layer 12 with an Al composition of 30% and a thickness of 200 nm.

[0125] Step 11: Form a P-type gallium nitride layer 13.

[0126] Specifically, TMGa, CP2Mg, NH3, H2, and N2 are introduced, with the temperature range being 800℃-1200℃ and the Mg concentration ranging from 1E19 / cm³. 3 -4E19 / cm 3 A p-type gallium nitride layer 13 is formed under the following conditions, wherein the thickness of the p-type gallium nitride layer 13 ranges from 200 nm to 600 nm; in this embodiment of the invention, the conditions are: a temperature of 1050 °C and a Mg concentration of 3E19 / cm³. 3 The optimal embodiment is to form a P-type gallium nitride layer 13 under the following conditions, wherein the thickness of the P-type gallium nitride layer 13 is 400 nm.

[0127] Step 12: Perform cooling and annealing treatment to end the growth process.

[0128] In this embodiment of the present invention, the above-mentioned LED epitaxial structure with V-shaped pits and dual wavelengths was tested and chip fabricated. Photoelectric parameter testing by EL showed that, compared with the traditional structure, the V-shaped pit design changed the active light-emitting region from the traditional planar structure to a three-dimensional structure, and added a horizontal PN junction, which can control the carrier transport path and carrier distribution, thereby realizing dual-wavelength light emission. However, there is a problem that the emission peak intensity in the first multiple quantum well layer 4 is relatively weak.

[0129] Optionally, in another embodiment of the present invention, considering the weak emission peak intensity in the first multi-quantum-well layer 4, another embodiment of the present invention also illustrates several optional implementation methods for fabricating LED epitaxial structures with V-shaped pits and dual wavelengths, detailed as follows:

[0130] The first method, based on the above example, for fabricating a dual-wavelength LED epitaxial structure with V-shaped pits, provides another optional implementation for step 6, forming the low-temperature gallium nitride layer 3:

[0131] Specifically, TMGa, NH3, and N2 are introduced to form a low-temperature gallium nitride layer 3 at a temperature range of 600℃-800℃. The thickness of the low-temperature gallium nitride layer 3 ranges from 50nm to 400nm. In this embodiment of the invention, the optimal embodiment is to form the low-temperature gallium nitride layer 3 at a temperature of 600℃ with a thickness of 250nm.

[0132] In this embodiment of the invention, the growth temperature of the low-temperature gallium nitride layer 3 was reduced and the thickness of the low-temperature gallium nitride layer 3 was increased. The scanning electron microscope results showed that, compared with the preparation method of the above example, the size of the V-shaped pit was increased and small-sized V-shaped pits appeared. The EL test results showed that the emission peak intensity of the first multi-quantum well layer 4 near the N-type gallium nitride layer 2 was improved.

[0133] The second method, based on the first example above, provides another optional implementation for step 8, forming the first multiple quantum well layer 4, and step 9, forming the second multiple quantum well layer 5:

[0134] Another optional implementation of step 8 above for forming the first multi-quantum well layer 4 is as follows: TEGa, TMI, TMAl, SiH4, NH3, H2, and N2 are introduced to form In... x Ga (1-x) When the N quantum well layer is 411, H2 is not allowed to pass through, Al y Ga (1-y) Si is doped in the N quantum barrier layer 412 and the first GaN quantum barrier layer 413, and In x Ga (1-x) The N quantum well layer 411 has a thickness of 2.5 nm, and Al y Ga (1-y) The total thickness of the N quantum barrier layer 412 and the first GaN quantum barrier layer 413 is 10.5 nm, and the total thickness of the first multi-quantum-well layer 4 ranges from 10 nm to 16 nm; where In x Ga (1-x) The temperature range of the N quantum well layer 411 is 700℃-850℃, Al y Ga (1-y) The temperature of the N quantum barrier layer 412 ranges from 700℃ to 850℃, the Al composition ranges from 0% to 50%, the temperature of the first GaN quantum barrier layer 413 ranges from 800℃ to 1000℃, and the number of well-barrier cycles ranges from 3 to 9.

[0135] In this embodiment of the invention, the total thickness of the first multiple quantum well layer 4 is 13 nm, and In... x Ga (1-x) The temperature of the N quantum well layer 411 is 750℃, Al y Ga (1-y) The optimal embodiment has an N quantum barrier layer 412 temperature of 750°C, an Al composition that is linearly reduced from 30% to 10%, a first GaN quantum barrier layer 413 temperature of 880°C, and a well-barrier period number of 5.

[0136] Another optional implementation of step 9 above to form the second multi-quantum well layer 5 is as follows: TEGa, TMI, SiH4, NH3, H2, and N2 (for In growth) are introduced. z Ga (1-z) H2 is not allowed in the N-quantum well layer 511, and Si is doped in the second GaN quantum barrier layer 512. z Ga (1-z)The N-quantum well layer 511 is 3 nm thick, the second GaN quantum barrier layer 512 is 11 nm thick, and the total thickness of the second multi-quantum well layer 5 ranges from 10 nm to 16 nm, where In... z Ga (1-z) The temperature of the N quantum well layer 511 ranges from 700℃ to 850℃, the temperature of the second GaN quantum barrier layer 512 ranges from 800℃ to 1000℃, and the number of well / barrier cycles ranges from 3 to 9.

[0137] In this embodiment of the invention, the total thickness of the second multiple quantum well layer 5 is 14 nm, and In... z Ga (1-z) The optimal embodiment has an N quantum well layer 511 temperature of 780°C, a second GaN quantum barrier layer 512 temperature of 880°C, and a well barrier period of 3.

[0138] In this embodiment of the invention, the number of well barrier periods in the first multiple quantum well layer 4 is increased, the number of well barrier periods in the second multiple quantum well layer 5 is decreased, and the Al in the first multiple quantum well layer 4 is made more efficient. y Ga (1-y) The Al content of the N quantum barrier layer 412 is linearly reduced from 30% to 10%. EL test results show that, compared with the preparation method of the first example mentioned above, the emission peak intensity of the first multi-quantum well layer 4 near the N-type gallium nitride layer 2 is improved, and the emission peak intensity is stronger than that of the second multi-quantum well layer 5.

[0139] The foregoing has provided a detailed description of the LED epitaxial structure with V-shaped pits and its fabrication method provided by the present invention. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

[0140] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to the method section.

[0141] It should also be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that elements inherent to a process, method, article, or apparatus that comprises a list of elements, or elements inherent to such processes, methods, articles, or apparatus, are also included. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0142] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An LED epitaxial structure with V-shaped craters and dual wavelengths, characterized in that, The LED epitaxial structure includes: Substrate; In a first direction, an N-type gallium nitride layer, a low-temperature gallium nitride layer, a first multiple quantum well layer, and a second multiple quantum well layer are sequentially located on one side of the substrate. The first direction is perpendicular to the substrate and extends from the substrate toward the N-type gallium nitride layer. The LED epitaxial structure further includes: a first V-shaped pit and a second V-shaped pit; In the first direction, the first V-shaped pit penetrates the first quantum well layer and the second quantum well layer, and extends partially to the low-temperature gallium nitride layer; the second V-shaped pit penetrates the second quantum well layer; in the first direction, the depth of the first V-shaped pit is different from the depth of the second V-shaped pit. The first multiple quantum well layer includes a plurality of first stacked film layers sequentially stacked in the first direction; The first stacked film layer includes In layers sequentially stacked in the first direction. x Ga （1-x） N quantum well layer, Al y Ga （1-y） The N quantum barrier layer and the first GaN quantum barrier layer; the value of x is in the range of 0 ≤ x ≤ 0.5, and the value of y is in the range of 0 ≤ y ≤ 0.5; The second multiple quantum well layer includes multiple sets of second stacked film layers sequentially stacked in the first direction; The second stacked film layer includes In layers sequentially stacked in the first direction. z Ga （1-z） The N-type quantum well layer and the second GaN quantum barrier layer; the value of z is in the range of 0 ≤ z ≤ 0.5; The In x Ga （1-x） The value of x in the N quantum well layer is greater than that of In. z Ga （1-z） The value of z in the N quantum well layer.

2. The LED epitaxial structure according to claim 1, characterized in that, The first V-shaped pit is an inverted hexagonal pyramidal V-shaped pit, and the second V-shaped pit is an inverted hexagonal pyramidal V-shaped pit.

3. The LED epitaxial structure according to claim 1, characterized in that, The LED epitaxial structure also includes: A buffer layer, a three-dimensional nucleation layer, and a two-dimensional merging layer are sequentially located on the side of the substrate facing the N-type gallium nitride layer; A stress relief layer located between the low-temperature gallium nitride layer and the first multiple quantum well layer; The P-type electron blocking layer and the P-type gallium nitride layer are located on the side of the second quantum well layer opposite to the first quantum well layer.

4. The LED epitaxial structure according to claim 3, characterized in that, The P-type electron blocking layer fills the first V-shaped pit and the second V-shaped pit.

5. The LED epitaxial structure according to claim 1, characterized in that, The opening size of the first V-shaped pit ranges from 98 nm to 280 nm, the depth of the first V-shaped pit in the first direction ranges from 90 nm to 200 nm, and the density of the first V-shaped pit ranges from 1.5 E8 / cm³. 2 -6E8 / cm 2 ; The opening size of the second V-shaped pit ranges from 98 nm to 280 nm, the depth of the second V-shaped pit in the first direction ranges from 90 nm to 200 nm, and the density of the second V-shaped pit ranges from 1.5 E8 / cm³. 2 -6E8 / cm 2 .

6. The LED epitaxial structure according to claim 1, characterized in that, The thickness of the low-temperature gallium nitride layer ranges from 50nm to 400nm, and the In... x Ga （1-x） The thickness of the N quantum well layer ranges from 2nm to 4nm, and the Al y Ga （1-y） The thickness of the N quantum barrier layer ranges from 2nm to 4nm, and the In z Ga （1-z） The thickness of the N quantum well layer ranges from 2nm to 4nm, the thickness of the first GaN quantum barrier layer ranges from 8nm to 15nm, and the thickness of the second GaN quantum barrier layer ranges from 8nm to 15nm.

7. The LED epitaxial structure according to claim 1, characterized in that, The number of periods in the first multiple quantum well layer ranges from 3 to 9, and the number of periods in the second multiple quantum well layer also ranges from 3 to 9.

8. A method for fabricating an LED epitaxial structure containing a V-shaped pit and dual wavelengths, characterized in that, The preparation method includes: Provide a substrate; An N-type gallium nitride layer, a low-temperature gallium nitride layer, a first multiple quantum well layer, and a second multiple quantum well layer are sequentially formed on one side of the substrate. The LED epitaxial structure includes a first V-shaped pit and a second V-shaped pit. In a first direction, the first V-shaped pit penetrates the first quantum well layer and the second quantum well layer, and extends partially to the low-temperature gallium nitride layer. The second V-shaped pit penetrates the second quantum well layer. The first direction is perpendicular to the substrate and points from the substrate to the N-type gallium nitride layer. In the first direction, the depth of the first V-shaped pit is different from the depth of the second V-shaped pit. The first multiple quantum well layer includes multiple sets of first stacked film layers sequentially stacked in the first direction, and the first stacked film layers include In layers sequentially stacked in the first direction. x Ga （1-x） N quantum well layer, Al y Ga （1-y） The N quantum barrier layer and the first GaN quantum barrier layer; the value of x is in the range of 0 ≤ x ≤ 0.5, and the value of y is in the range of 0 ≤ y ≤ 0.5; The second multiple quantum well layer includes a plurality of second stacked film layers sequentially stacked in the first direction, and the second stacked film layers include In layers sequentially stacked in the first direction. z Ga （1-z） The N quantum well layer and the second GaN quantum barrier layer, the value of z is in the range of 0 ≤ z ≤ 0.5; the In x Ga （1-x） The value of x in the N quantum well layer is greater than that of In. z Ga （1-z） The value of z in the N quantum well layer.

9. The preparation method according to claim 8, characterized in that, Prior to forming the N-type gallium nitride layer, the fabrication method further includes: A buffer layer, a three-dimensional nucleation layer, and a two-dimensional merging layer are sequentially formed on the side of the substrate facing the N-type gallium nitride layer.

10. The preparation method according to claim 8, characterized in that, After forming the low-temperature gallium nitride layer, the preparation method further includes: A stress relief layer is formed on one side of the first multiple quantum well layer on the low-temperature gallium nitride layer.

11. The preparation method according to claim 8, characterized in that, After forming the second multiple quantum well layer, the fabrication method further includes: A P-type electron blocking layer and a P-type gallium nitride layer are sequentially formed on the side of the second quantum well layer away from the first quantum well layer.

12. The method according to claim 8, characterized in that, The formation of the low-temperature gallium nitride layer includes: The low-temperature gallium nitride layer is formed under conditions of 600℃-800℃.

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