A PWM control device and method of using the same

Abstract

The application provides a PWM control device and a use method thereof. The PWM control device comprises a clock source, a clock interface CLK, a reset interface RESET, an input control interface PWM_CTRL, input parallel bus interfaces PWM_REG0 and PWM_REG1, a logic IP and an output interface PWM_OUT. A clock counter unit is externally selected from a 50M active clock source outside an FPGA hardware, and is frequency-converted to 500MHz through a PLL (phase-locked loop). The clock counting precision can reach 2ns, and the clock stability can reach the 0.2ns level.

Description

Technical Field

[0001] This invention relates to the field of PWM control technology, and in particular to a PWM control device and its usage method. Background Technology

[0002] PWM is a pulse width modulation technique used as an IP core in embedded systems to achieve square wave output. It is widely used in many fields such as measurement, communication, motor control, power control and conversion.

[0003] Currently, PWM signal generation is based on MCUs or dedicated PWM chips, with duty cycles adjustable from 0-100%. However, the periods are generally in the millisecond or microsecond range, and switching is not fast enough, meaning the level transition response time is also in the millisecond range. This insufficient switching speed leads to inadequate control precision for lasers or other controlled devices. For example, Chinese patent CN103870421A discloses an IP core for a combined application of serial interface and PWM based on FPGA, including a serial interface module, a pulse width modulation module, and a connection module. The serial interface module is connected to the pulse width modulation module through the connection module. The serial interface module receives input data, and the connection module converts the input data into timing data and duty cycle data, which are then transmitted to the pulse width modulation module. The pulse width modulation module outputs a PWM wave based on the timing data and duty cycle data. Since the system main frequency is 50MHz and the timer count value ranges from 0 to 65535, the system time for each count is 0.02µs. Therefore, the period of this PWM module can be configured by the user between 5.12µs and 335ms, resulting in low output precision. The PWM output precision directly affects the measurement or control precision of subsequent devices. Therefore, how to design a higher precision PWM control device is an urgent technical problem that needs to be solved. Summary of the Invention

[0004] In view of this, the present invention proposes a PWM control device and its usage method to solve the problem of low output accuracy of existing PWM devices.

[0005] The technical solution of the present invention is implemented as follows: On one hand, the present invention provides a PWM control device, wherein the PWM control device includes: Clock source, clock interface CLK, reset interface RESET, input control interface PWM_CTRL, input parallel bus interfaces PWM_REG0 and PWM_REG1, logic IP, and output interface PWM_OUT; The logic IP includes a PLL (phase-locked loop) unit, a clock counter unit, a clock comparator unit, and a PWM output controller unit; The clock source is electrically connected to the clock interface CLK and is used to generate an external clock signal and send the external clock signal to the PLL unit via the clock interface CLK. The PLL unit is electrically connected to the clock interface CLK and the clock counter unit, and is used to increase the frequency of the external clock signal and send the up-frequency signal HCLK to the clock counter unit. The clock counter unit is electrically connected to the clock comparator unit, and is used for clock increment counting, and sends the counting result to the clock comparator unit; The clock comparator unit is electrically connected to the PWM output controller unit and is used to compare the counting result of the clock counter unit with the two stored pulse width data, and send the comparison result to the PWM output controller unit; The reset interface RESET is electrically connected to the clock comparator unit and the PWM output controller unit, and is used to change the reset signal state to reset the clock comparator unit and the PWM output controller unit when power is on or during an abnormality.

[0006] The input control interface PWM_CTRL is electrically connected to the PWM output controller unit and is used to store the initial level voltage of the PWM and send the initial level voltage of the PWM to the PWM output controller unit. The input parallel bus interfaces PWM_REG0 and PWM_REG1 are electrically connected to the clock comparator unit and are used to store the first pulse width data and the second pulse width data, and send the two pulse width data to the clock comparator unit. The output interface PWM_OUT is electrically connected to the PWM output controller unit and is used to output a voltage level based on the result of the PWM output controller unit. The logic IP is electrically connected to the clock interface CLK, reset interface RESET, input control interface PWM_CTRL, input parallel bus interfaces PWM_REG0 and PWM_REG1, and output interface PWM_OUT. It is used to store the control signals and pulse width data of each interface and control the PWM output to the output interface PWM_OUT.

[0007] Based on the above technical solutions, preferably, the PLL unit receives an external clock signal provided by a clock source, increases the clock frequency through an internal frequency division factor, and outputs an up-frequency signal HCLK to the clock counter unit.

[0008] Based on the above technical solution, preferably, the clock counter unit receives the count reset signal sent by the clock comparator unit, starts receiving the up-frequency signal HCLK output by the PLL unit, performs high-speed clock self-counting, and sends the count count to the clock comparator unit.

[0009] Based on the above technical solution, preferably, the clock comparator unit sends a count reset signal, the clock counter unit starts counting from zero, the clock comparator unit first compares the count of the clock counter unit with the data of the input parallel bus interface PWM_REG0, when the two are equal, the result is output to the PWM output controller unit to change the output level voltage to the output interface PWM_OUT, and at the same time, the clock counter unit sends a count reset signal again, the clock counter unit starts counting from zero again, the clock comparator unit compares the count of the clock counter unit with the data of the input parallel bus interface PWM_REG1, when the two are equal, the result is output to the PWM output controller unit to change the output level voltage to the output interface PWM_OUT, thus forming a standard PWM square wave; In the event of power-on or abnormality, the clock comparator unit is reset by changing the state of the reset signal through the RESET interface.

[0010] Based on the above technical solution, the PWM output controller unit receives the result of the clock comparator unit and changes the output level voltage to the output interface PWM_OUT; In the event of power-on or abnormality, the reset signal state is changed via the RESET interface to reset the PWM output controller unit.

[0011] Based on the above technical solutions, preferably, the clock interface CLK, reset interface RESET, input control interface PWM_CTRL, input parallel bus interfaces PWM_REG0 and PWM_REG1, logic IP, and output interface PWM_OUT are all implemented on the FPGA hardware using Verilog code.

[0012] Based on the above technical solutions, the preferred FPGA hardware is Altera's EP4CE10.

[0013] On the other hand, the present invention provides a method of using a PWM control device, which employs the PWM control device as described above, and includes the following steps: S1. Change the state of the reset signal during power-on or abnormality, and reset the clock comparator unit and PWM output controller unit through the RESET interface; S2. Input control signal to PWM_CTRL interface: Set the output level voltage of PWM output controller unit and output it from output interface PWM_OUT. S3. The clock counter unit receives the count reset signal from the clock comparator unit and starts receiving the external clock signal. Through the PLL unit, it is converted into an up-frequency signal HCLK. The clock counter unit increments the up-frequency signal HCLK clock and sends the count to the clock comparator unit. S4. The first 32-bit pulse width data is input through the parallel bus interface PWM_REG0 and sent to the clock comparator unit. The clock comparator unit compares the count of the clock counter unit with the first 32-bit pulse width data. When the two are equal, the PWM output controller unit changes the output level voltage through the output interface PWM_OUT. At the same time, the clock comparator unit sends a count reset signal to reset the clock counter unit, and the clock counter unit starts clock counting again. The second 32-bit pulse width data is input through the parallel bus interface PWM_REG1. The clock comparator unit compares the count of the clock counter unit with the second 32-bit pulse width data. When the two are equal, the output level voltage is changed again through the output interface PWM_OUT. S5. The clock counter unit continuously increments and compares with the 32-bit pulse width data. When they are equal, the output level is changed. This cycle is repeated to complete the output of the frequency and duty cycle of the continuous PWM square wave.

[0014] The PWM control device and its usage method of the present invention have the following advantages over the prior art: (1) The clock counter unit uses an external 50MHz active clock source selected by the FPGA hardware, which is boosted to 500MHz by a PLL (phase-locked loop). The counting accuracy of each clock can reach 2ns, the clock stability can reach 0.2ns level, the adjustable frequency range of PWM is 0.00193356Hz--250000000Hz, and the duty cycle range is 0.000000023%--99.999999977%; (2) The duration, frequency, and duty cycle of PWM high and low levels are directly based on pulse count, resulting in higher quantization accuracy and a wider adjustable range for frequency and duty cycle, which greatly improves PWM accuracy. (3) By pre-quantizing the calculation and directly configuring the pulse count value using the parallel data interface, there is no temporary floating-point operation during PWM output, which does not occupy the computing resources in the system operation process, resulting in higher efficiency and less impact on the system. It can also avoid the reduction in PWM time accuracy caused by the counting and output control time disturbance caused by temporary complex calculation. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a schematic diagram of the PWM control device module of the present invention; Figure 2 This is a schematic diagram of the working principle of the PWM control device of the present invention. Detailed Implementation

[0017] The technical solutions of the present invention will be clearly and completely described below with reference to the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0018] Example 1 like Figure 1 As shown, a PWM control device of the present invention includes: Clock source, clock interface CLK, reset interface RESET, input control interface PWM_CTRL, input parallel bus interfaces PWM_REG0 and PWM_REG1, logic IP, and output interface PWM_OUT; The logic IP includes a PLL (phase-locked loop) unit, a clock counter unit, a clock comparator unit, and a PWM output controller unit; The clock source is electrically connected to the clock interface CLK and is used to generate an external clock signal and send the external clock signal to the PLL unit via the clock interface CLK. The PLL unit is electrically connected to the clock interface CLK and the clock counter unit, and is used to increase the frequency of the external clock signal and send the up-frequency signal HCLK to the clock counter unit. The clock counter unit is electrically connected to the clock comparator unit, and is used for clock increment counting, and sends the counting result to the clock comparator unit; The clock comparator unit is electrically connected to the PWM output controller unit and is used to compare the counting result of the clock counter unit with the two stored pulse width data, and send the comparison result to the PWM output controller unit; The reset interface RESET is electrically connected to the clock comparator unit and the PWM output controller unit, and is used to change the reset signal state to reset the clock comparator unit and the PWM output controller unit when power is on or during an abnormality.

[0019] The input control interface PWM_CTRL is electrically connected to the PWM output controller unit and is used to store the initial level voltage of the PWM and send the initial level voltage of the PWM to the PWM output controller unit. The input parallel bus interfaces PWM_REG0 and PWM_REG1 are electrically connected to the clock comparator unit and are used to store the first pulse width data and the second pulse width data, and send the two pulse width data to the clock comparator unit. The output interface PWM_OUT is electrically connected to the PWM output controller unit and is used to output a voltage level based on the result of the PWM output controller unit. The logic IP is electrically connected to the clock interface CLK, reset interface RESET, input control interface PWM_CTRL, input parallel bus interfaces PWM_REG0 and PWM_REG1, and output interface PWM_OUT. It is used to store the control signals and pulse width data of each interface and control the PWM output to the output interface PWM_OUT.

[0020] This device uses a logic IP core to implement a high-precision PWM, with pulse width accuracy reaching the nanosecond level. Through design, simulation, and verification, it forms a modular product that can be quickly ported between different platforms, accelerating the product development process.

[0021] The PLL unit receives an external clock signal from a clock source, increases the clock frequency through an internal frequency division factor, and outputs an up-frequency signal HCLK to the clock counter unit.

[0022] The clock source provides an active clock to the logic IP, selecting 50MHz, and sends it to the internal phase-locked loop (PLL) circuit of the logic IP through the clock interface CLK; the PLL unit receives the 50MHz clock provided by the clock source, and increases the output clock frequency to 500MHz through the frequency division factor inside the PLL.

[0023] The clock counter unit receives the count reset signal from the clock comparator unit, starts receiving the up-frequency signal HCLK output by the PLL unit, performs high-speed clock self-counting, and sends the count to the clock comparator unit.

[0024] The clock counter unit uses an external 50MHz active clock source selected by the FPGA hardware, which is then boosted to 500MHz by a PLL unit. Each clock cycle has a counting accuracy of 2ns and a clock stability of 0.2ns, ensuring signal accuracy from the source. The clock counter unit increments the 500MHz boosted signal HCLK starting from 0.

[0025] The clock comparator unit sends a count reset signal, the clock counter unit starts counting from zero, the clock comparator unit first compares the count of the clock counter unit with the data of the input parallel bus interface PWM_REG0, when the two are equal, the result is output to the PWM output controller unit to change the output level voltage to the output interface PWM_OUT, and at the same time, the clock counter unit sends a count reset signal again, the clock counter unit starts counting from zero again, the clock comparator unit compares the count of the clock counter unit with the data of the input parallel bus interface PWM_REG1, when the two are equal, the result is output to the PWM output controller unit to change the output level voltage to the output interface PWM_OUT, thus forming a standard PWM square wave; In the event of power-on or abnormality, the clock comparator unit is reset by changing the state of the reset signal through the RESET interface.

[0026] Upon power-up or in case of an abnormality, the reset signal changes from high to low and is sent to the logic IP for reset via the reset interface; two 32-bit parallel data inputs are input to the clock comparator unit through the parallel bus interfaces PWM_REG0 and PWM_REG1 to realize a complete square wave pulse; by infinitely looping this standard PWM square wave, a continuous PWM square wave is formed. The duration, frequency, and duty cycle of PWM high and low levels are directly based on pulse count, resulting in higher quantization accuracy and a wider adjustable range for frequency and duty cycle, significantly improving PWM accuracy.

[0027] The PWM output controller unit receives the result from the clock comparator unit and changes the output level voltage to the output interface PWM_OUT. In the event of power-on or abnormality, the reset signal state is changed via the RESET interface to reset the PWM output controller unit.

[0028] The input control interface PWM_CTRL controls the voltage level of the first waveform output through a control signal. When the control signal is 0, the output voltage is low; when the control signal is 1, the output voltage is high. When the clock comparator unit compares the count with the parallel data, it changes the output voltage of the PWM output controller unit and outputs it through the output interface.

[0029] The clock interface CLK, reset interface RESET, input control interface PWM_CTRL, input parallel bus interfaces PWM_REG0 and PWM_REG1, logic IP, and output interface PWM_OUT are all implemented on the FPGA hardware using Verilog code.

[0030] It can receive commands sent from an external serial port and is implemented in the NIOS system driver of the FPGA.

[0031] The FPGA hardware uses Altera's EP4CE10.

[0032] An external 50MHz clock source is selected, which is up-frequencyd to 500MHz via a PLL, and the counting accuracy of each clock can reach 2ns.

[0033] The PWM control device in this embodiment uses a logic IP core to implement a nanosecond-level high-precision PWM with a pulse width accuracy of up to the nanosecond level. Through design, simulation, and verification, it forms a modular product that can be quickly ported between different platforms, accelerating the product development process.

[0034] Example 2 A method for using a PWM control device is provided, which employs the PWM control device as described in Embodiment 1, comprising the following steps: S1. Change the state of the reset signal during power-on or abnormality, and reset the clock comparator unit and PWM output controller unit through the RESET interface; S2. Input control signal to PWM_CTRL interface: Set the output level voltage of PWM output controller unit and output it from output interface PWM_OUT. S3. The clock counter unit receives the count reset signal from the clock comparator unit and starts receiving the external clock signal. Through the PLL unit, it is converted into an up-frequency signal HCLK. The clock counter unit increments the up-frequency signal HCLK clock and sends the count to the clock comparator unit. S4. The first 32-bit pulse width data is input through the parallel bus interface PWM_REG0 and sent to the clock comparator unit. The clock comparator unit compares the count of the clock counter unit with the first 32-bit pulse width data. When the two are equal, the PWM output controller unit changes the output level voltage through the output interface PWM_OUT. At the same time, the clock comparator unit sends a count reset signal to reset the clock counter unit, and the clock counter unit starts clock counting again. The second 32-bit pulse width data is input through the parallel bus interface PWM_REG1. The clock comparator unit compares the count of the clock counter unit with the second 32-bit pulse width data. When the two are equal, the output level voltage is changed again through the output interface PWM_OUT. S5. The clock counter unit continuously increments and compares with the 32-bit pulse width data. When they are equal, the output level is changed. This cycle is repeated to complete the output of the frequency and duty cycle of the continuous PWM square wave.

[0035] like Figure 2 As shown, a computer or other serial controller pre-converts the PWM frequency and duty cycle into the duration of high and low levels, then converts the duration into an integer multiple of the minimum pulse unit 2ns, and sends the data to the NIOS memory space via RXD (serial communication) for parameter configuration; the RESET interface can realize the erase and clear control of parameters; the PWM output interface PWM_OUT directly connects the output voltage level to the laser device's IO control port to realize the control of whether the laser output is on or off; By pre-quantizing and directly configuring the pulse count value using a parallel data interface, there are no temporary floating-point operations during PWM output, which does not occupy the computing resources of the system during operation, resulting in higher efficiency and less impact on the system. It also avoids the reduction in PWM timing accuracy caused by counting and output control time disturbances due to temporary complex calculations.

[0036] The PWM control device in this embodiment is implemented using standard Verilog language and a modular design approach. It can receive commands sent from an external serial port and uses the NIOS driver IP core inside the FPGA, which improves flexibility and scalability, enabling the FPGA hardware to generate nanosecond-level high-precision PWM square waves.

[0037] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A PWM control device, characterized in that: The PWM control device includes: Clock source, clock interface CLK, reset interface RESET, input control interface PWM_CTRL, input parallel bus interfaces PWM_REG0 and PWM_REG1, logic IP, and output interface PWM_OUT; The logic IP includes a PLL unit, a clock counter unit, a clock comparator unit, and a PWM output controller unit; The clock source is electrically connected to the clock interface CLK and is used to generate an external clock signal and send the external clock signal to the PLL unit via the clock interface CLK. The PLL unit is electrically connected to the clock interface CLK and the clock counter unit, and is used to increase the frequency of the external clock signal and send the up-frequency signal HCLK to the clock counter unit. The clock counter unit is electrically connected to the clock comparator unit, and is used for clock increment counting, and sends the counting result to the clock comparator unit; The clock comparator unit is electrically connected to the PWM output controller unit and is used to compare the counting result of the clock counter unit with the two stored pulse width data, and send the comparison result to the PWM output controller unit; The reset interface RESET is electrically connected to the clock comparator unit and the PWM output controller unit, and is used to change the reset signal state to reset the clock comparator unit and the PWM output controller unit when power is on or in case of an abnormality. The input control interface PWM_CTRL is electrically connected to the PWM output controller unit and is used to store the initial level voltage of the PWM and send the initial level voltage of the PWM to the PWM output controller unit. The input parallel bus interfaces PWM_REG0 and PWM_REG1 are electrically connected to the clock comparator unit and are used to store the first pulse width data and the second pulse width data, and send the two pulse width data to the clock comparator unit. The output interface PWM_OUT is electrically connected to the PWM output controller unit and is used to output a voltage level based on the result of the PWM output controller unit. The logic IP is electrically connected to the clock interface CLK, reset interface RESET, input control interface PWM_CTRL, input parallel bus interfaces PWM_REG0 and PWM_REG1, and output interface PWM_OUT. It is used to store the control signals and pulse width data of each interface and control the PWM output to the output interface PWM_OUT.

2. The PWM control device as described in claim 1, characterized in that: The PLL unit receives an external clock signal from a clock source, increases the clock frequency through an internal frequency division factor, and outputs the up-frequency signal HCLK to the clock counter unit.

3. The PWM control device as described in claim 2, characterized in that: The clock counter unit receives the count reset signal from the clock comparator unit, starts receiving the up-frequency signal HCLK output by the PLL unit, performs high-speed clock self-counting, and sends the count count to the clock comparator unit.

4. The PWM control device as described in claim 3, characterized in that: The clock comparator unit sends a count reset signal, and the clock counter unit starts counting from zero. The clock comparator unit first compares the count of the clock counter unit with the data of the input parallel bus interface PWM_REG0. When the two are equal, the result is output to the PWM output controller unit to change the output level voltage to the output interface PWM_OUT. At the same time, the clock comparator unit sends a count reset signal to the clock counter unit again, and the clock counter unit starts counting from zero again. The clock comparator unit then compares the count of the clock counter unit with the data of the input parallel bus interface PWM_REG1. When the two are equal, the result is output to the PWM output controller unit to change the output level voltage to the output interface PWM_OUT. Thus, a standard PWM square wave is formed. In the event of power-on or abnormality, the clock comparator unit is reset by changing the state of the reset signal through the RESET interface.

5. The PWM control device as described in claim 4, characterized in that: The PWM output controller unit receives the result from the clock comparator unit and changes the output level voltage to the output interface PWM_OUT. In the event of power-on or abnormality, the reset signal state is changed via the RESET interface to reset the PWM output controller unit.

6. The PWM control device as described in claim 1, characterized in that: The clock interface CLK, reset interface RESET, input control interface PWM_CTRL, input parallel bus interfaces PWM_REG0 and PWM_REG1, logic IP, and output interface PWM_OUT are all implemented on the FPGA hardware using Verilog code.

7. A method of using the PWM control device as described in any one of claims 1-6, characterized in that: Includes the following steps: S1. Change the state of the reset signal during power-on or abnormality, and reset the clock comparator unit and PWM output controller unit through the RESET interface; S2. Input control signal to PWM_CTRL interface: Set the output level voltage of PWM output controller unit and output it from output interface PWM_OUT. S3. The clock counter unit receives the count reset signal from the clock comparator unit and starts receiving the external clock signal. Through the PLL unit, it is converted into an up-frequency signal HCLK. The clock counter unit increments the up-frequency signal HCLK clock and sends the count to the clock comparator unit. S4. The first 32-bit pulse width data is input through the parallel bus interface PWM_REG0 and sent to the clock comparator unit. The clock comparator unit compares the count of the clock counter unit with the first 32-bit pulse width data. When the two are equal, the PWM output controller unit changes the output level voltage through the output interface PWM_OUT. At the same time, the clock comparator unit sends a count reset signal to reset the clock counter unit, and the clock counter unit starts clock counting again. The second 32-bit pulse width data is input through the parallel bus interface PWM_REG1. The clock comparator unit compares the count of the clock counter unit with the second 32-bit pulse width data. When the two are equal, the output level voltage is changed again through the output interface PWM_OUT. S5. The clock counter unit continuously increments and compares with the 32-bit pulse width data. When they are equal, the output level is changed. This cycle is repeated to complete the output of the frequency and duty cycle of the continuous PWM square wave.

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