Integrated circuit with output driver to compensate for supply voltage variations

Abstract

Embodiments of the present disclosure relate to integrated circuits having output drivers that compensate for supply voltage variations. An integrated circuit includes an output pad, an I / O driver that drives data to the output pad, and a predriver that controls the I / O driver. The integrated circuit includes a maximum voltage generator that receives a first supply voltage and a second supply voltage and outputs a maximum voltage to the predriver that corresponds to the higher of the first supply voltage and the second supply voltage.

Description

Technical Field

[0001] This invention relates to integrated circuits, and more particularly to input / output (I / O) circuits of integrated circuits. Background Technology

[0002] Integrated circuits include I / O pads. I / O pads can receive data from circuits or devices external to the integrated circuit. Integrated circuits include driver circuitry that transfers data from core transistors to the I / O pads external to the integrated circuit. The core transistors process input data and can generate output data. The driver circuitry transfers output data from the core to the I / O pads.

[0003] In many cases, serial interface protocols manage the parameters of data reception and I / O pad conversion. Serial interface protocols can specify a maximum total loopback delay. Total loopback delay corresponds to the time elapsed between the input data received from external circuitry at the I / O pad and the output data provided from the core of the integrated circuit to the I / O pad in response to the input data.

[0004] Variations in the supply voltage can cause the total loop delay of the integrated circuit to exceed the maximum loop delay allowed by the serial interface protocol. If this occurs, a communication failure may exist between the integrated circuit and the external circuitry. Summary of the Invention

[0005] Embodiments of the present invention provide an integrated circuit with an I / O transmitter circuitry that helps maintain a small total loop delay even when there are undesirable variations in the supply voltage. The integrated circuit includes a core supply voltage and an I / O supply voltage. The integrated circuit includes a maximum voltage generator that generates a maximum voltage corresponding to the higher of the core supply voltage and the I / O supply voltage. The integrated circuit provides the maximum voltage to the I / O transmitter circuitry.

[0006] Therefore, if a supply voltage change causes the I / O supply voltage to drop below the core supply voltage, the maximum voltage generator will select the core supply voltage to be supplied to the I / O transmitter circuitry. This ensures that the I / O transistor circuitry will have a sufficiently high supply voltage to drive output data to the I / O pads at a sufficient speed, thereby maintaining a sufficiently small total loop delay. Attached Figure Description

[0007] Figure 1 This is a block diagram of an integrated circuit according to some embodiments.

[0008] Figure 2 This is a block diagram of an integrated circuit including a maximum voltage generator according to some embodiments.

[0009] Figure 3 This is a schematic diagram of a maximum voltage generator according to some embodiments.

[0010] Figure 4 This is a flowchart of a method for operating an integrated circuit according to some embodiments. Detailed Implementation

[0011] In the following description, certain specific details are set forth in order to provide a thorough understanding of the various disclosed embodiments. However, those skilled in the art will recognize that the embodiments may be practiced without one or more of these specific details or using other methods, components, materials, etc., in order to avoid unnecessarily obscuring the description of the embodiments. Furthermore, well-known components and circuitry associated with the memory array are not shown or described in detail to avoid unnecessarily obscuring the description of the embodiments.

[0012] Unless the context otherwise requires, throughout the specification and the following claims, the word “comprising” and its variations, such as “including” and “comprise”, shall be interpreted as having an open-ended, inclusive meaning, i.e., “including but not limited to.” Furthermore, the terms “first,” “second,” and similar sequence indicators shall be interpreted as interchangeable unless the context clearly indicates otherwise.

[0013] Throughout this specification, references to "an embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment. Therefore, the phrases "in one embodiment" or "in an embodiment" appearing throughout this specification do not necessarily refer to the same embodiment. Furthermore, specific features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0014] As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” include plural indicators unless otherwise clearly indicated. It should also be noted that the term “or” is generally used in its broadest sense, meaning “and / or,” unless otherwise clearly indicated.

[0015] Figure 1 This is a block diagram of an integrated circuit 100 according to one embodiment. The integrated circuit 100 includes I / O pads 102, I / O drivers 104, a pre-driver block 106, a core 108, and a maximum voltage generator 110. As will be described in more detail below, the maximum voltage generator 110 helps the components of the integrated circuit 100 compensate for variations in the supply voltage.

[0016] I / O pad 102 is a terminal of integrated circuit 100. I / O pad 102 receives data and other signals from devices outside integrated circuit 100. I / O pad also provides data and other signals to devices outside integrated circuit 100.

[0017] I / O pads 102 can be wire-bonded to pins of the leadframe. Data can be supplied to and received from integrated circuit 100 via pins. Other types of connections can be used to enable external devices to communicate with I / O pads 102 without departing from the scope of this invention.

[0018] Core 108 processes data received from a receiver via I / O pads 102. Core 108 may include processing circuitry. Core 108 may include circuitry for writing data to and reading data from memory. Core 108 may include circuitry for executing software instructions.

[0019] Core 108 may include a large number of transistors coupled together in a complex arrangement. The transistors cooperate to process data, write data to memory, read data from memory, and execute software instructions. The transistors may be coupled together via metal interconnects formed in integrated circuit 100.

[0020] Because a large number of transistors can exist to perform a wide range of tasks, the transistors in core 108 can utilize a significant amount of power. High power usage can lead to the generation of substantial heat. If integrated circuit 100 cannot safely dissipate the heat generated by core 108, this could be problematic.

[0021] To reduce the heat generated by the transistors in core 108, the transistors in core 108 can operate at a relatively low voltage. Specifically, core 108 can operate at the core supply voltage VDDc. The core supply voltage VDDc can be between 1.0V and 2.0V, but other core supply voltages can be used without departing from the scope of this disclosure. A lower core supply voltage value results in a lower amount of power utilized by the transistors in core 108.

[0022] The transistor in core 108 may include a relatively thin gate dielectric. For example, the gate dielectric of the transistor in core 108 may include... and The thickness between. Other thicknesses of the gate dielectric of the transistor in core 108 may be used without departing from the scope of this disclosure.

[0023] The pre-driver block 106 facilitates the transfer of data signals from the core 108 to the I / O driver 104. In one embodiment, the pre-driver block 106 and the I / O driver 104 include one or more PMOS transistors and one or more NMOS transistors. The NMOS and PMOS transistors can be enabled to transfer signals from the core 108 to the I / O pads 102.

[0024] I / O driver 104 provides signals to I / O pads 102. These signals may include data that will be transferred from I / O pads 102 to circuitry or devices outside the integrated circuit 100. I / O driver 104 may include multiple transistors, such as one or more NMOS and PMOS transistors. The NMOS and PMOS transistors can be selectively operated to provide data to I / O pads 102. By selectively enabling the NMOS and PMOS transistors, data can be provided to the I / O pads by modulating the output voltage of the I / O driver between high and low logic values.

[0025] Pre-driver block 106 controls I / O driver 104. Pre-driver block 106 can receive signals and data from core 108. Pre-driver block 106 provides data to I / O pad 102 by selectively controlling the NMOS and PMOS transistors of I / O driver 104 to modulate the output voltage provided by I / O driver 104 to I / O pad 102. The modulated voltage can correspond to the signals and data provided from core 108 to I / O pad 102.

[0026] I / O driver 104 and pre-driver block 106 can operate at I / O supply voltage VDDio. I / O supply voltage VDDio is typically higher than the relatively low core supply voltage VDDc used by core 108. I / O supply voltage VDDio can include values ​​between 2.5V and 5.5V, but other values ​​can be used for I / O supply voltage VDDio without departing from the scope of the invention.

[0027] Because the analog pre-driver block 106 and I / O driver 104 operate at a supply voltage higher than the core voltage supply, the transistors of the analog pre-driver block 106 and I / O driver 104 can have a gate dielectric thickness greater than that of the transistors in the core 108. In one example, the transistors of I / O driver 104 and pre-driver block 106 have a gate dielectric thickness greater than that of the transistors in the core 108. and The thickness of the gate dielectric between them.

[0028] Although the I / O supply voltage VDDio is typically higher than VDDc, in some cases VDDio and VDDc may vary. VDDio may temporarily fall below VDDc. If the pre-driver block 106 is driven by VDDio when VDDio is low, an underdrive situation may occur. Underdrive occurs when the supply voltage to the driving transistor is only slightly greater than or even less than the transistor's threshold voltage. In an underdrive situation, the pre-driver block 106 may not be able to supply a sufficiently high current to properly drive the transistors of the I / O driver 104.

[0029] Underdrive conditions can cause various problems for integrated circuit 100. If the pre-driver block 106 cannot provide sufficient current or voltage to the gate terminals of the transistors in I / O driver 104, then I / O driver 104 may not be able to quickly provide data to I / O pads 102. This may cause the total delay of integrated circuit 100 to exceed the total loopback tolerance specified by the serial interface protocol. Another potential problem is that low current and voltage from the pre-driver block 106 may cause short circuits in I / O driver 104. Transistors in I / O driver 104 that should be turned off may not be completely turned off, resulting in short circuits in the I / O driver.

[0030] To mitigate the risk of underdrive, integrated circuit 100 includes a maximum voltage generator 110. The maximum voltage generator 110 receives the I / O supply voltage VDDio and the core supply voltage VDDc. The maximum voltage generator 110 outputs a maximum voltage signal. The maximum voltage signal is the higher of the I / O supply voltage VDDio and the core supply voltage VDDc. The maximum voltage generator 110 provides the maximum voltage signal to the pre-drive block 106.

[0031] In one embodiment, the maximum voltage generator 110 compares the I / O supply voltage VDDio with the core supply voltage VDDc. The maximum voltage generator 110 selects the higher of the I / O supply voltage VDDio and the core supply voltage VDDc as the maximum voltage signal. The maximum voltage generator 110 supplies the maximum voltage signal to the pre-driver block 106.

[0032] Because the pre-driver block 106 receives the maximum voltage signal, it can control the I / O driver 104 using either of the higher supply voltages. This reduces the risk of underdrive. This helps ensure that the total loopback tolerance according to the serial interface protocol standard is met.

[0033] Figure 2This is a block diagram of an integrated circuit 100 according to one embodiment. The integrated circuit 100 includes I / O pads 102, I / O drivers 104, a pre-driver block 106, a core 108, and a maximum voltage generator 110. Figure 2 In the example, pre-driver block 106 and I / O driver 104 correspond to transmitter block. Pre-driver block 106 controls the transmission from I / O pad 102. Although this disclosure primarily describes the use of a maximum voltage generator 110 with transmission or output circuitry, the principles of this disclosure can also be applied to receiver circuitry that controls the reception of input data from I / O pad 102.

[0034] Core 108 supplies data to pre-driver block 106. Core 108 can supply data via one or more multiplexers. One or more multiplexers can receive data from multiple core outputs. One or more multiplexers supply data to pre-driver block 106 from one of the core outputs at a time. Core 108 is driven by the core supply voltage VDDc.

[0035] The pre-driver block 106 includes a first level shifter 112, a second level shifter 114, a first pre-driver 116, and a second pre-driver 118. Level shifters 112, 114, pre-drivers 116, and 118 all receive a maximum voltage from the maximum voltage generator 110.

[0036] Level shifter 112 receives data values ​​from core 108. The data value received from core 108 is the core supply voltage VDDc. This means that if a data signal corresponding to a data value of 1 is received, the data signal will have the value VDDc. If the data signal has a data value corresponding to 0, the data signal will have a ground value. Level shifter 112 shifts the data signal from VDDc to the maximum voltage. Typically, VDDio is greater than VDDc. Therefore, typically, level shifter 112 shifts the data signal from VDDc to VDDio because the maximum voltage is usually VDDio. However, if for some reason VDDio has dropped below the value of VDDc, the maximum voltage signal will correspond to VDDc, and the level shifter will output the data value at the level of VDDc. This helps to reduce the risk of undervoltage situations where VDDio has been significantly reduced.

[0037] Traditional level shifters perform voltage conversion in one direction. This can mean a low-to-high or high-to-low voltage conversion. In transmitters, a low-voltage VDDc to high-voltage VDDio level shifter is typically used. A traditional level shifter shifts the data signal from VDDc to VDDio. If VDDio drops below VDDc, it will cause an underdrive condition and lead to a malfunction of the level shifter. However, by means of a maximum voltage generator 110, level shifters 112 and 114 avoid this condition and always output the data signal at the maximum voltage value. The operation of level shifter 114 is essentially the same as that of level shifter 112.

[0038] Before describing the function of the pre-driver 116, the I / O driver 104 will be described first. The I / O driver 104 includes a transistor of a first conductivity type P1, such as a PMOS transistor, and a transistor of a second conductivity type N1, such as an NMOS transistor, wherein the second conductivity type is different from the first conductivity type. Transistor P1 has a source terminal connected to VDDio, a gate terminal coupled to the pre-driver 116, and a drain terminal coupled to the I / O pad 102. Transistor N1 has a source terminal coupled to ground, a gate terminal coupled to the pre-driver 118, and a drain terminal coupled to the I / O pad 102.

[0039] If core 108 provides a data value of 1 to be supplied to I / O pad 102, then pre-driver 116 will supply a low voltage to turn on transistor P1. Pre-driver 118 will supply a low voltage to turn off transistor N1. With transistor P1 turned on, I / O pad 102 is connected to VDDio via transistor P1.

[0040] If core 108 provides a data value of 0 to be supplied to I / O pad 102, then pre-driver 116 will supply a high voltage to disconnect transistor P1, and pre-driver 118 will supply a high voltage to turn on transistor N1. When transistor N1 is on, I / O pad 102 is grounded via transistor N1.

[0041] Pre-drivers 116 and 118 carefully drive the gate terminals of transistors P1 and N1 to avoid short circuits. Specifically, pre-drivers 116 and 118 help ensure that transistors P1 and N1 do not turn on simultaneously. If transistors P1 and N1 turn on simultaneously, a short circuit will exist between VDDio and ground. This could result in very high currents that could damage transistors P1 and N1. Therefore, pre-drivers 116 and 118 carefully control the switching rate at the gate terminals of P1 and N1. If a data value of 1 is provided to I / O pad 102, pre-drivers 116 and 118 operate to ensure that transistor N1 is turned off before transistor P1 is turned on. If a data value of 0 is provided to I / O pad 102, pre-drivers 116 and 118 operate to ensure that transistor P1 is turned off before transistor N1 is turned on.

[0042] If the pre-drivers 116 and 118 are driven by a low voltage, there will be a delay in turning on transistors P1 and N1. This is because the gate terminals of transistors P1 and N1 are relatively large, and their gate terminals are rapidly charged using a high current. If the pre-drivers 116 and 118 are supplied with a low voltage, they will not be able to charge the gate terminals of transistors P1 and N1 quickly. This results in a delay in the data supplied to I / O pad 102.

[0043] To ensure that pre-drivers 116 and 118 are not powered by low voltage, a maximum voltage generator 110 provides a maximum voltage to both pre-drivers 116 and 118. As a result, pre-drivers 116 and 118 have a sufficiently large supply voltage to properly drive transistors P1 and N1. This allows the integrated circuit to have a total loop delay that conforms to the total loop delay tolerance specified by the serial interface protocol.

[0044] Figure 3 This is a schematic diagram of a maximum voltage generator 110 according to one embodiment. Figure 3 The maximum voltage generator 110 is Figure 1 This is one embodiment of the maximum voltage generator 110 of the overvoltage protection circuit 112. Other embodiments of the maximum voltage generator 110 may be used without departing from the scope of this disclosure.

[0045] The maximum voltage generator 110 receives the I / O supply voltage VDDio and the core supply voltage VDDc as input signals. The maximum voltage generator 110 outputs a maximum voltage signal VMAX corresponding to the higher voltage between VDDio and VDDc. Therefore, the maximum voltage generator 110 effectively compares the I / O supply voltage VDDio with the core supply voltage VDDc and outputs the higher voltage between VDDc and VDDio.

[0046] The maximum voltage generator 110 includes PMOS transistors P2, PMOS transistor P3, and PMOS transistor P4. PMOS transistors P2, P3, and P4 are coupled together and receive voltage signals at their terminals, causing PMOS transistors P2, P3, and P4 to output VMAX.

[0047] PMOS transistor P4 receives the I / O supply voltage VDDio at its source terminal. PMOS transistor P4 receives the core supply voltage VDDc at its gate terminal. PMOS transistor P4 receives the voltage VMAX at its body terminal. The drain terminal of PMOS transistor P4 is coupled to the drain terminal of PMOS transistor P2 and the source and gate terminals of PMOS transistor P3. The drain terminal of PMOS transistor P4 outputs VMAX. The body terminal connections of the various transistors are not... Figure 3 It is shown in the document, but described here.

[0048] PMOS transistor P2 receives the core supply voltage VDDc at its source terminal. PMOS transistor P2 receives the I / O supply voltage VDDio at its gate terminal. PMOS transistor P2 receives the voltage VMAX at its body terminal.

[0049] PMOS transistor P3 receives VMAX at its gate and source terminals. PMOS transistor P3 receives VDDio at its drain terminal. PMOS transistor P3 receives voltage VMAX at its body terminal.

[0050] If VDDc is greater than VDDio, then PMOS transistor P4 has a positive gate-source voltage. In this state, PMOS transistor P4 is disabled. If VDDc is greater than VDDio, then PMOS transistor P2 has a negative gate-source voltage, and PMOS transistor P2 is enabled. When PMOS transistor P2 is enabled, VDDc is supplied at the drain terminal of PMOS transistor P2. In this case, VDDc is used as VMAX because VDDc is greater than VDDio.

[0051] If VDDio is greater than VDDc, PMOS transistor P2 has a positive gate-source voltage and is disabled. If VDDio is greater than VDDc, PMOS transistor P4 has a negative gate-source voltage. In this state, PMOS transistor P4 is enabled. When PMOS transistor P4 is enabled, VDDio is supplied at its drain terminal. In this case, VDDio is provided as VMAX because VDDio is greater than VDDc.

[0052] The maximum voltage generator 110 supplies VMAX to level shifters 112, 114, pre-driver 116, and pre-driver 118. Figure 3 The maximum voltage generator 110 is one embodiment of a circuit capable of outputting a voltage VMAX corresponding to the higher of VDDc and VDDio. Based on this disclosure, those skilled in the art will recognize that other circuit configurations can be used to generate VMAX without departing from the scope of this disclosure.

[0053] Figure 4 This is a flowchart of a method 400 for operating an integrated circuit according to some embodiments. At 402, method 400 includes receiving a first supply voltage and a second supply voltage using a maximum voltage generator of the integrated circuit. At 404, method 400 includes outputting a maximum voltage corresponding to the higher of the first and second supply voltages using the maximum voltage generator. At 406, method 400 includes receiving the maximum voltage using a pre-driver block of the integrated circuit. At 408, method 400 includes controlling the I / O drivers of the integrated circuit using the pre-driver block.

[0054] In one embodiment, an integrated circuit includes an output pad, an output driver coupled to the output pad, and a pre-driver block coupled to the output driver. The integrated circuit includes a maximum voltage generator coupled to the pre-driver block. The maximum voltage generator is configured to receive a core supply voltage and an input / output (I / O) supply voltage and supply a maximum voltage to the pre-driver block.

[0055] In one embodiment, the integrated circuit includes an output pad and an I / O driver coupled to the output pad. The integrated circuit includes a maximum voltage generator that receives a core supply voltage and an I / O supply voltage, and outputs a maximum voltage corresponding to the higher of the core supply voltage and the I / O supply voltage. The integrated circuit includes a core that provides data values ​​and a pre-driver block that receives the data values ​​and the maximum voltage and controls the I / O driver to drive the data values ​​at the output pad.

[0056] In one embodiment, a method includes: receiving a first supply voltage and a second supply voltage using a maximum voltage generator of an integrated circuit; and outputting a maximum voltage corresponding to the higher of the first supply voltage and the second supply voltage using the maximum voltage generator. The method includes receiving the maximum voltage using a pre-driver block of the integrated circuit and controlling the I / O drivers of the integrated circuit using the pre-driver block.

[0057] The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments based on the detailed description above. Generally, the terminology used in the following claims should not be construed as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted to include all possible embodiments and the full scope of the authorized equivalents of these claims. Therefore, the claims are not limited to this disclosure.

Claims

1. An integrated circuit, comprising: Output pads; An output driver is coupled to the output pad; The pre-driver block is coupled to the output driver; as well as A maximum voltage generator, coupled to the pre-driver block, wherein the maximum voltage generator is configured to receive a core supply voltage and an input / output (I / O) supply voltage, compare the core supply voltage with the I / O supply voltage, select a maximum voltage corresponding to the higher of the core supply voltage and the I / O supply voltage based on the comparison, and supply the maximum voltage to the pre-driver block, wherein the maximum voltage generator includes: The first transistor receives the I / O supply voltage at its source terminal and the core supply voltage at its gate terminal; The second transistor receives the core supply voltage at the source terminal and the I / O supply voltage at the gate terminal; The output is coupled to the drain terminal of the first transistor; and The third transistor has a source terminal coupled to the output, a gate terminal coupled to the output, and a drain terminal for receiving the I / O supply voltage.

2. The integrated circuit of claim 1, further comprising a core, the core including a plurality of core transistors powered by a supply voltage from the core.

3. The integrated circuit of claim 2, wherein the pre-driver block is coupled to the core, receives data from the core, and controls the driver to output the data on the output pad.

4. The integrated circuit of claim 3, wherein the pre-driver block includes a first level shifter that receives the maximum voltage signal and the data, and shifts the data to the level of the maximum voltage signal.

5. The integrated circuit of claim 4, wherein the pre-driver block includes a first pre-driver coupled to the first level shifter, wherein the first pre-driver receives the level-shifted data from the first level shifter and receives the maximum voltage signal, and the first pre-driver controls the I / O driver based on the level-shifted data.

6. The integrated circuit of claim 5, wherein the pre-driver block includes a second level shifter that receives the maximum voltage signal and complementary data from the core and shifts the complementary data to the level of the maximum voltage signal, wherein the complementary data is a logical complement of the data.

7. The integrated circuit of claim 6, wherein the pre-driver block includes a second pre-driver coupled to the second level shifter, wherein the second pre-driver receives the level-shifted complementary data from the second level shifter and receives the maximum voltage signal, and the second pre-driver controls the I / O driver based on the level-shifted complementary data.

8. The integrated circuit of claim 7, wherein the I / O driver comprises: A PMOS transistor having a source terminal coupled to the I / O supply voltage, a drain terminal coupled to the output pad, and a gate terminal coupled to the first pre-driver; as well as An NMOS transistor having a source terminal coupled to ground, a drain terminal coupled to the output pad, and a gate terminal coupled to the second pre-driver.

9. The integrated circuit of claim 8, wherein the first pre-driver controls the switching rate of the gate terminal of the PMOS transistor based on the level-shifted data.

10. The integrated circuit of claim 9, wherein the second pre-driver controls the switching rate of the gate terminal of the NMOS transistor based on the level-shifted complementary data.

11. An integrated circuit, comprising: Output pads; I / O drivers, coupled to the output pads; A maximum voltage generator receives the core supply voltage and the I / O supply voltage, and outputs a maximum voltage corresponding to the higher of the core supply voltage and the I / O supply voltage. The core provides data values; as well as A pre-driver block receives the data value and the maximum voltage, and controls the I / O driver to drive the data value at the output pad; The maximum voltage generator mentioned above includes: The first transistor receives the I / O supply voltage at its source terminal and the core supply voltage at its gate terminal; The second transistor receives the core supply voltage at the source terminal and the I / O supply voltage at the gate terminal; The output is coupled to the drain terminal of the first transistor; and The third transistor has a source terminal coupled to the output, a gate terminal coupled to the output, and a drain terminal for receiving the I / O supply voltage.

12. A method for operating an integrated circuit, comprising: The first and second supply voltages are received using the maximum voltage generator of the integrated circuit. The first supply voltage is compared with the second supply voltage using the maximum voltage generator; Using the maximum voltage generator, the maximum voltage corresponding to the higher of the first supply voltage and the second supply voltage is output based on the comparison; The maximum voltage is received using the pre-driver block of the integrated circuit; as well as The pre-driver block is used to control the I / O drivers of the integrated circuit; The maximum voltage generator mentioned above includes: The first transistor receives the I / O supply voltage at its source terminal and the core supply voltage at its gate terminal; The second transistor receives the core supply voltage at the source terminal and the I / O supply voltage at the gate terminal; The output is coupled to the drain terminal of the first transistor; and The third transistor has a source terminal coupled to the output, a gate terminal coupled to the output, and a drain terminal for receiving the I / O supply voltage.

13. The method of claim 12, further comprising: Data is received from the core of the integrated circuit using the level shifter of the pre-driver block; The maximum voltage is received using the level shifter. as well as The data level is shifted to the level of the maximum voltage.

14. The method of claim 13, further comprising: The level-shifted data and the maximum voltage are received using the pre-driver of the pre-driver block; as well as The pre-driver controls the I / O driver to drive the data onto the output pads of the integrated circuit based on the level-shifted data and the maximum voltage.

15. The method of claim 14, further comprising: The pre-driver controls the gate terminal of the transistor of the I / O driver based on the level shift data.

Images