Systems and methods for testing and configuring FPGAs

Abstract

Configuration values ​​for lookup tables (LUTs) and programmable routing switches in an FPGA are provided through a series of trigger circuits arranged in a shift register. This shift register can receive test values ​​in factory test mode and operational configuration values ​​in operational mode (implementing whatever functionality the customer requires for the FPGA). A bitstream is provided at one end of the shift register and timed until the last trigger circuit receives its value. The value can also be timed at the other end of the shift register to compare with the initial bitstream to identify stored values, for example, errors due to radiation exposure. A clock gate architecture is proposed for loading data into or reading data from a specific selected shift register.

Description

[0001] This application is a divisional application of the same patent application, filed on October 7, 2016, with application number 201680007693.4. Technical Field

[0002] This invention relates to programmable logic devices, and more particularly, to field-programmable gate array devices. Background Technology

[0003] An FPGA is a programmable logic device. They are typically based on standard programmable logic blocks, which are arranged in large numbers to perform various functions.

[0004] Figure 1 An example of an FPGA system known in the prior art is illustrated schematically.

[0005] like Figure 1 As shown, the FPGA chip 10 includes a plurality of logic blocks 11, such as those described above. The chip also includes a plurality of input / output ports 12. Connecting these logic blocks 11 and the input / output ports 12 are a plurality of tracks 14. Connection points for these tracks and a plurality of programmable routing regions 13 are provided. Within these programmable routing regions, switches are provided that can selectively connect any pair of cross tracks under the control of logic values ​​stored in memory cells connected to each switch. The switch memory values ​​are set according to non-volatile memory during system initialization. Therefore, by setting the values ​​in the switch memory as required, any connection of any logic block can be coupled to any other logic block, or to those connections in any input / output port 12. Thus, by appropriately configuring the memory cells to define the operation of each logic block and the switch memory 13 to establish suitable connections between the logic blocks, any desired functionality can be achieved.

[0006] Figure 2 Further details of the components of an FPGA system known in the prior art are shown.

[0007] Figure 2 The components shown are configured regarding Figure 1 A representative example of a partial implementation of the functionality described above.

[0008] like Figure 2As shown, a first lookup table (LUT) 21 and a second lookup table (LUT) 22 are provided, along with a number of additional LUTs (not shown). The first LUT 21 comprises seven two-input multiplexers 211, 212, 213, 214, 215, 216, and 217. The second LUT and the additional LUTs are configured similarly. These multiplexers are arranged in three rows in a cascaded manner to form an 8-input multiplexer whose output constitutes the output of the LUT. The first row (211, 213, 215, and 217) of the multiplexers in each cascaded arrangement has a total of eight inputs. These eight inputs constitute the programming inputs of the first LUT 21. The selection inputs of each row are combined together to form the three data inputs of the LUT. The data inputs and data outputs of the first LUT are connected to a set of tracks 2501 and 2502. The inputs and outputs of the second and additional LUTs are connected accordingly to a network of additional tracks (not shown). Conventionally, a LUT with three data inputs in this manner is called "LUT3". Each of the eight programming inputs of the first LUT 21 is connected to its respective static RAM memory device 251, 252, 253, 254, 255, 256, 257, 258. The corresponding static RAM memory devices provide configuration inputs (not shown) for the second LUT 22 and other LUTs provided in the system. In operation, these memory devices 251, 252, 253, 254, 255, 256, 257, 258 provide a constant, predetermined logic value to each of the eight programming inputs of each LUT. The contents of each SRAM cell are schematically shown as comprising a latch constructed of two inverters, each receiving the output of the other. This latch has a transistor switch, shifted by word line 23, which allows the value at the output of one of the inverters in the latch to be selectively output to a bit line connected to a respective configuration input of LUT 217, and also to a data line 24 through which the value of the latch can be set. The bit lines of each memory device 251, 252, 253, 254, 255, 256, 257, and 258 are connected to the select bus 24, and the word lines of each memory device 251, 252, 253, 254, 255, 256, 257, and 258 are connected to the data bus 23. During the circuit initialization phase, each memory device 251, 252, 253, 254, 255, 256, 257, and 258 is addressed sequentially, and the desired value is set to the latch discussed in this discussion. Thus, the logical behavior of the LUT in response to any binary value on the three data inputs of the LUT can be defined as required. This is a fundamental concept based on FPGA technology.However, it should be recognized that the functionality of a single logic block comprising two LUT3s is limited, but any arbitrary combination of functions can be achieved by interconnecting many LUTs with appropriate configurations as described above. This interconnection is accomplished through programmable interconnection of data channels 2501, 2502 and additional channels (not shown) carrying data from other LUTs. As shown, while channels 2501 and 2502 are arranged vertically, an additional channel 2503 is provided that intersects with channels 2501 and 2502. A programmable switching unit 26 is provided at the intersection of the respective lines of channels 2501 and 2503. Considering that the intersection of two lines forms a total of four connections in the switching unit, the switching unit includes six transistor switches arranged to establish or disconnect connections between any two of these four connections. Each of these transistor switches is set to open or closed based on values ​​received from respective static memory units 261, 262, 263, 264, 265, and 266. Furthermore, such programmable switching units with corresponding static memory devices are provided at many or all intersections of the tracks (not shown). The static memory devices 261, 262, 263, 264, 265, and 266 shown are equivalent to memory devices 251, 252, 253, 254, 255, 256, 257, and 258, and are connected to the same address and data buses 23 and 24. This allows both the LUT memory devices and the switch memory devices to be addressed sequentially during the circuit initialization phase, and the desired values ​​to the latches discussed can be set so that the behavior of each LUT and its connections to any other LUT can be configured as required.

[0009] WO2012 / 123243 A1, US7463056 B1, US6021513 A, US5432441 A, US8091001 B2, US5675589 A and US5027355 A describe some of the aforementioned aspects.

[0010] Further background information is provided in section 3.22 of Victor Olubunmi Aken'Ova's article entitled "Bridging the Gap between Soft and Hard eFPGA Design" (available at https: / / www.ece.ubc.ca / ~lemieux / publications / akenova-masc2005.pdf).

[0011] While the described method is highly flexible, it should be recognized that the interconnect tracks between LUTs, as well as the address and data buses for memory cells, occupy a significant amount of space. Even in Figure 2 In a highly simplified layout, the number of lines shown is enormous, and this quickly becomes cumbersome in any practical implementation. The need to implement the functionality in the test circuitry (providing it to verify suitable behavior during device manufacturing) further exacerbates this situation, which will require the addition of yet another set of features. Summary of the Invention

[0012] According to a first aspect, a field-programmable gate array (FPGA) capable of implementing logic functions is provided. The FPGA includes a plurality of hardware lookup tables, each lookup table having a selection line or output programmably interconnected with the selection line or output of another lookup table via a plurality of programmable switches. The FPGA is further characterized by including, in a shift register configuration, a plurality of trigger circuits constituting a programmable shift register. Each lookup table has at least one input coupled to the output of its respective trigger circuit, and each programmable switch is coupled to the output of another respective trigger circuit. The FPGA is arranged to operate in a first mode and a second mode, wherein in the first mode the programmable shift register is loaded with a predefined test value, and in the second mode the programmable shift register is loaded with a value implementing the logic function.

[0013] Programming FPGAs with programmable shift registers reduces the space required for addressing memory cells and improves testability through scan chain technology, especially for industrial-scale production targets.

[0014] According to the development of the first aspect, a first trigger circuit in a programmable shift register is coupled to an input multiplexer that receives a predefined test value on a first input and a value on a second input that implements the logic function, and responds to a mode selection signal suitable for feeding a test model or data bit stream to the first trigger circuit.

[0015] This means that certain physical resources can be shared between the two functions without increasing the surface area.

[0016] According to a further development of the first aspect, the programmable shift register is one of a plurality of such programmable shift registers configured to supply different portions of the field programmable gate array.

[0017] Multiple programmable shift registers increase testing flexibility due to the possibility of using a modular approach for organization into the scan chain, and reduce power consumption by timing fewer trigger circuits at any given time.

[0018] As a further development of the first aspect, multiple programmable shift registers are configured to load the predefined test value in the first mode or the value implementing the logic function in the second mode in parallel.

[0019] Loading multiple programmable shift registers in parallel can reduce initialization time and constrain total power consumption by sharing a clock signal.

[0020] According to a further development of the first aspect, multiple programmable shift registers are configured to serially load the predefined test value in the first mode or load the value that implements the logic function in the second mode.

[0021] Serial loading of multiple programmable shift registers simplifies programming and constrains total power consumption.

[0022] As a further development of the first aspect, the field-programmable gate array further includes an addressing system, thereby enabling individual or group addressing of any of the plurality of programmable shift registers to load the predefined test value in the first mode or to load a value implementing the logic function in the second mode.

[0023] The ability to address programmable shift registers individually or in groups increases flexibility and reduces initialization time and power consumption, as it allows addressing only those programmable shift registers that are actually needed for a specific application.

[0024] According to a further development of the first aspect, the addressing system includes a respective addressable clock gate associated with each programmable shift register or group, the clock gate being adapted to provide a clock signal to the programmable shift register associated with it during such addressing.

[0025] Addressing is controlled by clock signals, which reduces power consumption by limiting clock propagation.

[0026] According to a further development of the first aspect, the field-programmable gate array is further adapted to implement a third mode of operation, wherein the value for implementing the logic function loaded into the programmable shift register in the second mode of operation is read back from the programmable shift register for comparison with the value loaded for implementing the logic function in the second mode.

[0027] The possibility of comparing the initial configuration bitstream with the actual configuration in the trigger circuit after the operation phase provides a way to detect erroneous results caused by misconfiguration of configuration values, for example in aerospace, military, or nuclear industry applications.

[0028] According to a second aspect, a method for operating an FPGA is provided, comprising the steps of: instructing a multiplexer having an output coupled to a programmable shift register to selectively receive an input of a configuration value implementing a test protocol, and instructing a plurality of LUT trigger circuits to enter a test configuration, wherein each of the LUT trigger circuits receives an input implementing the test protocol, and wherein the LUT trigger circuits are connected as shift registers. The programmable shift register is then timed to load a first set of elements having an LUT configuration value belonging to the configuration value implementing the test protocol, and a second set of elements having a routing switch configuration belonging to the configuration value implementing the test protocol. The plurality of LUT trigger circuits are then instructed to enter an operating configuration, wherein each of the LUT trigger circuits receives an input from the outputs of the plurality of LUTs respectively, and then applies the data input to the plurality of LUTs. The LUT trigger circuits are then timed to sample the output of each of the LUTs into its respective trigger circuit, the output being responsive to the test protocol and the data input. The LUT trigger circuit is then instructed to enter a test configuration, wherein the LUT trigger circuit is connected in the LUT shift register and is connected as a shift register, and the LUT trigger circuit is timed to read the value of the LUT shift register, which includes the output of the LUT in response to the test protocol and the data input.

[0029] According to a third aspect, a method for operating an FPGA is provided, comprising the steps of: instructing a multiplexer having an output coupled to a programmable shift register to select receiving an input of a configuration value implementing a logic function, and instructing a plurality of LUT trigger circuits to enter an operational configuration, wherein each of the LUT trigger circuits receives an input from the output of a LUT, respectively. The method then times the programmable shift register to load a first set of elements having an LUT configuration value belonging to the configuration value implementing the logic function, and loads a second set of elements of the shift register having a routing switch configuration belonging to the configuration value implementing the logic function.

[0030] According to the third aspect of the development, the method includes the additional steps of: implementing the output of the first programmable shift register as the programmable shift register, and repeating the timing and indication steps for use in another of the programmable shift registers.

[0031] According to a fourth aspect, a method for operating an FPGA is provided, comprising the steps of: timing a first programmable shift register to read out a first set of elements having LUT configuration values ​​that implement the logic function, and reading out a second set of elements of the shift register having routing switch configurations that implement the logic function.

[0032] According to the fourth aspect of the development, the method includes the additional steps of: implementing the output of the first programmable shift register as the programmable shift register, and repeating the timing step for use in another programmable shift register.

[0033] According to an additional development of the fourth aspect, the method includes the additional step of comparing the LUT configuration and routing switch configuration that implement the logic function when reading from the programmable shift register with the original LUT configuration and routing switch configuration that implement the logic function when writing to the shift register.

[0034] According to a fifth aspect of the invention, a computer program suitable for implementing the steps of the method of the second or third aspect is provided.

[0035] Implementing this method in a computer program provides a convenient mechanism for integrating with FPGAs on flexible and standardized platforms and for implementing the present invention.

[0036] According to a sixth aspect of the present invention, a computer-readable medium comprising a computer program of the fifth aspect is provided. Attached Figure Description

[0037] The above and other advantages of the present invention will now be described with reference to the accompanying drawings, in which:

[0038] Figure 1 An example of a known FPGA system in the prior art is illustrated schematically;

[0039] Figure 2 Further details of the components of an FPGA system known in the prior art are shown;

[0040] Figure 3 Elements of an FPGA system according to an embodiment of the present invention are shown;

[0041] Figure 4 A first configuration for the FPGA circuit system is shown;

[0042] Figure 5 A second configuration for configuring an FPGA circuit system is shown;

[0043] Figure 6 A third configuration for the FPGA circuit system is shown;

[0044] Figure 7 This shows a configuration suitable for reading. Figure 4 Modification of the structure;

[0045] Figure 8 This shows a configuration suitable for reading. Figure 6 Modification of the structure;

[0046] Figure 9 Further details of the operating unit according to another embodiment are shown;

[0047] Figure 10 A method for loading an FPGA according to an embodiment is shown;

[0048] Figure 11 A method for operating an FPGA according to an embodiment is shown;

[0049] Figure 12 A method for verifying an FPGA according to another embodiment is shown;

[0050] Figure 13 A general computing system suitable for implementation of embodiments of the present invention is shown. Detailed Implementation

[0051] Figure 3 Elements of an FPGA system according to an embodiment of the present invention are shown.

[0052] Figure 3 The elements shown constitute the components according to embodiments of the present invention. Figure 1 The above describes a representative example of a partial implementation of some of the functionalities.

[0053] like Figure 3 As shown, a first lookup table (LUT) 21 and a second lookup table (LUT) 22 are provided, as well as a number of other LUTs (not shown). The first LUT 21 includes seven two-input multiplexers 211, 212, 213, 214, 215, 216, and 217 (reference numerals from...). Figure 3 (omitted). A similar configuration is made for the second and subsequent LUTs. These multiplexers are arranged in three rows in a cascaded manner to form an 8-input multiplexer whose output constitutes the LUT output. The first row of multiplexers in each cascaded arrangement (211, 213, 215, and 217) has a total of eight inputs. These eight inputs constitute the programming inputs of the first LUT 21. The selection inputs of each row are combined to form the three data inputs of the LUT. The data inputs and data outputs of the first LUT are connected to a set of tracks 2501, 2502. The inputs and outputs of the second and subsequent LUTs are connected accordingly to additional track networks (not shown). Traditionally, a LUT with three data inputs in this manner is called "LUT3".

[0054] According to this embodiment, each of the eight programming inputs of the first LUT 21 is connected to the Q terminal of the D trigger circuits 3707, 3708, 3709, 3710, 3711, 3712, 3713, and 314, respectively.

[0055] Similarly, the configuration inputs (not shown) of the second LUT 22 and other LUTs provided in the system are provided by additional D trigger circuits (not shown). These trigger circuits, together with trigger circuits 3707, 3708, 3709, 3710, 3711, 3712, 3713, and 314, are arranged to form a programmable shift register 37 by connecting the output Q of each trigger circuit to the input D of the next and combining the clock inputs of each trigger circuit into a single clock line 372. In operation, these memory devices are configured with reference to... Figure 2 In the same manner as the described SRAM device, a constant, predetermined logic value is provided to each of the eight programming inputs of each LUT.

[0056] During the initialization phase of the circuit, codewords corresponding to the expected final value of each trigger circuit in the programmable shift register are input bit by bit into the first trigger circuit 3701 in the programmable shift register, and the timing is performed bit by bit along the programmable shift register until the first bit reaches the last trigger circuit and the first trigger circuit receives its final value.

[0057] Figure 3 The system implementation is similar to the above. Figure 2 The interconnection mechanism described. However, according to this embodiment, each transistor switch of the programmable conversion unit 26 is set to open or close by values ​​received from respective trigger circuits 3701, 3702, 3703, 3704, 3705, 3706 belonging to the programmable shift register 37. Furthermore, such programmable conversion units with corresponding trigger circuit devices are provided at many or all intersections of the tracks (not shown). Therefore, during the circuit initialization phase, the desired final value corresponding to each trigger circuit in the programmable shift register to implement the logic function required by the FPGA is input bit by bit to the first trigger circuit 3701 in the programmable shift register, and timing is performed one bit at a time along the programmable shift register until the first bit reaches the last trigger circuit and the first trigger circuit receives its final value, thereby defining the values ​​of the routing switches and LUT configuration inputs all at once.

[0058] Figure 3The system further includes a multiplexer 38 that switches between two inputs 381 and 382. According to an embodiment, one input 381 may receive a setup stream corresponding to the setup values ​​to be loaded into the programmable shift register 37 to implement the currently used FPGA program, i.e., any arbitrary bit sequence, and may be requested by the user, while the other multiplexer input 382 may receive a setup stream corresponding to the setups required by different system components in the test configuration.

[0059] Replacing SRAM memory cells with D-flash circuits implies an increase in transistor count, and therefore violates standard IC design rules.

[0060] By employing trigger circuits to control the routing switches and LUT configuration inputs, it becomes possible to implement scan chain testing techniques without adding additional trigger circuitry specifically for testing purposes. This not only offsets the aforementioned increase in transistor count but also further simplifies chip design, particularly for routing and controlling the components being tested.

[0061] Furthermore, by eliminating the need for addressing and data buses for a large number of SRAM cells, it is possible to achieve significant savings in chip area that would normally be reserved for these purposes.

[0062] Therefore, a field-programmable gate array (FPGA) capable of implementing logic functions is disclosed. The FPGA includes multiple hardware lookup tables, each lookup table's selection line or output being programmably interconnected with the selection line or output of another lookup table via multiple programmable switches. The FPGA is further characterized by including: multiple trigger circuits in a programmable shift register configuration, each lookup table having at least one input coupled to the output of its respective trigger circuit, and each programmable switch coupled to the output of another respective trigger circuit; and

[0063] The field-programmable gate array is arranged to operate in a first mode, in which the programmable shift register is loaded with a predefined test value, and to operate in a second mode, in which the programmable shift register is loaded with a value that implements the logic function.

[0064] The first trigger circuit in the programmable shift register may be coupled to an input multiplexer that receives the predefined test value on a first input and a value on a second input that implements the logic function, and responds to a mode selection signal suitable for feeding the test model or the data bit stream to the first trigger circuit.

[0065] Although Figure 3A single programmable shift register 37 is shown, but it will be appreciated that multiple or multi-dimensional programmable shift registers may be expected as the proposed mechanism is scaled to include more LUTs and programmable conversion units.

[0066] Therefore, for example, refer to Figure 3 The described programmable shift register may be one of a plurality of such programmable shift registers configured to supply different portions of the field-programmable gate array.

[0067] Such multiple programmable shift registers can be configured to load predefined test values ​​in parallel or serially in a first mode or to load values ​​that implement logical functions in a second mode.

[0068] Those skilled in the art will recognize that, although Figure 3 The system has been highly simplified, but real-world systems will be much more complex without departing from the principles described herein. In particular, each logic block may include more than one LUT and may further include additional logic, such as to support extended functionality or to introduce sequential control. Many such logic blocks can be arranged together as groups.

[0069] Back to reference Figure 1 While track 14, which provides connectivity between tiles in the operating mode, is schematically shown, address and data buses 23 and 24 are not shown and will contribute significantly to the surface area of ​​the device in a real device. Figure 3 The programmable shift register (PFR) arrangement solves this problem because it allows the bitstream for a large number of memory devices to be loaded into a PFR without needing to address each memory cell individually. This is both simpler in terms of operation and less demanding in terms of surface area in terms of addressing and bus tracks. It should be recognized, however, that it may not be desirable to provide a single PFR containing all configuration units for the entire FPGA device, as such a PFR would become unmanageably long and impact clock management, power consumption, etc. Instead, it is possible to employ an approach based on multiple PFRs, each managing configuration settings for a specific part of the chip. This can be achieved with... Figure 2Individual memory cells address the first trigger circuitry in each such programmable shift register or set of programmable shift registers in a similar (or reverse) manner. The choice of length for each programmable shift register then becomes a trade-off between a longer programmable shift register with a simpler bitstream allocation on the one hand, and a shorter programmable shift register with a more complex bitstream allocation on the other hand (which may imply a wider bus and / or more complex addressing). The optimal trade-off in any given case will depend on the semiconductor technology currently in use and the various characteristics of the FPGA circuitry itself.

[0070] Figure 4 A first configuration for configuring an FPGA circuit system is shown. As shown, an operation unit 41 is provided, including one or more LUTs, possibly with auxiliary circuitry and corresponding programmable routing switches, etc. As shown, the operation unit 41 is provided with configuration values ​​by three programmable shift registers 421, 431, and 441, which receive input values ​​from three input connections 422, 432, and 442, and each has its own clocks 451, 452, and 453. Each of the lines 422, 432, and 442 has its own input multiplexer 481, 482, and 483. These multiplexers can be controlled, for example, under software control, to switch between operating bitstreams or test modes, as described above. In an alternative embodiment, multiple programmable shift registers can receive inputs from a single multiplexer. The output of the multiplexer can be dispatched to the respective programmable shift registers by a properly controlled demultiplexer, or it can be addressed, as explained in the following embodiments.

[0071] As shown, the three programmable shift registers have only five trigger circuits; however, it should be recognized that in working implementations, programmable shift registers will typically be significantly longer. Working implementations will also typically include more than three programmable shift registers. The programmable shift registers shown all include the same number of trigger circuits; however, in some cases, a programmable shift register may include any number of trigger circuits.

[0072] The timing of different programmable shift registers must be considered to ensure that the appropriate value arrives at each trigger circuit. This implies that each programmable shift register should receive a number of clock pulses equal to and no more than its length, as further pulses would cause the timed value to advance past its proper destination. One approach to this problem is to define all programmable shift registers as having the same length, such as... Figure 4As shown. Alternatively, in the case of shift registers of different lengths, these shift registers can be associated with a clock management circuitry system suitable for ensuring that each shift register receives a number of clock signals equal to its length during the initial phase. According to a further approach, each programmable shift register can be provided with clock management circuitry suitable for identifying a specific bit sequence that indicates a specific position in the bit stream desired for that shift register, such as the start or end of the bit stream. When the clock manager detects this sequence, it disables the clock entry. This method has the advantage of making each shift register independent and giving designers the freedom to define programmable shift registers of arbitrary sizes. Alternatively, the conversion between signals and the timing of the programmable shift registers can be software-driven.

[0073] Figure 5 A second configuration for configuring an FPGA circuit system is shown. (Example) Figure 5 As shown, around the matrix of logic blocks 511, 512, 513, 514, 515, and 516, there is a similar... Figure 1 The FPGA is constructed using an FPGA-like approach. Each row of logic blocks provides its own programmable shift register, so that logic blocks 511 and 512 receive configuration values ​​from programmable shift register 521, logic blocks 513 and 514 receive configuration values ​​from programmable shift register 531, and logic blocks 515 and 516 receive configuration values ​​from programmable shift register 541. As shown, each of the three programmable shift registers includes six trigger circuits, and each logic block is coupled to three of them. All trigger circuits in the respective programmable shift registers have their common clock input, while each programmable shift register has its own individual clocks 551, 552, and 553.

[0074] As shown, three programmable shift registers have only six trigger circuits, but it should be recognized that in working implementations, programmable shift registers will typically be significantly longer. Working implementations will also typically include more than three programmable shift registers. Programmable shift registers are shown all including the same number of trigger circuits; however, in some cases, each programmable shift register may include any number of trigger circuits, which may be an unacceptable design constraint.

[0075] The timing of different programmable shift registers must be considered to ensure that the appropriate value arrives at each trigger circuit, where the above-discussed principles regarding... Figure 4 A similar approach.

[0076] For example, as described with respect to the foregoing embodiments, multiplexing between the operation bitstream and the test mode can be achieved. For example, as described with respect to the foregoing embodiments, the allocation of the operation bitstream or test mode and their respective clock signals can be performed among programmable shift registers.

[0077] By achieving direct structural consistency between the programmable shift register architecture and the layout of logic blocks, and by applying a structured approach to generating configuration bitstreams, FPGA programming can be facilitated.

[0078] Figure 6 A second configuration for configuring an FPGA circuit system is shown. (Example) Figure 6 As shown, around the matrix of logic blocks 611, 612, 613, 614, 615, and 616, there is a similar... Figure 5 The FPGA is constructed using an FPGA-like approach. Each logic block provides its own programmable shift registers 621, 622, 623, 624, 625, and 626. As shown, each of the six programmable shift registers 621, 622, 623, 624, 625, and 626 includes three trigger circuits that provide configuration values ​​for their associated logic blocks.

[0079] The first trigger circuit of each programmable shift register receives its input on input line 67, which is coupled to the D input of the first trigger circuit of each programmable shift register.

[0080] All trigger circuits in each programmable shift register share a common clock input.

[0081] A single clock distribution network 66 is coupled to the clock line of each programmable shift register via respective clock gates 631, 632, 633, 634, 635, and 636. Each of these clock gates, as shown, has a row select and a column select input, whereby a concurrent logic high on both inputs turns off the switch connecting the clock line of the respective programmable shift register to the clock distribution network 66 to receive clock pulses.

[0082] As shown, there are two column select lines 651 and 652, and three row lines 641, 642, and 643. The select input of each clock gate is connected to different combinations of the column select lines and the row select lines, thereby activating a single clock gate whose row select input and column select input are connected to those two select lines by setting a specific column select line and row select line to logic high.

[0083] Because the data value from the input line will only be propagated through the programmable shift register when a clock input is received, it is possible to selectively program any programmable shift register with a single input line 67 by directing the clock signal to a selected programmable shift register.

[0084] Column select lines 651 and 652 are controlled by column decoder 65, while row select lines 641, 642, and 643 are controlled by row decoder 64. These decoders receive instructions coordinated with the values ​​on input line 67 to address the values ​​on input line 67 to any programmable shift register intended for use. Thus, during the initial phase, Figure 6 The circuit will receive not only the configuration bit stream on line 67 and the clock on line 66, but also the address bit stream at decoders 64 and 65.

[0085] The fact that only a subset of the trigger circuits (i.e., those belonging to the logic blocks programmed to them at a given time) is timed results in a significant reduction in power consumption.

[0086] It should be recognized that in a real system implemented in an FPGA, many logic blocks will be configured identically to achieve a common function. An advantage of this invention is that it can potentially implement clock gates for more than one programmable shift register, allowing the same configuration value to be timed in parallel into several programmable shift registers. This reduces FPGA initialization time and power consumption.

[0087] As shown, the three programmable shift registers have only three trigger circuits; however, it should be recognized that in a working implementation, the programmable shift registers will typically be significantly longer. A working implementation will also typically include more than six logic blocks and correspondingly more than six programmable shift registers. The programmable shift registers are shown all including the same number of trigger circuits; however, because each programmable shift register is timed independently, Figure 6 The same method applies well to arrangements where each programmable shift register may include any number of trigger circuits.

[0088] This addressing function can also be implemented using standard integrated clock gate units or others. In some embodiments, a set or all programmable shift registers can be implemented together with individual addressing.

[0089] By achieving direct structural consistency between the programmable shift register architecture and the layout of logic blocks, and by applying a structured approach to generating configuration bitstreams, FPGA programming can be facilitated.

[0090] It should be recognized that a given FPGA can be divided into independently programmable segments, and that within the same FPGA, there may be various combinations of programmable shift register architectures for different parts (e.g., regarding...). Figure 4 , 5 (As described in 6).

[0091] In some applications, it is desirable to read back configuration settings stored in various configuration memory cells. While in principle these can be expected to be the same as the configuration bitstream provided during system initialization, in practice, there are scenarios where this may not be the case. For example, exposure to ionizing radiation, which can occur in outer space, high-altitude flight, nuclear power, and military applications, can randomly alter values ​​in configuration memory cells, tampering with the results subsequently processed by the FPGA. Comparing the original bitstream with the stored values ​​read from the configuration memory bits provides a means of determining whether this could have occurred.

[0092] Thus, a field-programmable gate array (FPGA) including an addressing system is disclosed, which allows individual addressing of any one of the plurality of programmable shift registers to load the predefined test value in the first mode or to load a value that implements the logic function in the second mode.

[0093] In addition, the addressing system may include a separate addressable clock gate associated with each programmable shift register, which, when addressed in this way, is adapted to provide a clock signal to the programmable shift register associated with it.

[0094] Figure 7 This shows a configuration suitable for reading. Figure 4 Structural modifications. For example... Figure 7 As shown, provided as referenced Figure 4 The same operating unit 41 is described and associated with the same programmable shift registers 421, 431, and 441. As shown, the last trigger circuit of each of the three programmable shift registers provides its output not only to the components of the FPGA circuit system 41 but also to the multiplexer 48. The multiplexer 48 therefore receives input from the last trigger circuit of each of the three programmable shift registers 421, 431, and 441.

[0095] In operation, once the FPGA processing phase is complete and results have been produced, it is desirable to clear the configuration of the configuration trigger circuitry to ensure consistency with the original bitstream as described above. Where desired, the programmable shift registers are timed via clock line 46, and the output of each programmable shift register sampled by multiplexer 48 produces a multiplexed bitstream, which should generally be identical to the original configuration bitstream. The select signal 481 for the multiplier may cause only a polling schedule selection of the three inputs at three times the clock frequency on clock line 46, or, for example, in the case where the programmable shift registers have different lengths, may include a programmed sequence specific to each clock pulse.

[0096] It should be recognized that, Figure 7 The method can be easily applied to Figure 5 The structure.

[0097] Figure 8 This shows a configuration suitable for reading. Figure 6 Structural modifications. For example... Figure 8 As shown, the FPGA is constructed around the same matrix in logic blocks 611, 612, 613, 614, 615, and 616, and each logic block provides information about... Figure 6 The respective programmable shift registers 621, 622, 623, 624, 625, 626 and clock gates 631, 632, 633, 634, 635, 636 are described. As shown, the structure further includes six AND gates 681, 682, 683, 684, 685, 686, each having one input connected to the output of the last trigger circuit of one of the six programmable shift registers 621, 622, 623, 624, 625, 626. A second input to each of the six AND gates 681, 682, 683, 684, 685, 686 is connected to the output of the AND gate of the respective clock gate 631, 632, 633, 634, 635, 636. In this way, the addressable clock implementation mechanism can also be used to selectively implement the operation unit for the output. The outputs of the six AND gates are each connected to their respective inputs of the six OR gates 691, and the outputs of the OR gates 691 are fed to the D input of the output trigger circuit 692.

[0098] In operation, once the FPGA processing phase is complete and results have been produced, it may be desirable to clear the configuration of the configuration trigger circuits to ensure consistency with the original bitstream as described above. Where desired, the implementation line is set to logic high so that the selected AND gate passes the value on the output of the last trigger circuit of each programmable shift register to OR gate 691. The value of the programmable shift register is implemented via row decoder 64 and column decoder 65 in the same manner as for the configuration bitstream input as described above, to either of the clock gates to which it will be output, and the first clock pulse arrives at the selected programmable shift register. If the last trigger circuit in the timing programmable shift register produces a logic high, this causes the respective AND gate output of the received value to be logic high, which is passed through OR gate 691 to the D input of output trigger circuit 692 and stored there until the output trigger circuit receives a clock pulse on input 693, thereby outputting the value on line 684. In this way, by implementing the output via clock gates as described above, timing the programmable shift registers and output trigger circuits in a coordinated manner, the value stored in each configuration programmable shift register can be read and compared with the original bitstream.

[0099] Therefore, the field-programmable gate array can be further adapted to implement a third mode of operation in which the value for implementing the logic function loaded into the programmable shift register in the second mode of operation is read back from the programmable shift register.

[0100] It should be understood that certain embodiments may be described in terms of a series of methodological steps for programming an FPGA.

[0101] While the foregoing generally describes programmable shift registers for routing switches or LUT configuration, it should be recognized that any triggering circuitry in any programmable shift register can be coupled to any FPGA element as required.

[0102] Figure 9 Further details of the operating unit according to a further embodiment are shown.

[0103] like Figure 9As shown, an operation unit 910 corresponding to, for example, the operation unit register described with reference to the foregoing embodiments is provided. This operation unit 910 includes two LUTs 911 and 912. The output of each LUT 911, 912 is connected to its respective multiplexer 913, 914. The outputs of these multiplexers 913, 914 are connected to their respective trigger circuits 915, 916. The respective multiplexers 913, 914, together with their respective trigger circuits 915, 916, constitute respective dual-configuration LUT trigger circuits 921, 922. The second input of multiplexer 913 is connected to test value input line 917. The second input of multiplexer 914 is connected to the output of LUT trigger circuit 916. The selection inputs of the two multiplexers 913, 914 are commonly connected to test mode selection line 918. The output of each LUT trigger circuit 915, 916 supplies the output line of operation unit 910. The two LUT trigger circuits 915, 916 are driven by a common clock line 919. Each of LUTs 911 and 912 has three data inputs, which together constitute the six data inputs 920 of the operating unit. A programmable shift register 930 is further provided, corresponding to, for example, the programmable shift register described with reference to the foregoing embodiments. Generally as described with reference to the foregoing embodiments, the programmable shift register provides configuration values ​​for LUTs 911 and 912 and a number of programmable routing switches (not shown). Clock 941 is selectively connected to clock line 942 of programmable shift register 930 via clock gate 940. Clock gate 940 has an implementation input, as shown, whereby a logic high closes the switch connecting the clock line of the programmable shift register to clock 941 to receive clock pulses. Clock implementation input 943 is also connected to one input of programming output AND gate 950, the other input of which is connected to the output of the last trigger circuit of programmable shift register 930. The first trigger circuit of the programmable shift register constitutes the data input 67 of the programmable shift register. It should be recognized that the operating unit can include any number of LUTs, which can have any number of inputs, and regardless of the number of inputs, the LUTs can have multiple outputs, some or all of which can be associated with LUT trigger circuitry. As described above, when multiplexers 913 (and 914) receive a suitable selection input, the two LUT trigger circuits 915 and 916 (referred to as the test mode) constitute an LUT shift register. This shift register can include any number of LUT trigger circuits, including trigger circuitry in different operating units. Any configuration of the various configurations described in the foregoing embodiments is equally suitable for Figure 9 The arrangement.

[0104] During operation, this arrangement supports reference. Figure 10 The method for testing FPGAs is described.

[0105] Figure 10 A method for loading an FPGA according to an embodiment is shown.

[0106] like Figure 10 As shown, a method for operating an FPGA is provided, including the following steps. The method begins at step 1001 and proceeds to step 1002, instructing a multiplexer 38 having an output coupled to a programmable shift register 930 to select to receive an input 381 of a configuration value implementing a test protocol.

[0107] In step 1003, a plurality of LUT trigger circuits 921, 922 are instructed to enter a test configuration, wherein each of the LUT trigger circuits receives an input implementing the test protocol, and wherein the LUT trigger circuit is connected as an LUT shift register.

[0108] In step 1004, the programmable shift register 930 is timed to load a first set of elements having LUT configuration values ​​belonging to the configuration values ​​for implementing the test protocol; and the programmable shift register is timed to load a second set of elements having routing switch configurations belonging to the configuration values ​​for implementing the test protocol.

[0109] It should be understood that the first set of shift register elements and the second set of shift register elements can be distributed across the same shift register. Loading a value into a shift register involves timing the shift register to move the relevant configured value to its desired final position. In some cases, it may be necessary to address the shift registers into which values ​​are loaded. It may be desirable to load values ​​into multiple shift registers in parallel or serially; in such cases, the method can be iterated among multiple shift registers before proceeding to the next step.

[0110] In step 1005, the plurality of LUT trigger circuits 921, 922 are instructed to enter an operation configuration, wherein each of the LUT trigger circuits 921, 922 receives input from the output of the plurality of LUTs.

[0111] In step 1006, the data values ​​are applied to the plurality of LUTs (on input 920).

[0112] In step 1007, the LUT trigger circuit is timed to sample the output of each LUT into its respective trigger circuit, the output being in response to the test protocol and the data input.

[0113] In step 1008, the LUT trigger circuit is instructed to enter the test configuration, wherein the LUT trigger circuit is connected in the LUT shift register and is connected as a shift register, and

[0114] In step 1009, the LUT trigger circuit is timed to read the value of the LUT shift register, which includes the output of the LUT in response to the test protocol and the data input, and the process terminates in step 1010.

[0115] Once the test values ​​are loaded, the FPGA's operation will be evaluated to determine if it meets expectations. The details of this testing process will depend on the nature of the FPGA system itself and are outside the scope of this invention.

[0116] Generally speaking, the test modes described above are only used for factory settings to ensure that the FPGA is fully usable after manufacturing.

[0117] In some embodiments, multiple test protocols can be defined, in which case the aforementioned steps can be iterated multiple times, with different test protocols loaded sequentially in each iteration.

[0118] During operation, Figure 9 The arrangement further supports, as referenced Figure 11 The described method for operating an FPGA.

[0119] Figure 11 A method for operating an FPGA according to an embodiment is shown.

[0120] like Figure 11 As shown, a method for operating an FPGA is provided, comprising the following steps. The method begins at step 1101 and proceeds to step 1102, instructing a multiplexer having an output coupled to a programming trigger circuit to select an input of a configuration value that implements a logic function.

[0121] In step 1103, multiple LUT trigger circuits are instructed to enter an operation configuration, wherein each of the LUT trigger circuits receives input from the output of the multiple LUTs respectively.

[0122] In step 1104, the programmable shift register is timed to load a first set of elements having LUT configuration values ​​belonging to the configuration values ​​that implement the logic function; and the programmable shift register is timed to load a second set of elements having routing switch configurations belonging to the configuration values ​​that implement the logic function, and the process terminates in step 1105.

[0123] according to Figure 11 In the development of embodiments, the method may include the following additional steps: implementing the output of a first programmable shift register from a plurality of programmable shift registers, implementing the first programmable shift register... Figure 11 The steps are then repeated for each of the plurality of shift registers.

[0124] During operation, Figure 9 The arrangement further supports methods for verifying the FPGA. This method may include the following steps: timing the first programmable shift register to read a first set of elements having LUT configuration values ​​that implement the logic function; and timing the first programmable shift register to read a second set of elements of the shift register having routing switch configurations that implement the logic function.

[0125] According to the development of this embodiment, the method may include the following additional steps: implementing the output of a first programmable shift register from a plurality of programmable shift registers, implementing the above description regarding the first programmable shift register, and then repeating these steps for each of the plurality of shift registers.

[0126] Figure 12 A method for verifying an FPGA according to a further embodiment is shown.

[0127] Figure 12 The embodiments described above are developments of the aforementioned embodiments.

[0128] like Figure 12 As shown, a method for operating an FPGA is provided, comprising the following steps. The method begins at step 1201 and proceeds to step 1202, whereby timing is performed on a first programmable shift register to read out a first set of elements having the LUT configuration value implementing the logic function; and timing is performed on the first programmable shift register to read out a second set of elements having a routing switch configuration implementing the logic function. The method then proceeds to step 1203, whereby comparing the LUT configuration implementing the logic function and the routing switch configuration implementing the logic function when read from the shift register with the original LUT configuration implementing the logic function and the routing switch configuration implementing the logic function when originally read into the shift register, for example, according to reference... Figure 11 The method described. The method then terminates at step 1204.

[0129] In typical scenarios, it is desirable that the bitstream loaded into the shift register is the same as the bitstream read from the shift register. If the two bitstreams are found to be identical, the FPGA's operating state and the corresponding results can be considered verified. If the bitstream loaded into the shift register is different from the bitstream read from the shift register, some or all of the results must be considered unreliable.

[0130] It should be recognized that, in reference to Figure 10 , 11 Different combinations of the steps described in 12 can constitute embodiments of the present invention.

[0131] In many cases, some or all of the method steps can be implemented through computer programming, interaction with an FPGA, and providing a suitable bitstream as described above during the test, operation, and verification modes of operation. In some cases, some or all of this functionality can be implemented on the same chip as the FPGA, or performed as part of a larger system to which the FPGA belongs. In other cases, for the purpose of post-manufacturing testing or verification after generating questionable results or being exposed to error-induced conditions, this functionality may be provided by a test or verification system temporarily coupled to the FPGA.

[0132] In some embodiments, the methods and processes described herein can be implemented, in whole or in part, by a computing device. These methods and processes can be implemented by any combination of computer applications or services, application programming interfaces (APIs), libraries, and / or other computer program products or such entities.

[0133] Figure 13 A general computing system suitable for implementation of embodiments of the present invention is shown.

[0134] like Figure 13 As shown, the system includes a logic device 1301 and a storage device 1302. The system may optionally include a display subsystem 1311, input subsystems 1312, 1313, 1315, a communication subsystem 1320, and / or other components not shown.

[0135] Logic device 1301 includes one or more physical devices configured to execute instructions. For example, logic device 1301 may be configured to execute instructions that are part of one or more applications, services, programs, routes, libraries, objects, components, data structures, or other logical constructs. Such instructions can be implemented to perform tasks, implement data types, change the state of one or more components, achieve technical effects, or obtain desired results.

[0136] Logic device 1301 may include one or more processors configured to execute software instructions. Additionally or alternatively, the logic device may include one or more hardware or firmware logic devices configured to execute hardware or firmware instructions. The processor of the logic device may be single-core or multi-core, and the instructions executed thereon may be configured for sequential, parallel, and / or distributed processing. Individual components of logic device 1301 may optionally be distributed across two or more separate devices, which may be remotely located and / or configured for coordinated processing. Various aspects of logic device 1301 may be virtualized and executed via remotely accessible, networked computing devices configured in a cloud computing configuration.

[0137] Storage device 1302 includes one or more physical devices configured to hold instructions executable by a logical device to implement the methods and steps described herein. When such methods and steps are implemented, the state of storage device 1302 can be changed, for example, to hold different data.

[0138] Storage device 1302 may include removable and / or built-in devices. Storage device 1302 may include one or more types of storage devices, including optical memory (e.g., CD, DVD, HD-DVD, Blu-ray disc, etc.), semiconductor memory (e.g., RAM, EPROM, EEPROM, etc.), and / or magnetic memory (e.g., hard disk drive, floppy disk drive, magnetic tape drive, MRAM, etc.), and others. Storage devices may include volatile, non-volatile, dynamic, static, read / write, read-only, random access, sequential access, location-addressable, file-addressable, and / or content-addressable devices.

[0139] In some arrangements, the system may include an interface 1303 suitable for supporting communication between logic device 1301 and other system components. For example, additional system components may include removable and / or built-in extended storage devices. Extended storage devices may include one or more types of storage devices, including optical memory 1332 (e.g., CD, DVD, HD-DVD, Blu-ray disc, etc.), semiconductor memory 1333 (e.g., RAM, EPROM, EEPROM, flash memory, etc.), and / or magnetic memory 1331 (e.g., hard disk drive, floppy disk drive, magnetic tape drive, MRAM, etc.), and others. Such extended storage devices may include volatile, non-volatile, dynamic, static, read / write, read-only, random access, sequential access, location-addressable, file-addressable, and / or content-addressable devices.

[0140] It should be recognized that a storage device comprises one or more physical devices and excludes the propagation of signals. However, unlike storage on a storage device, aspects of the instructions described herein can alternatively be propagated via a communication medium (e.g., electromagnetic signals, optical signals, etc.).

[0141] Various aspects of logic device 1301 and storage device 1302 can be integrated together into one or more hardware logic components. Such hardware logic components may include, for example, field-programmable gate arrays (FPGAs), application-specific integrated circuits (PASICs / ASICs), application-specific standard products (PSSPs / ASSPs), system-on-a-chip (SOCs), and complex programmable logic devices (CPLDs).

[0142] The term "program" can be used to describe an aspect of a computing system implemented to perform a specific function. In some cases, a program can be instantiated by a logical device that executes machine-readable instructions held in storage. It should be understood that different modules can be instantiated from the same applications, services, code blocks, objects, libraries, routines, APIs, functions, etc. Similarly, the same program can be instantiated from different applications, services, code blocks, objects, libraries, routines, APIs, equations, etc. The term "program" can include individual or grouped executable files, data files, libraries, drives, scripts, database records, etc.

[0143] In particular, Figure 13 The system can be used to implement embodiments of the present invention.

[0144] For example, to achieve about Figure 10 , 11 The procedure described in step 12 can be stored in storage device 1302 and executed by logic device 1301. A bitstream loaded into shift registers or multiple shift registers can be generated by logic device 1301 and / or stored in storage device 1302 or extended storage devices 1332, 1333, or 1331. The bitstream can be loaded into shift registers via communication interface 1320 through the activity of logic device 1301. A bitstream read from shift registers or multiple shift registers can be obtained via communication interface 1320 through the activity of logic device 1301, and / or stored in storage device 1302 or extended storage devices 1332, 1333, or 1331. Logic device 1301 can obtain the bitstream loaded into shift registers or multiple shift registers and the bitstream read from shift registers or multiple shift registers in check mode, and perform a comparison to determine the validity of the result.

[0145] Therefore, the present invention can be specifically manifested in the form of a computer program.

[0146] It should be recognized that, as used herein, a "service" is an application that can be executed across multiple user sessions. A service can be used for one or more system components, programs, and / or other services. In some implementations, a service may run on one or more server computing devices.

[0147] When included, the display subsystem 1311 can be used to present a visual representation of data held by a storage device. This visual representation can take the form of a graphical user interface (GUI). As described herein, methods and processes that change the data held by storage device 1302 and thus transition the state of storage device 1302, the state of the display subsystem 1311 can also be transitioned to visually represent changes in the underlying data. The display subsystem 1311 may include one or more display devices that virtually utilize any type of technology. Such display devices may be combined with logical devices and / or storage devices in a shared enclosure, or such display devices may be peripheral display devices.

[0148] When included, the input subsystem may include or engage with one or more user input devices, such as a keyboard 1312, a mouse 1313, a touchscreen 1311, or a game controller (not shown). In some embodiments, the input subsystem may include or engage with selected Natural User Input (NUI) component portions. Such component portions may be integrated or peripheral, and the transduction and / or processing of input actions may be on-board or off-board. Example NUI component portions may include microphones for voice and / or speech recognition; infrared, color, stereo, and / or depth cameras for machine vision and / or gesture recognition; head trackers, eye trackers, accelerometers, and / or gyroscopes for motion detection and / or content recognition; and electric field sensing component portions for assessing brain activity.

[0149] When included, the communication subsystem 1320 can be configured to communicatively couple the computing system to one or more other computing devices. For example, the communication module can communicatively couple the computing device to a remote service hosted on a remote server 1376, for example, via a network of any size, including, for example, a personal area network, a local area network, a wide area network, or the Internet. The communication subsystem may include wired and / or wireless communication devices compatible with one or more different communication protocols. As a non-limiting example, the communication subsystem can be configured for communication via a wireless telephone network 1374 or a wired or wireless local or wide area network. In some embodiments, the communication subsystem may allow the computing system to send and / or receive messages to and / or from other devices via a network such as the Internet 1375. The communication subsystem may additionally support short-range sensing communication 1321 with passive devices (NFC, RFID, etc.).

[0150] According to some embodiments, configuration values ​​for lookup tables (LUTs) and programmable routing switches in an FPGA are provided via a plurality of trigger circuits arranged in a shift register. This shift register can receive test values ​​in factory test mode and operational configuration values ​​in operational mode (implementing whatever functionality the customer requires of the FPGA). A bitstream is provided at one end of the shift register and is timed until the last trigger circuit receives its value. The value can also be timed at the other end of the shift register to compare with the initial bitstream to identify stored values, for example, errors due to radiation exposure. Clock gate architectures are proposed for loading data into or reading data from a particular selected shift register.

[0151] It should be understood that the configurations and / or methods described herein are exemplary in nature and should not be considered in a limiting sense, as numerous variations are possible. The specific routines or methods described herein may represent one or more of any number of processing strategies. Thus, the various behaviors shown and / or described may be performed in the shown and / or described order, in other orders, in parallel, or omitted. Similarly, the order of the processes described above may be changed.

[0152] The subject matter of this disclosure includes all novel and significant combinations and sub-combinations of various processes, systems and configurations, other features, functions, behaviors and / or properties disclosed herein, and any and all their equivalents.

Claims

1. A method of operating an FPGA, the FPGA including a programmable shift register (37), a LUT (21), and a routing switch (26), the programmable shift register (37) including a first set of elements (3707, 3708, 3709, 3710, 3711, 3712, 3713, 3714, 3715) coupled to the LUT (21) and for providing LUT configuration values ​​for the LUT (21), and a second set of elements (3701, 3702, 3703, 3704, 3705, 3706) coupled to the routing switch (26) and for providing routing switch configuration values ​​for the routing switch (26), the method comprising the following steps: Clock control is provided to the programmable shift register (37) to read the LUT configuration value from the first element set (3707, 3708, 3709, 3710, 3711, 3712, 3713, 3714, 3715), the LUT configuration value implementing the logical function; and Clock control is provided to the programmable shift register (37) to read the routing switch configuration value from the second element set (3701, 3702, 3703, 3704, 3705, 3706), the routing switch configuration value implementing the logic function.

2. The method of claim 1, further comprising the steps of: enabling the output of the first programmable shift register (37) as the programmable shift register, and For additional programmable shift registers, repeat the steps of enabling and providing clock control.

3. The method according to claim 2, further comprising the step of: comparing the LUT configuration value and the routing switch configuration value read from the programmable shift register with the original LUT configuration value and routing switch configuration value that implement the logic function and were originally read into the programmable shift register.

4. An apparatus for operating an FPGA, comprising a unit for performing the method according to any one of claims 1-3.

5. A computer-readable medium having instructions stored thereon, which, when executed by a processor, cause the processor to perform the method according to any one of claims 1-3.

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