A circuit and method for canceling non-ptat current components in total current

Abstract

The application discloses a circuit for offsetting non-PTAT current components in total current, and has the characteristics that the circuit comprises a non-PTAT unit, a PTAT unit and a proportional conversion unit; the non-PTAT unit is used for generating a non-PTAT current; the PTAT unit is used for generating a PTAT current; the proportional conversion unit is connected with the non-PTAT unit and the PTAT unit respectively, and is used for generating a first mirror current with non-PTAT characteristics of the non-PTAT unit according to a preset proportion, and generating a second mirror current of the PTAT unit based on the difference between the PTAT current and the first mirror current. The method is simple, easy to realize, has a wide application range and good effect.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and more specifically, to a circuit and method for canceling the non-PTAT current component in the total current. Background Technology

[0002] Currently, within the same circuit structure, depending on the current generation and regulation methods, both PTAT (Proportional to Absolute Temperature) current and non-PTAT current (not proportional to absolute temperature) may simultaneously exist. Since these two current components together constitute the total current of the circuit structure, and because this total current cannot fully maintain PTAT characteristics, the total current of the circuit is not proportional to absolute temperature. This leads to significant deviations in estimating ambient temperature using the total circuit current value or vice versa. Because PTAT circuits offer more accurate ambient temperature prediction, they are widely used. However, the circuit in this invention, lacking complete PTAT current characteristics, suffers from limited utilization and a narrow application range.

[0003] Therefore, there is an urgent need for a circuit and method to cancel the non-PTAT current component in the total current. Summary of the Invention

[0004] To address the shortcomings of existing technologies, the present invention aims to provide a circuit and method for offsetting non-PTAT current components in the total current. This method employs a proportional conversion unit to proportionally convert the PTAT current and non-PTAT current in the circuit, thereby ensuring that the total current of the circuit retains only PTAT characteristics.

[0005] The present invention adopts the following technical solution.

[0006] In a first aspect, the present invention relates to a circuit for canceling the non-PTAT current component in a total current. The circuit includes a non-PTAT unit, a PTAT unit, and a proportional conversion unit. The non-PTAT unit is used to generate a non-PTAT current, and the PTAT unit is used to generate a PTAT current. The proportional conversion unit is connected to the non-PTAT unit and the PTAT unit respectively, and is used to generate a first mirror current of the non-PTAT unit with non-PTAT characteristics according to a preset ratio, and to generate a second mirror current of the PTAT unit based on the difference between the PTAT current and the first mirror current.

[0007] Preferably, the proportional conversion unit includes a first, second, and third mirror unit; wherein, the input terminal of the first mirror unit is connected to the non-PTAT unit, and the output terminal is connected to the second and third mirror units respectively, for generating output currents for the second and third mirror units respectively according to a preset ratio based on the non-PTAT current; the input terminals of the second and third mirror units are connected to the first mirror unit, and the output terminals are connected to the first branch and the second branch of the PTAT unit respectively, for injecting the output currents generated by the second and third mirror units in a preset ratio to the non-PTAT current into the PTAT unit respectively.

[0008] Preferably, the first mirror unit includes a first NMOS transistor Mn1, a second NMOS transistor Mn2, and a first PMOS transistor Mp1; wherein the gate and drain of the first NMOS transistor Mn1 are connected to the output terminal of the non-PTAT unit and the gate of the second NMOS transistor Mn2, and the source is grounded; the drain of the second NMOS transistor Mn2 is connected to the drain of the first PMOS transistor Mp1, and the source is grounded; the source of the first PMOS transistor is connected to the power supply voltage Vdd, and the gate and drain serve as the output terminal of the first mirror unit.

[0009] Preferably, the second mirror unit includes a second PMOS transistor Mp2; wherein the source of the second PMOS transistor Mp2 is connected to the power supply voltage Vdd, the gate is connected to the output terminal of the first mirror unit, and the drain is connected to the first branch of the PTAT unit.

[0010] Preferably, the third mirror unit includes a third PMOS transistor Mp3; wherein the source of the third PMOS transistor Mp3 is connected to the power supply voltage Vdd, the gate is connected to the output terminal of the first mirror unit, and the drain is connected to the second branch of the PTAT unit.

[0011] Preferably, the preset ratio of the first mirror unit is (N-1):1; the preset ratio of the second and third mirror units is 1:N.

[0012] Preferably, the value of N is such that the current flowing through bipolar transistors Q1 and Q2 in the PTAT unit is greater than the output current of the second and third mirror units.

[0013] Preferably, the proportional conversion unit further includes a fourth mirror unit; wherein the input of the fourth mirror unit is connected to the PTAT unit.

[0014] Preferably, the fourth mirror unit includes a sixth PMOS transistor Mp6 and a fifth NMOS transistor Mn5; wherein, the source of the sixth PMOS transistor Mp6 is connected to the power supply voltage, the gate is connected to the gate and drain of the PMOS transistor Mp5 in the PTAT unit, and the drain is connected to the drain and gate of the fifth NMOS transistor Mn5; the source of the fifth NMOS transistor Mn5 is grounded.

[0015] Preferably, the preset ratio of the fourth mirror unit is 1:1.

[0016] Preferably, the preset ratio is determined based on the width of the MOS transistors that are mirror images of each other in the mirror unit; the lengths of the MOS transistors that are mirror images of each other in the mirror unit are equal, and the value ranges from 6 to 10 μm.

[0017] A second aspect of the present invention relates to a method for canceling non-PTAT current components in a total current, wherein the method is implemented using a circuit for canceling non-PTAT current components in a total current as described in the first aspect of the present invention.

[0018] The beneficial effects of this invention are that, compared with the prior art, the circuit and method for canceling the non-PTAT current component in the total current of this invention can convert the PTAT current and non-PTAT current in the circuit according to a preset ratio through a proportional conversion unit, thereby ensuring that the total current of the circuit retains the characteristic of having only PTAT current. The method of this invention is simple, easy to implement, widely applicable, and effective.

[0019] The beneficial effects of the present invention also include:

[0020] 1. Since the total current generated in the circuit of this invention is PTAT current, the circuit has a wider range of applications. For example, the circuit structure in this invention can be applied to various aspects such as temperature sensing, industrial temperature measurement, and remote temperature sensing.

[0021] 2. The most important technical contribution of this invention is that by injecting a proportional current of non-PTAT current into the PTAT unit, the non-PTAT current component in the total current is canceled out. The idea is ingenious and the implementation method is simple.

[0022] 3. In this invention, the PTAT current component and the non-PTAT current component are obtained proportionally by mirror units, resulting in accurate performance and a wide range of applications. Based on the width ratio between mirrored MOSFETs, a preset current ratio can be accurately obtained. This method allows the circuit to easily obtain different output currents by adjusting the MOSFET parameters according to actual conditions, thus making the circuit suitable for more diverse scenarios. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of a circuit structure that simultaneously includes PTAT units and non-PTAT units in the prior art of this invention;

[0024] Figure 2 This is a schematic diagram of a circuit for offsetting the non-PTAT current component in the total current according to the present invention. Detailed Implementation

[0025] The present application will be further described below with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solutions of the present invention, and should not be construed as limiting the scope of protection of the present application.

[0026] Figure 1 This is a schematic diagram of a circuit structure that simultaneously includes PTAT units and non-PTAT units, according to the prior art of this invention. For example... Figure 1 As shown, the circuit includes two units, A and B. Unit A is a non-PTAT unit, and unit B is a PTAT unit. Specifically, in this invention, all current-generating units that do not possess a positive temperature coefficient can be referred to as non-PTAT units. For example, units that generate currents with zero temperature coefficient, negative temperature coefficient, or currents that change with other parameters regardless of temperature should all be classified as non-PTAT units.

[0027] In this invention Figure 1 This is a typical PTAT generation unit. Its components include a second PMOS transistor Mp2, a third PMOS transistor Mp3, a third NMOS transistor Mn3, a fourth NMOS transistor Mn4, a resistor R1, a first transistor Q1, and a second transistor Q2. The second PMOS transistor Mp2, the third NMOS transistor Mn3, and the first transistor Q1 form the first branch. The third PMOS transistor Mp3, the fourth NMOS transistor Mn4, the resistor R1, and the second transistor Q2 form the second branch.

[0028] Specifically, in the first branch, the source of the second PMOS transistor Mp2 is connected to the power supply voltage Vdd, and its gate is connected to the gate and drain of the third PMOS transistor Mp3 in the second branch. Its drain is connected to the gate and drain of the third NMOS transistor Mn3. The gate and drain of the third NMOS transistor Mn3 are also connected to the gate of the fourth NMOS transistor Mn4 in the second branch. The source of the third NMOS transistor is connected to the emitter of the first transistor Q1, and its base is connected to the base and ground of the second transistor Q2 in the second branch. Its collector is grounded.

[0029] In the second branch, the source of the third PMOS transistor Mp3 is connected to the power supply voltage Vdd, and its gate and drain are connected to the gate of the second PMOS transistor Mp2 and the drain of the fourth NMOS transistor Mn4 in the first branch. The gate of the fourth NMOS transistor is connected to the gate and drain of the third NMOS transistor Mn3 in the first branch, and its source is connected to one end of resistor R1. The other end of resistor R1 is connected to the emitter of the second transistor Q2, and the base of the second transistor Q2 is connected to the base and ground of the first transistor Q1 in the first branch, with its collector grounded.

[0030] This invention Figure 1The PTAT unit shown is a typical PTAT current generation circuit, and its principle will not be elaborated in this article. In this circuit, since a current mirror is formed between the second PMOS transistor Mp2 and the third PMOS transistor Mp3, the first branch current I1 and the second branch current I2 are equal in magnitude.

[0031] Meanwhile, assuming the output current of the non-PTAT unit in this invention is I = N * I0, the total output current of the circuit is Iout = N * I0 + 2I1. It is clear that the total output current of this circuit is not the PTAT current.

[0032] In order to achieve a complete PTAT characteristic in the total output of the circuit, a new circuit is used in this invention to cancel the non-PTAT current component in the total current.

[0033] Figure 2 This is a schematic diagram of a circuit for canceling the non-PTAT current component in the total current according to the present invention. Figure 2 As shown, a circuit for canceling the non-PTAT current component in the total current includes a non-PTAT unit, a PTAT unit, and a proportional conversion unit; wherein, the non-PTAT unit is used to generate a non-PTAT current, and the PTAT unit is used to generate a PTAT current; the proportional conversion unit is connected to the non-PTAT unit and the PTAT unit respectively, and is used to generate a first mirror current of the non-PTAT unit with non-PTAT characteristics according to a preset ratio, and generate a second mirror current of the PTAT unit based on the difference between the PTAT current and the first mirror current.

[0034] It is understood that this invention primarily utilizes PMOS and NMOS transistors to form a mirror circuit, enabling the mirror circuit to generate mirror current according to a predetermined ratio based on the original circuit. Since the mirror circuit not only generates non-PTAT mirror currents based on the non-PTAT cells in the original circuit, but also generates mirror currents based on the difference between the PTAT current and the non-PTAT cells generated within the non-PTAT cells, the total output of the circuit maintains PTAT characteristics, thus eliminating the non-PTAT component in the total current.

[0035] Preferably, the proportional conversion unit includes a first, second, and third mirror unit; wherein, the input terminal of the first mirror unit is connected to the non-PTAT unit, and the output terminal is connected to the second and third mirror units respectively, for generating output currents for the second and third mirror units respectively according to a preset ratio based on the non-PTAT current; the input terminals of the second and third mirror units are connected to the first mirror unit, and the output terminals are connected to the first branch and the second branch of the PTAT unit respectively, for injecting the output currents generated by the second and third mirror units in a preset ratio to the non-PTAT current into the PTAT unit respectively.

[0036] Understandably, as mentioned above, the first, second, and third mirror units replicate the current in the non-PTAT unit proportionally and input the replicated current into the PTAT unit. In this way, the two bipolar transistors in the PTAT unit generate PTAT current, and the current flowing through the MOS transistors connected in series with them, namely Mp4, Mn3 and Mp5, Mn4, acquires some of the non-PTAT characteristics.

[0037] Specifically, such as Figure 2 As shown, this is because the current flowing through the MOSFET, I2 = I1 - N*I0, is the difference between the current flowing through the bipolar transistor, I1, and the current generated by the mirror unit, N*I0. It not only has the PTAT characteristic of I1, but also the non-PTAT characteristic of -N*I0.

[0038] Preferably, the first mirror unit includes a first NMOS transistor Mn1, a second NMOS transistor Mn2, and a first PMOS transistor Mp1; wherein the gate and drain of the first NMOS transistor Mn1 are connected to the output terminal of the non-PTAT unit and the gate of the second NMOS transistor Mn2, and the source is grounded; the drain of the second NMOS transistor Mn2 is connected to the drain of the first PMOS transistor Mp1, and the source is grounded; the source of the first PMOS transistor is connected to the power supply voltage Vdd, and the gate and drain serve as the output terminal of the first mirror unit.

[0039] Specifically, the present invention can employ a mirror circuit, a method commonly used in the prior art, to generate the mirrored current. In one embodiment of the present invention, a MOSFET is used as the mirror circuit. Of course, other methods in the prior art can also be used to generate the mirrored current.

[0040] Preferably, the second mirror unit includes a second PMOS transistor Mp2; wherein the source of the second PMOS transistor Mp2 is connected to the power supply voltage Vdd, the gate is connected to the output terminal of the first mirror unit, and the drain is connected to the first branch of the PTAT unit.

[0041] By inputting the mirrored currents generated by the second and third mirror units into the PTAT unit, the difference between the PTAT current and the non-PTAT current can be calculated. To implement the PTAT current generation logic, the same current needs to be input simultaneously into the first and second branches of the PTAT unit; therefore, the present invention employs both the second and third mirror units. Typically, the second and third mirror units can use completely identical structures and components.

[0042] Preferably, the third mirror unit includes a third PMOS transistor Mp3; wherein the source of the third PMOS transistor Mp3 is connected to the power supply voltage Vdd, the gate is connected to the output terminal of the first mirror unit, and the drain is connected to the second branch of the PTAT unit.

[0043] Similar to the first mirror unit, in one embodiment of the present invention, a MOS transistor is used as the mirror circuit. Of course, it is also feasible to use other methods in the prior art to generate the mirror current.

[0044] Preferably, the preset ratio of the first mirror unit is (N-1):1, meaning that the current occupied by non-PTAT current is N parts. This ratio is not fixed; it only needs to ensure that the value of the non-PTAT current is less than the PTAT current. Based on the preset ratio of the first mirror unit, it can be deduced that the ratio of the second and third mirror units is 1:N. That is, when the preset ratio of the second and third mirror units is determined, the ratio of the first mirror unit is also determined. In order to obtain a suitable preset ratio for the first, second, and third mirror units to generate proportional current, it is necessary to first calculate the total output current of the entire circuit.

[0045] like Figure 2 As shown, in this invention, the components of the total current include: the original non-PTAT unit, whose generated current is recorded as Inonptat; the current Im1 of the first mirror unit; the current I1 of the first bipolar transistor Q1 and the current of the second bipolar transistor Q2 in the PTAT unit; and the output current I3 of the fourth mirror unit.

[0046] Understandably, based on the characteristics of the fourth mirror unit, we have I3 = I2, and I2 = I1 - Im2 = I1 - Im3. Here, Im2 is the current generated by the second mirror unit, and Im3 is the current generated by the third mirror unit. Therefore, the total current I = Inonptat + Im1 + 2I1 + I3. By derivation, we know that I = (Inonptat + Im1 + I2) + 2I1.

[0047] Referring to the above formula, in order for the total current I to have complete PTAT characteristics, Inonptat + Im1 + I2 in the formula should have complete PTAT characteristics, that is, characteristics similar to I1. Therefore, the simplest way is to let Inonptat + Im1 + I2 = I1, that is, Inonptat + Im1 = Im2 = Im3.

[0048] Therefore, as described above, in order for the output to have complete PTAT characteristics, the sum of the current Inonptat generated by the original non-PTAT unit and the first mirror current should be equal to the second and third mirror currents. Therefore, in this invention, the ratio of the first mirror unit and the second and third mirror units can be determined.

[0049] In this invention, the value of N is not fixed; it is only necessary to ensure that Inonptat is less than I1. Specifically, in order to achieve the preset ratio of the mirror cell, the width-to-length ratio of the two symmetrical MOS transistors forming the mirror cell can be designed proportionally. The lengths L of the two symmetrical MOS transistors are the same, and the length L should not be the minimum process dimension; it can be appropriately increased to 6-10 μm. This can reduce the influence of the channel length effect on the result. The width W can be designed according to the mirror ratio (N-1):1.

[0050] Preferably, the value of N is such that the current flowing through bipolar transistors Q1 and Q2 in the PTAT unit is greater than the output current of the second and third mirror units.

[0051] In this invention, "greater than" means that the difference between the current I1 flowing through bipolar transistors Q1 and Q2 and the output current N*I0 of the second and third mirror units is greater than zero, which means that the current I3 of the fourth mirror unit can be generated.

[0052] Preferably, the proportional conversion unit further includes a fourth mirror unit; wherein the input of the fourth mirror unit is connected to the PTAT unit. As described above, the fourth mirror unit is used to generate the difference between the PTAT current and the non-PTAT current.

[0053] Preferably, the fourth mirror unit includes a sixth PMOS transistor Mp6 and a fifth NMOS transistor Mn5; wherein, the source of the sixth PMOS transistor Mp6 is connected to the power supply voltage, the gate is connected to the gate and drain of the PMOS transistor Mp5 in the PTAT unit, and the drain is connected to the drain and gate of the fifth NMOS transistor Mn5; the source of the fifth NMOS transistor Mn5 is grounded.

[0054] Preferably, the preset ratio of the fourth mirror unit is 1:1. This ensures that the output current I3 = I2. Various other methods can also be used in this invention to achieve the preset ratio of the first to fourth mirror units, as long as the PTAT characteristics of the total output are met.

[0055] Preferably, the preset ratio is determined based on the width of the MOS transistors that are mirror images of each other in the mirror unit; the lengths of the mirror images of the MOS transistors in the mirror unit are equal, and the value ranges from 6 to 10 μm. That is, the preset ratio between the MOS transistors that make up the mirror structure in the first to fourth mirror units is achieved based on the width ratio. The current mirroring accuracy directly affects the overall output accuracy. In order to reduce the influence of the length channel effect on the current, the length L of Mn1 to Mn5 and Mp1 to Mp6 in this invention is as large as possible, for example, it can be 6 to 10 μm, and the width W is determined according to the mirroring ratio. In this invention, all mirroring ratios are not fixed and unique. In practice, it is only necessary that the non-PTAT current canceled by Mp6 is exactly equal to the non-PTAT current consumed by the non-PTAT unit. Regardless of the structure of the non-PTAT unit, we only need to express its total current consumption in the form of a mirroring ratio to achieve the cancellation of the non-PTAT current of the non-PTAT unit.

[0056] In a second aspect, the present invention provides a method for canceling non-PTAT current components in a total current. The method employs a current source as described in the first aspect of the present invention for canceling non-PTAT current components in the total current.

[0057] The beneficial effects of this invention are that, compared with the prior art, the circuit and method for canceling the non-PTAT current component in the total current of this invention can convert the PTAT current and non-PTAT current in the circuit according to a preset ratio through a proportional conversion unit, thereby ensuring that the total current of the circuit retains the characteristic of having only PTAT current. The method of this invention is simple, easy to implement, widely applicable, and effective.

[0058] The applicant of this invention has provided a detailed description of the embodiments of the invention in conjunction with the accompanying drawings. However, those skilled in the art should understand that the above embodiments are merely preferred embodiments of the invention. The detailed description is only intended to help readers better understand the spirit of the invention and is not intended to limit the scope of protection of the invention. On the contrary, any improvements or modifications made based on the inventive spirit of the invention should fall within the scope of protection of the invention.

Claims

1. A circuit for canceling the non-PTAT current component in the total current, characterized in that: The circuit includes a non-PTAT unit, a PTAT unit, and a proportional conversion unit; wherein... The non-PTAT unit is used to generate non-PTAT current, and the PTAT unit is used to generate PTAT current. The proportional conversion unit is connected to the non-PTAT unit and the PTAT unit respectively, and is used to generate a first mirror current with non-PTAT characteristics of the non-PTAT unit according to a preset ratio, and generate a second mirror current of the PTAT unit based on the difference between the PTAT current and the first mirror current. The proportional conversion unit includes a first, second, and third mirror unit; wherein, the input terminal of the first mirror unit is connected to the non-PTAT unit, and the output terminals are respectively connected to the second and third mirror units, for generating output currents for the second and third mirror units respectively according to a preset ratio based on the non-PTAT current; the input terminals of the second and third mirror units are connected to the first mirror unit, and the output terminals are respectively connected to the first branch and the second branch of the PTAT unit, for injecting the output currents generated by the second and third mirror units in a preset ratio to the non-PTAT current into the PTAT unit respectively.

2. The circuit for canceling the non-PTAT current component in the total current according to claim 1, characterized in that: The first mirror unit includes a first NMOS transistor Mn1, a second NMOS transistor Mn2, and a first PMOS transistor Mp1; wherein, The gate and drain of the first NMOS transistor Mn1 are connected to the output terminal of the non-PTAT unit and the gate of the second NMOS transistor Mn2, and the source is grounded. The drain of the second NMOS transistor Mn2 is connected to the drain of the first PMOS transistor Mp1, and the source is grounded; The source of the first PMOS transistor is connected to the power supply voltage Vdd, and the gate and drain serve as the output terminals of the first mirror unit.

3. The circuit for canceling the non-PTAT current component in the total current according to claim 2, characterized in that: The second mirror unit includes a second PMOS transistor Mp2; wherein, The source of the second PMOS transistor Mp2 is connected to the power supply voltage Vdd, the gate is connected to the output terminal of the first mirror unit, and the drain is connected to the first branch of the PTAT unit.

4. The circuit for canceling the non-PTAT current component in the total current according to claim 2, characterized in that: The third mirror unit includes a third PMOS transistor Mp3; wherein... The source of the third PMOS transistor Mp3 is connected to the power supply voltage Vdd, the gate is connected to the output terminal of the first mirror unit, and the drain is connected to the second branch of the PTAT unit.

5. The circuit for canceling the non-PTAT current component in the total current according to claim 1, characterized in that: The preset ratio of the first mirror unit is (N-1):1; The preset ratio of the second and third mirror units is 1:N.

6. The circuit for canceling the non-PTAT current component in the total current according to claim 5, characterized in that: The value of N is chosen such that the current flowing through bipolar transistors Q1 and Q2 in the PTAT unit is greater than the output current of the second and third mirror units.

7. A circuit for canceling non-PTAT current components in the total current according to claim 1, characterized in that: The scaling conversion unit further includes a fourth mirror unit; wherein... The input terminal of the fourth mirror unit is connected to the PTAT unit.

8. A circuit for canceling non-PTAT current components in the total current according to claim 7, characterized in that: The fourth mirror unit includes a sixth PMOS transistor Mp6 and a fifth NMOS transistor Mn5; wherein... The source of the sixth PMOS transistor Mp6 is connected to the power supply voltage, the gate is connected to the gate and drain of the PMOS transistor Mp5 in the PTAT unit, and the drain is connected to the drain and gate of the fifth NMOS transistor Mn5. The source of the fifth NMOS transistor Mn5 is grounded.

9. A circuit for canceling non-PTAT current components in the total current according to claim 7, characterized in that: The preset ratio of the fourth mirror unit is 1:

1.

10. A circuit for canceling the non-PTAT current component in the total current according to any one of claims 5, 6 and 9, characterized in that: The preset ratio is determined based on the width of the MOS transistors that are mirror images of each other in the mirror unit; The MOS transistors in the mirror unit that are mirror images of each other have equal lengths, ranging from 6 to 10 μm.

11. A method for canceling non-PTAT current components in the total current, characterized in that: It is implemented using a circuit as described in claims 1-8 to cancel the non-PTAT current component in the total current.

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