Managing memory command engines using command sequence analysis

Abstract

The present disclosure relates to managing a memory command engine using analysis of a sequence of commands. Various embodiments described herein provide for managing a memory command component, such as a read engine or a write engine of a memory system, using analysis of a sequence of commands (initiated by a host system).

Description

Technical Field

[0001] Embodiments of this disclosure generally relate to memory devices, and more specifically, to managing memory command components, such as the read engine or write engine of a memory system, using (e.g., initiated by a host system) analysis of command sequences. Background Technology

[0002] The memory subsystem may include one or more memory devices for storing data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system may use the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the Invention

[0003] According to an aspect of this disclosure, a system is provided. The system includes: a memory device; a writing component that writes data to the memory device; a reading component that reads data from the memory device; and a processing device operatively coupled to the memory device, the processing device being configured to perform operations including: storing commands received from a host system in a command queue of the system; and when retrieving one or more commands from the command queue for execution: analyzing the command queue to detect when a sequence of read commands is queued for subsequent retrieval from the command queue for execution by the reading component; and in response to detecting the sequence of read commands: determining the number of read commands in the sequence; determining whether the number exceeds a read command threshold; and in response to determining that the number exceeds the read command threshold: determining a current state of the writing component; and enabling or disabling the writing component based on the current state of the writing component.

[0004] According to another aspect of this disclosure, a method is provided. The method includes: storing commands received from a host system in a command queue of a memory system; and when one or more commands are retrieved from the command queue for execution: analyzing the command queue to detect when a sequence of write commands is queued for subsequent retrieval from the command queue for execution by a write component of the memory system; and in response to detecting the sequence of write commands: determining the number of write commands in the sequence; determining whether the number exceeds a write command threshold; and in response to determining that the number exceeds the write command threshold: determining the current state of a read component of the memory system; and enabling or disabling the read component based on the current state of the read component.

[0005] According to another aspect of this disclosure, at least one non-transitory machine-readable storage medium is provided. The non-transitory machine-readable storage medium includes instructions that, when executed by a processing device of a memory system, cause the processing device to perform operations including: storing commands from a host system in a command queue of the memory system; and when retrieving one or more commands from the command queue for execution: analyzing a sequence of commands of the same command type in the command queue, the command sequences being queued and subsequently retrieved from the command queue for execution by a read or write component of the memory system; enabling or disabling the write component based on its current state and the analysis of the command sequences; and enabling or disabling the read component based on its current state and the analysis of the command sequences. Attached Figure Description

[0006] This disclosure will be more fully understood from the detailed description given below and from the accompanying drawings, which illustrate various embodiments of the present disclosure. However, the drawings should not be construed as limiting the disclosure to the specific embodiments, but are merely for illustration and understanding.

[0007] Figure 1 This is a block diagram illustrating an example computing system including a memory subsystem according to some embodiments of the present disclosure.

[0008] Figure 2 This is a diagram illustrating an example memory subsystem that uses the analysis of command sequences to manage a memory command component according to some embodiments of the present disclosure.

[0009] Figures 3 to 9 This is a flowchart of an example method for managing memory command components (e.g., read engine or write engine) of a memory system using analysis of command sequences, according to some embodiments of this disclosure.

[0010] Figure 10 An interaction diagram is provided illustrating the interactions between components of a computing environment in the context of some embodiments, wherein methods for managing memory command components using analysis of command sequences, as described herein, are performed.

[0011] Figure 11 This is a block diagram of an example computer system in which embodiments of the present disclosure can be operated. Detailed Implementation

[0012] This disclosure relates to using (e.g., initiated by a host system) analysis of command sequences to manage memory command components (e.g., engines), such as the read or write engine of a memory system (e.g., a memory subsystem). As used herein, a memory subsystem may be a storage device, a memory module, or a combination of a storage device and a memory module. The following is combined with… Figure 1 Describe examples of storage devices and memory modules. Generally, a host system may use a memory subsystem that includes one or more components, such as a memory device for storing data (e.g., host data). The host system may send access requests to the memory subsystem to store data at the memory subsystem and to read data from the memory subsystem.

[0013] The host system may send access requests (e.g., write commands, read commands) to the memory subsystem to store data on memory devices at the memory subsystem, read data from memory devices at the memory subsystem, or write / read constructs (e.g., commit and complete queues) relative to memory devices at the memory subsystem. The data to be read or written, as specified by the host request, is referred to hereinafter as "host data". The host request may contain logical address information (e.g., logical block address (LBA), namespace) of the host data, which is the location associated between the host system and the host data. The logical address information (e.g., LBA, namespace) may be part of the metadata of the host data. The metadata may also include error handling data (e.g., error correction code (ECC) codeword, parity check code), data version (e.g., the period used to distinguish the data being written), a validity bitmap (which LBAs or logical pass units contain valid data), and so on.

[0014] The memory subsystem can initiate media management operations, such as write operations, on host data stored on the memory device. For example, as part of a garbage collection management operation, the firmware of the memory subsystem can rewrite previously written host data from its location on the memory device to a new location. The rewritten data (e.g., as initiated by the firmware) is referred to below as "garbage collection data".

[0015] In the following text, "user data" broadly refers to host data and garbage collection data. "System data" refers to data generated and / or maintained by the memory subsystem for performing operations in response to host requests and for media management. Examples of system data include, but are not limited to, system tables (e.g., logical-to-physical memory address mapping tables, also referred to herein as L2P tables), data from logging, high-speed scratchpad data, etc.

[0016] The memory device can be a non-volatile memory device. A non-volatile memory device is a package of one or more dies. Each die can consist of one or more planes. For some types of non-volatile memory devices (e.g., NAND devices), each plane consists of a set of physical blocks. For some memory devices, a block is the smallest erasable area. Each block consists of a set of pages. Each page consists of a set of memory cells storing data bits. The memory device can be a raw memory device (e.g., NAND), which is managed externally, for example, by an external controller. The memory device can be a managed memory device (e.g., managed NAND), which is a raw memory device combined with a local embedded controller for memory management within the same memory device package.

[0017] For example, storage systems such as solid-state drives (SSDs) traditionally keep their respective read and write components (e.g., engines) enabled (e.g., active or switched on), regardless of the type of command workload the storage system is currently processing (e.g., long sequences of read or write commands). Therefore, conventional storage systems can consume significant amounts of power during certain command workloads. For instance, on average, a conventional SSD (e.g., a PCIe Generator 3 SSD) can consume approximately 3.5 watts while performing an input / output operation, regardless of the type of command workload being processed. With the advent of thinner and lighter mobile devices (e.g., laptops with lighter batteries and smaller capacities), the importance of reducing the power consumption of their various components, including their storage systems, will only increase.

[0018] This disclosure addresses the aforementioned and other shortcomings by managing memory command components (e.g., engines), such as the read or write engine of a memory system (e.g., a memory subsystem), through the analysis of command sequences (e.g., received from a host system). For example, when the host system interacts with the memory using read and write commands, the memory system (e.g., an SSD) can process one command at a time by allocating and using the resources of the memory system's read or write engine. Therefore, at a given point in time, a specific type of command workload (e.g., read command workload or write command workload) can be observed on the memory system. For example, when the host system (e.g., a laptop computer) is booting up, the memory system coupled to the host system will primarily handle read command workloads, while when files are being copied on the host system, the memory system will primarily handle write command workloads. The various embodiments described herein provide an algorithm that manages (or assists in managing) the power consumption of a memory system by separating the read components (e.g., engines) or write components (e.g., engines) of the memory system based on the current or upcoming command workload of the memory system (e.g., determining the pattern of commands queued for execution based on analysis of commands received from the host system). The algorithm also enables / disables the read components, write components, or both (e.g., by turning on / off specific components (e.g., IP or circuitry) according to hardware mapping).

[0019] Specifically, some embodiments analyze a sequence (or series) of commands of a single command type (e.g., a read command sequence or a write command sequence) queued up for subsequent execution by the memory system, and based on this analysis, enable or disable a write component (e.g., an engine) of the memory system, enable or disable a read component (e.g., an engine) of the memory system, or enable or disable both. For example, embodiments may store commands received from the host system in a command table (or command queue) and analyze the command table to detect when a read command sequence is queued up for subsequent retrieval from the command table for execution by the memory system, or when a write command sequence is queued up for subsequent retrieval from the command table for execution by the memory system. Based on this analysis, embodiments may enable (e.g., activate or turn on) or disable (e.g., deactivate or disconnect) the write component, or enable or disable the read component.

[0020] Furthermore, the various embodiments described herein, given the time delay parameters, allow disabled write components or disabled read components to be enabled (e.g., re-enabled). This can allow embodiments to reduce or eliminate any delays caused by enabling or disabling specific memory command components of the memory system (e.g., by moving from a power-saving mode (e.g., disabled read or write components) to an operational state (e.g., enabled read or write components) for a specific type of command workload). For example, when a write component is disabled (e.g., disconnected) during a read command workload, it can be re-enabled (e.g., re-connected) when a write command is detected in the command queue, or when a write command is expected to arrive in the command queue within a certain execution time. Similarly, when a read component is disabled (e.g., disconnected) during a write command workload, it can be re-enabled (e.g., re-connected) when a read command is detected in the command queue, or when a read command is expected to arrive in the command queue within a certain execution time.

[0021] Various embodiments enable and disable the write components, read components, or both of the memory system, allowing for better management of power consumption. Furthermore, various embodiments allow the memory system to manage power consumption while it is processing commands (e.g., performing input / output operations). Some of the embodiments described herein can be implemented as firmware (e.g., algorithms in a command handler) in existing memory systems, such as SSDs, without requiring modification to the existing memory system hardware.

[0022] As used herein, a memory command engine of a memory system (e.g., a memory subsystem) may include one or more components (e.g., hardware or firmware components) and data paths used by the memory system to access one or more memory devices of the memory system. As used herein, a write engine of a memory system may include one or more components and data paths used by the memory system to write data to one or more memory devices of the memory system. As used herein, a read engine of a memory system may include one or more components and data paths used by the memory system to read data from one or more memory devices of the memory system. As used herein, enabling or disabling a memory command engine may include turning on or off one or more voltage gates (e.g., voltage gates of memory command engine components) associated with the memory command engine.

[0023] As used herein, a command workload (or workload) can refer to a sequence of commands of a single command type, where the command type can be a memory system to host system type (hereinafter referred to as M2H command type), such as a read command, or a host system to memory system type (hereinafter referred to as H2M command type), such as a write command. For example, an M2H workload type may include a sequence (or series) of read commands received from a host system and stored in a command queue of a memory system, from which the memory system retrieves and executes commands. In another instance, an H2M workload type may include a sequence (or series) of write commands received from a host system and stored in a command queue of a memory system. As used herein, a read command may include a command type that facilitates memory M2H data transfer, and a write command may include a command type that facilitates H2M data transfer. The command type associated with a particular command can be determined based on the opcode of that particular command.

[0024] As used herein, the command table of a memory system can be used as a command queue to store commands retrieved from the host system and to store commands associated with indexes or tags. In some embodiments, indexes / tags are assigned to commands in the command table (e.g., to associate indexes / tags with commands in the command table) based on the available space in the command table. Commands are typically retrieved from the command table and executed in the order in which the memory subsystem receives the commands.

[0025] This article discloses some examples of using the analysis of command sequences to manage memory command engines, as described herein.

[0026] Figure 1 An example computing system 100 including a memory subsystem 110 is illustrated according to some embodiments of the present disclosure. The memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination thereof.

[0027] The memory subsystem 110 may be a storage device, a memory module, or a combination of a storage device and a memory module. Examples of storage devices include SSDs, flash drives, Universal Serial Bus (USB) flash drives, Secure Digital (SD) cards, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small form factor DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0028] The computing system 100 may be a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), device with Internet of Things (IoT) capabilities, embedded computer (e.g., embedded computer contained in a vehicle, industrial equipment or networked business device), or such computing device containing memory and processing devices.

[0029] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1 An example of a host system 120 coupled to a memory subsystem 110 is shown. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without an intermediate component), whether wired or wireless, and includes connections such as electrical, optical, magnetic, etc.

[0030] Host system 120 may include a processor chipset and software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a Serial Advanced Technology Attachment (SATA) controller). Host system 120 uses memory subsystem 110 to, for example, write data to memory subsystem 110 and read data from memory subsystem 110.

[0031] Host system 120 may be coupled to memory subsystem 110 via a physical host interface. Examples of host interfaces include, but are not limited to, SATA interfaces, PCIe interfaces, USB interfaces, Fibre Channel, Serial Attached SCSI (SAS), Small Computer System Interface (SCSI), Dual Data Rate (DDR) memory bus, DIMM interfaces (e.g., DIMM sockets supporting Dual Data Rate (DDR)), Open NAND Flash Interface (ONFI), Dual Data Rate (DDR), Low Power Dual Data Rate (LPDDR), or any other interface. The physical host interface may be used to transfer data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a PCIe interface, host system 120 may further use an NVM High Speed ​​(NVMe) interface to access components (e.g., memory device 130). The physical host interface provides an interface for transferring control, address, data, and other signals between memory subsystem 110 and host system 120. Figure 1Memory subsystem 110 is shown as an example. Typically, host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or combinations of communication connections.

[0032] Memory devices 130 and 140 may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be (but are not limited to) random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0033] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND-type flash memory and in-place write memory, such as three-dimensional cross-point (3D cross-point) memory devices, which are cross-point arrays of non-volatile memory cells. The cross-point array of non-volatile memory can be combined with a stackable cross-grid data access array to perform bit storage based on changes in volume resistance. Furthermore, compared to many flash-based memories, cross-point non-volatile memory allows for in-place write operations, where non-volatile memory cells can be programmed without pre-erasing them. NAND-type flash memory includes, for example, two-dimensional NAND (2D NAND) and 3D NAND.

[0034] Each of the memory devices 130 may include one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cell (MLC), three-level cell (TLC), four-level cell (QLC), and five-level cell (PLC), may store multiple bits per cell. In some embodiments, each memory device 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, or any combination thereof. In some embodiments, a particular memory device may include an SLC portion of memory cells, as well as an MLC portion, a TLC portion, or a QLC portion. The memory cells of the memory device 130 may be grouped into pages, which may refer to logical cells of the memory device used for storing data. In the case of some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0035] Although non-volatile memory components such as 3D cross-point arrays of non-volatile memory cells and NAND flash memory (e.g., 2D NAND, 3D NAND) are described, memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), select memory, other chalcogenide-based memory, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0036] The memory subsystem controller 115 (or, for simplicity, controller 115) can communicate with the memory device 130 to perform operations such as reading data, writing data, or erasing data at the memory device 130, and other such operations. The memory subsystem controller 115 may include hardware such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include digital circuitry with dedicated (i.e., hard-decoded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0037] The memory subsystem controller 115 may include a processor (processing device) 117 configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110 (including handling communication between the memory subsystem 110 and the host system 120).

[0038] In some embodiments, local memory 119 may include memory registers storing memory pointers, retrieved data, etc. Local memory 119 may also include ROM for storing microcode. Although... Figure 1 The instance memory subsystem 110 is shown to include a memory subsystem controller 115, but in another embodiment of this disclosure, the memory subsystem 110 does not include a memory subsystem controller 115 and may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0039] Typically, the memory subsystem controller 115 receives commands or operations from the host system 120 and translates these commands or operations into instructions or appropriate commands to enable desired access to memory devices 130 and / or 140. The memory subsystem controller 115 may handle other operations such as wear leveling, garbage collection, error detection and ECC, encryption, caching, and address translation between logical addresses (e.g., LBAs, namespaces) associated with memory device 130 and physical memory addresses (e.g., physical block addresses). The memory subsystem controller 115 may further include host interface circuitry for communication with the host system 120 via a physical host interface. The host interface circuitry translates commands received from the host system 120 into command instructions to access memory devices 130 and / or 140, and translates responses associated with memory devices 130 and / or 140 into information for the host system 120.

[0040] The memory subsystem 110 may also include additional circuitry or components not shown. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and an address circuitry (e.g., a row decoder and a column decoder) that can receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0041] In some embodiments, memory device 130 includes a local media controller 135, which operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory device 130 is a managed memory device, which is a native memory device combined with a local controller (e.g., local media controller 135) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0042] The memory subsystem controller 115 includes a memory command engine manager 112 (hereinafter referred to as "Memory Command Engine Manager 112"), a write engine 113, and a read engine 114, all based on command sequence analysis. According to various embodiments, the memory command engine manager 112 enables or facilitates operations regarding enabling or disabling the write engine 113, the read engine 114, or both, based on analyzing command sequences of the same command type (e.g., read command type and write command type) stored in a command queue (e.g., a command table) of the memory subsystem 110, where the command sequences are queued and subsequently executed on the memory subsystem 110 (e.g., by the memory subsystem controller 115). Commands stored in the command queue can be received or retrieved from the host system 120. Depending on the embodiment, the command queue of the memory subsystem 110 may be part of the memory subsystem controller 115 (e.g., implemented on local memory 119) or external to the memory subsystem controller 115. Additionally, in some embodiments, the command queue includes a command table storing commands associated with an index or tag, wherein the order in which commands are assigned to the command table (e.g., associating an index / tag with a command in the command table) is determined by iterating and analyzing the command queue (e.g., the command table) to determine the order of the command sequence, and (e.g., by the memory subsystem controller 115) the order in which commands are retrieved from the command table for execution on the memory subsystem 110.

[0043] In some embodiments, write engine 113 includes one or more components (e.g., hardware IP or circuitry) of memory subsystem 110 that implement or facilitate the writing of data on one or more of memory devices 130, 140. In some embodiments, read engine 114 includes one or more components (e.g., hardware IP or circuitry) of memory subsystem 110 that implement or facilitate the reading of data from one or more of memory devices 130, 140. According to some embodiments, memory command engine manager 112 uses mapping (e.g., hardware mapping) to enable or disable one or more components in write engine 113. For example, memory command engine manager 112 may use mapping to determine (e.g., identify) which components within memory subsystem 110 are associated with (e.g., implemented) write engine 113; the identified components are enabled when write engine 113 is enabled, and the identified components are disabled when write engine 113 is disabled. Similarly, in some embodiments, memory command engine manager 112 uses mapping to enable or disable one or more components in read engine 114. For example, the memory command engine manager 112 can use mapping to determine (e.g., identify) which components within the memory subsystem 110 are associated with (e.g., implemented) the read engine 114; when the write engine 113 is enabled, the identified components are enabled, and when the write engine 113 is disabled, the identified components are disabled. In some embodiments, one or more components are associated with both the write engine 113 and the read engine 114 (e.g., used by or shared by them), so disabling the write engine 113 or disabling the read engine 114 does not disable those one or more shared components.

[0044] The memory command engine manager 112 can, for example, according to the methods described herein, regarding Figure 3-9 One of the described methods involves performing operations to implement various embodiments on the memory subsystem 110. For example, the memory command engine manager 112 can enable... Figure 3-9 The memory subsystem controller 115 is operated by one or more of the methods 300, 400, 500, 600, 700, 800, and 900.

[0045] Figure 2This is a diagram illustrating an example memory subsystem 204 that uses command sequence analysis to manage a memory command engine according to some embodiments of the present disclosure. As shown, a host system 202 is coupled to and interacts with the memory subsystem 204. The memory subsystem 204 includes a command table 210 from the host system 202, which can be used as a command queue for commands to be sent to the memory subsystem 204. The memory subsystem 204 includes a command processor 212, a write engine 214, a read engine 216, a main buffer 218, a memory device manager 220, and a memory device 222.

[0046] Command processor 212 enables and disables write engine 214, read engine 216, or both, according to the various embodiments described herein. Command processor 212 may use write engine 214, read engine 216, or both to process the execution of commands from command table 210. Write engine 214 includes one or more components (e.g., hardware IP and circuitry) that facilitate the writing of data to memory device 222 based on the execution of write commands from command table 210 (via main buffer 218 and memory device manager 220). Similarly, read engine 216 includes one or more components (e.g., hardware IP and circuitry) that facilitate the reading of data from memory device 222 (via main buffer 218 and memory device manager 220) based on the execution of read commands from command table 210. As shown, write engine 214 includes H2M direct memory access (DMA) component 250, intermediate data buffer 252, encryption / compression component 254, DMA description queue 230, and DMA status queue 232. When a write command is executed, data flows from the H2M DMA component 250 to the intermediate data buffer 252 and the encryption / compression component 254, where the H2M DMA component 250 and the encryption / compression component 254 access the DMA description queue 230 and the DMA status queue 232 during operation. Finally, the data flows out of the write engine 214 via the main buffer 218 and the memory device manager 220 and flows to the memory device 222 for storage.

[0047] As also shown in the figure, the read engine 216 includes an M2H DMA component 260, an intermediate data buffer 262, a decryption / decompression component 264, a DMA description queue 240, and a DMA status queue 242. When a read command is executed, data flows from the memory device 222 to the read engine 216 via the memory device manager 220 and the main buffer 218. Within the read engine 216, data flows from the decryption / decompression component 264 to the intermediate data buffer 262 and the M2H DMA component 260, wherein the M2H DMA component 260 and the decryption / decompression component 264 access the DMA description queue 240 and the DMA status queue 242 during operation. In some embodiments, the DMA description queue 230 and the DMA description queue 240 represent components shared by the write engine 214 and the read engine 216, and the DMA status queue 232 and the DMA status queue 242 represent another component shared by the write engine 214 and the read engine 216.

[0048] Command table 210 stores commands from host system 202 according to tags (e.g., 1-256), which are used to index the commands within command table 210. As shown, command table 210 includes 256 tag slots for storing commands. The size or depth of command table 210 may vary between different embodiments. Figure 2 In this configuration, command table 210 currently stores a sequence of read (RD) commands from tags 1 to 99, and a mixture of read (RD) and write (WR) commands from tags 100 to 256. Depending on the embodiment, commands stored in command table 210 may be retrieved by memory subsystem 204 from host system 202 (e.g., extracted or pulled from a host system command queue on host system 202, rather than pushed from host system 202 to memory subsystem 204). Additionally, commands may be retrieved from host system 202 into command table 210 based on space availability. For example, since command processor 212 retrieves commands from command table 210 for execution, and because of this retrieval, space in command table 210 becomes available, more commands may be retrieved from host system 202 into command table 210.

[0049] For command processing / execution on memory subsystem 204, command processor 212 can retrieve (e.g., remove) individual commands from tag slots in command table 210 for execution. In some embodiments, individual commands are retrieved from command table 210 according to the order in which they were stored (e.g., placed) in command table 210 (e.g., by command processor 212). In some embodiments, the order in which commands are executed within command table 210 is not determined by the order of the tags, but by the order in which commands are received by memory subsystem 204. In some embodiments, individual commands are stored in a single tag slot of currently available command table 210 (e.g., no command is currently stored or marked as available). For example, a single tag slot may become available after a currently stored command has been retrieved (e.g., removed) from a single tag slot for execution by command processor 212. In some embodiments, the order in which indexes / tags are assigned to commands in command table 210 (e.g., associating indexes / tags with commands in the command table) is determined by iterating and analyzing the commands in command table 210 to determine the order of the command sequence.

[0050] Command processor 212 includes command list analyzer 224 and engine controller 226. According to some embodiments, one or both of command list analyzer 224 and engine controller 226 represent references. Figure 1 The described implementation of the memory command engine manager 112. In some embodiments, the command table analyzer 224 retrieves individual commands from the command table 210 according to the order in which commands are stored in the command table 210 (e.g., according to the order of tag assignment), analyzes the opcode of each of the individual commands, and can classify each individual command as an M2H type command (e.g., a read command type), where data is transferred from the memory subsystem 204 to the host system 202, or as an H2M type command (e.g., a write command type), where data is transferred from the host system 202 to the memory subsystem 204. Therefore, when the memory subsystem 204 is processing a read workload, the command table 210 can be primarily occupied by M2H commands. When the memory subsystem 204 is processing a write workload, the command table 210 can be primarily occupied by H2M commands.

[0051] Command table analyzer 224 implements one or more features of the various embodiments described herein. Depending on the embodiment, command table analyzer 224 may include firmware as part of command processor 212. Command table analyzer 224 may maintain an M2H command counter (e.g., a read command counter) and an H2M command counter (e.g., a write command counter) and use both counters to analyze command table 210. In some embodiments, command table analyzer 224 analyzes command table 210 to determine future or upcoming command modes (e.g., a read command mode or a write command mode) and uses this determination to (e.g., via engine controller 226) control when to enable (e.g., turn on) and disable (e.g., turn off) at least one of the write engine 214 or read engine 216 of memory subsystem 204. Additionally, in some embodiments, command table analyzer 224 considers a latency parameter when determining whether to enable or disable write engine 214, read engine 216, or both, which helps to reduce or eliminate any latency caused by enabling or disabling the engine. Therefore, command table analyzer 224 enables memory subsystem 204 to selectively enable or disable write engine 214 or read engine 216 based on (consecutive) M2H command (e.g., read command) sequences or (consecutive) H2M command (e.g., write command) sequences queued in command table 210 and subsequently retrieved for execution by command processor 212. Additionally, command table analyzer 224 enables memory subsystem 204 to selectively enable or disable write engine 214 or read engine 216 while reducing or eliminating latency effects caused by enabling / disabling write engine 214 or read engine 216. An example of how command table analyzer 224 analyzes commands in command table 210 and enables / disables write engine 214 or read engine 216 is provided below. Figure 3-9 The instance methods are used to illustrate this.

[0052] In some embodiments, the command list analyzer 224 facilitates the enabling or disabling of the write engine 214, the read engine 216, or both by accordingly instructing or triggering the engine controller 226. Based on instructions or signals from the command list analyzer 224, the engine controller 226 may individually signal or instruct the write engine 214, the read engine 216, or both to enable or disable themselves. In some embodiments, before disabling the write engine 214 (based on instructions / signals from the command list analyzer 224), the engine controller 226 determines the status of the write engine 214 via a status signal from the write engine 214. If the status indicates that the write engine 214 is busy, the disabling of the write engine 214 may be postponed for a period of time when the status indicates that the write engine 214 is no longer busy. Additionally, in some embodiments, before disabling the read engine 216 (based on instructions / signals from the command list analyzer 224), the engine controller 226 determines the status of the read engine 216 via a status signal from the read engine 216. If the status indicator shows that the read engine 216 is busy, the shutdown of the read engine 216 can be postponed for a period of time when the status indicator shows that the read engine 216 is no longer busy.

[0053] In some embodiments, engine controller 226 enables or disables write engine 214 by enabling or disabling one or more components (e.g., hardware IP and circuitry) associated with write engine 214. For example, engine controller 226 may specifically enable or disable only those components in write engine 214 that are not shared with read engine 216, such as H2M DMA component 250, intermediate data buffer 252, and encryption / compression component 254. To enable or disable write engine 214, engine controller 226 identifies one or more components associated with write engine 214 based on mapping data describing (e.g., mapping) those components of write engine 214. Similarly, engine controller 226 enables or disables read engine 216 by enabling or disabling one or more components (e.g., hardware IP and circuitry) associated with read engine 216. For example, engine controller 226 may specifically enable or disable only those components in read engine 216 that are not shared with write engine 214, such as decryption / decompression component 264, intermediate data buffer 262, and M2H DMA component 260. To enable or disable read engine 216, engine controller 226 identifies one or more components associated with read engine 216 based on mapping data describing (e.g., mapping) those components of read engine 216.

[0054] For illustrative purposes, suppose in one use case, command table 210 stores a sequence of 200 read commands initiated by host system 202, and 50 of those read commands have been retrieved from command table 210 (e.g., retrieved by command processor 212) and are being executed using read engine 216. Command table analyzer 224 can iterate through command table 210 in the order in which the commands were tagged. Based on this iteration, command table analyzer 224 can determine that the next sequence of commands to be retrieved from command table 210 is a sequence of 150 read commands (representing the remaining 150 commands out of the original 200 read commands), followed by at least one write command. While retrieving the sequence of 150 read commands from command table 210 (e.g., in a small portion) and executing them using read engine 216, write engine 214 is expected to be idle and unused; command table analyzer 224 can determine this and deactivate write engine 214. Ultimately, when command table analyzer 224 determines that at least one write command will be retrieved from command table 210 for execution (or, considering a latency parameter, determines that at least one write command will follow within a certain timeframe), command table analyzer 224 can determine and re-enable write engine 214. Additionally, determining that at least one write command will be retrieved from command table 210 for execution, command table analyzer 224 can determine the next command sequence to retrieve from command table 210 and whether the write command sequence has at least a certain length (e.g., the number of write commands is greater than a write command threshold). This allows command table analyzer 224 to deactivate read engine 216 (because it remains idle and unused during the processing of the write command sequence). For example, the write command threshold can be set to 50, and the write command sequence can include 100 write commands followed by at least one read command. The write command threshold can be set by the user of memory subsystem 204. A similar threshold (e.g., a read command threshold) can be used to determine when to deactivate write engine 214 and can also be set by the user of memory subsystem 204.

[0055] Figures 3 to 9 This is a flowchart illustrating example methods for managing a memory command engine (e.g., a read engine or a write engine) of a memory system using analysis of command sequences, according to some embodiments of this disclosure. Methods 300, 400, 500, 600, 700, 800, and 900 can be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, at least one of methods 300, 400, 500, 600, 700, 800, and 900 is... Figure 1The memory subsystem controller 115 is executed based on the memory command engine manager 112. Alternatively, in some embodiments, at least in part, it is executed by... Figure 1 The local media controller 135 of the memory device 130 executes at least one of methods 300, 400, 500, 600, 700, 800, and 900. Although shown in a specific order or sequence, the order of processes may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. Additionally, one or more processes may be omitted in various embodiments. Therefore, not all processes are used in every embodiment. Other process flows are possible.

[0056] Now for reference Figure 3 Method 300, in some embodiments, represents a method of managing a memory command component (e.g., an engine), such as a read engine or write engine of a memory system, using analysis of command sequences. At operation 302, a processing device (e.g., processor 117 of memory subsystem controller 115) stores commands received from a host system (e.g., 120) in a command queue of the memory system (e.g., 110). The host system (e.g., 120) generates commands for the memory system (e.g., 110), and those commands may be sent to the memory system (e.g., 110) or retrieved by the memory system from the host system (e.g., from a queue on the host system). In some embodiments, the command queue includes a command table (e.g., 210), in which each command is stored in the command table associated with a single tag. In some such embodiments, the order in which the memory subsystem (e.g., 110) receives commands determines the order in which commands are retrieved from the command table and executed, and thus determines when a sequence of commands of a single command type (e.g., a read command type or a write command type) exists in the command table.

[0057] For various embodiments, operations 304 to 308 are performed when one or more commands (e.g., read commands and write commands) are retrieved from the command queue for execution (e.g., by a processing device). For example, when one or more commands are retrieved from the command queue for execution, operations 304 to 308 may be performed in response to a condition (e.g., a new read command or write command is stored in command table 210) or periodically (e.g., based on a certain time interval).

[0058] At operation 304, the processing device (e.g., 117) analyzes (e.g., observes) a sequence of commands of the same command type (e.g., M2H / read command type or D2H / write command type) in a command queue, wherein the command sequences are queued and then retrieved from the command queue for execution by a read component (e.g., 114) or write component (e.g., 113) of the memory system (e.g., 110) (on the memory device 130 of the memory subsystem 110). In some embodiments, analyzing the command sequences (of the same command type) in the command queue involves iteratively traversing the command queue according to the order in which tags are assigned to the command queue (e.g., a command table) (e.g., associating tags with commands in the command queue). During iteration, the processing device may classify the command type (e.g., read command type or write command type) of each command based on the opcode of the command.

[0059] At operation 306, based on the analysis of the command sequence (at operation 304) and the current state of the write component (e.g., 113), the processing device (e.g., 117) enables or disables the write component (e.g., 113) of the memory system. In some embodiments, the execution of operations 302, 304, and 306 is... Figure 4 and 5 Methods 400 and 500 are described below. Additionally, at operation 308, based on the analysis of the command sequence (at operation 304) and the current state of the read component (e.g., 113), the processing device (e.g., 117) enables or disables the read component of the memory system. In some embodiments, the execution of operations 302, 304, and 308 is... Figure 6 and 7 Methods 600 and 700 are explained.

[0060] Now for reference Figure 4 Method 400, in some embodiments, represents a method of managing the write components (e.g., engines) of a memory system using analysis of command sequences. At operation 402, a processing device (e.g., processor 117 of memory subsystem controller 115) stores commands received from a host system (e.g., 120) in a command queue of the memory system (e.g., 110). In some embodiments, operation 402 is similar to reference... Figure 3 The described method 300 is operation 302.

[0061] For various embodiments, operations 404 to 412 are performed when one or more commands (e.g., read commands and write commands) are retrieved from the command queue for execution (e.g., executed by a processing device). For example, when one or more commands are retrieved from the command queue for execution, operations 404 to 412 may be performed in response to a condition (e.g., a new read command or write command is stored in command table 210) or periodically (e.g., based on a certain time interval).

[0062] At operation 404, the processing device (e.g., 117) analyzes the command queue to detect when a sequence of read commands is queued, and then retrieves them from the command queue for execution by the read component (e.g., 114) of the memory system (e.g., 110). Analyzing the command queue (to detect when a sequence of read commands is queued and then retrieved from the command queue) includes iteratively traversing the command queue according to the tag assignment order.

[0063] In response to the detection of a read command sequence, at operation 406, the processing device (e.g., 117) determines the number of read commands in the read command sequence, and at operation 408, determines whether the number of read commands exceeds (e.g., is greater than) a read command threshold. Depending on the embodiment, the read command threshold may be set by the memory system manufacturer or the memory system user. Alternatively, the read command threshold may be determined based on (e.g., manufacturer or user) testing and tuning of the memory system.

[0064] In response to determining that the number of read commands exceeds a read command threshold, at operation 410, the processing device (e.g., 117) determines the current state of a write component (e.g., 113) of the memory system. Instances of the write component's state may include, but are not limited to, enabled (e.g., active or on) or disabled (e.g., deactivated or off), wherein when the write component is enabled, its state may further be busy (e.g., operational) or idle. At operation 412, the processing device (e.g., 117) enables or disables the write component (e.g., 113) based on its current state. For example, the processing device can enable or disable the write component based on its current state by determining whether its current state indicates that it is idle (e.g., enabled and not busy), and disabling it in response to a current state indicating that it is idle. In response to a current state indicating that it is not idle, the processing device can disable the write component after its current state has changed to indicate that it is idle. Alternatively, in response to a current state indicating that the write component is not in an idle state, the processing device may redetermine the number of read command sequences (since they may have changed since the last determination at operation 408), and redetermine the current state of the write component in response to the determination that the (redetermined) number exceeds the read command threshold, and enable or disable the write component based on the redetermined current state of the write component.

[0065] In some embodiments, disabling a write component may include disabling sub-components associated with the write component (e.g., sub-components not shared with the read component). As described herein, a processing device may enable or disable a write component by enabling or disabling sub-components of the write component based on mapping data describing the sub-components associated with the write component. Depending on the embodiment, the mapping data may be stored on the memory system (e.g., local memory 119) by the manufacturer of the memory system.

[0066] Now for reference Figure 5 Method 500, in some embodiments, represents a method for managing the write components (e.g., the engine) of a memory system using analysis of command sequences. In some embodiments, operations 502, 504, 506, and 508 are respectively similar to those in reference [reference needed]. Figure 4 Operations 402, 404, 406, and 408 of the described method 400. In response to determining that the number of read commands does not exceed (e.g., not greater than) a read command threshold, at operation 510, the processing device (e.g., 117) determines the current state of the write component (e.g., 113) of the memory system. Subsequently, at operation 512, the processing device (e.g., 117) determines whether the current state of the write component (e.g., 113) indicates that the write component is disabled (e.g., disconnected).

[0067] According to various embodiments, the processing device (e.g., 117) does not respond to the current state of a write component that indicates it is not disabled (i.e., enabled). However, in response to determining that the current state of the write component indicates it is disabled, at operation 514, the processing device (e.g., 117) determines the time (e.g., an estimated time for memory system execution) for executing any remaining read commands in the read command sequence, and at operation 516, the processing device determines whether the (determined) time for execution is less than a delay time parameter.

[0068] In some embodiments, the processing device (e.g., 117) does not respond to a time for execution that is not less than the delay time parameter. However, in response to a time for execution that is less than the delay time parameter, at operation 518, the processing device (e.g., 117) enables the write component (e.g., 113). By enabling the write component in this way based on the delay time parameter, various embodiments can reduce or eliminate the latency effects of disabling the write component when a write command is finally retrieved from the command queue for execution.

[0069] Depending on the embodiment, the latency parameters can be set by the memory system manufacturer or the memory system user. Alternatively, the latency parameters can be determined based on (e.g., manufacturer or user) testing and tuning of the memory system. The latency parameters used for the write component and method 500 can differ from those used for the read component (and Figure 7 The delay time parameter of method 700).

[0070] Now for reference Figure 6 Method 600, in some embodiments, represents a method of managing the read components (e.g., engine) of a memory system using analysis of command sequences. At operation 602, a processing device (e.g., processor 117) stores commands received from a host system (e.g., 120) in a command queue of the memory system (e.g., 110). In some embodiments, operation 602 is similar to that described in reference [reference]. Figure 4 The described method 400 is operation 402.

[0071] For various embodiments, operations 604 to 612 are performed when one or more commands (e.g., read commands and write commands) are retrieved from the command queue for execution (e.g., by a processing device). For example, when one or more commands are retrieved from the command queue for execution, operations 604 to 612 may be performed in response to a condition (e.g., a new read command or write command is stored in command table 210) or periodically (e.g., based on a certain time interval).

[0072] At operation 604, the processing device (e.g., 117) analyzes the command queue to detect when a sequence of write commands has been queued, and then retrieves them from the command queue for execution by the write component (e.g., 113) of the memory system (e.g., 110). Analyzing the command queue (to detect when a sequence of write commands has been queued and then retrieved from the command queue) includes iteratively traversing the command queue according to the tag assignment order.

[0073] In response to the detection of a write command sequence, at operation 606, the processing device (e.g., 117) determines the number of write commands in the write command sequence, and at operation 608, determines whether the number of write commands exceeds (e.g., is greater than) a write command threshold. Depending on the embodiment, the write command threshold may be set by the memory system manufacturer or the memory system user. Alternatively, the write command threshold may be determined based on (e.g., manufacturer or user) testing and tuning of the memory system.

[0074] In response to determining that the number of write commands exceeds a write command threshold, at operation 610, the processing device (e.g., 117) determines the current state of a read component (e.g., 114) of the memory system. Instances of the read component's state may include, but are not limited to, enabled (e.g., active or on) or disabled (e.g., deactivated or off), wherein when the read component is enabled, its state may further be busy (e.g., operational) or idle. At operation 612, the processing device (e.g., 117) enables or disables the read component (e.g., 114) based on its current state. For example, the processing device can enable or disable the read component based on its current state by determining whether its current state indicates that the read component is idle (e.g., enabled and not busy), and disabling the read component in response to a current state indicating that the read component is idle. In response to a current state indicating that the read component is not idle, the processing device can disable the read component after its current state changes to indicate that the read component is idle. Alternatively, in response to a current state indicating that the read component is not idle, the processing device may redetermine the number of write command sequences (since they may have changed since the last determination at operation 608), and redetermine the current state of the read component in response to the determination that the (redetermined) number exceeds the write command threshold, and enable or disable the read component based on the redetermined current state of the read component.

[0075] In some embodiments, disabling the read engine may include disabling sub-components associated with the read component (e.g., sub-components not shared with the read component). As described herein, the processing device may enable or disable the read component by enabling or disabling sub-components of the read component based on mapping data describing the sub-components associated with the read engine. Depending on the embodiment, the mapping data may be stored on the memory system (e.g., local memory 119) by the manufacturer of the memory system.

[0076] Now for reference Figure 7 Method 700, in some embodiments, represents a method for managing the read components (e.g., engine) of a memory system using analysis of command sequences. In some embodiments, operations 702, 704, 706, and 708 are respectively similar to those in reference [reference needed]. Figure 6 Operations 602, 604, 606, and 608 of method 600 are described. In response to determining that the number of write commands does not exceed (e.g., not greater than) a write command threshold, at operation 710, the processing device (e.g., 117) determines the current state of the read component (e.g., 114) of the memory system. Subsequently, at operation 712, the processing device (e.g., 117) determines whether the current state of the read component (e.g., 114) indicates that the read component is disabled (e.g., disconnected).

[0077] According to various embodiments, the processing device (e.g., 117) does not respond to the current state of a read component that indicates the read component is not disabled (i.e., enabled). However, in response to determining that the current state of the read component indicates that the read component is disabled, at operation 714, the processing device (e.g., 117) determines the time (e.g., an estimated time for memory system execution) for executing any remaining write commands in the write command sequence, and at operation 716, the processing device determines whether the (determined) time for execution is less than a delay time parameter.

[0078] In some embodiments, the processing device (e.g., 117) does not respond to a time for execution that is not less than the delay time parameter. However, in response to a time for execution that is less than the delay time parameter, at operation 718, the processing device (e.g., 117) enables the read component (e.g., 114). By enabling the read component in this way based on the delay time parameter, various embodiments can reduce or eliminate the latency effects of disabling the read component when a write command is finally retrieved from the command queue for execution.

[0079] Depending on the embodiment, the latency parameters can be set by the memory system manufacturer or the memory system user. Alternatively, the latency parameters can be determined based on (e.g., manufacturer or user) testing and tuning of the memory system. The latency parameters used for the read component and method 700 may differ from those used for the write component (and Figure 5 The delay time parameter of method 500).

[0080] Now for reference Figure 8 Method 800, in some embodiments, represents a method of managing the write engine 214 of a memory system using analysis of a read command sequence. At operation 802, a processing device (e.g., processor 117) determines whether the number of read commands in the read command sequence in command table 210 is greater than a read command threshold. If the processing device (e.g., 117) determines that the number is greater than the read command threshold, method 800 proceeds to operation 806; otherwise, method 800 proceeds to operation 804.

[0081] At operation 806, the processing device (e.g., 117) determines whether the write engine 214 of the memory system is idle. If the processing device (e.g., 117) determines that the write engine 214 is idle (at operation 806), the processing device disables the write engine 214; otherwise, method 800 returns to operation 802 (e.g., because the write engine 214 is busy).

[0082] At operation 804, the processing device (e.g., 117) determines whether the write engine 214 is disabled (e.g., disconnected). If the processing device (e.g., 117) determines that the write engine 214 is disabled, method 800 proceeds to operation 808; otherwise, the processing device does not perform any operation (810). At operation 808, the processing device (e.g., 117) determines whether the time (e.g., estimated time) for executing the pending (e.g., remaining) read commands from command table 210 is less than a delay time parameter (e.g., zero delay time parameter). If the processing device (e.g., 117) determines that the time is less than the delay time parameter (at operation 808), the processing device enables the write engine 214; otherwise, the processing device does not perform any operation (810).

[0083] Now for reference Figure 9 Method 900, in some embodiments, represents a method of managing the read engine 216 of a memory system using analysis of a write command sequence. At operation 902, a processing device (e.g., processor 117) determines whether the number of write commands in the write command sequence in command table 210 is greater than a write command threshold. If the processing device (e.g., 117) determines that the number is greater than the write command threshold, method 900 proceeds to operation 906; otherwise, method 900 proceeds to operation 904.

[0084] At operation 906, the processing device (e.g., 117) determines whether the read engine 216 of the memory system is idle. If the processing device (e.g., 117) determines that the read engine 216 is idle (at operation 906), the processing device disables the read engine 216; otherwise, method 900 returns to operation 902 (e.g., because the read engine 216 is busy).

[0085] At operation 904, the processing device (e.g., 117) determines whether the read engine 216 is disabled (e.g., disconnected). If the processing device (e.g., 117) determines that the read engine 216 is disabled, method 900 proceeds to operation 908; otherwise, the processing device does not perform any operation (910). At operation 908, the processing device (e.g., 117) determines whether the time (e.g., estimated time) for executing the pending (e.g., remaining) write commands from command table 210 is less than a delay time parameter (e.g., zero delay time parameter). If the processing device (e.g., 117) determines that the time is less than the delay time parameter (at operation 908), the processing device enables the read engine 216; otherwise, the processing device does not perform any operation (910).

[0086] Figure 10 Interaction diagrams are provided illustrating interactions between components of a computing environment in the context of some embodiments, where methods as described herein for managing memory command components (e.g., engines) using analysis of command sequences are executed. The operation of the methods may be performed by processing logic, which may include hardware (e.g., processing devices, circuit systems, dedicated logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions running or executed on the processing device), or a combination thereof. In some embodiments, the methods are performed by a host system (e.g., 120), a memory subsystem controller (e.g., 115), a write component (e.g., 113), a read component (e.g., 114), or some combination thereof. Although operations are shown in a specific order or sequence, the order of processes may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. Additionally, one or more processes may be omitted in various embodiments. Therefore, not all processes are used in every embodiment. Figure 10 In the context of the example shown, the host system may include host system 120, the memory subsystem controller may include memory subsystem controller 115, the write component may include write engine 113, and the read component may include read engine 114.

[0087] As shown in the figure, at operation 1002, the host system 120 sends one or more commands to the memory subsystem 110. At operation 1010, the memory subsystem controller 115 receives one or more commands from the host system 120.

[0088] At operation 1012, the memory subsystem controller 115 stores one or more commands in the command queue of the memory subsystem 110. Subsequently, at operation 1014, the memory subsystem controller 115 analyzes the current command sequence of the same command type to be executed next in the command queue. At operation 1016, based on the analysis of the command sequence (at operation 1014) and the current state of the write engine 113, the memory subsystem controller 115 enables or disables the write engine 113. At operation 1032, the write engine 113 responds to the memory subsystem controller by correspondingly facilitating the enabling or disabling of the memory subsystem controller 115. At operation 1018, based on the analysis of the command sequence (at operation 1014) and the current state of the read engine 114, the memory subsystem controller 115 enables or disables the read engine 114. At operation 1042, read engine 114 responds to memory subsystem controller by correspondingly enabling or disabling memory subsystem controller 115.

[0089] Figure 11 An example machine in the form of a computer system 1100 is shown, within which an executable instruction set is provided to cause the machine to perform any one or more of the methods discussed herein. In some embodiments, the computer system 1100 may be coupled to a host system (e.g., Figure 1 The host system 120 corresponds to a memory subsystem (e.g., Figure 1 The memory subsystem 110 may be used to perform the operations described herein. In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a local area network (LAN), intranet, extranet, and / or the Internet. The machine may operate as a peer-to-peer machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment, or within the capacity of a server or client machine in a client-server network environment.

[0090] The machine can be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular telephone, network appliance, server, network router, switch, or bridge, or any machine capable of (sequentially or otherwise) executing a set of instructions specifying actions to be taken by said machine. Furthermore, although a single machine is shown, it should also be understood that the term "machine" includes any set of machines that individually or jointly execute a set (or sets of sets) of instructions to perform any or more of the methods discussed herein.

[0091] Example computer system 1100 includes processing device 1102, main memory 1104 (e.g., ROM, flash memory, DRAM such as SDRAM or Rambus DRAM (RDRAM), static memory 1106 (e.g., flash memory, static random access memory (SRAM), etc.), and data storage device 1118, which communicate with each other via bus 1130.

[0092] Processing device 1102 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, processing device 1102 may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets or combinations of instruction sets. Processing device 1102 may also be one or more special-purpose processing devices, such as ASICs, FPGAs, digital signal processors (DSPs), network processors, etc. Processing device 1102 is configured to execute instructions 1126 for performing the operations and steps discussed herein. Computer system 1100 may also include a network interface device 1108 for communication on network 1120.

[0093] Data storage device 1118 may include machine-readable storage medium 1124 (also referred to as computer-readable medium) storing one or more instruction sets 1126 or software embodying any or more of the methods or functions described herein. The instructions 1126 may also reside wholly or at least partially within main memory 1104 and / or processing device 1102 during execution by computer system 1100, which also constitute machine-readable storage media. Machine-readable storage medium 1124, data storage device 1118, and / or main memory 1104 may correspond to... Figure 1 The memory subsystem 110.

[0094] In one embodiment, instruction 1126 includes instructions that implement functions corresponding to the analysis of the command sequence to manage the write components (e.g., the engine) of the memory system described herein. Figure 1(Memory command engine manager 112). Although the machine-readable storage medium 1124 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions for machine execution and causing the machine to perform any one or more of the methods of this disclosure. The term "machine-readable storage medium" may include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0095] Some parts of the previously described descriptions have been presented based on the algorithms and symbolic representations of operations on data bits within computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the essence of their work to others skilled in the art. An algorithm here is generally considered to be a self-consistent sequence of operations that produce a desired result. An operation is an operation that requires physical manipulation of physical quantities. These quantities are usually, but not necessarily, in the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Sometimes, primarily for general reasons, it has proven convenient to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, etc.

[0096] However, it should be remembered that all these and similar terms should be associated with appropriate physical quantities and are merely convenient notations applied to those quantities. This disclosure can refer to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities within the registers and memories of a computer system into other data similarly represented as physical quantities within the computer system's memory or registers or other such information storage systems.

[0097] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specifically constructed for its intended purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. Such computer programs may be stored in computer-readable storage media, each coupled to a computer system bus, such as, but not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards, or optical cards, or any type of media suitable for storing electronic instructions.

[0098] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with the programs taught herein, or it may be convenient to construct more specialized devices to perform the methods described herein. The structures of various such systems will be presented as set forth in the description below. Furthermore, this disclosure is described without reference to any particular programming language. It will be understood that the teachings of this disclosure as described herein can be implemented using a variety of programming languages.

[0099] This disclosure can be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon that can be used to program a computer system (or other electronic device) to perform processes according to this disclosure. The machine-readable medium includes any mechanism for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, the machine-readable (e.g., computer-readable) medium includes machine-readable storage media, such as ROM, RAM, disk storage media, optical storage media, flash memory components, etc.

[0100] In the foregoing description, embodiments of the present disclosure have been described with reference to specific examples. It will be apparent that various modifications can be made to the present disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative rather than restrictive sense.

Claims

1. A system comprising: Memory devices; A writing component that writes data to the memory device; A read component that reads data from the memory device; as well as A processing device operatively coupled to the memory device, the processing device being configured to perform operations including: Commands received from the host system are stored in the system's command queue; as well as When one or more commands are retrieved from the command queue for execution: The command queue is analyzed to detect when a sequence of read commands is queued, and then retrieved from the command queue for execution by the read component. as well as In response to the detection of the read command sequence: Determine the number of read commands in the read command sequence; Determine whether the number exceeds the read command threshold; as well as In response to determining that the number exceeds the read command threshold: Determine whether the current state of the write component indicates that the write component is in an idle state; and At least one of the following: In response to determining that the current state of the write component indicates that the write component is in an idle state, the write component is deactivated; or In response to determining that the current state of the write component indicates that the write component is not in an idle state, the write component is deactivated after the current state of the write component changes to indicate that the write component is in an idle state.

2. The system of claim 1, wherein analyzing the command queue to detect when the read command sequence is queued for subsequent retrieval from the command queue for execution by the read component comprises: The command queue is iterated through according to the order in which the one or more commands are stored in the command queue.

3. The system of claim 2, wherein the command queue includes a command table, each command is stored in the command table in association with a tag, and the order is determined based on the order in which tags are assigned to commands stored in the command table.

4. The system of claim 1, wherein disabling the write component includes disabling the write component based on mapping data describing components associated with the write component.

5. The system according to claim 1, wherein the operation further comprises: In response to determining that the current state of the write component indicates that the write component is not in an idle state: Re-determine the number of read command sequences; as well as In response to determining that the number of re-determined values ​​exceeds the read command threshold: Re-determine the current state of the writing component; and The write component is enabled or disabled based on the redefined current state of the write component.

6. The system of claim 1, wherein the operation includes: In response to determining that the number does not exceed the read command threshold: Determine the current state of the writing component; Determine whether the current state of the writing component indicates that the writing component is disabled; as well as In response to determining the current state of the write component, indicating that the write component is disabled: Determine the time for executing any remaining read commands in the sequence of read commands; Determine whether the time used for execution is less than the delay time parameter; and In response to determining that the time available for execution is less than the delay time parameter, the write component is enabled.

7. The system of claim 6, wherein the delay time parameter is user-defined.

8. The system according to claim 1, wherein the read command threshold is user-defined.

9. The system of claim 1, wherein the processing means is part of the memory subsystem controller of the system, and the command queue is stored in the local memory of the memory subsystem controller.

10. A method comprising: Commands received from the host system are stored in the command queue of the memory system; as well as When one or more commands are retrieved from the command queue for execution: The command queue is analyzed to detect when a sequence of write commands is queued, and then retrieved from the command queue for execution by the write component of the memory system. as well as In response to the detection of the write command sequence: Determine the number of write commands in the write command sequence; Determine whether the number exceeds the write command threshold; as well as In response to determining that the number exceeds the write command threshold: Determine whether the current state of the read component of the memory system indicates that the read component is in an idle state; and The reading component is deactivated in response to determining that the current state of the reading component indicates that the reading component is in an idle state.

11. The method of claim 10, wherein analyzing the command queue to detect when the write command sequence is queued and then retrieved from the command queue for execution by the write component comprises: The command queue is iteratively traversed according to the order in which one or more commands are retrieved from the host system by the command queue.

12. The method of claim 10, wherein disabling the reading component includes disabling a component of the reading component based on mapping data describing components associated with the reading component.

13. The method of claim 10, further comprising: In response to determining that the current state of the reading component indicates that the reading component is not in an idle state: Re-determine the number of the write command sequence; as well as In response to determining that the number of re-determined values ​​exceeds the write command threshold: Re-determine the current state of the reading component; and The reading component is enabled or disabled based on its current state as determined.

14. The method of claim 10, further comprising: In response to determining that the number does not exceed the write command threshold: Determine the current state of the reading component; The current state of the reading component indicates that the reading component is disabled; as well as In response to determining the current state of the reading component, the reading component is disabled: Determine the time for executing any remaining write commands in the sequence of write commands; Determine whether the time used for execution is less than the delay time parameter; and In response to determining that the time available for execution is less than the delay time parameter, the reading component is enabled.

15. The method of claim 14, wherein the delay time parameter is user-defined.

16. The method of claim 10, wherein the write command threshold is user-defined.

17. At least one non-transitory machine-readable storage medium, comprising instructions that, when executed by a processing device of a memory system, cause the processing device to perform operations including: Commands from the host system are stored in the command queue of the memory system; and When one or more commands are retrieved from the command queue for execution: The command sequence of the same command type is analyzed in the command queue, and the command sequence is queued and then retrieved from the command queue for execution by the read or write component of the memory system. The writing component is enabled or disabled based on its current state and analysis of the command sequence, wherein enabling or disabling the writing component includes: Determine whether the current state of the write component indicates that the write component is in an idle state; and At least one of the following: In response to determining that the current state of the write component indicates that the write component is in an idle state, the write component is deactivated; or In response to determining that the current state of the write component indicates that the write component is not in an idle state, the write component is deactivated after the current state of the write component changes to indicate that the write component is in an idle state; and The reading component is enabled or disabled based on its current state and analysis of the command sequence, wherein enabling or disabling the reading component includes: Determine whether the current state of the reading component indicates that the reading component is in an idle state; and The reading component is deactivated in response to determining that the current state of the reading component indicates that the reading component is in an idle state.

Images