Method, device, equipment and medium for asset information function processing of pcie device

Abstract

The application provides a kind of PCIE device's asset information function processing method, device, equipment and readable medium, method includes: the information of all PCIE devices in system and topological architecture are collected, and PCIE device information table is drawn;In response to determining that board card is directly connected to CPU PCIE Root Port, first physical slot number is designed, and first physical slot number is written into the PCIE configuration space of each Root Port;In response to determining that board card exists multi-level topological card, the physical slot number information of all levels of PCIE bridge in board card is collected;In response to the physical slot number information of all levels of PCIE bridge in board card collected and first physical slot number match, BIOS finds the silk printing information of slot in PCIE device information table based on the physical slot number matched, and physical slot number and silk printing information are sent to BMC.Using the scheme of the application, the maintenance personnel can be positioned to the error device, the maintenance cost can be saved, the customer satisfaction can be improved, and the product competitiveness can be enhanced.

Description

Technical Field

[0001] This invention relates to the field of computers, and more specifically to a method, apparatus, and readable medium for processing asset information functions of a PCIe device. Background Technology

[0002] In a PCIe (Peripheral Component Interconnect Express) topology, there are one or more PCIe bridges, followed by PCIe end devices. Some models, such as AI server models, use a Switch (PCIe converter) board architecture in their system design. The Switch board connects some PCIe devices. The BIOS implements the PCIe device asset information function, collecting relevant attribute information of the PCIe devices and sending it to the BMC. The BMC then displays it on its WebUI interface for the user. An important part of the asset information is the device's location information. This location information needs to show the silkscreen of the PCIe device's slot to achieve a one-to-one correspondence between the device and its physical location in the machine.

[0003] For PCIe devices with multi-level PCIe topologies, because there are one or more PCIe bridges before the PCIe end devices, the device's Physical Slot Number attribute cannot be inherited from the pre-designed value. Instead, it inherits the value from the bridge in its own topology, resulting in a value that does not match the design. Furthermore, in multi-level topologies, devices are generally assigned a default value of 0. Therefore, when multiple devices exist, each device's Physical Slot Number will be 0, which is not only not the designed value but also does not meet the uniqueness requirement, rendering the solution ineffective and unable to match the correct location information. Consequently, neither the display on the BMC webUI nor the error location function can accurately reflect the device's location information. Not only will the correspondence between the device and the physical slot position fail, but the error location function will also fail. Summary of the Invention

[0004] In view of this, the purpose of this invention is to provide a method, apparatus, device and readable medium for processing asset information of PCIe devices. By using the technical solution of this invention, maintenance personnel can locate the faulty device, save maintenance costs, improve customer satisfaction and enhance product competitiveness.

[0005] To achieve the above objectives, one aspect of the present invention provides a method for processing asset information functions of a PCIe device, comprising the following steps:

[0006] Collect information and topology of all PCIe devices in the system, and draw a PCIe device information table;

[0007] In response to determining that the board is directly connected to the CPU PCIE Root Port, the first physical slot number is designed and written into the PCIE configuration space of each Root Port;

[0008] In response to the determination that the board has a multi-level topology, collect the physical slot number information of the PCIe bridges at all levels in the board;

[0009] In response to the matching of the physical slot number information of all levels of PCIe bridges in the collected board with the first physical slot number, the BIOS looks up the silkscreen information of the slot in the PCIe device information table based on the matched physical slot number, and sends the physical slot number and silkscreen information to the BMC.

[0010] According to one embodiment of the present invention, it further includes:

[0011] In response to determining that the board is connected to the Switch board, a second physical slot number is designed and written into each slot of the Switch board.

[0012] According to one embodiment of the present invention, it further includes:

[0013] Collect the physical slot number information of all levels of PCIe bridges in the Switch board;

[0014] In response to the matching of the physical slot number information of all levels of PCIe bridges in the Switch board with the second physical slot number, the BIOS looks up the silkscreen information of the slot in the PCIe device information table based on the matched physical slot number, and sends the physical slot number and silkscreen information to the BMC.

[0015] According to one embodiment of the present invention, in response to determining that the board is directly connected to the CPU PCIe Root Port, designing a first physical slot number and writing the first physical slot number into the PCIe configuration space of each Root Port includes:

[0016] Determine whether the board is directly connected to the CPU PCIe RootPort based on the topology of all collected PCIe devices;

[0017] In response to determining that the board is directly connected to the CPU PCIe Root Port, a first physical slot number is designed that is different from the physical slot numbers of all PCIe bridges;

[0018] The first physical slot number is written into the physical slot number field in the PCIe configuration space of each Root Port through software read / write access.

[0019] According to one embodiment of the present invention, in response to determining that the card has a multi-level topology, collecting the physical slot number information of the PCIe bridges at all levels in the card includes:

[0020] In response to the implementation of the system's asset information function and SMBIOS type 9 function, the BIOS cyclically collects information from PCIe devices;

[0021] Based on the vendor ID, device ID, subsystem ID, and subsystem vendor ID collected from the information, determine whether there are cards with multi-level topologies in the board.

[0022] According to one embodiment of the present invention, in response to determining that the board is connected to the Switch board, designing a second physical slot number and writing the second physical slot number into each slot of the Switch board includes:

[0023] In response to determining that the board is connected to the Switch board, a second physical slot number is designed that is different from the physical slot numbers of all PCIe bridges;

[0024] The value of the second physical slot number can be set to the physical slot number of each slot or socket on the Switch board by rewriting or setting the firmware of the Switch board.

[0025] Another aspect of the present invention provides an apparatus for processing asset information functions of a PCIe device, the apparatus comprising:

[0026] The drawing module is configured to collect information and topology of all PCIe devices in the system and draw a PCIe device information table.

[0027] The write module is configured to design a first physical slot number in response to determining that the board is directly connected to the CPU PCIE Root Port, and write the first physical slot number to the PCIE configuration space of each Root Port.

[0028] The collection module is configured to collect the physical slot number information of all levels of PCIe bridges in the board in response to determining that the board has a multi-level topology;

[0029] The processing module is configured to respond to the matching of the physical slot number information of all levels of PCIe bridges in the board with the first physical slot number. Based on the matched physical slot number, the BIOS looks up the silkscreen information of the slot in the PCIe device information table and sends the physical slot number and silkscreen information to the BMC.

[0030] According to one embodiment of the present invention, it further includes a sending module, which is configured to design a second physical slot number and write the second physical slot number into each slot of the Switch board in response to determining that the board is connected to the Switch board.

[0031] Collect the physical slot number information of all levels of PCIe bridges in the Switch board;

[0032] In response to the matching of the physical slot number information of all levels of PCIe bridges in the Switch board with the second physical slot number, the BIOS looks up the silkscreen information of the slot in the PCIe device information table based on the matched physical slot number, and sends the physical slot number and silkscreen information to the BMC.

[0033] Another aspect of the embodiments of the present invention also provides a computer device, the computer device comprising:

[0034] At least one processor; and

[0035] The memory stores computer instructions that can be executed by a processor, which, when executed by the processor, implement the steps of any of the methods described above.

[0036] In another aspect, embodiments of the present invention also provide a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of any of the above methods.

[0037] The present invention has the following beneficial technical effects: The method for processing PCIe device asset information provided in the embodiments of the present invention collects information and topology of all PCIe devices in the system and draws a PCIe device information table; in response to determining that the board is directly connected to the CPU PCIe Root Port, a first physical slot number is designed and written into the PCIe configuration space of each Root Port; in response to determining that the board has a multi-level topology, the physical slot number information of all levels of PCIe bridges in the board is collected; in response to matching the collected physical slot number information of all levels of PCIe bridges in the board with the first physical slot number, the BIOS searches for the silkscreen information of the slot in the PCIe device information table based on the matched physical slot number and sends the physical slot number and silkscreen information to the BMC. This technical solution enables maintenance personnel to locate the faulty device, saves maintenance costs, improves customer satisfaction, and enhances product competitiveness. Attached Figure Description

[0038] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other embodiments can be obtained based on these drawings without creative effort.

[0039] Figure 1 A schematic flowchart illustrating a method for processing asset information functions of a PCIe device according to an embodiment of the present invention;

[0040] Figure 2 This is a schematic diagram of an apparatus for processing asset information functions of a PCIe device according to an embodiment of the present invention;

[0041] Figure 3 This is a schematic diagram of a computer device according to an embodiment of the present invention;

[0042] Figure 4 This is a schematic diagram of a computer-readable storage medium according to an embodiment of the present invention. Detailed Implementation

[0043] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be further described in detail below with reference to specific examples and the accompanying drawings.

[0044] Based on the above objectives, a first aspect of the embodiments of the present invention provides an embodiment of a method for processing asset information functions of a PCIe device. Figure 1 The diagram shown is a schematic flowchart of the method.

[0045] like Figure 1 As shown, the method may include the following steps:

[0046] S1 collects information and topology data for all PCIe devices in the system and generates a PCIe device information table. Before implementing the PCIe device asset information function and the SMBIOS type 9 information function, it first studies the board's technical documentation and collects information and topology data for all PCIe devices on the machine through functions such as lspci under the operating system or UEFI shell. Based on the collected information and topology data, it generates a PCIe device information table containing relevant information for all PCIe devices.

[0047] In response to determining that the board is directly connected to the CPU PCIe Root Port, S2 designs the first physical slot number and writes it into the PCIe configuration space of each Root Port. It can determine whether the board is directly connected to the CPU PCIe Root Port based on the PCIe device topology. For cases where the board is directly connected to the CPU PCIe Root Port (i.e., without an intermediate adapter), a unique physical slot number is designed for each Root Port of the connected device. This number is different from the physical slot numbers of other PCIe bridges, such as A, B, C, and D. Simultaneously, the designed first physical slot number and its location information are stored in the corresponding positions in the information table. Then, through software read / write access methods, such as IO read / write and memory configuration space read / write, the first physical slot number is written into the physical slot number field of the PCIe configuration space of each Root Port, as in the example above, writing the values ​​of A, B, C, and D respectively.

[0048] In response to determining that a card has a multi-level topology, S3 collects the physical slot number information of all levels of PCIe bridges on the card. When collecting PCIe device information, four IDs are obtained: vendor ID, device ID, subsystem ID, and subsystem vendor ID. These IDs are used to identify the card's manufacturer and model. When implementing asset information and SMBIOS type 9 functions, the BIOS uses these four IDs to determine if a card has a multi-level topology when collecting device information in a loop. If not, no special processing is done; if so, the algorithm provided by the PCI / PCIe specification collects the PCIe bridge information for all levels of the card, including its own existing PCIe bridge information and the physical slot number information of each level of PCIe bridge.

[0049] S4 responds by matching the physical slot number information of all levels of PCIe bridges in the board with the first physical slot number. Based on the matched physical slot number, the BIOS searches for the slot's silkscreen information in the PCIe device information table and sends the physical slot number and silkscreen information to the BMC. In the physical slot number values ​​of each PCIe bridge level, it checks if the first physical slot number exists (i.e., one of the special values ​​A, B, C, or D mentioned above). If it exists, this special value is assigned to the physical slot number of the terminal device of that multi-level topology board. Then, using this physical slot number, it searches the information table for the silkscreen information of the corresponding slot, i.e., the device's location information. Finally, the physical slot number and silkscreen information are sent to the BMC.

[0050] By using the technical solution of this invention, maintenance personnel can locate the faulty device, save maintenance costs, improve customer satisfaction, and enhance product competitiveness.

[0051] In a preferred embodiment of the present invention, it further includes:

[0052] In response to the confirmation that the board is connected to the Switch board, a second physical slot number is designed and written into each slot of the Switch board. If there are devices with multi-level topologies that are not directly connected to the CPU PCIe root port, but are connected to the Switch board, a special and unique set of values ​​(not duplicated with the physical slot numbers of other devices) should be designed, preferably consecutive values ​​for easy identification, such as 100, 101, 102. Then, by rewriting or setting the Switch board's firmware, the designed values ​​are set as the physical slot numbers of the slots or sockets on the Switch board.

[0053] In a preferred embodiment of the present invention, it further includes:

[0054] Collect the physical slot number information of all levels of PCIe bridges in the Switch board;

[0055] In response to the collected physical slot number information of all levels of PCIe bridges in the Switch board matching the second physical slot number, the BIOS searches for the slot's silkscreen information in the PCIe device information table based on the matched physical slot number, and sends the physical slot number and silkscreen information to the BMC. Using the algorithm provided by the PCI / PCIe specification, the BIOS collects information on all levels of PCIe bridges on the board, including its own existing PCIe bridges and the physical slot numbers of each level of PCIe bridge. Among the physical slot number values ​​of each level of PCIe bridge, it checks if there is a value (second physical slot number) assigned to the physical slot number of the slot or socket on the Switch board, i.e., one of 100, 101, or 102. If so, this special value is assigned to the physical slot number of the terminal device on the board. Then, this physical slot number is used to match the information table to find the silkscreen information of the corresponding slot, i.e., the device's location information. Finally, the physical slot number and silkscreen information are sent to the BMC.

[0056] The Slot ID for SMBIOS Type 9 functionality, also known as the device physical slot number, is processed and implemented using the above method to match the correct location information. At this point, the location information for device asset information, SMBIOS Type 9 related information, and device alarm and error reporting functions are all accurately implemented. The device location information matching function described above can also be implemented through the BMC, using the same processing method as the BIOS.

[0057] In a preferred embodiment of the present invention, in response to determining that the board is directly connected to the CPU PCIe Root Port, designing a first physical slot number and writing the first physical slot number into the PCIe configuration space of each Root Port includes:

[0058] Determine whether the board is directly connected to the CPU PCIe RootPort based on the topology of all collected PCIe devices;

[0059] In response to determining that the board is directly connected to the CPU PCIe Root Port, a first physical slot number is designed that is different from the physical slot numbers of all PCIe bridges;

[0060] The first physical slot number is written into the physical slot number field in the PCIe configuration space of each Root Port through software read / write access.

[0061] In a preferred embodiment of the present invention, in response to determining that the card has a multi-level topology, collecting the physical slot number information of all levels of PCIe bridges in the card includes:

[0062] In response to the implementation of the system's asset information function and SMBIOS type 9 function, the BIOS cyclically collects information from PCIe devices;

[0063] Based on the vendor ID, device ID, subsystem ID, and subsystem vendor ID collected from the information, determine whether there are cards with multi-level topologies in the board.

[0064] In a preferred embodiment of the present invention, in response to determining that the board is connected to the Switch board, designing a second physical slot number and writing the second physical slot number into each slot of the Switch board includes:

[0065] In response to determining that the board is connected to the Switch board, a second physical slot number is designed that is different from the physical slot numbers of all PCIe bridges;

[0066] The value of the second physical slot number can be set to the physical slot number of each slot or socket on the Switch board by rewriting or setting the firmware of the Switch board.

[0067] This invention effectively solves the problems of malfunction in the location information of PCIe device assets and the device location function of the error reporting function, which are jointly implemented by the BIOS and BMC, when the system is connected to a board with a PCIe bridge topology of one or more levels. It also solves the problem of inaccurate SMBIOS type9 function information implemented by the BIOS. This makes it easier for equipment maintenance personnel to locate the faulty device for maintenance, saves maintenance costs, improves customer satisfaction, enhances product competitiveness, and indirectly increases revenue.

[0068] It should be noted that those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc. The embodiments of the computer program described above can achieve the same or similar effects as any of the corresponding foregoing method embodiments.

[0069] Furthermore, the method disclosed in the embodiments of the present invention can also be implemented as a computer program executed by a CPU, which may be stored in a computer-readable storage medium. When the computer program is executed by the CPU, it performs the functions defined in the method disclosed in the embodiments of the present invention.

[0070] Based on the above objectives, a second aspect of the embodiments of the present invention provides an apparatus for processing asset information functions of a PCIe device, such as... Figure 2 As shown, the device 200 includes:

[0071] The drawing module is configured to collect information and topology of all PCIe devices in the system and draw a PCIe device information table.

[0072] The write module is configured to design a first physical slot number in response to determining that the board is directly connected to the CPU PCIE Root Port, and write the first physical slot number to the PCIE configuration space of each Root Port.

[0073] The collection module is configured to collect the physical slot number information of all levels of PCIe bridges in the board in response to determining that the board has a multi-level topology;

[0074] The processing module is configured to respond to the matching of the physical slot number information of all levels of PCIe bridges in the board with the first physical slot number. Based on the matched physical slot number, the BIOS looks up the silkscreen information of the slot in the PCIe device information table and sends the physical slot number and silkscreen information to the BMC.

[0075] In a preferred embodiment of the present invention, a sending module is further included, which is configured to design a second physical slot number and write the second physical slot number into each slot of the Switch board in response to determining that the board is connected to the Switch board.

[0076] Collect the physical slot number information of all levels of PCIe bridges in the Switch board;

[0077] In response to the matching of the physical slot number information of all levels of PCIe bridges in the Switch board with the second physical slot number, the BIOS looks up the silkscreen information of the slot in the PCIe device information table based on the matched physical slot number, and sends the physical slot number and silkscreen information to the BMC.

[0078] In view of the above objectives, a third aspect of the present invention provides a computer device. Figure 3 The diagram shown is a schematic representation of an embodiment of the computer device provided by the present invention. Figure 3 As shown, embodiments of the present invention include the following apparatus: at least one processor 21; and a memory 22, the memory 22 storing computer instructions 23 that can be executed on the processor, the instructions implementing the above method when executed by the processor.

[0079] In view of the above objectives, a fourth aspect of the present invention provides a computer-readable storage medium. Figure 4 The diagram shown is a schematic representation of an embodiment of the computer-readable storage medium provided by the present invention. Figure 4 As shown, the computer-readable storage medium 31 stores a computer program 32 that, when executed by a processor, performs the methods described above.

[0080] Furthermore, the method disclosed in the embodiments of the present invention can also be implemented as a computer program executed by a processor, which may be stored in a computer-readable storage medium. When the computer program is executed by the processor, it performs the functions defined in the method disclosed in the embodiments of the present invention.

[0081] Furthermore, the above-described method steps and system units can also be implemented using a controller and a computer-readable storage medium for storing a computer program that enables the controller to perform the functions of the above-described steps or units.

[0082] Those skilled in the art will also understand that the various exemplary logic blocks, modules, circuits, and algorithm steps described in conjunction with the disclosure herein can be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability between hardware and software, the functionality of various illustrative components, blocks, modules, circuits, and steps has been generally described. Whether this functionality is implemented as software or as hardware depends on the specific application and the design constraints imposed on the system as a whole. Those skilled in the art can implement the functionality in various ways for each specific application, but such implementation decisions should not be construed as departing from the scope of the embodiments disclosed herein.

[0083] In one or more exemplary designs, functionality may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, functionality may be stored as one or more instructions or code on or transmitted via a computer-readable medium. Computer-readable media include computer storage media and communication media, including any medium that facilitates the transfer of a computer program from one location to another. Storage media may be any available medium accessible to a general-purpose or special-purpose computer. By way of example, and not limitation, computer-readable media may include RAM, ROM, EEPROM, CD-ROM or other optical disc storage devices, disk storage devices or other magnetic storage devices, or any other medium that may be used to carry or store the required program code in the form of instructions or data structures and is accessible to a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Furthermore, any connection may be appropriately referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the aforementioned coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are all included in the definition of media. As used herein, disks and optical discs include compact discs (CDs), laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs, where disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. Combinations of the above should also be included within the scope of computer-readable media.

[0084] The above are exemplary embodiments disclosed in this invention. However, it should be noted that various changes and modifications can be made without departing from the scope of the embodiments of this invention as defined by the claims. The functions, steps, and / or actions of the methods according to the disclosed embodiments described herein do not need to be performed in any particular order. Furthermore, although the elements disclosed in the embodiments of this invention may be described or claimed individually, they may be understood as multiple unless explicitly limited to a singular number.

[0085] It should be understood that, as used herein, the singular form “a” is intended to include the plural form as well, unless the context clearly supports an exception. It should also be understood that, as used herein, “and / or” refers to any and all possible combinations of one or more of the associated listed items.

[0086] The embodiment numbers disclosed in the above embodiments of the present invention are merely for description and do not represent the superiority or inferiority of the embodiments.

[0087] Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware or by a program instructing related hardware. The program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk.

[0088] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of the invention (including the claims) is limited to these examples. Within the framework of the invention, technical features of the above embodiments or different embodiments can be combined, and many other variations of different aspects of the invention exist, which are not provided in the details for the sake of brevity. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the invention should be included within the protection scope of the invention.

Claims

1. A method for processing asset information functions of a PCIe device, characterized in that, Includes the following steps: Collect information and topology of all PCIe devices in the system, and draw a PCIe device information table; Determine whether the board is directly connected to the CPU PCIe Root Port based on the topology of all collected PCIe devices; In response to the determination that the board is directly connected to the CPU PCIe Root Port, a first physical slot number is designed that is different from the physical slot numbers of all PCIe bridges; the first physical slot number is written into the physical slot number bit in the PCIe configuration space of each Root Port through software read and write access. In response to the determination that the board has a multi-level topology, collect the physical slot number information of the PCIe bridges at all levels in the board; In response to the matching of the physical slot number information of all levels of PCIe bridges in the collected board with the first physical slot number, the BIOS looks up the silkscreen information of the slot in the PCIe device information table based on the matched physical slot number, and sends the physical slot number and silkscreen information to the BMC.

2. The method according to claim 1, characterized in that, Also includes: In response to determining that the board is connected to the Switch board, a second physical slot number is designed and written into each slot of the Switch board.

3. The method according to claim 2, characterized in that, Also includes: Collect the physical slot number information of all levels of PCIe bridges in the Switch board; In response to the matching of the physical slot number information of all levels of PCIe bridges in the Switch board with the second physical slot number, the BIOS looks up the silkscreen information of the slot in the PCIe device information table based on the matched physical slot number, and sends the physical slot number and silkscreen information to the BMC.

4. The method according to claim 1, characterized in that, In response to the determination that a card has a multi-level topology, the physical slot number information of the PCIe bridges at all levels in the card is collected, including: In response to the implementation of the system's asset information function and SMBIOS type 9 function, the BIOS cyclically collects information from PCIe devices; Based on the vendor ID, device ID, subsystem ID, and subsystem vendor ID collected from the information, determine whether there are cards with multi-level topologies in the board.

5. The method according to claim 2, characterized in that, In response to determining that the board is connected to the Switch board, a second physical slot number is designed, and the second physical slot number is written into each slot of the Switch board, including: In response to determining that the board is connected to the Switch board, a second physical slot number is designed that is different from the physical slot numbers of all PCIe bridges; The value of the second physical slot number can be set to the physical slot number of each slot or socket on the Switch board by rewriting or setting the firmware of the Switch board.

6. A device for processing asset information of a PCIe device, characterized in that, The device includes: A drawing module is configured to collect information and topology of all PCIe devices in the system and draw a PCIe device information table. The writing module is configured to determine whether the board is directly connected to the CPU PCIe Root Port based on the topology of all collected PCIe devices; in response to determining that the board is directly connected to the CPU PCIe Root Port, design a first physical slot number that is different from the physical slot numbers of all PCIe bridges; and write the first physical slot number into the physical slot number bit in the PCIe configuration space of each Root Port through software read / write access. A collection module is configured to collect the physical slot number information of all levels of PCIe bridges in the board in response to determining that the board has a multi-level topology; The processing module is configured to, in response to the physical slot number information of all levels of PCIe bridges in the board being collected and matched with the first physical slot number, search for the silkscreen information of the slot in the PCIe device information table based on the matched physical slot number, and send the physical slot number and silkscreen information to the BMC.

7. The apparatus according to claim 6, characterized in that, It also includes a sending module configured to design a second physical slot number and write the second physical slot number into each slot of the Switch board in response to determining that the board is connected to the Switch board. Collect the physical slot number information of all levels of PCIe bridges in the Switch board; In response to the matching of the physical slot number information of all levels of PCIe bridges in the Switch board with the second physical slot number, the BIOS looks up the silkscreen information of the slot in the PCIe device information table based on the matched physical slot number, and sends the physical slot number and silkscreen information to the BMC.

8. A computer device, characterized in that, include: At least one processor; as well as A memory storing computer instructions executable on the processor, which, when executed by the processor, implement the steps of the method according to any one of claims 1-5.

9. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1-5.

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