Partial superblock memory management

Abstract

An apparatus can include a partial superblock memory management component. The partial superblock memory management component can identify bad blocks in respective planes of blocks of non-volatile memory units. The partial superblock memory management component can determine that a plane of the respective planes includes at least good blocks in at least one different block of non-volatile memory units. The partial superblock memory management component can perform operations to reallocate the at least one good block in the plane to the at least one bad block in the plane to form a block of non-volatile memory units having a number of bad blocks that satisfies a bad block threshold.

Description

Technical Field

[0001] The embodiments of this disclosure generally relate to memory subsystems, and more specifically to partial superblock memory management. Background Technology

[0002] A memory subsystem may include one or more memory devices for storing data. These memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system can utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the Invention

[0003] A method for partial superblock memory management is described. The method includes: identifying defective blocks in corresponding planes of non-volatile memory cell blocks among a plurality of NAND memory cell blocks in a non-volatile memory device; determining that a certain plane among the corresponding planes contains at least one good block among at least one different non-volatile memory cell block among the plurality of non-volatile memory cell blocks; and performing operations to reallocate the at least one good block in the plane to the at least one defective block among the defective blocks in the plane to form a plurality of non-volatile memory cell blocks having a number of defective blocks satisfying a defective block threshold.

[0004] A device for partial superblock memory management is described. The device includes a partial superblock memory management component. The partial superblock memory management component is configured to: determine that a corresponding number of bad blocks in a non-volatile memory cell block is greater than a bad block threshold; perform an operation to reallocate good blocks from a plane in another non-volatile memory cell block to replace bad blocks in the same plane of the non-volatile memory cell block to form a plurality of non-volatile memory cell blocks, each having a number of bad blocks less than or equal to the bad block threshold; and write host data to the plurality of non-volatile memory cell blocks having a number of bad blocks less than or equal to the bad block threshold.

[0005] A system for partial superblock memory management is described. The system includes: a memory subsystem comprising a plurality of memory components arranged in a stackable cross-grid array of a plurality of superblocks forming fault-tolerant non-volatile memory cells; and a processing means coupled to the plurality of memory components. The processing means is configured to perform operations including: identifying a corresponding number of bad blocks in a partial superblock of the plurality of superblocks; determining that the corresponding number of bad blocks satisfies a bad block threshold; performing operations to reallocate good blocks from a plane in another superblock of the plurality of superblocks to replace bad blocks in the same plane of the partial superblocks to form a plurality of partial superblocks, each having a number of bad blocks less than or equal to the bad block threshold; and writing host data to the plurality of partial superblocks having a number of bad blocks less than or equal to the bad block threshold. Attached Figure Description

[0006] This disclosure will be more fully understood from the detailed description given below and the accompanying drawings of various embodiments thereof.

[0007] Figure 1 Examples of computing systems including a memory subsystem are shown according to some embodiments of the present disclosure.

[0008] Figure 2A Examples of non-volatile memory arrays according to some embodiments of the present disclosure are shown.

[0009] Figure 2B Another example of a non-volatile memory array according to some embodiments of the present disclosure is shown.

[0010] Figure 3 An example flowchart of partial superblock memory management according to some embodiments of the present disclosure is shown.

[0011] Figure 4 Example methods of superblock memory management according to embodiments of the present disclosure are shown.

[0012] Figure 5 This is a block diagram of an example computer system in which embodiments of this disclosure may be operated. Detailed Implementation

[0013] This disclosure pertains to partial superblock memory management, and more specifically to a memory subsystem that includes partial superblock memory management components. The memory subsystem can be a storage device, a memory module, or a hybrid of a storage device and a memory module. An example of a memory subsystem is a storage system, such as a solid-state drive (SDD). The following description, in conjunction with… Figure 1Describe examples of storage devices and memory modules. Generally, a host system may utilize a memory subsystem that includes one or more components (e.g., a "memory device" for storing data). The host system can provide data to be stored in the memory subsystem and can request data to be retrieved from the memory subsystem.

[0014] Memory devices can be non-volatile memory devices. An example of a non-volatile memory device is a NAND flash memory device (also known as flash memory). The following section combines... Figure 1 Other examples of non-volatile memory devices are described. A non-volatile memory device is a package of one or more dies. Each die may consist of one or more planes. Planes may be grouped into logical units (LUNs). For some types of non-volatile memory devices (e.g., NAND devices), each plane consists of a set of physical blocks. Each block consists of a set of pages. Each page consists of a set of memory cells (“cells”). A cell is an electronic circuit that stores information. Hereinafter, a block refers to a unit of a memory device used to store data and may contain groups of memory cells, groups of word lines, word lines, or individual memory cells. For some memory devices, a block (also referred to below as a “memory block”) is the smallest erasable area. Pages cannot be erased individually; only the entire block can be erased.

[0015] Each memory device may contain one or more arrays of memory cells. Depending on the cell type, a cell may be written to store one or more bits of binary information and has various logical states related to the number of bits being stored. Logical states may be represented by binary values ​​(e.g., "0" and "1") or combinations of these values. Various types of cells exist, such as single-level cell (SLC), multi-level cell (MLC), three-level cell (TLC), and four-level cell (QLC). For example, an SLC may store one bit of information and have two logical states.

[0016] Some NAND memory devices employ a floating gate architecture, where memory access is controlled based on a relative voltage change between the bit line and the word line. Other examples of NAND memory devices may employ an alternative gate architecture that may include a word line layout, which allows for the trapping of charges corresponding to data values ​​within the memory cell based on the properties of the materials used to construct the word lines.

[0017] NAND performance can be determined by the programming speed of NAND. That is, the speed at which pages of NAND are programmed. A system can improve performance by grouping multiple NAND pages together to program them in parallel. For example, superblocks can be formed to increase system performance. As used in this article, a superblock can refer to a collection of blocks that span multiple dies written in an interleaved manner. In some cases, a superblock can span all dies within the SSD. A superblock can contain multiple blocks from a single die. A superblock can be a management unit within the SSD.

[0018] Traditionally, a superblock contains blocks from each plane of each die in a NAND flash memory. However, due to non-uniformity and variation during the manufacturing process, NAND flash memory may initially contain a small percentage of defective blocks. Furthermore, as blocks wear out during the operational lifespan of the NAND flash memory, good blocks (i.e., blocks that were not classified as defective and could initially reliably store data) may become defective.

[0019] As used herein, a bad block refers to an area of ​​the storage medium that is no longer reliably able to store and retrieve data due to physical damage or decay. Bad blocks are also called bad sectors. Conversely, as used herein, a good block refers to a functional block that can be used to store data. When a block in any die plane becomes a bad block, a traditional superblock (i.e., a complete superblock) is not formed. This essentially reduces the number of superblocks that can be formed, thereby degrading the performance of the NAND array.

[0020] To address this issue, partial superblocks can be used. Partial superblocks remove planes that have defective blocks across the die (e.g., a partial superblock has one or more fewer planes than a full superblock). The use of partial superblocks (e.g., having at least one defective block) provides benefits to NAND devices in several ways. For example, with partial superblocks, the die can be considered good as long as other planes have fewer defects. For acceptable dies, having fewer good blocks per plane necessitates designing fewer redundant blocks or planes into the NAND. Therefore, a lower total block count and smaller die size reduce the cost per die of the NAND. This effect also achieves higher manufacturing yields because a single plane defect will not result in a die defect.

[0021] However, the use of partial superblocks can provide reduced performance compared to the performance achieved with traditional full superblocks. The amount of performance reduction in partial superblocks can be a function of the number of bad blocks in the partial superblock. A larger number of bad blocks can lead to a significant performance degradation. For example, an individual bad block in a partial superblock can cause a performance degradation of ~12.5%, while two bad blocks in a partial superblock can cause a degradation of 25%. A significant performance degradation can be perceived by the end user and / or may interfere with the operation of the memory device.

[0022] Thus, some methods attempt to reallocate blocks to reduce the number of partial superblocks. While this reduces the number of partial superblocks, it can also cause bad blocks to accumulate in the remaining partial superblocks, thereby exacerbating the performance degradation of the remaining partial superblocks. Furthermore, in some other methods, partial superblocks are not used (e.g., not used for data storage). However, not using these partial superblocks can also degrade system performance. The performance degradation caused by the accumulation of bad blocks in partial superblocks and / or the non-use of partial superblocks may be undesirable, especially in critical applications and / or applications with high expectations for memory subsystem performance. Moreover, this performance degradation that may occur in such methods can be further exacerbated in mobile (e.g., smartphones, IoT, etc.) memory deployments, where the amount of space available to accommodate the memory subsystem is limited compared to traditional computing architectures.

[0023] The present disclosure addresses the above and other deficiencies by performing partial superblock memory management. For example, partial superblock memory management may involve performing operations to reallocate good blocks in a plane to replace bad blocks in the plane, thereby forming a partial superblock having a number of bad blocks that satisfy (e.g., less than or equal to) a bad block threshold.

[0024] As used herein, a reallocation block may refer to a reallocation logical block, a physical block, or both. As used herein, the terms "physical block" and "logical block" generally refer to various representations of memory blocks that can be classified according to their physical location within a memory subsystem or their logical location corresponding to the address of that physical location within the memory subsystem. For example, a "physical block" generally refers to a collection of memory cells storing charges corresponding to data values. A physical block has an associated address (e.g., a physical block address). A "logical block" generally refers to a data structure containing logical address information (e.g., a logical block address) corresponding to the physical address of a memory location within the physical block. Reallocation may involve updating mapping entries (e.g., address or data indicating the address, and other possible information) in data structures (e.g., tables) such as physical-to-logical (P2L) tables and / or logical-to-physical (L2P) tables.

[0025] Accordingly, such as Figure 2A and Figure 2B As detailed in the text, redistributing blocks can create partial superblocks with a number of bad blocks that satisfy (e.g., less than or equal to) a bad block threshold, such as a bad block threshold equal to one bad block. Creating partial superblocks with a number of bad blocks satisfying the bad block threshold can, in contrast to other methods that attempt to reduce the number of partial superblocks, conversely increase the number of partial superblocks, as described herein relative to... Figure 2A and Figure 2B Detailed explanation. Increasing the number of partial superblocks allows for the use of partial superblocks while still ensuring that any performance degradation associated with a particular partial superblock is limited to an amount that will not be perceptible to the end user and / or will not significantly affect the performance of the memory system (e.g., an amount proportional to the individual bad blocks within the partial superblocks).

[0026] Figure 1 Example computing system 100 including memory subsystem 110 according to some embodiments of the present disclosure is shown. Memory subsystem 110 may include media such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or combinations of such devices.

[0027] The memory subsystem 110 may be a storage device, a memory module, or a combination of both. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0028] The computing system 100 may be a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), device with Internet of Things (IoT) capabilities, embedded computer (e.g., embedded computer contained in a vehicle, industrial equipment or networked business device), or such computing device containing memory and processing devices.

[0029] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1An example of a host system 120 coupled to a memory subsystem 110 is shown. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without an intermediate component), whether wired or wireless, and includes connections such as electrical, optical, magnetic, etc.

[0030] Host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). Host system 120 uses memory subsystem 110 to, for example, write data to memory subsystem 110 and read data from memory subsystem 110.

[0031] Host system 120 can be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include (but are not limited to) Serial Advanced Technology Attachment (SATA) interface, Peripheral Component Interconnect High Speed ​​(PCIe) interface, Universal Serial Bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), Small Computer System Interface (SCSI), Dual Data Rate (DDR) memory bus, Dual In-line Memory Module (DIMM) interface (e.g., a DIMM socket interface supporting Dual Data Rate (DDR)), Open NAND Flash Interface (ONFI), Dual Data Rate (DDR), Low Power Dual Data Rate (LPDDR), or any other interface. The physical host interface can be used to transmit data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via PCIe interface, host system 120 can further utilize NVM Express (NVMe) interface to access components (e.g., memory device 130). The physical host interface provides an interface for transmitting control, address, data and other signals between the memory subsystem 110 and the host system 120. Figure 1 Memory subsystem 110 is shown as an example. Generally, host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or combinations of communication connections.

[0032] Memory devices 130 and 140 may include various combinations of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be (but are not limited to) random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0033] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND flash memory and in-place write memory, such as three-dimensional crosspoint (“3D crosspoint”) memory devices, which are crosspoint arrays of non-volatile memory cells. Crosspoint arrays of non-volatile memory can perform bit storage based on changes in volume resistance in conjunction with stackable cross-grid data access arrays. Furthermore, compared to many flash-based memories, crosspoint non-volatile memory can perform in-place write operations, where non-volatile memory cells can be programmed without pre-erasing them. NAND flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0034] Each of the memory devices 130 and 140 may include one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cell (MLC), three-level cell (TLC), four-level cell (QLC), and five-level cell (PLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, or any combination thereof. In some embodiments, a particular memory device may include an SLC portion of memory cells as well as an MLC portion, a TLC portion, a QLC portion, or a PLC portion. The memory cells of the memory device 130 may be grouped into pages, which may refer to logical units of the memory device used for storing data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0035] Although non-volatile memory components such as three-dimensional cross-point arrays of non-volatile memory cells and NAND flash memories (e.g., 2D NAND, 3D NAND) are described, memory device 130 may be based on any other type of non-volatile memory or storage device, such as read-only memory (ROM), phase-change memory (PCM), select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0036] The memory subsystem controller 115 (for simplicity, controller 115) can communicate with the memory device 130 to perform operations, such as reading data, writing data, or erasing data at the memory device 130, and other such operations. The memory subsystem controller 115 may include hardware such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system having dedicated (i.e., hard-decoded) logic for performing the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0037] The memory subsystem controller 115 may include a processor 117 (e.g., a processing device) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communication between the memory subsystem 110 and the host system 120.

[0038] In some embodiments, local memory 119 may include memory registers storing memory pointers, retrieved data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although Figure 1 The instance memory subsystem 110 in the present disclosure is shown to include a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but may rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0039] Typically, the memory subsystem controller 115 may receive commands or operations from the host system 120 and may translate these commands or operations into instructions or appropriate commands to enable desired access to memory devices 130 and / or 140. The memory subsystem controller 115 may be responsible for other operations, such as wear leveling, garbage collection, error detection and error correction (ECC) operations, encryption, caching, and address translation between logical addresses (e.g., logical block addresses (LBAs), namespaces) and physical addresses (e.g., physical block addresses, physical media locations, etc.) associated with memory device 130. The memory subsystem controller 115 may further include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry may translate commands received from the host system into command instructions to access memory devices 130 and / or 140, and translate responses associated with memory devices 130 and / or 140 into information for the host system 120.

[0040] The memory subsystem 110 may also include additional circuitry or components not shown. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and an address circuitry (e.g., a row decoder and a column decoder) that can receive addresses from the memory subsystem controller 115 and decode the addresses to access memory device 130 and / or memory device 140.

[0041] In some embodiments, memory device 130 includes a local media controller 135 that operates together with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory device 130 is a managed memory device, which is a raw memory device combined with a local controller (e.g., local controller 135) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0042] Memory subsystem 110 includes a portion of the superblock memory management component 113. Although Figure 1To avoid obscuring the diagram, the partial superblock memory management component 113 may include various circuit systems to: identify a plurality of bad blocks in a corresponding plane of NAND memory cell blocks; determine that a plane in the corresponding plane contains at least one good block from at least one different block of NAND memory cells; and perform operations to reallocate the at least one good block in the plane to the at least one bad block in the plane to form a plurality of NAND memory cell blocks having a number of bad blocks less than or equal to a bad block threshold. In some embodiments, the partial superblock memory management component 113 may include a dedicated circuit system in the form of an ASIC, FPGA, state machine and / or other logic circuit system or software and / or firmware, which may allow the partial superblock memory management component 113 to orchestrate and / or perform partial superblock memory management for memory devices 130 and / or memory devices 140.

[0043] In some embodiments, the memory subsystem controller 115 includes at least a portion of the superblock memory management component 113. For example, the memory subsystem controller 115 may include a processor 117 (processing means) configured to execute instructions stored in local memory 119 for performing the operations described herein. In some embodiments, the superblock memory management component 113 is part of a host system 110 (not shown), an application, or an operating system.

[0044] In a non-limiting instance, the device (e.g., computing system 100) may include a portion of the superblock memory management component 113. The portion of the superblock memory management component 113 may reside on the memory subsystem 110. As used herein, the term "resides on" means that something is physically located on a particular component. For example, "resides on memory subsystem 110" means that the hardware circuitry including the portion of the superblock memory management component 113 is physically located on memory subsystem 110. The term "resides on" may be used interchangeably with other terms such as "deployed on" or "located on" as mentioned herein.

[0045] A partial superblock memory management component 113 may be configured to identify the number of bad blocks in a NAND memory cell block. For example, the partial superblock memory management component 113 may identify bad blocks in a corresponding plane of multiple NAND memory cell blocks. In some embodiments, the multiple NAND memory cell blocks may be a superblock. As mentioned, a superblock generally refers to a collection of data blocks spanning multiple memory devices written in an interleaved manner. As used herein, the terms “block,” “memory cell block,” and / or “interleaved NAND memory block,” and variations thereof, may be used interchangeably given the context of this disclosure.

[0046] In some embodiments, the superblock memory management component 113 may determine that a plane in a given plane having at least one bad block contains at least one good block. For example, the superblock memory management component 113 may determine that a plane in a given plane contains at least one good block that is different from a bad block in at least one block of NAND memory cells. Determining that the plane has at least one good block allows for the reallocation of the at least one good block.

[0047] For example, in some embodiments, the partial superblock memory management component 113 may perform operations to reallocate at least one good block in the plane to at least one bad block in the plane. This reallocation may desirably form a block of NAND memory cells having a number of bad blocks that satisfy (e.g., less than or equal to) a bad block threshold. As mentioned, forming a block of NAND memory cells having a number of bad blocks that satisfy the bad block threshold ensures that any performance degradation is limited (e.g., limited to an amount that is proportional to the individual bad blocks in the partial superblock and will not be perceptible to the end user / will not significantly affect the memory system performance), and still allows the use of the partial superblock compared to other methods that do not employ partial superblock memory management.

[0048] Figure 2AExamples of non-volatile memory arrays 221 according to some embodiments of the present disclosure are shown. In some embodiments, the non-volatile memory array 221 may be a NAND memory array. In some embodiments, the non-volatile memory array 221 may reside on a mobile computing device such as a smartphone, laptop computer, phablet, IoT device, autonomous vehicle, etc. As used herein, the term "mobile computing device" generally refers to a handheld computing device having a tablet or phablet form factor. Typically, a tablet form factor may include a display between about 3 inches and 5.2 inches (diagonally measured), while a phablet form factor may include a display between about 5.2 inches and 7 inches (diagonally measured). However, examples of "mobile computing device" are not limited thereto, and in some embodiments, "mobile computing device" may refer to IoT devices, as well as other types of edge computing devices.

[0049] The non-volatile memory array 221 may include a plurality of dies (“die 0”) 223-1 and (“die 1”) 223-2 (hereinafter referred to as a plurality of dies 223). Although shown as including two dies 223-1 and 223-2, the number of dies may be increased or decreased. For example, a plurality of dies 223 may be equal to two dies, three dies, or four dies, as well as other possible numbers of dies.

[0050] In some embodiments, the bad block threshold may be based on the number of dies 223 and / or on an acceptable amount of latency. For example, the bad block threshold may be based on the number of dies 223 in the memory device. In some embodiments, the bad block threshold may be proportional to the number of dies in the memory device. For example, for a larger number of dies, the bad block threshold may be higher (e.g., it may include a larger number of bad blocks).

[0051] In some embodiments, the bad block threshold may be based on an acceptable amount of latency. The amount of latency or performance degradation may be equal to or based on the number of bad blocks divided by the number of planes in a NAND memory cell block (e.g., in a superblock). For example, having an individual bad block in a NAND memory cell block can result in a 1 / 8 performance degradation (i.e., an increase in latency of ~12.5%) in a non-volatile memory array 221 having two dies, each die having four corresponding planes, such as... Figure 2A and Figure 2BAs shown in the diagram. Similarly, having two bad blocks in a block of NAND memory cells can result in a 2 / 8 performance degradation in the non-volatile memory array 221 (i.e., a 25% increase in latency). In these instances, the bad block threshold can be the number of bad blocks with a corresponding increase in latency that is less than or equal to the allowable amount of latency. For example, if the allowable amount of latency is 20%, then for a given block of NAND memory cells (e.g., a superblock), the bad block threshold can be set to one bad block (e.g., with 12.5% ​​latency).

[0052] However, other values ​​for the bad block threshold are possible. For example, the bad block threshold may increase as the number of dies in the non-volatile memory array 221 increases and / or as the allowable latency increases. In some embodiments, the bad block threshold may be equal to four or fewer bad blocks in a NAND memory block. For example, the bad block threshold may be equal to four bad blocks. In some embodiments, the bad block threshold may be equal to three or fewer bad blocks in a NAND memory block. For example, the bad block threshold may be equal to three bad blocks. In some embodiments, the bad block threshold may be equal to two or fewer bad blocks in a NAND memory block. For example, the bad block threshold may be equal to two bad blocks. Other values ​​for the bad block threshold, such as five or six bad blocks, are possible.

[0053] A plurality of dies 223 may comprise a plurality of planes, including a first plane 224-0, a second plane 224-1, a third plane 224-2, and a fourth plane 224-3 (collectively referred to herein as "planes 224") (e.g., "PL0", "PL1", "PL2" to "PL3" of "die 0" 223-1), and a first plane 225-0, a second plane 225-1, a third plane 225-2, and a fourth plane 225-3 (collectively referred to herein as "planes 225") (e.g., "PL0", "PL1", "PL2" to "PL3" of "die 1" 223-2). The plurality of dies 223 and planes 224, 225 may comprise a certain number of blocks (i.e., superblocks) 227-1, 227-2, 227-3, 227-4, 227-5, 227-6, 227-7 to 227-8 (collectively referred to herein as superblocks 227) of NAND memory cells. Each block in superblock 227 can be referred to as a good block as indicated by (“G”) or a bad block as indicated by (“B”).

[0054] A complete superblock can refer to a superblock that contains a specific number of good blocks. For example, the first superblock 227-1 could be a complete superblock that contains all good blocks (e.g., all blocks designated "G") spanning the planes of both die 223-1 and die 223-2. Similarly, the fourth superblock 227-4, the fifth superblock 227-5, and the eighth superblock 227-8 are complete superblocks. These complete superblocks can be described as having 100% performance, or in other words, performance unaffected by bad blocks.

[0055] As mentioned, a partial superblock can refer to a superblock that has at least one defective block. For example, the second superblock 227-2 contains a first defective block (e.g., "B") in the second plane 224-1 of the first die 223-1 and a second defective block in the first plane 225-0 of the second die 223-2. Therefore, the second superblock 227-2 may experience a performance degradation of ~25% compared to a full superblock. Similarly, the sixth superblock 227-6 contains two defective blocks and may experience a performance degradation of ~25%, while the seventh superblock 227-7 contains three defective blocks and may experience a performance degradation of ~37.5%.

[0056] In the aforementioned methods, the second superblock 227-2, the sixth superblock 227-6, and the seventh superblock 227-7 may have been discarded or ignored when processing data in the non-volatile memory array 221. However, as mentioned, not writing data to these superblocks may degrade memory performance, for example, by preventing the utilization of good blocks in the second superblock 227-2, the sixth superblock 227-6, and the seventh superblock 227-7. Furthermore, in other prior methods, some / all blocks in the second superblock 227-2, the sixth superblock 227-6, and / or the seventh superblock 227-7 may be relocated to different superblocks, thereby reducing the number of partial superblocks. However, as mentioned, reducing the number of partial superblocks may cause bad blocks to accumulate in the remaining partial superblocks, thereby exacerbating the performance degradation of the remaining partial superblocks.

[0057] Compared to these methods, partial superblock memory management can increase the number of partial superblocks. Increasing the number of partial superblocks allows for their use while still ensuring that any performance degradation associated with a particular partial superblock is limited to an amount that will not be perceptible to the end user and / or will not significantly affect the memory system performance (e.g., an amount proportional to the individual bad blocks within the partial superblock). For example, such as Figure 2B As described, blocks can be reallocated to form NAND memory cell blocks (partial superblocks) with a number of bad blocks that satisfy (e.g., less than or equal to) a bad block threshold.

[0058] Figure 2BAnother example of a non-volatile memory array 221 according to some embodiments of the present disclosure is shown. The non-volatile memory array 221 illustrates an example of block reallocation consistent with partial superblock memory management. For example... Figure 2B As shown, one or more blocks (e.g., a full superblock) from a NAND memory cell block can be reallocated to different NAND memory cell blocks (e.g., partial superblocks). Relocating blocks from a NAND memory cell block (e.g., from a full superblock) to different NAND memory cell blocks (e.g., to partial superblocks) can occur without reallocating good blocks from any partial superblocks. Reallocating good blocks, for example, from a full superblock to a partial superblock without reallocating good blocks from any partial superblocks ensures that the total number of partial superblocks increases, thereby ensuring that any bad blocks are evenly distributed among the resulting partial superblocks, each having a number of bad blocks that meet the bad block threshold.

[0059] For example, the fourth superblock 227-4 contains the first good block in the fourth plane 224-3 of the first die 223-1. The first good block of the fourth superblock can be reassigned to defective blocks in the same die (first die 223-1) and the same plane (fourth plane 224-3). For example, the first good block in the fourth plane 224-3 can be reassigned to the first defective block in the first die 223-1 and the fourth plane 224-3 of the seventh superblock 227-7.

[0060] Similarly, the second good block in the first plane 225-0 of the second die 223-2 of the first superblock 227-1 can be reallocated to the second bad block in the first plane 225-0 of the second die 223-2 of the second superblock 227-2; the third good block in the third plane 225-2 of the second die 223-2 of the fifth superblock 227-5 can be reallocated to the third bad block in the third plane 225-2 of the second die 223-2 of the sixth superblock 227-6; and the fourth good block in the third plane 225-2 of the second die 223-2 of the eighth superblock 227-8 can be reallocated to the fourth bad block in the third plane 225-2 of the second die 223-2 of the seventh superblock 227-7. As mentioned, reallocation may involve updating mapping entries in data structures such as physical-to-logical (P2L) tables and / or logical-to-physical (L2P) tables. For example, logical blocks and / or physical blocks (e.g., good blocks) can be reassigned to physical and / or logical blocks associated with said good blocks by updating mapping entries in a table of physical and / or logical mappings (from different physical and / or logical blocks, such as physical and / or logical blocks associated with bad blocks).

[0061] As mentioned, forming a subset of superblocks with the number of bad blocks that meet the bad block threshold can increase the number of partial superblocks compared to other methods that attempt to reduce the number of partial superblocks, such as... Figure 2A and Figure 2B As shown in the diagram. For example, each of superblocks 227-1 to 227-8 can be a partial superblock with the same number (e.g., one bad block) of bad blocks that satisfy the bad block threshold (e.g., one bad block). That is, Figure 2A It contains four superblocks: 227-2, 227-3, 227-6, and 227-7. Figure 2B It contains eight partial superblocks, 227-1 to 227-8. As mentioned, increasing the number of partial superblocks allows for the use of partial superblocks while still ensuring that any performance degradation associated with a particular partial superblock is limited to an amount that will not be perceptible to the end user and / or will not significantly affect the performance of the memory system (e.g., an amount proportional to the individual bad blocks in the partial superblock).

[0062] Figure 3 A flowchart 331 illustrates an example of partial superblock memory management according to some embodiments of the present disclosure. At operation 332, partial superblock memory management components (e.g., Figure 1 The partial superblock memory management (113) can identify the corresponding number of bad blocks in the partial superblock. For example, bad blocks (and similarly, good blocks) can be determined based on a block set region or other types of information corresponding to the location of a block in the non-volatile memory array (e.g., plane, die, superblock, etc.). In some examples, a block can be determined to be a good block or a bad block based on whether it satisfies fault propagation. For example, it can be determined that a read, write, or both for a given block has failed. In this case, the block can be considered to satisfy fault propagation and can then be designated as a bad block (e.g., designated as a bad block in the block set region). However, the examples are not limited to this, and in some embodiments, a block can be designated as a bad block based on the number of program erase cycles the block has undergone, the raw bit error rate associated with the block, etc. Conversely, a read, write, or both for a given block can be successful (e.g., successfully storing data at the block and / or reading data from the block) and the block can therefore be designated as a good block.

[0063] At operation 333, a portion of the superblock memory management components can determine whether the corresponding number of bad blocks meets a bad block threshold. For example, a determination can be made as to whether the corresponding number of bad blocks is less than or equal to the bad block threshold. The bad block threshold can be fixed or variable. In some embodiments, the bad block threshold can be variable and can be adjusted based on several parameters at different stages of use of the memory device.

[0064] In response to determining that the corresponding number of defective blocks meets the defective block threshold, flowchart 331 may proceed to operation 336. However, in response to determining that the corresponding number of defective blocks does not meet (e.g., is greater than) the defective block threshold, flowchart 331 may return to 332, and the number of defective blocks in different superblocks (e.g., different partial superblocks) may be determined.

[0065] At operation 336, an operation can be performed to reallocate good blocks from a plane in another superblock of the plurality of superblocks to replace bad blocks in the same plane of a portion of the superblocks to form a plurality of partial superblocks, each partial superblock having a number of bad blocks less than or equal to a bad block threshold. For example, the operation can be performed in response to determining at operation 333 that the number of bad blocks meets the bad block threshold. At operation 338, host data can be written to a partial superblock having a number of bad blocks that meet the bad block threshold.

[0066] Figure 4 This is a flowchart corresponding to a method 450 for partial superblock memory management according to some embodiments of this disclosure. Method 450 can be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions running or executed on the processing device), or a combination thereof. In some embodiments, method 450 is performed by… Figure 1 Part of the superblock memory management component 113 is executed. Although shown in a specific sequence or order, the order of processes may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0067] At operation 452, the number of defective blocks in a corresponding plane of a block of non-volatile memory cells (e.g., NAND memory cells) can be identified. For example, defective blocks in a corresponding plane of a block of non-volatile memory cells contained in a plurality of non-volatile memory cell blocks within a non-volatile memory device can be identified. In some embodiments, a specific number of defective blocks can be determined when a user begins using the memory system, after manufacturing testing, at a specific lifespan of the memory system, etc. For example, the number of defective blocks can be identified before native use or before user use. As an example, the number of defective blocks can be identified during the testing and / or manufacturing phases of the memory subsystem.

[0068] At operation 454, it can be determined that a plane in the corresponding plane contains at least one good block from at least one different non-volatile memory cell block of the plurality of non-volatile memory cell blocks. At operation 456, the at least one good block in the plane can be reallocated to the at least one bad block in the same plane to form a corresponding block (e.g., a partial superblock) of non-volatile memory cells having a number of bad blocks that satisfy a bad block threshold. In some embodiments, each of the non-volatile memory cell blocks having a number of bad blocks that satisfy a bad block threshold has the same number of bad blocks (e.g., each has one, two, or three bad blocks, and other possible numbers of bad blocks).

[0069] In some embodiments, host data may be written to a non-volatile memory cell block having a number of bad blocks that satisfy (e.g., less than or equal to) a bad block threshold. In one instance, writing host data to a non-volatile memory cell block (e.g., a partial superblock) having a number of bad blocks that satisfy the bad block threshold may include good blocks in the non-volatile memory cell block that write host data to, and prevent writing host data to the aforementioned number of bad blocks in the non-volatile memory cell block.

[0070] Figure 5 This is a block diagram of an example computer system 500 in which embodiments of this disclosure may operate. For example, Figure 5 An example machine of computer system 500 is shown, within which an instruction set executable for causing the machine to perform any one or more of the methods discussed herein is provided. In some embodiments, computer system 500 may correspond to a host system (e.g., Figure 1 The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110) or can be used to perform controller operations (e.g., execute operating system commands corresponding to...). Figure 1 (Operation of part of the superblock memory management component 113). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a peer machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment within the capacity of a server or client machine in a client-server network environment.

[0071] The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network appliance, server, network router, switch, or bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions specifying actions to be taken by the machine. Furthermore, although a single machine is described, the term "machine" should be understood to include any set of machines that individually or jointly execute a set (or sets of sets) of instructions to perform any or more of the methods discussed herein.

[0072] The example computer system 500 includes a processing device 502, a main memory 504 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), a static memory 506 (e.g., flash memory, static random access memory (SRAM)), and a data storage system 518, which communicate with each other via a bus 503.

[0073] Processing device 502 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a combination of instruction sets. Processing device 502 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 502 is configured to execute instructions 526 for performing the operations and steps discussed herein. Computer system 500 may further include a network interface device 508 for communication via network 511.

[0074] Data storage system 518 may include machine-readable storage medium 524 (also called computer-readable medium) on which one or more instruction sets 526 or software embodying any one or more methods or functions described herein are stored. Instructions 526 may also reside wholly or at least partially within main memory 504 and / or processing device 502 during execution by computer system 500, which also constitute machine-readable storage media. Machine-readable storage medium 524, data storage system 518, and / or main memory 504 may correspond to... Figure 1 The memory subsystem 110.

[0075] In one embodiment, instruction 526 includes instructions for implementing a component corresponding to a portion of the superblock memory management (e.g., Figure 1The machine-readable storage medium 524 is shown as a single medium in the exemplary embodiment, but the term "machine-readable storage medium" should be understood to include a single medium or multiple media storing the one or more instruction sets. The term "machine-readable storage medium" should also be understood to include any medium capable of storing or encoding instruction sets executable by a machine and causing the machine to perform any one or more methods of this disclosure. The term "machine-readable storage medium" should be accordingly understood to include (but is not limited to) solid-state memory, optical media, and magnetic media.

[0076] Some parts of the previously described descriptions have been presented based on the algorithms and symbolic representations of operations on data bits within computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the essence of their work to others skilled in the art. An algorithm here and generally is considered a self-consistent sequence of operations that produce the desired result. An operation is an operation that requires physical manipulation of physical quantities. These quantities are usually, but not necessarily, in the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Primarily for reasons of common use, it has proven convenient to sometimes refer to these signals as bits, values, elements, symbols, characters, items, numbers, etc.

[0077] However, it should be remembered that all these and similar terms should be associated with appropriate physical quantities and are merely convenient labels applied to those quantities. This disclosure may relate to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities within the registers and memories of a computer system into other data similarly represented as physical quantities within the computer system's memory or registers or other such information storage systems.

[0078] The present invention also relates to an apparatus for performing the operations described herein. This apparatus may be specifically constructed for a particular purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. This computer program may be stored in a computer-readable storage medium, such as (but not limited to) any type of disk (including solid-state drives (SSDs), hard disk drives (HDDs), floppy disks, optical disks, CD-ROMs, and magneto-optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards, or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0079] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with the teachings and procedures herein, or it may prove convenient to construct more specialized devices to implement the methods. The structures of various such systems will be presented as described below. Furthermore, this disclosure is described without reference to any particular programming language. It should be understood that the teachings of this disclosure described herein can be implemented using various programming languages.

[0080] This disclosure can be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, the instructions being usable for programming a computer system (or other electronic device) to perform processes according to this disclosure. The machine-readable medium includes any mechanism for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, the machine-readable (e.g., computer-readable) medium includes machine-readable (e.g., computer-readable) storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory devices, etc.

[0081] In the foregoing description, embodiments of the present disclosure have been described with reference to specific exemplary embodiments. It will be apparent that various modifications can be made to the present disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative rather than restrictive sense.

Claims

1. A method for managing a partial superblock memory, comprising: Identify defective blocks in the corresponding plane of a non-volatile memory cell block among multiple NAND memory cell blocks in a non-volatile memory device; Determine that a certain plane in the corresponding plane contains at least one good block among at least one different non-volatile memory cell block of the plurality of non-volatile memory cell blocks; as well as An operation is performed to reallocate at least one good block in the plane to at least one bad block in the bad blocks in the plane to form a partial superblock of a plurality of nonvolatile memory cells, each of the partial superblocks having a number of bad blocks that satisfy a bad block threshold, wherein the bad block threshold is determined based on an allowable latency amount based on the number of allowable bad blocks in the partial superblock divided by the number of the corresponding planes of the partial superblock.

2. The method of claim 1, wherein each of the plurality of partial superblocks having the same number of bad blocks as the number of bad blocks being less than or equal to the bad block threshold.

3. The method of claim 2, wherein the defective block threshold is equal to three or fewer defective blocks.

4. The method according to claim 2, wherein the defective block threshold is equal to one defective block.

5. The method according to any one of claims 1-4, wherein the defective block threshold is scaled based on a change in the allowable delay amount, and wherein the defective block threshold increases with an increase in the allowable delay amount.

6. The method according to any one of claims 1-4, wherein performing the operation to reallocate the at least one good block in the plane and thereby reallocate the at least one bad block further comprises updating the mapping of the at least one good block, updating the mapping of the at least one bad block, or both.

7. A device for partial superblock memory management, comprising: Some superblock memory management components are configured to: The number of bad blocks in a non-volatile memory cell block in a non-volatile memory array is determined to be greater than a bad block threshold, wherein the bad block threshold is based on an allowable latency, and the allowable latency is based on the number of allowable bad blocks in a fractional superblock divided by the number of corresponding planes in the fractional superblock. An operation is performed to reallocate good blocks from a plane in another nonvolatile memory cell block to replace bad blocks in the same plane of the nonvolatile memory cell block to form a plurality of partial superblocks of nonvolatile memory cells, each of the partial superblocks having a number of bad blocks less than or equal to the bad block threshold. as well as Host data is written to the plurality of non-volatile memory cell blocks having a number of bad blocks less than or equal to the bad block threshold.

8. The device of claim 7, wherein each of the partial superblocks having a number of bad blocks less than or equal to the bad block threshold is a partial superblock deployed across a plurality of memory dies having a plurality of planes and a plurality of pages.

9. The device of claim 8, wherein the plurality of memory dies comprises four or fewer memory dies.

10. The device of claim 8, wherein the plurality of memory dies comprises two memory dies.

11. The device according to any one of claims 7-10, wherein the non-volatile memory array resides on a mobile computing device.

12. A system for partial superblock memory management, comprising: The memory subsystem includes multiple memory dies in a stackable cross-mesh array of multiple superblocks arranged in the form of fault-tolerant non-volatile memory cells. as well as A processing device coupled to the plurality of memory dies, the processing device being configured to perform operations including: Identify the corresponding number of bad blocks in a subset of the multiple superblocks; Determine that the corresponding number of defective blocks meets the defective block threshold; An operation is performed to reallocate good blocks from a plane in another superblock of the plurality of superblocks to replace bad blocks in the same plane of the partial superblocks to form a plurality of partial superblocks, each of the partial superblocks of the plurality of superblocks having the same number of bad blocks and the number of bad blocks being less than or equal to a bad block threshold, wherein the bad block threshold is based on an allowable delay amount, the allowable delay amount being based on the number of allowable bad blocks in the partial superblocks divided by the number of the corresponding planes of the partial superblocks; as well as Host data is written to the plurality of partial superblocks having a number of bad blocks less than or equal to the bad block threshold.

13. The system of claim 12, wherein the processing device performs an operation, the operation further comprising determining that the corresponding number of defective blocks in the superblock is less than or equal to a defective block threshold.

14. The system of claim 13, wherein the processing means performs an operation, the operation further comprising writing host data to the superblock in response to the number of bad blocks in the superblock being less than or equal to the bad block threshold.

15. The system of claim 14, wherein the processing means performs an operation, the operation further comprising performing an operation to reallocate the good block from a plane in a fully superblock.

16. The system according to any one of claims 12-14, wherein the processing means performs an operation, the operation further comprising determining that the plurality of superblocks contains a complete superblock.

17. The system of claim 16, wherein the processing means performs an operation, the operation further comprising performing the operation to redistribute the good block from the plane in the full superblock without redistributing the good block from the partial superblock.

18. The system according to any one of claims 12-14, wherein the processing device performs an operation, the operation further comprising: The corresponding number of bad blocks in the superblock is determined to be two more than the bad block threshold; as well as An operation is performed to reallocate multiple good blocks from a full superblock to replace the two or more bad blocks, forming multiple partial superblocks, each having a number of bad blocks less than or equal to the bad block threshold.

19. The system of claim 12, wherein the defective block threshold is proportional to the number of memory dies in the memory subsystem, and wherein the defective block threshold is higher for a larger number of memory dies contained in the memory subsystem.

20. The system according to claim 19, wherein: The plurality of memory dies includes two memory dies, and the bad block threshold is equal to the first bad block threshold; or The plurality of memory dies includes four memory dies, and the bad block threshold is equal to a second bad block threshold that is higher than the first bad block threshold.

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