Method, device and computer equipment for firmware implementation of PWRDIS function module
By designing a PWDIS module in the SSD firmware to detect the PWDIS signal and control the power module switch, the problem of complex power control circuits in traditional D3COLD support solutions is solved, achieving flexible power management and improving SSD read performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SUZHOU UNIONMEMORY INFORMATION SYST LTD
- Filing Date
- 2022-03-28
- Publication Date
- 2026-07-31
AI Technical Summary
Traditional D3COLD support solutions require the addition of complex power control circuitry on the host side to support power management of multiple PCIe devices, which increases design complexity.
By designing a PWDIS module in the SSD firmware, the PWDIS signal level transitions are detected and the switching of each power module of the SSD is controlled, enabling the D3COLD state to advance or retreat. The PWDIS function can be enabled or disabled using NVME commands, avoiding the need to add additional power switching hardware.
Without adding power switching hardware, a flexible PWDIS function design was achieved to adapt to different platform requirements and improve SSD read performance.
Smart Images
Figure CN115543884B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of solid-state drive technology, and in particular to a firmware implementation method, apparatus, computer device, and storage medium for a PWRDIS functional module. Background Technology
[0002] The D3COLD state is a power state defined by the PCI bus specification. For PCIe devices, after switching to D3COLD, the main device power supply VCC needs to be turned off to reduce power consumption. After restoring VCC power, the PCIe device will exit the D3COLD state and return to the uninitialized state.
[0003] Currently, traditional D3COLD support solutions involve a power control switch on the motherboard, where the host-side control program turns the main power supply of the PCIe devices on / off when entering / exiting D3COLD mode. Since multiple PCIe devices typically exist on the same host platform, supporting D3COLD requires adding complex power control circuitry to the host side. Summary of the Invention
[0004] Therefore, it is necessary to provide a firmware implementation method, apparatus, computer device, and storage medium for the PWRDIS functional module that can improve SSD read performance, addressing the aforementioned technical problems.
[0005] A firmware implementation method for a PWRDIS functional module, the method comprising:
[0006] Obtain the firmware implementation request for the PWRDIS functional module;
[0007] According to the firmware implementation request, the host and SSD are connected via the M.2 interface;
[0008] The host terminal controls the level state of the PWRDIS signal;
[0009] When the SSD firmware detects a change in the PWDIS signal level, it controls the switching of each power module of the SSD to enable D3COLD forward and backward.
[0010] In one embodiment, the step of controlling the switches of each power module of the SSD to achieve D3COLD advance and retreat after the SSD firmware detects a change in the PWDIS signal level includes:
[0011] When the PWRDIS signal level transition triggers an interrupt, check whether the PWDIS signal ASSERT hold time meets the protocol requirements.
[0012] If the protocol requirements are met, confirm whether the PCIE is in D3HOT state and the link is in L2 / L3 ready state.
[0013] If so, then shut down the peripheral circuitry and PCIe power supply to put PCIe into D3COLD state;
[0014] The SOC enters a low-power state.
[0015] In one embodiment, the step of controlling the switches of each power module of the SSD to achieve D3COLD advance and retreat after the SSD firmware detects a change in the PWDIS signal level further includes:
[0016] The PWDIS signal interruption triggers the SOC to exit the low-power state. Check whether the PWDIS signal DASSERT hold time meets the protocol requirements.
[0017] If the protocol requirements are met, power on the peripheral circuits and PCIe module.
[0018] Enable PCIe link training.
[0019] In one embodiment, the method further includes:
[0020] The host uses the set feature command to control the PWDIS function enable switch. When the SSD firmware receives the set feature command sent by the host, it controls the opening and closing of the internal PWDIS software module.
[0021] A firmware implementation apparatus for a PWRDIS functional module, the firmware implementation apparatus for the PWRDIS functional module comprising:
[0022] The acquisition module is used to acquire firmware implementation requests for PWRDIS functional modules;
[0023] A connection module, which is used to connect the host and the SSD via an M.2 interface according to the firmware implementation request;
[0024] A signal control module, which is used by the host to control the level state of the PWRDIS signal;
[0025] The power control module is used to control the switching of each power module of the SSD to achieve D3COLD advance and retreat when the SSD firmware detects a jump in the PWDIS signal level.
[0026] In one embodiment, the power control module is further configured to:
[0027] When the PWRDIS signal level transition triggers an interrupt, check whether the PWDIS signal ASSERT hold time meets the protocol requirements.
[0028] If the protocol requirements are met, confirm whether the PCIE is in D3HOT state and the link is in L2 / L3 ready state.
[0029] If so, then shut down the peripheral circuitry and PCIe power supply to put PCIe into D3COLD state;
[0030] The SOC enters a low-power state.
[0031] In one embodiment, the power control module is further configured to:
[0032] The PWDIS signal interruption triggers the SOC to exit the low-power state. Check whether the PWDIS signal DASSERT hold time meets the protocol requirements.
[0033] If the protocol requirements are met, power on the peripheral circuits and PCIe module.
[0034] Enable PCIe link training.
[0035] In one embodiment, the apparatus further includes a command module, the command module being used for:
[0036] The host uses the set feature command to control the PWDIS function enable switch. When the SSD firmware receives the set feature command sent by the host, it controls the opening and closing of the internal PWDIS software module.
[0037] A computer device includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of any of the methods described above.
[0038] A computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of any of the above methods.
[0039] The aforementioned firmware implementation method, apparatus, computer device, and storage medium for the PWRDIS functional module involve: acquiring a firmware implementation request for the PWRDIS functional module; connecting the host and SSD via an M.2 interface according to the firmware implementation request; controlling the level state of the PWRDIS signal; and controlling the switching of each power module of the SSD to enable / disable D3COLD when the SSD firmware detects a change in the PWDIS signal level. This invention controls the switching of each power module through SSD firmware, achieving PWDIS functionality without requiring additional power switching hardware, providing a flexible and feasible PWDIS functional design scheme. This invention also designs and implements a PWDIS enable interface, allowing the host to enable or disable the PWDIS function via NVME commands to adapt to different platform requirements. Attached Figure Description
[0040] Figure 1 A schematic diagram of the firmware implementation for the PWRDIS functional module;
[0041] Figure 2 This is a flowchart illustrating the firmware implementation method of the PWRDIS functional module in one embodiment;
[0042] Figure 3 This is a flowchart illustrating the firmware implementation method of the PWRDIS functional module in another embodiment;
[0043] Figure 4 This is a flowchart illustrating the main flow of the SSD firmware PWDIS program in one embodiment.
[0044] Figure 5 This is a schematic diagram of the host controlling the PWDIS function enable switch via command in one embodiment;
[0045] Figure 6 This is a structural block diagram of the firmware implementation device for the PWRDIS functional module in one embodiment;
[0046] Figure 7 This is a structural block diagram of the firmware implementation device for the PWRDIS functional module in another embodiment;
[0047] Figure 8 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation
[0048] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.
[0049] The PWRDIS signal is an optional signal defined by PCIe M.2. The host uses the PWRDIS signal to instruct the device to automatically turn the main circuit power on and off, thus enabling D3COLD support without requiring the host to control the PCIe VCC.
[0050] This invention proposes a PWDIS design scheme for SSDs, incorporating a PWDIS module within the SSD firmware. This module controls the switching of internal power modules by detecting the status of the PWDIS signal, thereby achieving PWDIS-controlled D3COLD on / off states. This functional module can be enabled and disabled via NVMe custom functions to meet the needs of different platforms.
[0051] Specifically, refer to Figure 1 The schematic diagram shows that this invention implements the PWDIS program in the SSD firmware, and the host and SSD are connected via an M.2 interface. The host controls the level of the PWDIS signal, and the SSD firmware, upon detecting a change in the PWDIS signal level, controls the power supply of the main circuit and the power switches of the internal SOC modules to enter / exit D3COLD.
[0052] In one embodiment, such as Figure 2 As shown, a firmware implementation method for a PWRDIS functional module is provided, the method including:
[0053] Step 202: Obtain the firmware implementation request for the PWRDIS functional module;
[0054] Step 204: Connect the host and SSD via the M.2 interface according to the firmware implementation request;
[0055] Step 206: The host controls the level state of the PWRDIS signal;
[0056] Step 208: When the SSD firmware detects a change in the PWDIS signal level, it controls the switching of each power module of the SSD to enable D3COLD forward and backward.
[0057] For reference Figure 1 The schematic diagram shows that the PWDIS program is implemented in the SSD firmware. The host and SSD are connected via an M.2 interface and communicate through the PCI Express M.2 protocol. Specifically, for D3COLD advance / retreat triggered by the PWDIS signal, the protocol requires a minimum duration of 100ms for PWDIS ASSERT / DASSERT.
[0058] The host controls the PWRDIS signal level. After the SSD firmware detects the PWRDIS signal level change, it controls the main circuit power supply and the power switch of the internal SOC module to enter / exit D3COLD.
[0059] In one embodiment, the host controls the PWDIS function enable switch via the set feature command. When the SSD firmware receives the set feature command sent by the host, it controls the opening and closing of the internal PWDIS software module.
[0060] For specific details, please refer to Figure 5 The diagram illustrates how the host controls the PWDIS function enable / disable via the NVMe set feature command. After receiving the set feature command from the host, the SSD firmware controls the internal PWDIS software module to be enabled or disabled.
[0061] In this embodiment, the PWDIS switch function is implemented through a custom NVME command.
[0062] In the above embodiment, a firmware implementation request for the PWRDIS functional module is obtained; the host and SSD are connected via an M.2 interface according to the firmware implementation request; the host controls the level state of the PWRDIS signal; when the SSD firmware detects a change in the PWDIS signal level, it controls the switching of each power module of the SSD to achieve D3COLD on / off. This solution controls the switching of each power module through the SSD firmware, realizing the PWDIS function without adding additional power switching hardware, providing a flexible and feasible PWDIS function design scheme. This solution also designs and implements a PWDIS enable interface, allowing the host to enable or disable the PWDIS function via NVME commands to adapt to different platform requirements.
[0063] In one embodiment, such as Figure 3 As shown, a firmware implementation method for a PWDIS functional module is provided. In this method, when the SSD firmware detects a change in the PWDIS signal level, the step of controlling the switching of each power module of the SSD to achieve D3COLD forward / backward states further includes:
[0064] Step 302: When the PWRDIS signal level transition triggers an interrupt, check whether the PWDIS signal ASSERT hold time meets the protocol requirements.
[0065] Step 304: If the protocol requirements are met, confirm whether the PCIe is in D3HOT state and the link is in L2 / L3 ready state.
[0066] Step 306: If yes, then turn off the peripheral circuitry and PCIe power supply to put PCIe into D3COLD state;
[0067] Step 308, the SOC enters a low-power state;
[0068] Step 310: The PWDIS signal interruption triggers the SOC to exit the low-power state. Check whether the PWDIS signal DASSERT hold time meets the protocol requirements.
[0069] Step 312: If the protocol requirements are met, turn on the power to the peripheral circuits and PCIe module.
[0070] Step 314: Enable PCIE link training.
[0071] For specific details, please refer to Figure 4 The flowchart shown is a diagram of the main flow of the SSD firmware PWDIS program. The specific implementation steps are as follows:
[0072] Step 4.1: The PWRDIS signal level transition triggers an interrupt.
[0073] Step 4.2: Check if the PWDIS signal ASSERT hold time meets the protocol requirements. Specifically, for D3COLD advance / retreat triggered by the PWDIS signal, the protocol requires the minimum hold time of the PWDIS signal ASSERT to be 100ms.
[0074] Step 4.3: Confirm whether the PCIe is in D3HOT state and the link is in L2 / L3 ready state.
[0075] Step 4.4: Turn off the external circuits and PCIe power supply. PCIe will enter the D3COLD state.
[0076] Step 4.5: The SOC enters a low-power state.
[0077] Step 4.6: The PWDIS signal interruption triggers the SOC to exit the low-power state.
[0078] Step 4.7: Check if the DASSERT hold time of the PWDIS signal meets the protocol requirements. Specifically, for D3COLD advance / retreat triggered by the PWDIS signal, the protocol requires the minimum hold time of the PWDIS signal DASSERT to be 100ms.
[0079] Step 4.8: Turn on the power to the peripheral circuits and PCIe module.
[0080] Step 4.9: Enable PCIe link training.
[0081] In this embodiment, the PWDIS function module is implemented by the SSD firmware. By detecting the PWDIS signal sent by the host, the switching of each power module of the SSD is controlled to realize the D3COLD advance and retreat, providing a flexible and feasible PWDIS function design scheme.
[0082] It should be understood that, although Figure 1-5 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 1-5 At least some of the steps in the process may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.
[0083] In one embodiment, such as Figure 6 As shown, a firmware implementation device 600 for a PWRDIS functional module is provided, the device comprising:
[0084] Acquisition module 601, the acquisition module is used to acquire firmware implementation requests of PWRDIS functional modules;
[0085] Connection module 602, the connection module is used to connect the host end and the SSD through the M.2 interface according to the firmware implementation request;
[0086] Signal control module 603, the signal control module is used to control the level state of PWRDIS signal on the host side;
[0087] The power control module 604 is used to control the switching of each power module of the SSD to achieve D3COLD advance and retreat when the SSD firmware detects a jump in the PWDIS signal level.
[0088] In one embodiment, the power control module 604 is further configured to:
[0089] When the PWRDIS signal level transition triggers an interrupt, check whether the PWDIS signal ASSERT hold time meets the protocol requirements.
[0090] If the protocol requirements are met, confirm whether the PCIE is in D3HOT state and the link is in L2 / L3 ready state.
[0091] If so, then shut down the peripheral circuitry and PCIe power supply to put PCIe into D3COLD state;
[0092] The SOC enters a low-power state.
[0093] In one embodiment, the power control module 604 is further configured to:
[0094] The PWDIS signal interruption triggers the SOC to exit the low-power state. Check whether the PWDIS signal DASSERT hold time meets the protocol requirements.
[0095] If the protocol requirements are met, power on the peripheral circuits and PCIe module.
[0096] Enable PCIe link training.
[0097] In one embodiment, such as Figure 7 As shown, a firmware implementation device 600 for a PWRDIS functional module is provided. This device further includes a command module 605 for:
[0098] The host uses the set feature command to control the PWDIS function enable switch. When the SSD firmware receives the set feature command sent by the host, it controls the opening and closing of the internal PWDIS software module.
[0099] For specific limitations on the firmware implementation device of the PWRDIS functional module, please refer to the limitations on the firmware implementation method of the PWRDIS functional module mentioned above, which will not be repeated here.
[0100] In one embodiment, a computer device is provided, the internal structure of which can be shown as follows: Figure 8 As shown, the computer device includes a processor, memory, and a network interface connected via a system bus. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and a database. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The network interface is used for communication with external terminals via a network connection. When the computer program is executed by the processor, it implements a firmware implementation method for a PWRDIS functional module.
[0101] Those skilled in the art will understand that Figure 8 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.
[0102] In one embodiment, a computer device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps in the various method embodiments described above.
[0103] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the steps in the various method embodiments described above.
[0104] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), Rambus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.
[0105] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0106] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.
Claims
1. A firmware implementation method for a PWRDIS functional module, the method comprising: Obtain the firmware implementation request for the PWRDIS functional module; According to the firmware implementation request, the host and SSD are connected via the M.2 interface; The host terminal controls the level state of the PWRDIS signal; When the SSD firmware detects a change in the PWRDIS signal level, it controls the switching of each power module of the SSD to enable D3COLD forward and backward. The steps for controlling the switching of each power module of the SSD to achieve D3COLD advance and retreat after the SSD firmware detects a change in the PWRDIS signal level include: When the PWRDIS signal level transition triggers an interrupt, check whether the PWRDIS signal ASSERT hold time meets the protocol requirements. If the protocol requirements are met, confirm whether the PCIE is in D3HOT state and the link is in L2 / L3 ready state. If so, then shut down the peripheral circuitry and PCIe power supply to put PCIe into D3COLD state; The SOC enters a low-power state; The step of controlling the switching of each power module of the SSD to achieve D3COLD advance and retreat after the SSD firmware detects a change in the PWRDIS signal level also includes: The PWRDIS signal interruption triggers the SOC to exit the low-power state. Check whether the PWRDIS signal DASSERT hold time meets the protocol requirements. If the protocol requirements are met, power on the peripheral circuits and PCIe module. Enable PCIe link training; The host side controls the PWRDIS function enable switch through the set feature command. When the SSD firmware receives the set feature command sent by the host side, it controls the opening and closing of the internal PWRDIS software module. The method controls the switching of each power module through SSD firmware, realizing the PWRDIS function without the need for additional power switching hardware.
2. A firmware implementation apparatus of a PWRDIS function module, characterized by, The firmware implementation device for the PWRDIS functional module includes: The acquisition module is used to acquire firmware implementation requests for PWRDIS functional modules; A connection module, which is used to connect the host and the SSD via an M.2 interface according to the firmware implementation request; A signal control module, which is used by the host to control the level state of the PWRDIS signal; The power control module is used to control the switching of each power module of the SSD to achieve D3COLD advance and retreat when the SSD firmware detects a jump in the PWRDIS signal level. The power control module is also used for: When the PWRDIS signal level transition triggers an interrupt, check whether the PWRDIS signal ASSERT hold time meets the protocol requirements. If the protocol requirements are met, confirm whether the PCIE is in D3HOT state and the link is in L2 / L3 ready state. If so, then shut down the peripheral circuitry and PCIe power supply to put PCIe into D3COLD state; The SOC enters a low-power state; The power control module is also used for: The PWRDIS signal interruption triggers the SOC to exit the low-power state. Check whether the PWRDIS signal DASSERT hold time meets the protocol requirements. If the protocol requirements are met, power on the peripheral circuits and PCIe module. Enable PCIe link training; It also includes a command module, which is used for: The host side controls the PWRDIS function enable switch through the set feature command. When the SSD firmware receives the set feature command sent by the host side, it controls the opening and closing of the internal PWRDIS software module. The firmware implementation device of the PWRDIS functional module controls the switching of each power module through SSD firmware, thereby realizing the PWRDIS function without the need for additional power switching hardware.
3. A computer device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the method of claim 1.
4. A computer-readable storage medium having stored thereon a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method of claim 1.