System, method and apparatus for sris mode selection for pcie

Abstract

Aspects of the embodiments are directed to systems, methods, and computer program products that facilitate a downstream port operating in a separate reference clock (SRIS) mode with independent spread spectrum clocking (SSC). The system can determine that the downstream port supports one or more SRIS selection mechanisms; determine a system clock configuration from the downstream port to a corresponding upstream port connected to the downstream port by a PCIe compliant link; set the SRIS mode in the downstream port; and transmit data across the link from the downstream port using the determined system clock configuration.

Description

[0001] This application is a divisional application of the same patent application, filed on September 5, 2018, with application number 201811030425.1. Background Technology

[0002] Interconnects can be used to provide communication between different devices within a system, using some type of interconnect mechanism. A typical communication protocol for interconnecting devices in a computer system is PCI Express Interconnect. TM (PCIe TM This communication protocol is an example of a load / store input / output (I / O) interconnect system. Typically, communication between devices is performed serially at very high speeds according to this protocol.

[0003] Devices can connect across a variety of data links, each including multiple data channels. Upstream and downstream devices undergo link training during initialization to optimize data transmission across various links and channels. Attached Figure Description

[0004] Figure 1 An embodiment of a computing system including a multi-core processor is shown in the block diagram.

[0005] Figure 2 This is a schematic diagram of an example Fast Peripheral Component Interconnect (PCIe) link architecture according to embodiments of the present disclosure.

[0006] Figure 3 This is a schematic diagram of a link capability register including bits supporting the SRIS mode selection mechanism, according to an embodiment of the present disclosure.

[0007] Figure 4 This is a schematic diagram of a link control register including bits supporting the SRIS mode selection mechanism, according to an embodiment of the present disclosure.

[0008] Figure 5 This is a flowchart illustrating the process by which a PCIe-compliant port operates based on the SRIS mode selection mechanism according to an embodiment of this disclosure.

[0009] Figure 6 An embodiment of a computing system including an interconnect architecture is shown.

[0010] Figure 7 An embodiment of an interconnect architecture including a layered stack is shown.

[0011] Figure 8 An example of a request or packet to be generated or received within an interconnect architecture is shown.

[0012] Figure 9An embodiment of a transmitter and receiver pair in an interconnect architecture is shown.

[0013] Figure 10 Another embodiment of a block diagram of a computing system including a processor is shown.

[0014] Figure 11 An embodiment of a computing system block including multiple processor sockets is shown.

[0015] Figure 12 Another embodiment of the block diagram of the computing system is shown. Detailed Implementation

[0016] Numerous specific details are set forth in the following description, such as examples of specific types of processors and system configurations, specific hardware architectures, specific architectural and microarchitectural details, specific register configurations, specific instruction types, specific system components, specific measurements / heights, specific processor pipeline stages and operations, etc., in order to provide a thorough understanding of the invention. However, it will be apparent to those skilled in the art that these specific details are not necessarily required to practice the invention. In other instances, the following well-known components or methods have not been described in detail to avoid unnecessarily obscuring the invention: for example, specific and alternative processor architectures, specific logic circuitry / code for the described algorithm, specific firmware code, specific interconnect operations, specific logic configurations, specific manufacturing techniques and materials, specific compiler implementations, specific algorithmic expressions in code form, specific power-down and gating techniques / logic, and other specific operational details of the computer system.

[0017] While the following embodiments (e.g., in a computing platform or microprocessor) may be described with reference to energy savings and energy efficiency in a particular integrated circuit, other embodiments are also applicable to other types of integrated circuits and logic devices. Similar techniques and teachings of the embodiments described herein can be applied to other types of circuits or semiconductor devices that can equally benefit from better energy efficiency and energy savings. For example, the disclosed embodiments are not limited to desktop computer systems or Ultrabooks. TMFurthermore, these methods can also be used in other devices, such as handheld devices, tablet computers, other thin-and-white notebook computers, system-on-a-chip (SoC) devices, and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol devices, digital cameras, personal digital assistants (PDAs), and handheld PCs. Embedded applications typically include microcontrollers, digital signal processors (DSPs), SoCs, network computers (NetPCs), set-top boxes, network centers, wide area network (WAN) switches, or any other system capable of performing the functions and operations taught below. Moreover, the apparatuses, methods, and systems described herein are not limited to physical computing devices and can also relate to software optimizations for energy conservation and efficiency. As will become apparent in the description below, embodiments of the methods, apparatuses, and systems described herein (whether referring to hardware, firmware, software, or combinations thereof) are essential for a “green technology” future that balances performance considerations.

[0018] As computing systems evolve, their components become increasingly complex. Consequently, the complexity of the interconnect architectures used for coupling and communication between components also increases to ensure optimal bandwidth requirements for component operation. Furthermore, different market segments require different aspects of interconnect architectures to meet market demands. For example, servers demand higher performance, while the mobile ecosystem sometimes sacrifices overall performance for power savings. However, the single objective of most architectures is to provide the highest possible performance and maximum power savings. Many interconnects are discussed below that will potentially benefit from aspects of the invention described herein.

[0019] refer to Figure 1 This diagram depicts an embodiment of a computing system including a multi-core processor. Processor 100 includes any processor or processing device, such as a microprocessor, embedded processor, digital signal processor (DSP), network processor, handheld processor, application processor, coprocessor, system-on-a-chip (SoC), or other device for executing code. In one embodiment, processor 100 includes at least two cores—cores 101 and 102—which may include asymmetric or symmetric cores (as shown in the embodiment). However, processor 100 may include any number of processing elements, which may be symmetric or asymmetric.

[0020] In one embodiment, a processing element refers to hardware or logic that supports software threads. Examples of hardware processing elements include: thread units, thread slots, threads, processing units, contexts, context units, logic processors, hardware threads, cores, and / or any other elements capable of maintaining the processor's state, such as execution state or architectural state. In other words, in one embodiment, a processing element refers to any hardware that can be independently associated with code (e.g., software threads, operating systems, applications, or other code). A physical processor (or processor socket) typically refers to an integrated circuit, which potentially includes any number of other processing elements, such as cores or hardware threads.

[0021] A kernel typically refers to logic residing on an integrated circuit capable of maintaining independent architectural states, each of which is associated with at least some dedicated execution resources. In contrast, a hardware thread typically refers to any logic residing on an integrated circuit capable of maintaining independent architectural states, where these independently maintained architectural states share access to execution resources. As can be seen, the boundary between the naming of hardware threads and kernels overlaps when specific resources are shared while others are dedicated to architectural states. However, often, operating systems treat kernels and hardware threads as individual logical processors, where the operating system can schedule operations independently on each logical processor.

[0022] like Figure 1 As shown, the physical processor 100 includes two cores—cores 101 and 102. Here, cores 101 and 102 are considered symmetric cores, i.e., cores with the same configuration, functional units, and / or logic. In another embodiment, core 101 includes unordered processor cores, while core 102 includes ordered processor cores. However, cores 101 and 102 can be individually selected from any type of core: for example, native cores, software-managed cores, cores adapted to execute native instruction set architectures (ISAs), cores adapted to execute translated instruction set architectures (ISAs), co-designed cores, or other known cores. In a heterogeneous core environment (i.e., asymmetric cores), some form of translation (e.g., binary translation) can be used to schedule or execute code on one or both cores. However, for further discussion, the functional units shown in core 101 are described in further detail below, as the units in core 102 operate in a similar manner in the depicted embodiment.

[0023] As depicted, core 101 includes two hardware threads 101a and 101b, which may also be referred to as hardware thread slots 101a and 101b. Therefore, in one embodiment, a software entity such as an operating system may potentially view processor 100 as four separate processors, i.e., four logical processors or processing elements capable of executing four software threads concurrently. As mentioned above, a first thread is associated with architecture state register 101a, a second thread with architecture state register 101b, a third thread may be associated with architecture state register 102a, and a fourth thread may be associated with architecture state register 102b. Here, each of the architecture state registers (101a, 101b, 102a, and 102b) may be referred to as a processing element, thread slot, or thread unit, as described above. As shown, architecture state register 101a is copied in architecture state register 101b, thus enabling the storage of individual architecture state / context for logical processors 101a and 101b. Within core 101, other smaller resources can also be copied for threads 101a and 101b, such as the instruction pointer and renaming logic in allocator and renamer block 130. Some resources can be shared via partitioning, such as the reorder buffer, ILTB 120, load / store buffer, and queues in reorder / exit unit 135. Other resources can potentially be fully shared, such as general-purpose internal registers, page table base registers(s), low-level data cache and data TLB 115, execution unit(s)(s), and portions of out-of-order unit 135.

[0024] Processor 100 often includes other resources, which may be fully shared, shared via partitions, or dedicated to / specifically used by the processing element. Figure 1 The diagram illustrates a purely exemplary embodiment of a processor with illustrative logic units / resources for the processor. Note that the processor may include or omit any of these functional units, as well as any other known functional units, logic, or firmware not depicted. As shown, core 101 includes a simplified, representative out-of-order (OOO) processor core. However, a sequential processor may be used in different embodiments. The OOO core includes a branch target buffer 120 for predicting the branch to be executed / adopted, and an instruction translation buffer (I-TLB) 120 for storing address translation entries for instructions.

[0025] Core 101 also includes a decoding module 125 coupled to the fetch unit 120 for decoding the fetched elements. In one embodiment, the fetch logic includes individual sequencers associated with thread slots 101a and 101b, respectively. Typically, core 101 is associated with a first ISA that defines / specifies instructions executable on processor 100. Often, machine code instructions that are part of the first ISA include portions of instructions (called opcodes) that reference / specify the instructions or operations to be performed. Decoding logic 125 includes circuitry that identifies these instructions from their opcodes and passes the decoded instructions through a pipeline for processing as defined by the first ISA. For example, as discussed in more detail below, in one embodiment, decoder 125 includes logic designed or adapted to identify specific instructions, such as transaction instructions. Due to the identification performed by decoder 125, the architecture or core 101 takes specific, predefined actions to perform the task associated with the appropriate instruction. It is important to note that any of the tasks, blocks, operations, and methods described herein can be performed in response to a single or multiple instructions; some of these instructions may be new or old. Note that in one embodiment, decoder 126 identifies the same ISA (or a subset thereof). Alternatively, in a heterogeneous core environment, decoder 126 identifies a second ISA (a subset of the first ISA or a different ISA).

[0026] In one example, allocator and renamer block 130 includes an allocator for reserving resources (e.g., a register file for storing instruction processing results). However, threads 101a and 101b are potentially capable of out-of-order execution, where allocator and renamer block 130 also reserves other resources, such as a reordering buffer for tracking instruction results. Unit 130 may also include a register renamer for renaming the program / instruction reference register to other registers within processor 100. Reordering / exit unit 135 includes components such as the reordering buffer, load buffer, and store buffer mentioned above to support out-of-order execution and the later, sequential exit of out-of-order executed instructions.

[0027] In one embodiment, the scheduler and execution unit block 140 includes a scheduler unit for scheduling instructions / operations on the execution unit. For example, floating-point instructions are scheduled on an execution unit port with available floating-point execution units. A register file associated with the execution unit is also included to store information about the results of instruction processing. Exemplary execution units include floating-point execution units, integer execution units, jump execution units, load execution units, store execution units, and other known execution units.

[0028] A lower-level data cache and data translation buffer (D-TLB) 150 are coupled to execution unit(s) 140. The data cache is used to store recently used / operated elements, such as data operands, which may remain in a memory coherence state. The D-TLB is used to store recent virtual / linear-to-physical address translations. As a specific example, the processor may include a page table structure to divide physical memory into multiple virtual pages.

[0029] Here, cores 101 and 102 share access to higher-level or more distant caches, such as the L2 cache associated with on-chip interface 110. Note that "higher-level or more distant" refers to cache levels increasing or receding further from execution units(s). In one embodiment, a higher-level cache is the last-level data cache—the last-level cache in the memory hierarchy on processor 100—e.g., a L2 or L3 data cache. However, higher-level caches are not limited to this, as they can be associated with or include an instruction cache. A trace cache—a type of instruction cache—can alternatively be coupled after decoder 125 to store traces of recently decoded instructions. Here, instructions potentially refer to macro instructions (i.e., general instructions recognized by the decoder), which can be decoded into multiple microinstructions (micro-operations).

[0030] In the depicted configuration, processor 100 also includes an on-chip interface module 110. Historically, the memory controller, described in more detail below, is included in a computing system external to processor 100. In this scenario, on-chip interface 110 is used to communicate with devices external to processor 100, such as system memory 175, chipsets (often including a memory controller hub for connecting to memory 175 and an I / O controller hub for connecting peripheral devices), memory controller hub, northbridge, or other integrated circuits. Furthermore, in this scenario, bus 105 can include any known interconnect, such as multipoint bus, point-to-point interconnect, serial interconnect, parallel bus, coherent (e.g., cache coherent) bus, hierarchical protocol architecture, differential bus, and GTL bus.

[0031] Memory 175 may be dedicated to processor 100 or shared with other devices in the system. Common examples of memory type 175 include DRAM, SRAM, non-volatile memory (NV memory), and other known storage devices. Note that device 180 may include a graphics accelerator, processor, or card coupled to the memory controller, a data storage device coupled to the I / O controller, a wireless transceiver, a flash memory device, an audio controller, a network controller, or other known devices.

[0032] However, recently, with more logic and devices being integrated onto a single die (e.g., a System-on-a-Chip), each of these devices can be combined onto processor 100. For example, in one embodiment, the memory controller is centrally located on the same package and / or die as processor 100. Here, a portion of the core (on-core portion) 110 includes one or more controllers for interfacing with other devices such as memory 175 or graphics device 180. The configuration including interconnects and controllers for interfacing with such devices is often referred to as on-core (or non-core configuration). As an example, on-chip interface 110 includes a ring interconnect for on-chip communication and a high-speed serial point-to-point link 105 for off-chip communication. However, in a System-on-a-Chip environment, even more devices (e.g., network interfaces, coprocessors, memory 175, graphics processor 180, and any other known computer devices / interfaces) can be integrated onto a single die or integrated circuit to provide a small form factor with high functionality and low power consumption.

[0033] In one embodiment, processor 100 is capable of executing compiler, optimizer, and / or transformer code 177 to compile, transform, and / or optimize application code 176 to support the apparatuses and methods described herein or their interface. Compilers often comprise programs or assemblies that transform source text / code into target text / code. Typically, compiling program / application code with a compiler is done in multiple stages and passes to transforming high-level programming language code into low-level machine or assembly language code. However, single-pass compilers can still be used for simple compilation. Compilers can utilize any known compilation techniques and perform any known compiler operations, such as lexical analysis, preprocessing, parsing, semantic analysis, code generation, code transformation, and code optimization.

[0034] Larger compilers often include multiple stages, but in most cases these stages are often encompassed within two general stages: (1) the front end, where syntactic processing, semantic processing, and some transformations / optimizations typically occur, and (2) the back end, where analysis, transformations, optimizations, and code generation typically occur. Some compilers refer to the middle, which describes the ambiguous area between the compiler's front and back ends. Thus, references to compiler insertions, associations, generation, or other operations can occur in any of the aforementioned stages or passes, as well as any other known stages or passes of the compiler. As an illustrative example, a compiler may potentially insert operations, calls, functions, etc., in one or more stages of compilation, for example, inserting calls / operations in the front-end stage of compilation and then transforming the calls / operations into lower-level code during the transformation stage. Note that during dynamic compilation, compiler code or dynamically optimized code can insert such operations / calls, as well as optimization code for execution during runtime. As a particular illustrative example, binary code (already compiled code) can be dynamically optimized during runtime. Here, program code can include dynamically optimized code, binary code, or a combination thereof.

[0035] Similar to compilers, transformers (e.g., binary transformers) statically or dynamically transform code to optimize and / or transform it. Therefore, references to executable code, application code, program code, or other software environments can refer to: (1) the dynamic or static execution of (multiple) compiler programs, code optimizers, or transformers to compile program code, maintain software structure, perform other operations, optimize code, or transform code; (2) the execution of main program code including operations / calls, such as already optimized / compiled application code; (3) the execution of other program code (e.g., libraries) associated with the main program code to maintain software structure, perform other software-related operations, or optimize code; or (4) combinations thereof.

[0036] Fast PCIe supports multiple clock architectures, where the essential difference between these architectures lies in whether the same reference clock is provided to both components on the link (“common” timing), in which case whether the clock is “spread” is generally irrelevant; or there is no shared reference, in which case whether the clock is spread is very important—this mode is called Separate Reference Clocking with Independent Spread Spectrum Timing (SRIS). When SRIS was initially defined, the choice between SRIS or non-SRIS mode operation was implementation-specific. However, this has proven unsuitable for the ways that platform and silicon vendors want to implement SRIS. This disclosure provides techniques for enabling system software to change the operating mode of downstream ports.

[0037] Silicon from different suppliers implements different approaches, and therefore, platform vendors face difficulties in building systems, for example, where some PCIe connectors connect directly to the root complex and others connect to switches and potentially to retimers.

[0038] This disclosure defines a register interface for system software that determines and controls the operation of the PCIe link and enables the timing mode to be changed at runtime when required (e.g., if the inserted device is hot-removed and replaced with a different type of unit).

[0039] The advantages of this disclosure will be apparent to those skilled in the art. Among these advantages are mechanisms for reconfiguring hardware. The techniques described herein can be integrated into the PCIe specification.

[0040] Figure 2 This is a schematic diagram of an example Fast Peripheral Component Interconnect (PCIe) link architecture 200 according to embodiments of the present disclosure. The PCIe link architecture 200 includes a first component 202, which may be an upstream component, a root complex, or a PCIe-compliant switch. The first component 202 may include a downstream port 210 that facilitates communication with the upstream component across a link 222 (e.g., a PCIe-compliant link). The first component 202 may be coupled to a second component 208, which may be a PCIe-compliant downstream component, endpoint, or switch. In some embodiments, the first component may be linked to one or more intermediate components, such as a first timer 204 and a second timer 206.

[0041] In an embodiment, the first component 202 may include a downstream port 210 to facilitate downstream communication (e.g., toward the second component 208) with the second component 208 (if directly connected) or with the upstream (pseudo) port 212 of the re-timer 204. The second component 208 may include an upstream port 220 to facilitate upstream communication (e.g., toward the first component 202) with the first component 202 (if directly connected) or with the downstream (pseudo) port 212 of the re-timer 204.

[0042] exist Figure 2 In the example shown, the first component 202 can be linked to the first timer 204 via the first link segment 224. Similarly, the first timer 204 can be linked to the second timer 206 via link segment 226. The second timer 206 can be linked to the second component 208 via link segment 228. Link segments 224, 226, and 228 can constitute all or part of link 222.

[0043] Link 222 can facilitate upstream and downstream communication between the first component 202 and the second component 208. In an embodiment, upstream communication refers to data and control information sent from the second component 208 toward the first component 202; and downstream communication refers to data and control information sent from the first component 202 toward the second component 208. As mentioned above, one or more retimers (e.g., retimers 204 and 206) can be used to extend the range of link 222 between the first component 202 and the second component 208.

[0044] Link 222, which includes one or more retimers (e.g., retimers 204, 206), can form two or more separate electronic links at data rates comparable to those implemented with a similar protocol but without retimers. For example, if link 222 includes a single retimer, link 222 can form a link with two separate sub-links, each operating at 8.0 GT / s or higher. Figure 2 As shown, multiple retimers 204 and 206 can be used to extend link 222. Three link segments 222, 224, and 226 can be defined using two retimers 204 and 206, where the first sub-link 222 connects the first component 202 to the first retimer 204, the second sub-link 224 connects the first retimer 204 to the second retimer 206, and the third sub-link 226 connects the second retimer 206 to the second component 208.

[0045] like Figure 2 As illustrated in the examples, in some implementations, a retimer may include two ports (or pseudo-ports), and the ports may dynamically determine their respective downstream / upstream directions. In an embodiment, retimer 204 may include an upstream port 212 and a downstream port 214. Similarly, retimer 206 may include an upstream port 216 and a downstream port 218. Each retimer 204, 206 may have an upstream path and a downstream path. Furthermore, retimers 204, 206 may support operating modes including forwarding mode and execution mode. In some instances, retimers 204, 206 may decode data received on a sublink and reencode data to be forwarded downstream on another sublink. Thus, a retimer can capture a received bitstream before regenerating it and retransmitting it to another device or even another retimer (or redriver or repeater). In some cases, a retimer may modify some values ​​in the data it receives, for example, when processing and forwarding ordered set data. Additionally, retimers can potentially support any width option as their maximum width, for example, a set of width options defined by a specification such as PCIe.

[0046] As data rates on serial interconnects (e.g., PCIe, UPI, USB, etc.) increase, retimers are increasingly used to extend channel range. Multiple retimers can be cascaded for even longer channel ranges. It is expected that channel range typically decreases as signal speeds increase. Therefore, the use of retimers is likely to become more prevalent as interconnect technologies accelerate. For example, the use of retimers in PCIe interconnects is likely to increase, such as with PCIe Gen-4 (16GT / s) supporting PCIe Gen-3 (8GT / s), and this may also be the case with other interconnects as speeds increase.

[0047] Before a link is established or when link 222 fails to function properly, the system software can access downstream port 210 (e.g., in the first component 202, which could be an upstream component, such as a root complex or switch). In an embodiment, a register (e.g., a link capability register) can be configured to perform clock mode selection in downstream port 210. The system firmware / software can configure downstream port 210 to the desired mode, and if a change is needed, this will be done by the system firmware / software rather than by hardware.

[0048] As noted above, PCIe essentially has two types of clock architectures: In the first scenario, there is no shared clock reference between each component. In this first scenario, the clock is spread out for electromagnetic interference (EMI) mitigation—this first mode is known as Separate Reference Clock (SRIS) with independent SSCs. In the second scenario, the same reference clock is provided to each component on link 222 (sometimes called common timing), in which case whether the clock is “spread out” is generally irrelevant (non-SRIS).

[0049] PCISIG has tentatively determined that components supporting "Gen 5" (also known as 5.0, aka 32GT / s) must support both SRIS and non-SRIS operating modes. It is proposed that the systems, methods, and functions described herein be included in the PCIe 5.0 base specification to support both SRIS and non-SRIS timing. Specific elements include:

[0050] Support for 32G mode operation and other downstream ports can indicate support for the "SRIS mode selection mechanism".

[0051] Indicate that the downstream port that supports this can:

[0052] It supports both SRIS operating mode and SRNS (“non-SRIS”) operating mode, and does so symmetrically, so that the Rx and Tx of the port are always in the same mode.

[0053] Implement a configuration mechanism (defined below) to select the operating mode of the downstream port;

[0054] When a link (e.g., link 222) is disabled (and not at other times), it supports changing the operating mode of the downstream port; and

[0055] The training set (TS) or ordered set (OS) sent by the downstream port (e.g., downstream port 210) indicates to the port (e.g., pseudo port) at the retimer and the upstream port which mode to use.

[0056] Figure 3 This is a schematic diagram of a link capability register 300 including bits supporting the SRIS mode selection mechanism, according to an embodiment of this disclosure. The link capability register 300 identifies specific capabilities of a Fast PCI link. The allocation of register fields in the link capability register 300 is as follows: Figure 3 As shown in Table 1, the corresponding bit definitions are provided.

[0057] The link capability register 300 may include multiple bits for various capability mechanisms. Among the bits in the link capability register 300 are reserved bits (e.g., bit 23), which can be used as set bits to indicate support for the SRIS mode selection mechanism. The following can be added to the 23-bit capability definition:

[0058] Table 1. Definition of Bit 23 in Link Capability Register

[0059]

[0060] Figure 4 This is a schematic diagram of a link control register 400 including bits supporting the SRIS mode selection mechanism, according to an embodiment of this disclosure. The link control register 400 may include multiple bits for various capability mechanisms. Among the bits in the link control register 400 are reserved bits (e.g., bit 12), which can be used as set bits to indicate support for the SRIS mode selection mechanism. The following can be added to the 12-bit capability definitions in Table 2:

[0061] Table 2. Definition of Link Control Register Bit 12

[0062]

[0063]

[0064] In this embodiment, the SRIS mode selection bit can be a multi-bit field. For example, a multi-bit field can be used to select from a menu of PPM / SKP policies, such as 1000 ppm, exceeding the definition of the current SRIS / non-SRIS mode. In this embodiment, the SRIS mode selection bit can also be used to allow SRIS mode selection to be implemented in the upstream port as well.

[0065] The Link Capability 2 register fields can be redefined as follows:

[0066]

[0067]

[0068] The link control register 3 can be redefined as follows:

[0069]

[0070] L1 PM substate

[0071] The L1 power management (PM) substate establishes the link power management regime, which creates lower power substates of the L1 link state and the associated mechanisms for using these substates.

[0072] Ports that support L1 PM substates do not require a reference clock when in an L1 PM substate other than L1.0.

[0073] When operating in SRIS mode, ports that support both L1 PM substates and SRIS mode are required to support L1 PM substates. In this case, the CLKREQ# signal is used by the L1 PM substate protocol, but has no defined relationship with any local clock used by any port on the link, and the management of these local clocks is implementation-specific.

[0074] Form factor requirements of RefClock architecture

[0075] Each form factor specification must include the following table, which provides a clear overview of the timing architecture requirements for devices that support the form factor specification. For each timing architecture, the table indicates whether the architecture is required, optional, or not allowed for that form factor. Note that this refers to device operation—not the underlying silicon capabilities. The SRIS mode selection mechanism described above is used to discover and control the underlying silicon capabilities.

[0076] Figure 5This is a flowchart 500 illustrating the process by which a PCIe-compliant port operates based on the SRIS mode selection mechanism according to an embodiment of this disclosure. First, software or firmware controlling a downstream port of an upstream component (e.g., a root complex or switch) can determine whether (or determine) the downstream port supports the SRIS mode selection mechanism (502). This determination can be based on bits set in one or more registers (e.g., link capability registers and / or link control registers). If the downstream port does not support the SRIS mode selection mechanism, the software / firmware can skip further steps regarding SRIS mode selection. Bits in the link capability registers and / or link control registers can be set during startup, reboot, warm boot, etc., or when a new device is connected to an existing host or root controller.

[0077] The software / firmware may determine the system clock configuration from the downstream port to the corresponding upstream port (or the pseudo-port of the retimer) based at least in part on set bits in one or both of the link capability register or link control register (or other registers). The software / firmware may determine the system clock configuration, for example, using an out-of-band management interface (e.g., for polling the device / switch's system management (SM) bus) and / or using system-level components such as expansion cards or backplanes.

[0078] The software / firmware can select the appropriate SRIS mode in the downstream port based on a determination of the system clock configuration (506). In some embodiments, the software / firmware can transmit the SRIS mode to one or more upstream ports, including across PCIe-compliant links to pseudo-ports of connected retimers(s). The downstream port can use the selected SRIS mode to perform downstream data and control information communication across the link (510). That is, when in SRIS mode, upstream and downstream components can each use independent clocks with spread spectrum for data and control transmissions.

[0079] One interconnect architecture includes the Fast Peripheral Component Interconnect (PCIe) architecture. The primary goal of PCIe is to enable interoperability in an open architecture across multiple market segments: client (desktop and mobile), server (standard and enterprise), and embedded and communication devices. Fast PCI is a high-performance, general-purpose I / O interconnect defined for a variety of future computing and communication platforms. Some PCI attributes (e.g., its usage model, load-store architecture, and software interface) have been maintained through its revisions, while previous parallel bus implementations have been replaced by highly scalable, fully serial interfaces. More recent versions of Fast PCI leverage point-to-point interconnects, switch-based technologies, and improvements to packet protocols to achieve new levels of performance and features. Some of the improved features supported by Fast PCI are power management, Quality of Service (QoS), hot-plug / hot-swap support, data integrity, and error handling.

[0080] refer to Figure 6 This illustration shows an embodiment of a structure consisting of point-to-point links interconnecting a set of components. System 600 includes a processor 605 and system memory 610 coupled to a controller center 615. Processor 605 includes any processing element, such as a microprocessor, host processor, embedded processor, coprocessor, or other processor. Processor 605 is coupled to controller center 615 via a front-side bus (FSB) 606. In one embodiment, FSB 606 is a serial point-to-point interconnect as described below. In another embodiment, link 606 includes a serial differential interconnect architecture conforming to different interconnect standards.

[0081] System memory 610 includes any memory device, such as random access memory (RAM), non-volatile (NV) memory, or other memory accessible to devices in system 600. System memory 610 is coupled to controller center 615 via memory interface 616. Examples of memory interfaces include double data rate (DDR) memory interfaces, dual-channel DDR memory interfaces, and dynamic RAM (DRAM) memory interfaces.

[0082] In one embodiment, controller center 615 is a root center, root complex, or root controller in a Fast Peripheral Component Interconnect (PCIe or PCIE) interconnect hierarchy. Examples of controller center 615 include chipsets, memory controller centers (MCH), northbridges, interconnect controller centers (ICH), southbridges, and root port controllers / centers. Often, the term chipset refers to two physically separate controller centers, namely the memory controller center (MCH) coupled to the interconnect controller center (ICH). Note that current systems often include an MCH integrated with processor 605, while controller 615 communicates with I / O devices in a manner similar to that described below. In some embodiments, peer-to-peer routing may optionally be supported via root complex 615.

[0083] Here, the controller center 615 is coupled to the switch / bridge 620 via a serial link 619. Input / output modules 617 and 621 (also referred to as interfaces / ports 617 and 621) include / implement a layered protocol stack to provide communication between the controller center 615 and the switch 620. In one embodiment, multiple devices can be coupled to the switch 620.

[0084] Switch / bridge 620 routes packets / messages upstream (i.e., hierarchically upwards towards the root complex) from device 625 to controller center 615, and downstream (i.e., hierarchically downwards away from the root port controller) from processor 605 or system memory 610 to device 625. In one embodiment, switch 620 is referred to as a logical component of a plurality of virtual PCI to PCI bridge devices. Device 625 includes any internal or external devices or components to be coupled to an electronic system, such as I / O devices, network interface controllers (NICs), insert cards, audio processors, network processors, hard drives, storage devices, CD / DVD ROMs, monitors, printers, mice, keyboards, routers, portable storage devices, Firewire devices, Universal Serial Bus (USB) devices, scanners, and other input / output devices. Often in PCIe, the term "device" is referred to as an endpoint. Although not specifically shown, device 625 may include a PCIe to PCI / PCI-X bridge to support legacy or other versions of PCI devices. Endpoint devices in PCIe are often classified as legacy, PCIe, or root complex integrated endpoints.

[0085] The graphics accelerator 630 is also coupled to the controller center 615 via a serial link 632. In one embodiment, the graphics accelerator 630 is coupled to the MCH, which in turn is coupled to the ICH. The switch 620, and therefore the I / O device 625, is then coupled to the ICH. I / O modules 631 and 618 are also used to implement a layered protocol stack for communication between the graphics accelerator 630 and the controller center 615. Similar to the MCH discussed above, the graphics controller or graphics accelerator 630 itself may be integrated into the processor 605.

[0086] Go to Figure 7 This illustrates an embodiment of a layered protocol stack. The layered protocol stack 700 includes any form of layered communication stack, such as a Fast Path Interconnect (QPI) stack, a PCIe stack, a next-generation high-performance computing interconnect stack, or other layered stacks. (See the reference below.) Figure 6-9 The discussion relates to the PCIe stack, but the same concepts can be applied to other interconnect stacks. In one embodiment, protocol stack 700 is a PCIe protocol stack including a transaction layer 705, a link layer 710, and a physical layer 720. Interfaces (e.g., Figure 1 Interfaces 617, 618, 621, 622, 626, and 631 in the code can be represented as communication protocol stack 700. A representation of a communication protocol stack can also be called a module or interface that implements / includes the protocol stack.

[0087] Fast PCI uses packets to transmit information between components. Packets are formed in transaction layer 705 and data link layer 710 to carry information from the sending component to the receiving component. As the transmitted packets flow through other layers, they are expanded with additional information required for processing at those layers. On the receiving side, the reverse process occurs, and packets are transformed from their physical layer 720 representation to their data link layer 710 representation, and finally (for transaction layer packets) into a form that can be processed by the transaction layer 705 of the receiving device.

[0088] Transaction layer

[0089] In one embodiment, transaction layer 705 provides an interface between the device's processing core and the interconnect architecture (e.g., data link layer 710 and physical layer 720). In this regard, the primary responsibility of transaction layer 705 is the assembly and disassembly of packets (i.e., transaction layer packets or TLPs). Transaction layer 705 typically manages credit-based flow control for TLPs. PCIe implements decoupled transactions, where requests and responses are time-separated, allowing the link to carry additional traffic while the target device collects data for the response.

[0090] Furthermore, PCIe utilizes credit-based flow control. In this scheme, the device announces the initial credit amount for each in the receive buffer at transaction layer 705. External devices at the opposite end of the link (e.g., Figure 1 The controller center (115) in the system counts the amount of credit consumed by each TLP. A transaction can be sent if it has not exceeded the credit limit. A certain amount of credit is restored upon receiving a response. The advantage of this credit scheme is that the delay in credit return does not impact performance if no credit limit is encountered.

[0091] In one embodiment, the four transaction address spaces include a configuration address space, a memory address space, an input / output address space, and a message address space. Memory space transactions include one or more read and write requests for transferring data to or from a memory-mapped location. In one embodiment, memory space transactions can use two different address formats, such as a short address format (e.g., a 32-bit address) or a long address format (e.g., a 64-bit address). Configuration space transactions are used to access the configuration space of a PCIe device. Configuration space transactions include read and write requests. Message space transactions (or simply messages) are defined as supporting in-band communication between PCIe agents.

[0092] Therefore, in one embodiment, transaction layer 705 assembles the packet header / payload 706. The format of the current packet header / payload can be found in the PCIe specification on the PCIe specification website.

[0093] Quick Reference Figure 8 The diagram illustrates an embodiment of a PCIe transaction descriptor. In one embodiment, transaction descriptor 800 is a mechanism for carrying transaction information. In this respect, transaction descriptor 800 supports the identification of transactions in the system. Other potential uses include tracking modifications to the default transaction ordering and associating transactions with channels.

[0094] Transaction descriptor 800 includes a global identifier field 802, an attribute field 804, and a channel identifier field 806. In the illustrated example, the global identifier field 802 is depicted as including a local transaction identifier field 808 and a source identifier field 810. In one embodiment, the global transaction identifier 802 is unique for all incomplete requests.

[0095] In one implementation, the local transaction identifier field 808 is a field generated by the request broker and is unique for all incomplete requests required to be completed by that request broker. Furthermore, in this example, the source identifier 810 uniquely identifies the requester broker within the PCIe tier. Therefore, together with the source ID 810, the local transaction identifier field 808 provides a global identifier for transactions within the tier domain.

[0096] Attribute field 804 specifies the characteristics and relationships of a transaction. In this respect, attribute field 804 can potentially be used to provide additional information that allows modification of the default processing of a transaction. In one embodiment, attribute field 804 includes a priority field 812, a reservation field 814, an ordering field 816, and a non-listening field 818. Here, the priority subfield 812 can be modified by the initiator to assign priority to transactions. The reserved attribute field 814 is reserved for future use or vendor-defined use. Reserved attribute fields can be used to implement possible use models that utilize priority or security attributes.

[0097] In this example, the sort attribute field 816 provides optional information conveying the sort type that can modify the default collation. According to one example implementation, sort attribute "0" indicates that the default collation should be applied, while sort attribute "1" indicates a non-strict sort, where writes can propagate in the same direction, and read completions can also propagate in the same direction. The listen attribute field 818 determines whether a transaction is being listened to. As shown, the channel ID field 806 identifies the channel to which the transaction is associated.

[0098] Link layer

[0099] Link layer 710 (also known as data link layer 710) acts as an intermediate stage between transaction layer 705 and physical layer 720. In one embodiment, the responsibility of data link layer 710 is to provide a reliable mechanism for exchanging transaction layer packets (TLPs) between the two link components. One side of data link layer 710 receives a TLP packet assembled by transaction layer 705, applies a packet sequence identifier 711 (i.e., an identifier number or packet number), calculates and applies an error detection code (i.e., CRC 712), and submits the modified TLP to physical layer 720 for transmission across physical to external devices.

[0100] physical layer

[0101] In one embodiment, physical layer 720 includes a logic subblock 721 and an electronic block 722 for physically transmitting packets to external devices. Here, logic subblock 721 is responsible for the "digital" functions of physical layer 720. In this respect, the logic subblock includes a transmitting portion for preparing outgoing information for transmission by physical subblock 722, and a receiving portion for identifying and preparing received information before passing it to link layer 710.

[0102] Physical block 722 includes a transmitter and a receiver. The transmitter, provided with symbols by logic subblock 721, serializes the symbols and transmits them to an external device. The receiver provides serialized symbols from the external device and converts the received signals into a bit stream. The bit stream is deserialized and provided to logic subblock 721. In one embodiment, an 8b / 10b transmission code is used, where ten-bit symbols are transmitted / received. Here, special symbols are used to frame packets into frames 723. Additionally, in one example, the receiver also provides a symbol clock recovered from the incoming serial stream.

[0103] As stated above, while the Transaction Layer 705, Link Layer 710, and Physical Layer 720 have been discussed with reference to specific embodiments of the PCIe protocol stack, the layered protocol stack is not limited thereto. In fact, any layered protocol can be included / implemented. As an example, a port / interface represented as a layered protocol includes: (1) a first layer for assembling packets, namely the Transaction Layer; a second layer for ordering packets, namely the Link Layer; and a third layer for transmitting packets, namely the Physical Layer. As a specific example, the Common Standard Interface (CSI) layered protocol is used.

[0104] Next reference Figure 9 An embodiment of a PCIe serial point-to-point architecture is illustrated. While an embodiment of a PCIe serial point-to-point link is shown, the serial point-to-point link is not limited to this, as it includes any transmission path for transmitting serial data. In the illustrated embodiment, the basic PCIe link includes two low-voltage differential drive signal pairs: transmit pair 906 / 911 and receive pair 912 / 907. Therefore, device 905 includes transmit logic 906 for transmitting data to device 910 and receive logic 907 for receiving data from device 910. In other words, two transmit paths (i.e., paths 916 and 917) and two receive paths (i.e., paths 918 and 919) are included in the PCIe link.

[0105] A transmission path refers to any path used to transmit data, such as a transmission line, copper line, optical line, wireless communication channel, infrared communication link, or other communication path. A connection between two devices (e.g., device 905 and device 910) is called a link, for example, link 915. A link can support a channel—each channel represents a set of differential signal pairs (one pair for transmitting and one pair for receiving). To extend bandwidth, a link can aggregate multiple channels represented by xN, where N is any supported link width, such as 1, 2, 4, 8, 12, 16, 32, 64, or wider.

[0106] A differential pair refers to two transmission paths, such as lines 916 and 917, used to transmit differential signals. As an example, when line 916 switches from a low voltage level to a high voltage level (i.e., rising edge), line 917 is driven from a high logic level to a low logic level (i.e., falling edge). Differential signals potentially exhibit better electrical characteristics, such as better signal integrity, i.e., better cross-coupling, voltage overshoot / undershoot, ringing, etc. This allows for better timing windows, supporting faster transmission frequencies.

[0107] Note that the apparatus, methods, and systems described above can be implemented in any electronic device or system as foregoing. For specific illustration, the accompanying drawings below provide exemplary systems for utilizing the inventions described herein. Since the systems are described in more detail below, many different interconnects have been disclosed, described, and reconsidered based on the discussion above. And it will be apparent that the improvements described above can be applied to any of these interconnects, structures, or architectures.

[0108] Go to Figure 10 This diagram illustrates a block diagram of an exemplary computer system according to an embodiment of the present invention. The computer system is formed using a processor comprising execution units that execute instructions, wherein one or more interconnects in the interconnects implement one or more features. According to the present invention, for example, in the embodiment described herein, system 1000 includes components such as processor 1002 for employing execution units including logic to execute algorithms for process data. System 1000 is represented based on a Pentium III processor available from Intel Corporation (Santa Clara, California). TM Pentium 4 TM Xeon TM Itanium, XScale TM and / or StrongARM TMThe system uses a microprocessor, but other systems (including PCs with other microprocessors, engineering workstations, set-top boxes, etc.) can also be used. In one embodiment, the sample system 1000 executes Windows, which is available from Microsoft Corporation (Redmond, Washington). TM The operating system version can be used, but other operating systems (e.g., UNIX and Linux), embedded software, and / or graphical user interfaces can also be used. Therefore, embodiments of the present invention are not limited to any particular combination of hardware circuitry and software.

[0109] The embodiments are not limited to computer systems. Alternative embodiments of the invention can be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol devices, digital cameras, personal digital assistants (PDAs), and handheld PCs. Embedded applications may include microcontrollers, digital signal processors (DSPs), system-on-a-chip (SoCs), network computers (NetPCs), set-top boxes, network hubs, wide area network (WAN) switches, or any other system capable of executing one or more instructions according to at least one embodiment.

[0110] In the illustrated embodiment, processor 1002 includes one or more execution units 1008 to implement an algorithm for executing at least one instruction. An embodiment may be described in the context of a single-processor desktop or server system, but alternative embodiments may be included in a multiprocessor system. System 1000 is an example of a “centralized” system architecture. Computer system 1000 includes processor 1002 for processing data signals. As an illustrative example, processor 1002 includes a Complex Instruction Set Computer (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, a processor implementing a combination of instruction sets, or any other processor device (e.g., a digital signal processor). Processor 1002 is coupled to a processor bus 1010, which transmits data signals between processor 1002 and other components in system 1000. The components of system 1000 (e.g., graphics accelerator 1012, memory controller center 1016, memory 1020, I / O controller center 1024, wireless transceiver 1026, flash BIOS 1028, network controller 1034, audio controller 1036, serial expansion port 1038, I / O controller 1040, etc.) perform their conventional functions well known to those skilled in the art.

[0111] In one embodiment, processor 1002 includes a Level 1 (L1) internal cache memory 1004. Depending on the architecture, processor 1002 may have a single internal cache or multiple levels of internal cache. Other embodiments include a combination of both internal and external caches, depending on the specific implementation and requirements. Register file 1006 is used to store different types of data in various registers, including integer registers, floating-point registers, vector registers, grouped registers, shadow registers, checkpoint registers, status registers, and instruction pointer registers.

[0112] An execution unit 1008, including logic for performing integer and floating-point operations, also resides in the processor 1002. In one embodiment, the processor 1002 includes a microcode ROM for storing microcode, which, when executed, will perform algorithms for specific macro instructions or to handle complex scenarios. Here, the microcode is potentially updatable to handle / fix logical errors in the processor 1002. In one embodiment, the execution unit 1008 includes logic for processing a packaged instruction set 1009. By including the packaged instruction set 1009, along with associated circuitry for executing instructions, in the instruction set of the general-purpose processor 1002, operations used by many multimedia applications can be performed using packaged data in the general-purpose processor 1002. Thus, many multimedia applications can be accelerated and executed more efficiently by performing operations on packaged data using the full width of the processor data bus. This potentially eliminates the need to transfer smaller data units across the processor's data bus to perform one or more operations (one data element at a time).

[0113] Alternative embodiments of execution unit 1008 may also be used in microcontrollers, embedded processors, graphics devices, DSPs, and other types of logic circuits. System 1000 includes memory 1020. Memory 1020 includes dynamic random access memory (DRAM) devices, static random access memory (SRAM) devices, flash memory devices, or other storage devices. Memory 1020 stores instructions and / or data represented by data signals to be executed by processor 1002.

[0114] Note that any of the foregoing features or aspects of the present invention can be used for Figure 10On one or more interconnects shown. For example, an on-die interconnect (ODI) (not shown) for coupling internal units of processor 1002 implements one or more aspects of the invention described above. Alternatively, the invention is associated with processor bus 1010 (e.g., Intel Quick Path Interconnect (QPI) or other known high-performance computing interconnects), high-bandwidth memory path 1018 to memory 1020, point-to-point link to graphics accelerator 1012 (e.g., conforming to Fast Peripheral Component Interconnect (PCIe) architecture), controller center interconnect 1022, I / O or other interconnects (e.g., USB, PCI, PCIe) for coupling other components shown. Some examples of these components include audio controller 1036, firmware center (Flash BIOS) 1028, wireless transceiver 1026, data storage device 1024, conventional I / O controller 1010 including user input and keyboard interface 1042, serial expansion port 1038 such as Universal Serial Bus (USB), and network controller 1034. Data storage device 1024 may include hard disk drives, floppy disk drives, CD-ROM devices, flash memory devices, or other high-capacity storage devices.

[0115] Now for reference Figure 11 A block diagram of a second system 1100 according to an embodiment of the present invention is shown. Figure 11 As shown, the multiprocessor system 1100 is a point-to-point interconnect system and includes a first processor 1170 and a second processor 1180 coupled via a point-to-point interconnect 1150. Each of processors 1170 and 1180 may be a version of a processor. In one embodiment, 1152 and 1154 are part of a serial point-to-point coherent interconnect structure, such as Intel's Fast Path Interconnect (QPI) architecture. Therefore, the present invention can be implemented within a QPI architecture.

[0116] Although only two processors 1170 and 1180 are shown, it should be understood that the scope of the invention is not limited thereto. In other embodiments, one or more additional processors may be present in a given processor.

[0117] Processors 1170 and 1180 are shown to include integrated memory controller units 1172 and 1182, respectively. Processor 1170 also includes point-to-point (PP) interfaces 1176 and 1178 as part of its bus controller unit; similarly, the second processor 1180 includes PP interfaces 1186 and 1188. Processors 1170 and 1180 can exchange information via PP interface 1150 using point-to-point (PP) interface circuitry 1178 and 1188. Figure 11As shown, IMC 1172 and 1182 couple the processor to the corresponding memory, namely memory 1132 and memory 1134, which may be portions of the main memory locally attached to the corresponding processor.

[0118] Processors 1170 and 1180 each use point-to-point interface circuits 1176, 1194, 1186, and 1198 to exchange information with chipset 1190 via individual PP interfaces 1152 and 1154. Chipset 1190 also exchanges information with high-performance graphics circuit 1138 via interface circuit 1192 along high-performance graphics interconnect 1139.

[0119] A shared cache (not shown) may be located in one or two processors; but still connected to the processor via the PP interconnect, so that if the processor is in a low-power mode, one or both of the processor’s local cache information may be stored in the shared cache.

[0120] Chipset 1190 can be coupled to first bus 1116 via interface 1196. In one embodiment, first bus 1116 may be a peripheral component interconnect (PCI) bus, or a bus such as a fast PCI bus or another third-generation I / O interconnect bus, but the scope of the invention is not limited thereto.

[0121] like Figure 11 As shown, various I / O devices 1114 are coupled to a first bus 1116 along with a bus bridge 1118, which couples the first bus 1116 to a second bus 1120. In one embodiment, the second bus 1120 includes a low pin count (LPC) bus. Various devices are coupled to the second bus 1120, including, for example, a keyboard and / or mouse 1122, a communication device 1127, and a storage unit 1128 such as a disk drive or other mass storage device, which in one embodiment often includes instructions / code and data 1130. Additionally, audio I / O 1124 is shown coupled to the second bus 1120. Note that other architectures are possible, with variations in the components and interconnect architectures included. For example, instead of... Figure 11 The point-to-point architecture allows the system to implement multi-point bus or other similar architectures.

[0122] Many different use cases can be realized by utilizing the various inertial and environmental sensors available on the platform. These use cases support advanced computational operations, including sensing computing, and also allow for enhancements regarding power management / battery life, safety, and system responsiveness.

[0123] For example, regarding power management / battery life issues, the ambient light conditions at the platform location are determined, at least in part, based on information from an ambient light sensor, and the intensity of the display is controlled accordingly. This reduces the power consumed by operating the display under specific lighting conditions.

[0124] Regarding security operations, based on contextual information (e.g., location information) obtained from sensors, it can be determined whether a user is allowed access to specific secure documents. For example, a user may be allowed access to these documents in a workplace or home location. However, when the platform is in a public location, user access to these documents is blocked. In one embodiment, this determination is based on location information, for example, identified via a GPS sensor or a camera recognizing a landmark. Other security operations may include providing pairing of devices within close proximity to each other, such as a portable platform as described herein and a user's desktop computer, mobile phone, etc. In some implementations, when these devices are paired in this way, specific sharing is achieved via near-field communication. However, this sharing can be disabled when the devices exceed a certain distance. Furthermore, when a platform as described herein is paired with a smartphone, when in a public location, an alarm can be configured to trigger when the devices move beyond a predetermined distance from each other. Conversely, when these paired devices are in a secure location (e.g., a workplace or home location), the devices may exceed this predetermined limit without triggering such an alarm.

[0125] Sensor information can also be used to enhance responsiveness. For example, even when the platform is in a low-power state, sensors can still operate at relatively low frequencies. Therefore, any changes in the platform's position, such as those determined by inertial sensors, GPS sensors, etc., can be detected. If no such changes have been registered, they occur at the previous wireless center (e.g., Wi-Fi). TM Faster connections from access points or similar wireless enablers (because scanning for available wireless network resources is not required in this case). This allows for a higher level of responsiveness when waking from a low-power state.

[0126] It should be understood that many other use cases can be realized using sensor information obtained via integrated sensors within a platform as described herein, and the examples above are for illustrative purposes only. Using a system as described herein, a perceptual computing system can allow the addition of alternative input modalities, including gesture recognition, and enable the system to sense user actions and intentions.

[0127] In some embodiments, one or more infrared or other thermal sensing elements, or any other elements for sensing the presence or movement of a user, may be present. Such sensing elements may include multiple different elements working together, working sequentially, or both. For example, sensing elements may include elements that provide initial sensing, such as light or sound projection, via, for example, an ultrasonic time-of-flight camera or a patterned light camera, followed by sensing gesture detection.

[0128] Also in some embodiments, the system includes a light generator to produce illumination lines. In some embodiments, the lines provide visual cues about virtual boundaries, i.e., fictitious or virtual locations in space, where a user's actions of passing through or crossing virtual boundaries or planes are interpreted as an intention to engage with the computing system. In some embodiments, the illumination lines may change color as the computing system transitions to different states with respect to the user. The illumination lines can be used to provide visual cues for the user regarding virtual boundaries in space and can be used by the system to determine the computer's state transitions with respect to the user, including determining when the user wishes to engage with the computer.

[0129] In some embodiments, the computer senses the user's position and manipulates to interpret the movement of the user's hand across a virtual boundary as a gesture indicating the user's intention to engage with the computer. In some embodiments, the light generated by a light generator may change as the user passes through a virtual line or plane, thereby providing the user with visual feedback that the user has entered an area used to provide gestures to provide input to the computer.

[0130] The display screen can provide a visual indication of the computing system's state transitions regarding the user. In some embodiments, the first screen is provided in a first state in which the system senses the user's presence, for example, by using one or more sensing elements.

[0131] In some implementations, the system is used to sense user identity, for example, through facial recognition. Here, a transition to a second screen can occur where a second state, in which the system has calculated that the user's identity has been recognized, is provided, whereby the second screen provides visual feedback to the user that the user has transitioned to the new state. A transition to a third screen can occur where a third state, in which the user has confirmed the user's recognition, occurs.

[0132] In some embodiments, the computing system may use a transition mechanism to determine the location of a user's virtual boundary, wherein the location of the virtual boundary may vary with the user and the context. The computing system may generate light (e.g., illumination lines) to indicate the virtual boundary for engagement with the system. In some embodiments, the computing system may be in a standby state and may generate light in a first color. The computing system may detect whether a user has reached the virtual boundary, for example, by sensing the user's presence and movement using sensing elements.

[0133] In some embodiments, if it is detected that a user has crossed the virtual boundary (e.g., the user's hand is closer to the computing system than the virtual boundary line), the computing system can transition to a state for receiving gesture input from the user, wherein the mechanism indicating the transition may include light indicating that the virtual boundary changes to a second color.

[0134] In some embodiments, the computing system may then determine whether a gesture movement has been detected. If a gesture movement is detected, the computing system may proceed with the gesture recognition process, which may include using data from a gesture database that may reside in memory within the computing device or be otherwise accessed by the computing device.

[0135] If a user's gesture is recognized, the computing system can perform a function in response to the input, and return to receive additional gestures if the user is within the virtual boundary. In some embodiments, if no gesture is recognized, the computing system can transition to an error state, wherein a mechanism indicating the error state may include an optical indicator of the virtual boundary changing to a third color, wherein if the user is within the virtual boundary, the system returns to receive additional gestures to engage with the computing system.

[0136] As mentioned above, in other embodiments, the system can be configured as a convertible tablet system that can be used in at least two different modes: tablet mode and laptop mode. The convertible system can have two panels, a display panel and a base panel, such that in tablet mode, the two panels are stacked on top of each other. In tablet mode, the display panel faces outwards and can provide touchscreen functionality found in conventional tablets. In laptop mode, the two panels can be arranged in an open, clamshell configuration.

[0137] In various embodiments, the accelerometer may be a 3-axis accelerometer with a data rate of at least 50 Hz. A gyroscope, which may be a 3-axis gyroscope, may also be included. Additionally, an electronic compass / magnetometer may be present. Furthermore, one or more proximity sensors may be provided (e.g., for opening a cover to sense when a person approaches (or does not approach) the system and adjust power / performance to extend battery life). Enhanced features may be provided for the sensor fusion capabilities of some operating systems (including accelerometers, gyroscopes, and compasses). Additionally, a sensor wake-up mechanism may be implemented via a sensor center with a real-time clock (RTC) to receive sensor input when the rest of the system is in a low-power state.

[0138] In some embodiments, an internal cover / display open switch or sensor is used to indicate when the cover is closed / opened, and can be used to put the system into connected standby or automatically wake it from connected standby. Other system sensors may include ACPI sensors for monitoring the internal processor, memory, and skin temperature to implement changes in processor and system operating states based on sensed parameters.

[0139] In this embodiment, the OS may be one that implements connected standby (also referred to herein as Win8 CS). 8 OS. Windows 8 connected standby or another OS in a similar state can provide very low idle power via a platform as described in this article, enabling applications to maintain a connection to, for example, cloud-based locations with very low power consumption. This platform can support three power states: screen on (normal); connected standby (as the default "off" state); and powered off (zero watts). Therefore, in connected standby, the platform is logically powered on (at minimum power levels) even when the screen is off. In such a platform, power management can be transparent to applications and continuous connectivity can be maintained, partly due to offloading techniques that allow the least powered components to operate.

[0140] Now for reference Figure 12 A block diagram of components present in a computer system according to an embodiment of the present invention is shown. Figure 12 As shown, system 1200 includes any combination of components. These components may be implemented as ICs, portions thereof, discrete electronic devices, or other modules, logic, hardware, software, firmware, or combinations thereof adapted into a computer system, or implemented as components otherwise incorporated into the chassis of the computer system. It should also be noted that... Figure 12 The block diagram is intended to show a high-level view of the many components of a computer system. However, it should be understood that in other implementations, some of the components shown may be omitted, additional components may be present, and different arrangements of the components shown may occur. Therefore, the invention described above can be implemented in any part of one or more interconnections shown or described below.

[0141] like Figure 12 As seen in the illustration, in one embodiment, processor 1210 includes a microprocessor, a multi-core processor, a multi-threaded processor, an ultra-low voltage processor, an embedded processor, or other known processing element. In the illustrated implementation, processor 1210 acts as a main processing unit and central hub for communicating with a number of components among the various components of system 1200. As an example, processor 1210 is implemented as a system-on-a-chip (SoC). As a specific illustrative example, processor 1210 includes components based on... Architecture Core TMThe processor (e.g., i3, i5, i7) or another such processor available from Intel Corporation (Santa Clara, CA) may be used. However, it should be understood that other low-power processors (e.g., available from Advanced Micro Devices (AMD) of Sunnyvale, CA; MIPS-based designs from MIPS Technologies of Sunnyvale, CA; ARM-based designs licensed from ARM Holdings or its customers or licensors or adopters) may instead exist in other embodiments, such as Apple A5 / A6 processors, Qualcomm Snapdragon processors, or TI OMAP processors. Note that many of these customer versions of processors are modified and altered; however, they may support or recognize a specific instruction set that executes algorithms as defined by the processor licensor. Here, the microarchitectural implementation may vary, but the processor's architectural functionality is generally consistent. Specific details regarding the architecture and operation of processor 1210 in one implementation will be discussed further below to provide illustrative examples.

[0142] In one embodiment, processor 1210 communicates with system memory 1215. As an illustrative example, this can be implemented in an embodiment via multiple memory devices to provide a fixed amount of system memory. As an example, the memory may conform to a design based on the Joint Electronic Devices Engineering Committee (JEDEC) Low Power Double Data Rate (LPDDR), such as the current LPDDR2 standard according to JEDEC JESD 209-2E (released April 2009), or the next-generation LPDDR standard known as LPDDR3 or LPDDR4, which will provide an extension of LPDDR2 to increase bandwidth. In various implementations, individual memory devices may have different package types, such as single-die package (SDP), dual-die package (DDP), or quad-die package (67P). In some embodiments, these devices are soldered directly onto the motherboard to provide a low-profile solution, while in other embodiments, these devices are configured as one or more memory modules that are then coupled to the motherboard via a given connector. And of course, other memory implementations are also possible, such as other types of memory modules, for example, different kinds of dual in-line memory modules (DIMMs), including but not limited to microDIMMs and miniDIMMs. In certain illustrative embodiments, the memory size is between 2GB and 16GB, and can be configured as DDR3LM packages or LPDDR2 or LPDDR3 memory soldered to the motherboard via a ball grid array (BGA).

[0143] To provide persistent storage for information such as data, applications, one or more operating systems, the mass storage device 1220 may also be coupled to the processor 1210. In various embodiments, the mass storage device may be implemented via an SSD to achieve a thinner and lighter system design and to improve system responsiveness. However, in other embodiments, the mass storage device may be implemented primarily using a hard disk drive (HDD), with a smaller amount of SSD storage acting as an SSD cache to provide non-volatile storage of context state and other such information during power-down events, thereby enabling rapid power-up when system activity is initiated. Similarly, as... Figure 12 As shown, the flash memory device 1222 can be coupled to the processor 1210, for example, via a Serial Peripheral Interface (SPI). This flash memory device can provide non-volatile storage for system software, including the Basic Input / Output Software (BIOS) and other system firmware.

[0144] In various embodiments, the system's mass storage device is implemented as a standalone SSD or as a disk drive, optical drive, or other drive with an SSD cache. In some embodiments, the mass storage device is implemented as an SSD or HDD and a Recovery-Speed ​​(RST) cache module. In various implementations, the HDD provides storage between 320GB and 4 terabytes (TB) and above, while the RST cache utilizes an SSD with a capacity of 24GB to 256GB. Note that this SSD cache can be configured as a single-level cache (SLC) or multi-level cache (MLC) option to provide an appropriate level of responsiveness. In the SSD-only option, the module can be housed in various locations, such as in mSATA or NGFF slots. As an example, the SSD capacity ranges from 120GB to 1TB.

[0145] Various input / output (I / O) devices can exist within the system 1200. Figure 12 The embodiment specifically illustrates a display 1224, which may be a high-definition LCD or LED panel disposed within a cover portion of a chassis. This display panel may also provide a touchscreen 1225 (e.g., externally adapted to the display panel), allowing user input to be provided to the system via user interaction with the touchscreen to achieve desired operations, such as display information, access information, etc. In one embodiment, the display 1224 may be coupled to the processor 1210 via a display interconnect, which may be implemented as a high-performance graphics interconnect. The touchscreen 1225 may be coupled to the processor 1210 via another interconnect, which in this embodiment may be an I2C interconnect. Figure 12As further shown, in addition to the touchscreen 1225, user input via touch can also occur through the touchpad 1230, which can be configured inside the chassis and can also be coupled to the same I2C interconnect as the touchscreen 1225.

[0146] The display panel can operate in several modes. In a first mode, the display panel can be arranged in a transparent state, meaning it is transparent to visible light. In various embodiments, most of the display panel, except for the surrounding bezel, can be a monitor. When the system operates in laptop mode and the display panel is transparent, the user can view the information presented on the display panel while also viewing objects behind the monitor. Additionally, the information displayed on the display panel can be viewed by a user located behind the monitor. Alternatively, the display panel can operate in an opaque state, where visible light does not pass through it.

[0147] In tablet mode, the system is folded closed, such that when the bottom surface of the substrate rests on the surface or is held by the user, the rear display surface of the display panel remains in a position facing outwards towards the user. In tablet operation mode, the rear display surface functions as both a display and a user interface, as this surface can have touchscreen functionality and can perform other known functions of conventional touchscreen devices (e.g., tablet devices). For this purpose, the display panel may include a transparency adjustment layer disposed between the touchscreen layer and the front display surface. In some embodiments, the transparency adjustment layer may be an electrochromic (EC) layer, an LCD layer, or a combination of an EC layer and an LCD layer.

[0148] In various embodiments, the display may have different sizes, such as 11.6" or 13.3" screens, and may have a 16:9 aspect ratio and a brightness of at least 300 nits. Furthermore, the display may be a full high-definition (HD) resolution (at least 1920x1080p), compatible with an embedded display port (eDP), and a low-power panel with panel self-refresh.

[0149] Regarding touchscreen capabilities, the system can provide a multi-touch capacitive display panel that supports at least five fingers. In some embodiments, the display can support up to ten fingers. In one embodiment, the touchscreen is housed in a low-friction, damage- and scratch-resistant glass with a coating (e.g., Gorilla Glass). TM Or Gorilla Glass 2 TMWithin this range, to reduce "finger burning" and avoid "finger skipping". To provide an enhanced touch experience and responsiveness, in some implementations, the touch panel features multi-touch capabilities (e.g., less than 2 frames (30Hz) per static view during pinch-to-zoom) and single-touch capabilities of less than 1cm per frame (30Hz) with a 200ms (finger-to-pointer lag) condition. In some implementations, the display supports edge-to-edge glass with a minimal screen bezel flush with the panel surface and limited IO interference when using multi-touch.

[0150] For sensing computing and other purposes, various sensors can exist within the system and can be coupled to processor 1210 in different ways. Specific inertial and environmental sensors can be coupled to processor 1210 through sensor center 1240, for example, via I2C interconnect. Figure 12 In the illustrated embodiments, these sensors may include an accelerometer 1241, an ambient light sensor (ALS) 1242, a compass 1243, and a gyroscope 1244. Other environmental sensors may include one or more thermal sensors 1246, which in some embodiments are coupled to the processor 1210 via a system management bus (SMBus).

[0151] Many different use cases can be realized by utilizing the various inertial and environmental sensors available on the platform. These use cases support advanced computational operations, including sensing computing, and also allow for enhancements regarding power management / battery life, safety, and system responsiveness.

[0152] For example, regarding power management / battery life issues, the ambient light conditions at the platform location are determined, at least in part, based on information from an ambient light sensor, and the intensity of the display is controlled accordingly. This reduces the power consumed by operating the display under specific lighting conditions.

[0153] Regarding security operations, based on contextual information (e.g., location information) obtained from sensors, it can be determined whether a user is allowed access to specific secure documents. For example, a user may be allowed access to these documents in a workplace or home location. However, when the platform is in a public location, user access to these documents is blocked. In one embodiment, this determination is based on location information, for example, identified via a GPS sensor or a camera recognizing a landmark. Other security operations may include providing pairing of devices within close proximity to each other, such as a portable platform as described herein and a user's desktop computer, mobile phone, etc. In some implementations, when these devices are paired in this way, specific sharing is achieved via near-field communication. However, this sharing can be disabled when the devices exceed a certain distance. Furthermore, when a platform as described herein is paired with a smartphone, when in a public location, an alarm can be configured to trigger when the devices move beyond a predetermined distance from each other. Conversely, when these paired devices are in a secure location (e.g., a workplace or home location), the devices may exceed this predetermined limit without triggering such an alarm.

[0154] Sensor information can also be used to enhance responsiveness. For example, even when the platform is in a low-power state, sensors can still operate at relatively low frequencies. Therefore, any changes in the platform's position, such as those determined by inertial sensors, GPS sensors, etc., can be detected. If no such changes have been registered, they occur at the previous wireless center (e.g., Wi-Fi). TM Faster connections from access points or similar wireless enablers (because scanning for available wireless network resources is not required in this case). This allows for a higher level of responsiveness when waking from a low-power state.

[0155] It should be understood that many other use cases can be realized using sensor information obtained via integrated sensors within a platform as described herein, and the examples above are for illustrative purposes only. Using a system as described herein, a perceptual computing system can allow the addition of alternative input modalities, including gesture recognition, and enable the system to sense user actions and intentions.

[0156] In some embodiments, one or more infrared or other thermal sensing elements, or any other elements for sensing the presence or movement of a user, may be present. Such sensing elements may include multiple different elements working together, working sequentially, or both. For example, sensing elements may include elements that provide initial sensing, such as light or sound projection, via, for example, an ultrasonic time-of-flight camera or a patterned light camera, followed by sensing gesture detection.

[0157] Also in some embodiments, the system includes a light generator to produce illumination lines. In some embodiments, the lines provide visual cues about virtual boundaries, i.e., fictitious or virtual locations in space, where a user's actions of passing through or crossing virtual boundaries or planes are interpreted as an intention to engage with the computing system. In some embodiments, the illumination lines may change color as the computing system transitions to different states with respect to the user. The illumination lines can be used to provide visual cues for the user regarding virtual boundaries in space and can be used by the system to determine the computer's state transitions with respect to the user, including determining when the user wishes to engage with the computer.

[0158] In some embodiments, the computer senses the user's position and manipulates to interpret the movement of the user's hand across a virtual boundary as a gesture indicating the user's intention to engage with the computer. In some embodiments, the light generated by a light generator may change as the user passes through a virtual line or plane, thereby providing the user with visual feedback that the user has entered an area used to provide gestures to provide input to the computer.

[0159] The display screen can provide a visual indication of the computing system's state transitions regarding the user. In some embodiments, the first screen is provided in a first state in which the system senses the user's presence, for example, by using one or more sensing elements.

[0160] In some implementations, the system is used to sense user identity, for example, through facial recognition. Here, a transition to a second screen can occur where a second state, in which the system has calculated that the user's identity has been recognized, is provided, whereby the second screen provides visual feedback to the user that the user has transitioned to the new state. A transition to a third screen can occur where a third state, in which the user has confirmed the user's recognition, occurs.

[0161] In some embodiments, the computing system may use a transition mechanism to determine the location of a user's virtual boundary, wherein the location of the virtual boundary may vary with the user and the context. The computing system may generate light (e.g., illumination lines) to indicate the virtual boundary for engagement with the system. In some embodiments, the computing system may be in a standby state and may generate light in a first color. The computing system may detect whether a user has reached the virtual boundary, for example, by sensing the user's presence and movement using sensing elements.

[0162] In some embodiments, if it is detected that a user has crossed the virtual boundary (e.g., the user's hand is closer to the computing system than the virtual boundary line), the computing system can transition to a state for receiving gesture input from the user, wherein the mechanism indicating the transition may include light indicating that the virtual boundary changes to a second color.

[0163] In some embodiments, the computing system may then determine whether a gesture movement has been detected. If a gesture movement is detected, the computing system may proceed with the gesture recognition process, which may include using data from a gesture database that may reside in memory within the computing device or be otherwise accessed by the computing device.

[0164] If a user's gesture is recognized, the computing system can perform a function in response to the input, and return to receive additional gestures if the user is within the virtual boundary. In some embodiments, if no gesture is recognized, the computing system can transition to an error state, wherein a mechanism indicating the error state may include an optical indicator of the virtual boundary changing to a third color, wherein if the user is within the virtual boundary, the system returns to receive additional gestures to engage with the computing system.

[0165] As mentioned above, in other embodiments, the system can be configured as a convertible tablet system that can be used in at least two different modes: tablet mode and laptop mode. The convertible system can have two panels, a display panel and a base panel, such that in tablet mode, the two panels are stacked on top of each other. In tablet mode, the display panel faces outwards and can provide touchscreen functionality found in conventional tablets. In laptop mode, the two panels can be arranged in an open, clamshell configuration.

[0166] In various embodiments, the accelerometer may be a 3-axis accelerometer with a data rate of at least 50 Hz. A gyroscope, which may be a 3-axis gyroscope, may also be included. Additionally, an electronic compass / magnetometer may be present. Furthermore, one or more proximity sensors may be provided (e.g., for opening a cover to sense when a person approaches (or does not approach) the system and adjust power / performance to extend battery life). Enhanced features may be provided for the sensor fusion capabilities of some operating systems (including accelerometers, gyroscopes, and compasses). Additionally, a sensor wake-up mechanism may be implemented via a sensor center with a real-time clock (RTC) to receive sensor input when the rest of the system is in a low-power state.

[0167] In some embodiments, an internal cover / display open switch or sensor is used to indicate when the cover is closed / opened, and can be used to put the system into connected standby or automatically wake it from connected standby. Other system sensors may include ACPI sensors for monitoring the internal processor, memory, and skin temperature to implement changes in processor and system operating states based on sensed parameters.

[0168] In this embodiment, the OS may be one that implements connected standby (also referred to herein as Win8 CS). 8 OS. Windows 8 connected standby or another OS in a similar state can provide very low idle power via a platform as described in this article, enabling applications to maintain a connection to, for example, cloud-based locations with very low power consumption. This platform can support three power states: screen on (normal); connected standby (as the default "off" state); and powered off (zero watts). Therefore, in connected standby, the platform is logically powered on (at minimum power levels) even when the screen is off. In such a platform, power management can be transparent to applications and continuous connectivity can be maintained, partly due to offloading techniques that allow the least powered components to operate.

[0169] Still Figure 12 As seen, various peripheral devices can be coupled to processor 1210 via a low pin count (LPC) interconnect. In the illustrated embodiment, various components can be coupled via an embedded controller 1235. These components may include a keyboard 1236 (e.g., coupled via a PS2 interface), a fan 1237, and a thermal sensor 1239. In some embodiments, a touchpad 1230 may also be coupled to EC 1235 via a PS2 interface. Additionally, a security processor such as a Trusted Platform Module (TPM) 1238 (according to Trusted Computing Group (TCG) TPM specification version 1.2 dated October 2, 2003) may also be coupled to processor 1210 via this LPC interconnect. However, it should be understood that the scope of the invention is not limited to this aspect, and secure processing and storage of security information may be performed in another protected location (e.g., static random access memory (SRAM) in a security coprocessor) or as a large binary object of encrypted data decrypted only when protected by a Secure Enclave (SE) processor mode.

[0170] In certain implementations, the peripheral ports may include a High Definition Media Interface (HDMI) connector (which may have different form factors, such as full-size, mini, or micro); one or more USB ports, such as a full-size external port according to the Universal Serial Bus Revision 3.0 specification (November 2008), at least one of which is powered to charge USB devices (e.g., smartphones) when the system is in connected standby mode and plugged into an AC wall power source. Additionally, one or more Thunderbolt ports may be provided. TMPorts. Other ports may include externally accessible card readers, such as full-size SD-XC card readers and / or WWAN SIM card readers (e.g., 8-pin card readers). For audio, a 3.5mm jack with stereo and microphone capabilities (e.g., combined functionality) may be present, supporting jack detection (e.g., only headphones using a microphone in the cover plate or headphones using a microphone in cable form are supported). In some embodiments, this jack can reassign tasks between stereo headphone and stereo microphone inputs. Additionally, a power jack may be provided for coupling to an AC block.

[0171] System 1200 can communicate with external devices in various ways, including wirelessly. Figure 12 In the illustrated embodiments, various wireless modules are present, each of which may correspond to a radio configured for a specific wireless communication protocol. One method for short-range wireless communication, such as near-field communication, could be via a Near Field Communication (NFC) unit 1245, which in one embodiment can communicate with the processor 1210 via an SMBus. Note that via this NFC unit 1245, devices that are very close to each other can communicate. For example, a user can enable system 1200 to communicate with another (e.g., a portable device, such as a user's smartphone) by tightly fitting two devices together, and enable the transmission of information such as identification information, payment information, and data such as image data. The NFC system can also be used to perform wireless power transfer.

[0172] Using the NFC unit described herein, a user can strike and place devices side-by-side by leveraging the coupling between the coils of one or more devices in such a device for near-field coupling functions (e.g., near-field communication and wireless power transfer (WPT)). More specifically, embodiments provide devices with strategically shaped and placed ferrite material to provide better coupling of the coils. Each coil has an associated inductance, which can be selected in conjunction with the system's resistance, capacitance, and other characteristics to achieve a common resonant frequency for the system.

[0173] As in Figure 12 As further seen, the additional wireless units may include other short-range wireless engines, including WLAN unit 1250 and Bluetooth unit 1252. Using WLAN unit 1250, Wi-Fi can be implemented according to the given Institute of Electrical and Electronics Engineers (IEEE) 802.11 standard. TM Communication, via Bluetooth unit 1252, can occur via short-range communication using the Bluetooth protocol. These units can communicate with processor 1210 via, for example, a USB link or a Universal Asynchronous Receiver Transmitter (UART) link. Alternatively, these units can be interconnected using Fast Peripherals.TM (PCIe TM The protocol is coupled to the processor 1210 via an interconnect, for example, according to Fast PCI. TM The specification base version 3.0 (released January 17, 2007), or another such protocol such as the Serial Data Input / Output (SDIO) standard. Of course, the actual physical connection between these peripherals (which can be configured on one or more plug-in cards) can be achieved through NGFF connectors adapted to the motherboard.

[0174] Additionally, wireless wide area communication, for example, according to cellular or other wireless wide area protocols, can occur via the WWAN unit 1256, which can then be coupled to the subscriber identity module (SIM) 1257. Furthermore, a GPS module 1255 may also be present to enable the reception and use of location information. Note that in Figure 12 In the illustrated embodiment, the WWAN unit 1256 and an integrated capture device such as a camera module 1254 can communicate via a given USB protocol (e.g., a USB 2.0 or 3.0 link, or a UART or I2C protocol). Again, the actual physical connection of these units can be via an NGFF connector that adapts the NGFF insert card for configuration on the motherboard.

[0175] In certain embodiments, the wireless function may be, for example, via WiFi. TM An 802.11ac solution is provided modularly (e.g., a backward-compatible insert card to IEEE 802.11abgn) to support Windows 8 CS. The card can be configured in an internal slot (e.g., via an NGFF adapter). Add-on modules can provide Bluetooth capability (e.g., Bluetooth 4.0 with backward compatibility) and... Wireless display functionality. Additionally, NFC support can be provided via a separate device or a multi-functional device, and as an example, it can be placed on the front right side of the chassis for easy access. An additional module can be a WWAN device, which can provide support for 3G / 4G / LTE and GPS. This module can be implemented in an internal (e.g., NGFF) slot. WiFi support is also possible. TM Bluetooth, WWAN, NFC, and GPS provide integrated antenna support, enabling communication from WiFi according to the wireless gigabit specification (July 2010). TM The seamless transition to WWAN radio and wireless gigabit (WiGig) is also possible.

[0176] As described above, the integrated camera can be incorporated into the cover plate. As an example, the camera can be a high-resolution camera, for example, with a resolution of at least 2.0 megapixels (MP) and extending to 6.0MP or higher.

[0177] To provide audio input and output, an audio processor can be implemented via a digital signal processor (DSP) 1260, which can be coupled to a processor 1210 via a high-definition audio (HDA) link. Similarly, the DSP 1260 can communicate with an integrated encoder / decoder (CODEC) and amplifier 1262, which can then be coupled to an output speaker 1263 that can be implemented within a chassis. Likewise, the amplifier and CODEC 1262 can be coupled to receive audio input from a microphone 1265, which in this embodiment can be implemented via a dual-array microphone (e.g., a digital microphone array) to provide high-quality audio input for voice-activated control of various operations within the system. It should also be noted that audio output can be provided from the amplifier / CODEC 1262 to a headphone jack 1264. While in Figure 12 These specific components are shown in the embodiments, but it should be understood that the scope of the invention is not limited to this aspect.

[0178] In certain embodiments, the digital audio codec and amplifier can drive a stereo headphone jack, a stereo microphone jack, an internal microphone array, and stereo speakers. In different implementations, the codec can be integrated into the audio DSP or coupled to the peripheral controller center (PCH) via an HD audio path. In some implementations, in addition to integrated stereo speakers, one or more subwoofers may be provided, and the speaker solution may support DTS audio.

[0179] In some embodiments, the processor 1210 may be powered by an external voltage regulator (VR) and multiple internal voltage regulators (referred to as fully integrated voltage regulators (FIVRs)) integrated within the processor die. Using multiple FIVRs in the processor allows components to be grouped into separate power planes, so that power is regulated by the FIVRs and supplied only to those components in the group. During power management, when the processor is placed in a specific low-power state, a given power plane of one FIVR may be de-energized or powered off, while another power plane of another FIVR remains active or fully powered.

[0180] In one embodiment, a sustaining power plane can be used during some deep sleep states to energize I / O pins for several I / O signals, such as the interface between the processor and the PCH, the interface with an external VR, and the interface with the EC1235. This sustaining power plane also powers an on-die voltage regulator that supports onboard SRAM or other cache memory that stores the processor context during sleep states. The sustaining power plane is also used to energize the processor's wake-up logic, which monitors and processes various wake-up source signals.

[0181] During power management, the power plane is kept powered on to support the components referenced above while other power planes are powered down or de-energized when the processor enters a specific deep sleep state. However, this can lead to unnecessary power consumption or dissipation when these components are not needed. To address this, embodiments may provide a connected standby sleep state to use a dedicated power plane to maintain the processor context. In one embodiment, the connected standby sleep state facilitates processor wake-up using the resources of the PCH, which itself may reside in the package along with the processor. In another embodiment, the connected standby sleep state facilitates maintaining processor architecture functionality in the PCH until the processor wakes up, enabling the shutdown of all unnecessary processor components previously powered on during deep sleep, including shutting down all clocks. In one embodiment, the PCH includes a timestamp counter (TSC) and connected standby logic for controlling the system during the connected standby state. An integrated voltage regulator for maintaining the power plane may also reside on the PCH.

[0182] In an embodiment, during connected standby, an integrated voltage regulator can serve as a dedicated power plane that remains powered on when the processor enters deep sleep and connected standby states to support a dedicated cache memory storing processor context (e.g., critical state variables). This critical state may include state variables associated with the architecture, microarchitecture, debug state, and / or similar state variables associated with the processor.

[0183] Wake-up source signals from the EC 1235 can be sent to the PCH instead of the processor during connected standby, allowing the PCH, rather than the processor, to manage wake-up processing. Additionally, the TSC is maintained in the PCH to help maintain processor architecture functionality. Although in Figure 12 These specific components are shown in the embodiments, but it should be understood that the scope of the invention is not limited to this aspect.

[0184] Power control in a processor can lead to enhanced power savings. For example, power can be dynamically allocated among cores, individual cores can change their frequency / voltage, and multiple deep low-power states can be provided to achieve very low power consumption. Additionally, dynamic control of a core or individual core segments can provide reduced power consumption by powering down components when they are not in use.

[0185] Some implementations can provide a specific power management IC (PMIC) to control platform power. Using this solution, when in a given standby state (e.g., when in Win8 connected standby), the system can see very low (e.g., less than 5%) battery degradation over an extended duration (e.g., 16 hours). In Win8 idle state, battery life exceeding, for example, 9 hours (e.g., at 150 nits) can be achieved. Regarding video playback, long battery life can be achieved; for example, full HD video playback can occur for at least 6 hours. One implementation's platform can have, for example, 35 watt-hours (Whr) of power capacity for a Win8 CS using an SSD and (e.g.) 40-44 Whr for a Win8 CS using an HDD with an RST cache configuration.

[0186] Certain implementations can support a nominal CPU thermal design power (TDP) of 15W, with configurable CPU TDPs up to approximately 25W TDP design points. Due to the thermal characteristics described above, the platform can include minimal ventilation. Additionally, the platform is pillow-friendly (as no hot air is blown towards the user). Different maximum temperature points can be achieved depending on the chassis material. In one implementation with a plastic chassis (which must at least have a plastic cover or base), the maximum operating temperature can be 52 degrees Celsius (°C). And for a metal chassis implementation, the maximum operating temperature can be 46°C.

[0187] In different implementations, security modules such as TPM can be integrated into the processor or can be discrete devices such as TPM 2.0 devices. Utilizing the integrated security module (also known as Platform Trust Technology (PTT)), the BIOS / firmware can be enabled to expose specific hardware features for specific security requirements, including security instructions, secure boot, etc. Anti-theft technology Identity protection technology Trusted Execution Technology (TXT) and Manageable engine technology and secure user interfaces such as secure keyboards and displays.

[0188] Although the invention has been described with respect to a limited number of embodiments, many modifications and variations will be apparent to those skilled in the art. The appended claims are intended to cover all such modifications and variations that fall within the true spirit and scope of the invention.

[0189] Design can go through various stages from creation to simulation to manufacturing. Data representing a design can be presented in a variety of ways. First, hardware can be represented using a hardware description language or another functional description language, as is useful in simulation. Additionally, circuit-level models with logic and / or transistor gates can be generated at certain stages of the design process. Furthermore, most designs reach a data level at some stage representing the physical placement of various devices in the hardware model. In the case of using conventional semiconductor manufacturing techniques, data representing the hardware model can be data specifying the presence or absence of various features on different mask layers of the mask used to produce the integrated circuit. In any representation of the design, data can be stored in any form of machine-readable medium. Memory such as a disk or magnetic or optical storage devices can be machine-readable media for storing information transmitted via light or radio waves modulated or otherwise generated to transmit such information. When an electrical carrier carrying instructions or designs is transmitted, a new copy is made to the extent that the electrical signal is copied, buffered, or retransmitted. Therefore, communication providers or network providers can at least temporarily store items (e.g., information encoded as a carrier wave embodying embodiments of the invention) on a tangible machine-readable medium.

[0190] As used herein, a module refers to any combination of hardware, software, and / or firmware. As an example, a module includes hardware associated with a non-transitory medium, such as a microcontroller, for storing code suitable for execution by the microcontroller. Therefore, in one embodiment, a reference to a module refers to hardware specifically configured to identify and / or execute code to be retained on a non-transitory medium. Furthermore, in another embodiment, the use of "module" refers to a non-transitory medium comprising code specifically suitable for execution by a microcontroller to perform predetermined operations. And as can be inferred, in yet another embodiment, the term "module" (in this example) may refer to a combination of a microcontroller and a non-transitory medium. Module boundaries, often depicted as separate, typically vary and potentially overlap. For example, a first module and a second module may share hardware, software, firmware, or a combination thereof, while potentially retaining some independent hardware, software, or firmware. In one embodiment, the use of the term "logic" includes hardware such as transistors, registers, or other hardware (e.g., programmable logic devices).

[0191] In one embodiment, the use of the phrase "for" or "configured to" refers to arranging, placing together, manufacturing, offering for sale, importing, and / or designing a device, hardware, logic, or element to perform a specified or defined task. In this example, if a device or element thereof is designed, coupled, and / or interconnected to perform the specified task, then a device or element thereof not in operation is still "configured to" perform the specified task. As a purely illustrative example, a logic gate may provide 0 or 1 during operation. However, the statement that a logic gate is "configured to" provide an enable signal to a clock does not imply that every potential logic gate may provide 1 or 0. Instead, the logic gate is coupled in a way that outputs 1 or 0 during operation to enable the clock. Again, note that the use of the term "configured to" does not require operation but focuses on the hidden state of a device, hardware, and / or element, in which the device, hardware, and / or element is designed to perform a specific task when the device, hardware, and / or element is in operation.

[0192] Furthermore, in one embodiment, the phrases "capable of / can be used with" and / or "operable for" refer to devices, logic, hardware, and / or elements designed in such a way that they can be used in a specified manner. Note that, as described above in one embodiment, "used for," "capable of," or "operable for" refers to a hidden state of devices, logic, hardware, and / or elements, wherein the devices, logic, hardware, and / or elements are not operational but are designed in such a way that they can be used in a particular manner.

[0193] As used herein, values ​​include any known representation of numbers, states, logical states, or binary logical states. Often, the use of logic levels, logic values, or logical values ​​is also referred to as the use of 1 and 0, which simply represent binary logical states. For example, 1 indicates a high logic level, and 0 indicates a low logic level. In one embodiment, a storage unit such as a transistor or flash memory cell is capable of holding a single logic value or multiple logic values. However, other representations of values ​​are already used in computer systems. For example, a decimal tens can also be represented as the binary value 1010 and the hexadecimal letter A. Therefore, values ​​include any representation of information that a computer system can store.

[0194] Furthermore, a state can be represented by a value or a portion of a value. As an example, a first value (e.g., logic one) can represent a default or initial state, while a second value (e.g., logic zero) can represent a non-default state. Additionally, in one embodiment, the terms reset and set refer to a default value or state and an updated value or state, respectively. For example, a default value potentially includes a high logic value (i.e., reset), while an updated value potentially includes a low logic value (i.e., set). Note that any combination of values ​​can be used to represent any number of states.

[0195] The embodiments of the methods, hardware, software, firmware, or code described above can be implemented via instructions or code stored on a machine-accessible, machine-readable, computer-accessible, or computer-readable medium executable by a processing element. Non-transitory machine-accessible / readable media include any mechanism that provides (i.e., stores and / or transmits) information in a machine-readable form (e.g., a computer or electronic system). For example, non-transitory machine-accessible media include random access memory (RAM), such as static RAM (SRAM) or dynamic RAM (DRAM); ROM; magnetic or optical storage media; flash memory devices; electrical storage devices; optical storage devices; acoustic storage devices; other forms of storage devices for retaining information received from transient (propagating) signals (e.g., carrier waves, infrared signals, digital signals); and so on, as distinct from non-transitory media from which information can be received.

[0196] Instructions for programming logic to execute embodiments of the present invention may be stored in the system's memory (e.g., DRAM, cache, flash memory, or other storage devices). Furthermore, the instructions may be distributed via a network or through other computer-readable media. Therefore, machine-readable media may include any mechanism for storing or transmitting information in a machine-readable (e.g., computer-readable) form, but are not limited to floppy disks, optical disks, CD-ROMs, magneto-optical disks, read-only memory (ROM), random access memory (RAM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), magnetic cards or optical cards, flash memory, or tangible machine-readable storage devices for transmitting information via the Internet via electrical, optical, acoustic, or other forms of propagation signals (e.g., carrier waves, infrared signals, digital signals, etc.). Therefore, computer-readable media include any type of tangible machine-readable medium suitable for storing or transmitting electronic instructions or information in a machine-readable (e.g., computer-readable) form.

[0197] The reference to "one embodiment" or "embodiment" in this specification means that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment of the invention. Therefore, the phrases "in one embodiment" or "in an embodiment" appearing throughout this specification do not necessarily refer to the same embodiment. Furthermore, particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0198] In the foregoing description, specific exemplary embodiments have been given in detail. However, it will be apparent that various modifications and changes can be made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims. Therefore, the description and drawings should be regarded as illustrative rather than restrictive. Furthermore, the foregoing use of embodiments and other exemplary language do not necessarily refer to the same embodiments or the same examples, but may refer to different and dissimilar embodiments, as well as potentially identical embodiments.

[0199] Systems, methods, and apparatus may include one or a combination of the following examples:

[0200] Example 1 is a method for operating a port of an upstream component connected to one or more downstream components across a PCIe-compliant link. The method includes: determining that the downstream port supports one or more Separate Reference Clock (SRIS) mode selection mechanisms with Independent Spread Spectrum Timing (SSC); determining a system clock configuration from the downstream port to a corresponding upstream port connected to the downstream port via a PCIe-compliant link; setting the SRIS mode in the downstream port; and transmitting data from the downstream port across the link using the determined system clock configuration.

[0201] Example 2 may include the subject of Example 1, wherein setting SRIS mode in the downstream port includes setting SRIS mode based at least in part on the determination of the system clock configuration.

[0202] Example 3 may include the subject of either Example 1 or 2, and may also include the transfer of SRIS mode across a PCIe compliant link to one or more upstream ports connected to the downstream port.

[0203] Example 4 may include the subject of Example 3, wherein one or more upstream ports include pseudo ports for retimers.

[0204] Example 5 may include the subject of any of Examples 1-4, wherein determining that a downstream port supports one or more SRIS mode selection mechanisms includes determining that the SRIS mode selection mechanism bit is set in the link-associated register.

[0205] Example 6 may include the subject of Example 5, wherein the link-associated registers include the link capability register.

[0206] Example 7 may include the subject of Example 6, wherein the bits set in the link capability register include 23 bits set to indicate the presence of SRIS mode selection capability.

[0207] Example 8 may include the subject of Example 5, wherein the link-associated registers include the link control register.

[0208] Example 9 may include the subject of Example 8, wherein the bits set in the link control register include 12 bits set to indicate SRIS mode selection.

[0209] Example 10 may include the subject of any one of 1-9, wherein determining the system clock configuration includes using an out-of-band management interface, which includes the system management bus.

[0210] Example 11 is a computer program product tangibly embodied on a non-transitory computer-readable medium, the computer program product comprising instructions that, when executed, cause logic embodied in a root port controller conforming to the Fast Peripheral Component Interconnect (PCIe) protocol to: determine that a downstream port supports one or more Separate Reference Clock (SRIS) mode selection mechanisms with Independent Spread Spectrum Timing (SSC); determine a system clock configuration from the downstream port to a corresponding upstream port connected to the downstream port via a PCIe-compliant link; set the SRIS mode in the downstream port; and transmit data across the link from the downstream port using the determined system clock configuration.

[0211] Example 12 may include the subject of Example 11, wherein setting SRIS mode in a downstream port includes setting SRIS mode based at least in part on the determination of the system clock configuration.

[0212] Example 13 may include the subject of any of Examples 11-12, which is an instruction for transmitting SRIS mode across a PCIe compliant link to one or more upstream ports connected to a downstream port.

[0213] Example 14 may include the subject of Example 13, wherein one or more upstream ports include pseudo ports of the retimer.

[0214] Example 15 may include the subject of any of Examples 11-14, wherein determining that a downstream port supports one or more SRIS mode selection mechanisms includes determining that the SRIS mode selection mechanism bit is set in the link-associated register.

[0215] Example 16 may include the subject of Example 15, wherein the link-associated registers include the link capability register.

[0216] Example 17 may include the subject of Example 16, wherein the bits set in the link capability register include 23 bits set to indicate the presence of SRIS mode selection capability.

[0217] Example 18 may include the subject of Examples 11-17, wherein the link-associated registers include the link control register.

[0218] Example 19 may include the subject of Example 18, wherein the bits set in the link control register include 12 bits set to indicate SRIS mode selection.

[0219] Example 20 may include the subject matter of Examples 11-19, wherein determining the system clock configuration includes using an out-of-band management interface, which includes a system management bus.

[0220] Example 21 is a computing system comprising: a root port controller conforming to the Fast Peripheral Component Interconnect (PCIe) protocol, the root port controller including a downstream port; the downstream port including at least partially hardware-implemented logic for: determining that the downstream port supports one or more Separate Reference Clock (SRIS) mode selection mechanisms with Independent Spread Spectrum Timing (SSC); determining a system clock configuration from the downstream port to a corresponding upstream port connected to the downstream port via a PCIe-compliant link; setting the SRIS mode in the downstream port; and transmitting data from the downstream port across the link using the determined system clock configuration.

[0221] Example 22 may include the subject of Example 21, wherein setting SRIS mode in a downstream port includes setting SRIS mode based at least in part on the determination of the system clock configuration.

[0222] Example 23 may include the subject of Examples 21-22, which are instructions for delivering SRIS mode to one or more upstream ports connected to downstream ports across a PCIe compliant link.

[0223] Example 24 may include the subject of Example 23, wherein one or more upstream ports include pseudo ports of the retimer.

[0224] Example 25 may include the subject of any of Examples 21-24, wherein determining that a downstream port supports one or more SRIS mode selection mechanisms includes determining that the SRIS mode selection mechanism bit is set in the link-associated register.

[0225] Example 26 may include the subject of Example 25, wherein the link-associated registers include the link capability register.

[0226] Example 27 may include the subject of Example 26, wherein the bits set in the link capability register include 23 bits set to indicate the presence of SRIS mode selection capability.

[0227] Example 28 may include the subject of any of Examples 21-27, wherein the link-associated registers include the link control register.

[0228] Example 29 may include the subject of Example 28, wherein the bits set in the link control register include 12 bits set to indicate SRIS mode selection.

[0229] Example 30 may include the subject of any of Examples 21-29, wherein determining the system clock configuration includes using an out-of-band management interface, which includes a system management bus.

Claims

1. A computing device, comprising: A port, the port being used to couple the device to another device via a link; as well as Control logic, the control logic being used for: Determine the timing architecture supported by the other device; as well as Based on the determined timing architecture, the timing architecture to be used on the link is set in the PCIe link control register of the Fast Peripheral Component Interconnect, wherein the device is used to send information to the other device via the link using the set timing architecture; The control logic is used to determine the timing architecture supported by the other device based on the PCIe link capability 2 register of the other device.

2. The computing device according to claim 1, wherein, The timing architecture includes a separate reference clock SRIS architecture with independent spread spectrum timing or a non-SRIS architecture.

3. The computing device according to claim 1, wherein, The control logic is used for: By setting the bits in the PCIe link control register to 1, the timing architecture is configured as a Separate Reference Clock (SRIS) architecture with independent spread spectrum timing; or By setting the bit in the PCIe link control register to 0, the timing architecture is set to a non-SRIS architecture.

4. The computing device according to claim 3, wherein, The control logic is used to set the timing architecture by setting bit 12 in the PCIe link control register.

5. The computing device according to claim 3, wherein, The control logic is used to set the timing architecture by setting another bit in the PCIe link control register.

6. The computing device according to any one of claims 1 to 5, wherein, The control logic is used to set the timing architecture using the training set.

7. The computing device according to any one of claims 1 to 5, wherein, The control logic is used to determine the timing architecture supported by the other device based on bits 9-22 in the PCIe link capability 2 register.

8. The computing device according to any one of claims 1 to 5, wherein, The control logic is further used to determine the data rate supported by the other device based on the PCIe link capability 2 register.

9. The computing device according to claim 8, wherein, The control logic is used to determine the data rate supported by the other device based on bits 9-15 in the PCIe link capability 2 register.

10. A calculation method, comprising: The timing architecture supported by the second device is determined by the first device; Based on the determined timing architecture, the timing architecture to be used on the link between the first device and the second device is set in the Fast Peripheral Component Interconnect (PCIe) link control register; as well as The information is transmitted from the first device to the second device via the link using the configured timing architecture; The timing architecture supported by the second device is determined based on the PCIe link capability 2 register of the second device.

11. The calculation method according to claim 10, wherein, The timing architecture includes a separate reference clock SRIS architecture with independent spread spectrum timing or a non-SRIS architecture.

12. The calculation method according to claim 10, wherein, Setting the timing architecture includes setting the timing architecture to a Separate Reference Clock (SRIS) architecture with independent spread spectrum timing by setting a bit in the PCIe link control register to 1.

13. The calculation method according to claim 12, wherein, The timing architecture is configured by setting bit 12 in the PCIe link control register.

14. The calculation method according to claim 12, wherein, The timing architecture is configured by setting another bit in the PCIe link control register.

15. The calculation method according to any one of claims 10 to 14, wherein, Setting the timing architecture includes setting the timing architecture to a non-SRIS architecture by setting the bit in the PCIe link control register to 0.

16. The calculation method according to claim 10, wherein, Use the training set to set up the timing architecture.

17. A computing system, comprising: A host device, the host device including a first port for supporting the link; as well as An endpoint device, the endpoint device including a second port for supporting the link, wherein the host device is coupled to the endpoint device via the link; The host device includes control logic, which is used for: Determine the timing architecture supported by the endpoint device; and Based on the determined timing architecture, the timing architecture to be used on the link is set in the PCIe link control register of the Fast Peripheral Component Interconnect, wherein the host device is used to send information to the endpoint device via the link using the set timing architecture; The control logic is used to determine the timing architecture supported by the endpoint device based on the PCIe link capability 2 register of the endpoint device.

18. The computing system according to claim 17, wherein, The timing architecture includes either a separate reference clock SRIS architecture with independent spread spectrum timing or a non-SRIS architecture.

19. The computing system according to claim 17, wherein, The control logic is used for: By setting the bits in the PCIe link control register to 1, the timing architecture is configured as a Separate Reference Clock (SRIS) architecture with independent spread spectrum timing; or By setting the bit in the PCIe link control register to 0, the timing architecture is set to a non-SRIS architecture.

20. The computing system according to any one of claims 17 to 19, wherein, The control logic is used to set the timing architecture by setting bit 12 in the PCIe link control register.

21. The computing system according to any one of claims 17 to 19, wherein, The control logic is used to set the timing architecture by setting another bit in the PCIe link control register.

22. The computing system according to any one of claims 17 to 19, wherein, The control logic is used to set the timing architecture using the training set.

23. A method for operating a downstream port of an upstream component, the upstream component being connected to the downstream component via a link, the method comprising: The timing architecture supported by the downstream component is determined based on the PCIe link capability 2 register of the downstream component. Based on the determined timing architecture, the system clock configuration from the downstream port to the upstream port of the downstream component is determined; as well as Configure the transmission of data across the link from the downstream port to the upstream port using the determined system clock; Determining the system clock configuration also includes using an out-of-band management interface, which includes the system management bus.

24. The method of claim 23, further comprising setting a Separate Reference Clock (SRIS) mode with independent spread spectrum timing in the downstream port.

25. A computing system, comprising: Upstream component, the upstream component including downstream port; as well as A downstream component coupled to the upstream component via a link, the downstream component including an upstream port; The downstream port includes logic for the following operations: The timing architecture supported by the downstream component is determined based on the PCIe link capability 2 register of the downstream component. Based on the determined timing architecture, the system clock configuration from the downstream port to the upstream port is determined; and Configure the transmission of data across the link from the downstream port to the upstream port using the determined system clock; Determining the system clock configuration also includes using an out-of-band management interface, which includes the system management bus.

26. The computing system according to claim 25, wherein, The logic is further used to set a separate reference clock (SRIS) mode with independent spread spectrum timing in the downstream port.

27. A computing device comprising a unit for performing the steps of the method according to claim 23 or 24.

28. One or more non-transitory computer-readable storage media, including instructions that, when executed by a processor, cause the processor to perform the method according to claim 23 or 24.

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