Memory control circuit and control method of erase operation of flash memory

Abstract

The present application discloses a memory control circuit and a control method of a flash memory erase operation. The memory control circuit is used in an integrated circuit. The integrated circuit includes a processor, an intellectual property core circuit and a flash memory. The memory control circuit includes a memory controller to start an erase operation on the flash memory according to an erase instruction of the processor to generate an erase signal, and a timing circuit to start a counting operation according to the erase signal. The memory controller and the timing circuit suspend the erase operation and the counting operation respectively according to an interrupt signal generated by the intellectual property core circuit. The memory controller and the timing circuit resume the erase operation and the counting operation respectively according to the interrupt signal being cleared. The timing circuit outputs a completion signal to the memory controller to indicate that the erase operation has been completed according to the timing circuit having counted to a predetermined value.

Description

Technical Field

[0001] This invention relates to integrated circuits, and more particularly to a memory control circuit and a method for controlling the erase operation of a flash memory. Background Technology

[0002] Traditionally, when flash memory receives an erase request, the erase operation takes a considerable amount of time, and during this period, the flash memory cannot receive other instructions. Therefore, processors in traditional integrated circuits must wait for the erase operation to complete before reading data from the flash memory. Even if the processor receives an interrupt signal from other circuits during the erase operation, it will delay the interrupt signal until the erase operation is complete to ensure the data in the flash memory is correctly erased. However, an excessively long erase operation time can affect the processor's response speed to interrupt signals, thereby reducing the performance of the integrated circuit.

[0003] Therefore, a memory control circuit and a control method for the erase operation of flash memory are needed to solve the above problems. Summary of the Invention

[0004] This invention provides a memory control circuit for an integrated circuit. The integrated circuit includes a processor, an intellectual property core circuit, and a flash memory. The memory control circuit includes: a memory controller for initiating an erase operation on a target data block in the flash memory based on an erase instruction from the processor, and generating an erase signal; and a timing circuit for initiating a counting operation in response to the erase signal. In response to an interrupt signal generated by the intellectual property core circuit, the memory controller and the timing circuit respectively pause the erase operation and the counting operation. In response to the interrupt signal of the intellectual property core circuit being cleared, the memory controller and the timing circuit respectively resume the erase operation and the counting operation. In response to the timing circuit counting to a predetermined value, the timing circuit outputs a completion signal to the memory controller to indicate that the erase operation has been completed.

[0005] In some embodiments, the intellectual property core circuit generates the interrupt signal in response to an interrupt event, and when the processor finishes processing the interrupt event, the processor sends an interrupt clear signal to the intellectual property core circuit to clear the interrupt signal.

[0006] In some embodiments, when the erase operation is erasing a specific page in the target data block and the memory controller interrupts the erase operation in response to the interrupt signal, the memory controller sets the page code of the specific page as the interrupt point, wherein when the interrupt signal is cleared, the memory controller resumes the erase operation from the interrupt point.

[0007] In some embodiments, the timing circuit includes: an inverter for converting the interrupt signal into an inverted interrupt signal; an AND gate for performing an AND operation on the inverted interrupt signal and the erase signal to generate an enable signal; a counter for counting according to the enable signal to generate a count value; and a comparator for comparing the count value with a predetermined value and generating the completion signal based on the comparison result.

[0008] In some embodiments, the completion signal generated by the comparator is in a high logic state when the count value is greater than or equal to the predetermined value. When the count value is less than the predetermined value, the completion signal generated by the comparator is in a low logic state. When the completion signal is in a high logic state, the counter resets the count value.

[0009] The present invention further provides a control method for erasing a flash memory, used in an integrated circuit, wherein the integrated circuit includes a processor, an intellectual property core circuit, a memory control circuit, and a flash memory, and the memory control circuit includes a memory controller and a timing circuit. The method includes: using the memory controller to initiate an erasure operation on a target data block in the flash memory according to an erasure instruction from the processor, and generating an erasure signal; using the timing circuit to start a counting operation in response to the erasure signal; in response to an interrupt signal generated by the intellectual property core circuit, using the memory controller and the timing circuit to pause the erasure operation and the counting operation respectively; in response to the interrupt signal of the intellectual property core circuit being cleared, using the memory controller and the timing circuit to resume the erasure operation and the counting operation respectively; and in response to the timing circuit counting to a predetermined value, using the timing circuit to output a completion signal to the memory controller to indicate that the erasure operation has been completed.

[0010] This invention provides a memory control circuit and a control method for erasing flash memory. When the memory controller resumes the erasing operation after an interrupt event is cleared, it does not need to re-execute a complete new erasing operation. Instead, it can continue the erasing operation from the interrupt point of the original erasing operation, thereby shortening the total erasing time of the flash memory and improving the operating performance of the integrated circuit. Attached Figure Description

[0011] Figure 1 This is a block diagram showing an integrated circuit according to an embodiment of the present invention.

[0012] Figure 2 According to the present invention Figure 1 A block diagram of the timing circuit in the embodiment.

[0013] Figure 3 This is a schematic diagram illustrating the period and interruption events of an erasure operation according to an embodiment of the present invention.

[0014] Figure 4 This is a control method for erasing operations of a flash memory according to an embodiment of the present invention.

[0015] Figure Labels

[0016] 100: Integrated Circuits

[0017] 110: Processor

[0018] 111: Host Command

[0019] 112: Interrupt Clear Signal

[0020] 120: Intellectual Property Core Circuit

[0021] 121: Interrupt signal

[0022] 130: Memory control circuit

[0023] 140: Memory controller

[0024] 141: Busy Signal

[0025] 142: Erase Signal

[0026] 145: Timing Circuit

[0027] 146: Completion signal

[0028] 150: Flash memory

[0029] 1451: Counter

[0030] 1452: Comparator

[0031] 1453: with the door

[0032] 1454: Inverter

[0033] 121': Inverting interrupt signal

[0034] EN: Enable signal

[0035] CNT: Count value

[0036] t0, t1, t2, t3: Time

[0037] T, T1, T2: Time length

[0038] S410-S470: Steps Detailed Implementation

[0039] The following description is a preferred embodiment of the invention and is intended to depict the basic spirit of the invention, but is not intended to limit the invention. The actual invention must be understood within the scope of the claims of this application.

[0040] It must be understood that the words "comprising" and "including" used in this specification are used to indicate the presence of specific technical features, values, method steps, work processes, elements and / or components, but do not preclude the addition of more technical features, values, method steps, work processes, elements, components, or any combination thereof.

[0041] Figure 1 is a block diagram showing an integrated circuit according to an embodiment of the present invention.

[0042] In one embodiment, the integrated circuit 100 includes a processor 110, one or more intellectual property core circuits 120, a memory control circuit 130, and a flash memory 150. The processor 110 may be, for example, a central processing unit (CPU), a general-purpose processor, or a microprocessor, but the invention is not limited thereto. The processor 110 may, for example, send host instructions 111 (which may be read instructions, write instructions, or erase instructions) to the memory control circuit 130 to access or erase data in one or more data blocks of the flash memory 150.

[0043] In the field of electronic circuit design, the intellectual property core circuit 120 can be a reusable unit for logic circuit or integrated circuit layout design. When an interrupt event occurs in the intellectual property core circuit 120, it sends an interrupt signal 121 to the processor 110. This interrupt signal 121 remains in the same logic state (e.g., a high logic state) until the processor 110 sends an interrupt clear signal 112 to the intellectual property core circuit 120, thereby notifying the intellectual property core circuit 120 that the interrupt event has been processed. At this time, the intellectual property core circuit 120 changes the logic state of the interrupt signal 121 (e.g., changes it to a low logic state) to indicate that there are no more interrupt events to process.

[0044] The memory control circuit 130 includes a memory controller 140 and a timing circuit 145. The memory controller 140 controls read operations, write operations, erase operations, etc., of the flash memory 150. When an interrupt event occurs in the intellectual property core circuit 120, the intellectual property core circuit 120 sends an interrupt signal 121 to the processor 110, and simultaneously sends an interrupt signal 121 to the timing circuit 145 and the memory controller 140. The timing circuit 145 starts counting (e.g., counting the number of clock cycles of the system clock signal of the integrated circuit 100) based on the erase signal 142 from the memory controller 140, and pauses counting based on the interrupt signal 121 from the intellectual property core circuit 120. When the count value of the timing circuit 145 reaches a predetermined value, the timing circuit 145 stops counting, clears the count value, and sends a finish signal 146 to the memory controller 140. The memory controller 140 interrupts the current erase operation based on the interrupt signal 121 from the intellectual property core circuit 120.

[0045] It is important to note that in some cases, the memory controller 140 may erase one or more data blocks in the flash memory 150, such as when receiving a data deletion instruction from the processor 110, or when performing garbage collection on the flash memory 150 to obtain spare blocks. For example, if the memory controller 140 erases a single data block in the flash memory 150, the erasure operation typically takes a fixed amount of time, such as 50 milliseconds (not limited).

[0046] During the normal execution of the erase operation by the memory controller 140, the memory controller 140 sets the BUSY signal 141 to a high logic state, thereby causing the processor 110 to suspend sending host instructions to the memory controller 140. When the processor 110 receives an interrupt signal 121 from the intellectual property core circuit 120 during the execution of the erase operation, the processor 110 will prioritize executing the interrupt handler to handle the interrupt event from the intellectual property core circuit 120. At the same time, the memory controller 140 and the timing circuit 145 also receive the interrupt signal 121 from the intellectual property core circuit 120.

[0047] When interrupt signal 121 is in a high logic state, memory controller 140 interrupts the erase operation and sets busy signal 141 to a low logic state, so that processor 110 can prioritize sending host instructions required by the interrupt handler to memory controller 140 to access data in flash memory 150. At this time, due to interrupt signal 121 being in a high logic state, timing circuit 145 pauses its counting operation.

[0048] After the processor 110 completes the interrupt handler, it issues an interrupt clear signal 112 to clear the interrupt signal 121 of the intellectual property core circuit 120, that is, to notify the intellectual property core circuit 120 to set the interrupt signal 121 to a low logic state. In response to the interrupt signal 121 being in a low logic state, the timing circuit 145 resumes counting from the previously paused count value, and the memory controller 140 resumes the erase operation.

[0049] For example, the memory controller 140 may sequentially erase pages in a target data block. When the memory controller 140 interrupts the erasure operation in response to an interrupt signal 121, the erasure operation is, for example, erasing a specific page in the target data block, and the memory controller 140 stops erasing that specific page and sets the page number of that specific page as the interrupt point. When the interrupt signal 121 is cleared, the memory controller 140 can then continue the erasure operation on that specific page from the interrupt point.

[0050] It should be noted that during the same erasure operation, the intellectual property core circuit 120 may send one or more interrupt signals 121 to the processor 110, memory controller 140, and timing circuit 145. Whenever the processor 110, memory controller 140, and timing circuit 145 receive an interrupt signal 121 from the intellectual property core circuit 120, the processor 110, memory controller 140, and timing circuit 145 may respectively execute the interrupt handler, interrupt erasure operation, and pause counting in the manner described above.

[0051] For the timing circuit 145, regardless of how many times its counting operation is interrupted, the timing circuit 145 will count until the count value reaches a predetermined value before stopping the counting and sending a completion signal 146 to the memory controller 140, and then resetting the count value to the initial value (e.g., 0). Therefore, the number of clock cycles of the system clock signal represented by the predetermined value can be converted into the corresponding time length, which is the fixed time spent on the erase operation.

[0052] Figure 2 According to the present invention Figure 1 A block diagram of the timing circuit in the embodiment.

[0053] like Figure 2 As shown, the timing circuit 145 includes a counter 1451, a comparator 1452, an AND gate 1453, and an inverter 1454. The interrupt signal 121 is inverted by the inverter 1454 to obtain an inverted interrupt signal 121', which is input to one input of the AND gate 1453. The erase signal 142 output by the memory controller 140 is input to the other input of the AND gate 1453. The inverted interrupt signal 121' and the erase signal 142 are passed through the AND gate 1453 to generate an enable signal EN, which controls the counting operation of the counter 1451. For example, when the enable signal EN is high, the counter 1451 continues counting. When the enable signal EN is low, the counter 1451 interrupts the counting operation. The counter 1451 then inputs the current count value CNT to one input of the comparator 1452. Comparator 1452 compares the count value CNT with a predetermined value, which may be from a temporary register (not shown), for example, the predetermined value may be loaded into the temporary register by processor 110 when the power of integrated circuit 100 is turned on.

[0054] When interrupt signal 121 is low, it indicates that no interrupt event has occurred in the intellectual property core circuit 120, and the inverted interrupt signal 121' is high. When erase signal 142 is low and inverted interrupt signal 121' is high, it indicates that the memory controller 140 is not currently performing an erase operation, and the enable signal EN generated by AND gate 1453 will be low, so counter 1451 will stop counting. When both erase signal 142 and inverted interrupt signal 121' are high, the enable signal EN output by AND gate 1453 will be high. At this time, counter 1451 will continue counting and output the count value CNT to comparator 1452.

[0055] When interrupt signal 121 is in a high logic state, it indicates that an interrupt event has occurred in intellectual property core circuit 120, and the inverted interrupt signal 121' is in a low logic state. At this time, regardless of the logic state of erase signal 142, the enable signal EN output by AND gate 1453 is in a low logic state, indicating that counter 1451 will interrupt the counting operation.

[0056] When the count value CNT of counter 1451 is less than a predetermined value, the completion signal 146 output by comparator 1452 is in a low logic state, indicating that the accumulated execution time of the current erase operation has not yet reached the predetermined time, and counter 1451 will continue to count while the enable signal EN is in a high logic state. When the count value CNT is greater than or equal to the predetermined value, the completion signal 146 generated by comparator 1452 is in a high logic state, indicating that the accumulated execution time of the current erase operation has reached the predetermined time (e.g., 50ms, not limited), and the completion signal 146 generated by comparator 1452 is output to memory controller 140. At this time, due to the high logic state of completion signal 146, memory controller 140 can continue to execute the next erase operation.

[0057] Figure 3 This is a schematic diagram illustrating the duration and interruption events of an erasure operation according to an embodiment of the present invention. Please also refer to... Figures 1-3 .

[0058] exist Figure 3 In this embodiment, assuming that the memory controller 140 requires a time period T to perform an erase operation, at time t0, the memory controller 140 begins the erase operation and sends an erase signal 142 to the timing circuit 145, so the counter 1451 in the timing circuit 145 starts counting. After a time period T1 (i.e., at time t1), an interrupt event occurs in the intellectual property core circuit 120, and the interrupt signal 121 issued by the intellectual property core circuit 120 is in a high logic state. Therefore, the enable signal EN generated by the AND gate 1453 of the timing circuit 145 is in a low logic state, so the counter 1451 interrupts the counting operation.

[0059] At time t2, after the processor 110 finishes processing the interrupt event of the intellectual property core circuit 120, it sends an interrupt clear signal 112 to the intellectual property core circuit 120 to clear the interrupt signal. Therefore, the interrupt signal 121 sent by the intellectual property core circuit 120 will be in a low logic state at this time. Consequently, the enable signal EN generated by the AND gate 1453 of the timing circuit 145 is in a high logic state, and the erase signal 142 is also in a high logic state. Therefore, the counter 1451 will resume the counting operation at time t2. That is, the elapsed time of the erase operation performed by the memory controller 140 will continue counting from the time length T1.

[0060] When the elapsed time of the erase operation accumulates to time length T after another time length T2 (e.g., time t3), it indicates that the count value CNT of counter 1451 has reached the predetermined value, so the completion signal 146 generated by comparator 1452 will be in a high logic state. Therefore, in response to the high logic state of completion signal 146, counter 1451 resets the count value CNT. In summary, the erase operation time in this invention is a total accumulation system, and when the memory controller 140 performs a second erase operation during the erase operation, the time length T2 of the second erase operation is the time length T of the erase operation minus the time length T1 of the first erase operation, that is, T2 = T - T1. Therefore, when the memory controller 140 resumes the erase operation after the interrupt event is cleared, it is not necessary to re-execute the complete new erase operation, but can continue the erase operation from the interrupt point of the erase operation, thus shortening the total erase time of flash memory 150 and improving the operating performance of integrated circuit 100.

[0061] It should be noted that during the same erase operation, the present invention does not limit the number of times the counting operation is suspended by the interrupt signal. As long as the memory controller 140 is in the state of performing the erase operation, the memory control circuit 130 will monitor whether an interrupt signal occurs in the integrated circuit 100 at any time, and can stop the counting operation of the flash memory 150 and the interrupt counter 1451 during the erase operation at any time.

[0062] In some embodiments, the second erase operation during the erase operation performed by the memory controller 140 can be achieved in two ways, for example: (1) by issuing an erase instruction to the flash memory 150 using the processor 110; or (2) by automatically issuing an erase instruction to the flash memory 150 by the memory controller 140 after the interrupt signal is cleared. The first method provides a high degree of operational flexibility. The second method allows the erase instruction to be executed automatically by hardware circuitry, avoiding the problem of incomplete erasure of the flash memory 150 due to software operational errors.

[0063] Figure 4 This is a control method for erasing flash memory according to an embodiment of the present invention. Please also refer to... Figure 1 , Figure 2 and Figure 4 .

[0064] In step S410, processor 110 sends an erase command to memory controller 140.

[0065] In step S420, the memory controller 140 begins an erase operation on a data block of the flash memory 150, and the timing circuit 145 begins a counting operation. For example, when the memory controller 140 begins the erase operation, it also simultaneously sends an erase signal 142 (e.g., a high logic state) to the counter 1451 in the timing circuit 145. In response to the erase signal 142, the counter 1451 begins a counting operation, for example, counting the number of system clock cycles that have elapsed.

[0066] In step S430, it is determined whether the intellectual property core circuit 120 generates an interrupt signal. If the intellectual property core circuit 120 generates an interrupt signal, step S440 is executed. If the intellectual property core circuit 120 does not generate an interrupt signal, step S460 is executed. For example, when an interrupt event occurs in the intellectual property core circuit 120, the intellectual property core circuit 120 sends an interrupt signal 121 to the processor 110, and the interrupt signal 121 maintains the same logic state (e.g., a high logic state) until the processor 110 sends an interrupt clear signal 112 to the intellectual property core circuit 120 to notify the intellectual property core circuit 120 that the interrupt event has been processed. At this time, the intellectual property core circuit 120 changes the logic state of the interrupt signal 121 (e.g., changes it to a low logic state) to indicate that there is no more interrupt event to process.

[0067] In step S440, the memory controller 140 and the timing circuit 145 respectively suspend the erase operation and the counting operation, and the processor 110 processes the interrupt event corresponding to the interrupt signal. For example, when the interrupt signal 121 is in a high logic state, Figure 2 The enable signal generated by AND gate 1453 will be in a low logic state, so the counter in timing circuit 145 will stop counting.

[0068] In step S450, in response to the clearing of the interrupt signal, the memory controller 140 and the timing circuit 145 respectively resume the erase operation and the counting operation. For example, after the processor 110 completes the interrupt handling routine, the processor 110 issues an interrupt clear signal 112 to clear the interrupt signal 121 of the intellectual property core circuit 120, that is, to notify the intellectual property core circuit 120 to set the interrupt signal 121 to a low logic state. In response to the interrupt signal 121 being in a low logic state, the timing circuit 145 continues counting from the previously interrupted count value, and the memory controller 140 resumes the erase operation.

[0069] In step S460, it is determined whether the timing circuit 145 has counted to a predetermined value. If the timing circuit 145 has counted to the predetermined value, then step S470 is executed. If the timing circuit 145 has not counted to the predetermined value, then the process returns to step S430. For example, the comparator 1452 in the timing circuit 145 compares the count value CNT of the counter 1451 with the predetermined value. When the count value CNT of the counter 1451 is less than the predetermined value, the completion signal 146 output by the comparator 1452 is in a low logic state, indicating that the accumulated execution time of the current erasure operation has not yet reached the predetermined time, and the counter 1451 will continue to count when the enable signal EN is in a high logic state.

[0070] In step S470, the erasure operation is completed. For example, when the count value CNT is greater than or equal to a predetermined value, the completion signal 146 generated by the comparator 1452 is in a high logic state, indicating that the accumulated execution time of the current erasure operation has reached the predetermined time (e.g., 50ms, not limited). At this time, because the completion signal 146 is in a high logic state, the memory controller 140 can continue to execute the next erasure operation.

[0071] In summary, the present invention provides a memory control circuit and a control method for erasing flash memory. When the memory controller resumes the erasing operation after an interrupt event is cleared, it does not need to re-execute a complete new erasing operation. Instead, it can continue the erasing operation from the interrupt point of the original erasing operation, thereby shortening the total erasing time of the flash memory and improving the operating performance of the integrated circuit.

[0072] The use of terms such as "first," "second," and "third" in the claims is to modify the elements in the claims, and is not to indicate a priority order, a prior relationship, or that one element precedes another, or the chronological order of the execution of method steps. They are only used to distinguish elements with the same name.

[0073] While the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the scope of the invention. Any person skilled in the art can make some modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention must be defined by reference to the appended claims.

Claims

1. A memory control circuit, characterized in that, For use in an integrated circuit, wherein the integrated circuit includes a processor, an intellectual property core circuit, and a flash memory, the memory control circuit including: A memory controller is configured to initiate an erase operation on a target data block in the flash memory based on an erase instruction from the processor, and generate an erase signal; and A timing circuit is provided to respond to the erase signal to begin the counting operation; In response to an interrupt signal generated by the intellectual property core circuit, the memory controller and the timing circuit respectively suspend the erase operation and the counting operation. In this context, in response to the interrupt signal of the intellectual property core circuit being cleared, the memory controller and the timing circuit respectively resume the erase operation and the counting operation; In this case, as the timing circuit has counted to a predetermined value, the timing circuit outputs a completion signal to the memory controller to indicate that the erasure operation has been completed.

2. The memory control circuit as described in claim 1, characterized in that, The intellectual property core circuit generates the interrupt signal in response to an interrupt event, and when the processor finishes processing the interrupt event, the processor sends an interrupt clear signal to the intellectual property core circuit to clear the interrupt signal.

3. The memory control circuit as described in claim 1, characterized in that, When the erase operation is erasing a specific page in the target data block and the memory controller interrupts the erase operation in response to the interrupt signal, the memory controller sets the page code of the specific page as the interrupt point; When the interrupt signal is cleared, the memory controller resumes the erase operation from the point of interruption.

4. The memory control circuit as described in claim 1, characterized in that, The timing circuit includes: An inverter is used to convert the interrupt signal into an inverted interrupt signal; An AND gate is used to perform an AND operation on the inverted interrupt signal and the erase signal to generate an enable signal; A counter for counting according to the enable signal to generate a count value; and A comparator is used to compare the count value with the predetermined value and generate the completion signal based on the comparison result.

5. The memory control circuit as described in claim 4, characterized in that, The completion signal generated by the comparator is in a high logic state when the count value is greater than or equal to the predetermined value. Since the count value is less than the predetermined value, the completion signal generated by the comparator is in a low logic state; as well as When the completion signal is in a high logic state, the counter resets the count value.

6. A method for controlling the erase operation of a flash memory, characterized in that, For an integrated circuit, wherein the integrated circuit includes a processor, an intellectual property core circuit, a memory control circuit, and a flash memory, and the memory control circuit includes a memory controller and a timing circuit, the method includes: The memory controller initiates an erase operation on a target data block in the flash memory based on an erase instruction from the processor, and generates an erase signal. The timing circuit is used in response to the erase signal to begin the counting operation; In response to an interrupt signal generated by the intellectual property core circuit, the erase operation and the counting operation are respectively paused using the memory controller and the timing circuit. In response to the interrupt signal being cleared from the intellectual property core circuit, the erase operation and the counting operation are respectively restored using the memory controller and the timing circuit; and In response to the timing circuit counting to a predetermined value, the timing circuit outputs a completion signal to the memory controller to indicate that the erasure operation has been completed.

7. The control method for erasure operation of flash memory as described in claim 6, characterized in that, The intellectual property core circuit generates the interrupt signal in response to an interrupt event, and the method further includes: when the processor finishes processing the interrupt event, transmitting an interrupt clear signal to the intellectual property core circuit to clear the interrupt signal.

8. The control method for erasure operation of flash memory as described in claim 6, characterized in that, Including: When the erase operation is erasing a specific page in the target data block and the memory controller interrupts the erase operation in response to the interrupt signal, the memory controller sets the page code of the specific page as the interrupt point. as well as When the interrupt signal is cleared, the memory controller resumes the erase operation from the point of interruption.

9. The control method for erasing operations of a flash memory as described in claim 6, characterized in that, Including: Convert the interrupt signal into an inverted interrupt signal; The inverted interrupt signal and the erase signal are combined to generate an enable signal. Counting is performed based on the enable signal to generate a count value; and The count value is compared with the predetermined value, and a completion signal is generated based on the comparison result.

10. The control method for erasure operation of flash memory as described in claim 9, characterized in that, Including: The completion signal is generated in a high logic state when the count value is greater than or equal to the predetermined value. In response to the count value being less than the predetermined value, a completion signal in a low logic state is generated; and The count value is reset when the completion signal is in a high logic state.

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