A SiC MOSFET device and its fabrication method

Abstract

This invention relates to a SiC MOSFET device and its fabrication method. The fabrication method includes: implanting ions at both ends of an N-type epitaxial layer 2 to form a P-well implantation region; forming an N-element implantation region and a P-element implantation region within the P-well implantation region; forming a B-element implantation region and an Al-element implantation region within the P-well implantation region; forming a gate oxide layer and a polysilicon layer (9) to form a gate; photolithographically forming a source ohmic contact region, and implanting C and Ge elements within the source ohmic contact region to form a surface modulation layer; fabricating a source electrode on the surface modulation layer; and fabricating a drain electrode on the back side of the N-type substrate. This invention can reduce the contact resistance of the N-type ohmic contact, reduce the contact resistance of the P-type ohmic contact, and reduce the sheet resistance of the implantation region.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device technology, specifically relating to a SiC MOSFET device and its fabrication method. Background Technology

[0002] Silicon carbide (SiC) has become one of the most advantageous semiconductor materials for manufacturing high-temperature, high-power electronic devices due to its excellent physicochemical and electrical properties, and it also has a power device quality factor that is much greater than that of Si material. The development of SiC MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) power devices began in the 1990s. It has a series of advantages such as high input impedance, fast switching speed, high operating frequency, and resistance to high temperature and high pressure, and has been widely used in switching power supplies, high-frequency heating, automotive electronics, and power amplifiers.

[0003] The ohmic contact problem of P-type doped SiC has not yet been well solved. In SiC MOSFET devices, this is mainly manifested in the following ways: 1. The source ohmic contact includes both N-type and P-type SiC ohmic contacts. In actual device fabrication, the formation of N-type ohmic contacts is prioritized, leading to the use of a Ni metal system. However, the ohmic contact resistance formed between the Ni metal system and P-type SiC is not small enough and the consistency is not high enough; 2. The sheet resistance of the implanted region is relatively large, resulting in a large resistance in the current transmission path; 3. The performance of the parasitic diode formed by the P-type ohmic contact and the N-type epitaxial layer also depends on the characteristics of the P-type ohmic contact, which affects the freewheeling capability of this diode.

[0004] Therefore, how to solve the ohmic contact problem of P-type doped SiC has become an urgent issue. Summary of the Invention

[0005] To address the aforementioned problems in the prior art, this invention provides a SiC MOSFET device and its fabrication method. The technical problem to be solved by this invention is achieved through the following technical solution:

[0006] One embodiment of the present invention provides a method for fabricating a SiC MOSFET device, the method comprising:

[0007] Select an N-type substrate layer;

[0008] An N-type epitaxial layer is formed on the N-type substrate layer;

[0009] Ions are implanted at both ends of the N-type epitaxial layer to form P-well implantation regions;

[0010] N element is injected into the P-well injection region to form an N element injection region;

[0011] P element is injected into the N element injection region to form a P element injection region, which is located on the remaining N element injection region;

[0012] B element is injected into the P-well injection region to form a B element injection region. The N element injection region and the P element injection region are located between the two B element injection regions, and the B element injection region is injected into the N-type epitaxial layer.

[0013] Al element is injected into the B element injection region to form an Al element injection region, which is located on the remaining B element injection region;

[0014] A gate oxide layer is formed on a portion of the P-element implantation region, the P-well implantation region, and the N-type epitaxial layer;

[0015] A polysilicon layer is fabricated on the gate oxide layer to form the gate;

[0016] Photolithography is used to form a source ohmic contact region, and C and Ge elements are implanted in the source ohmic contact region to form a surface modulation layer, which is located on the remaining Al element implantation region;

[0017] The source electrode is fabricated on the surface modulation layer;

[0018] A drain electrode is fabricated on the back side of the N-type substrate.

[0019] In one embodiment of the present invention, both the N-type substrate layer and the N-type epitaxial layer are made of 4H-SiC.

[0020] In one embodiment of the present invention, ions are implanted at both ends of the N-type epitaxial layer to form P-well implantation regions, including:

[0021] Al ions are implanted at both ends of the N-type epitaxial layer using an ion implantation method to form a P-well implantation region.

[0022] In one embodiment of the present invention, N element is injected into the P-well injection region to form an N element injection region, including:

[0023] A self-aligned process is used to implant nitrogen into the P-well implantation region to form a nitrogen-implanted region, wherein the implantation energy is 100–200 keV and the implantation dose is 1e¹⁵–3e¹⁵ cm⁻¹. -2 .

[0024] In one embodiment of the present invention, P element is injected into the N element injection region to form a P element injection region, including...

[0025] A self-aligned process is used to inject P element into the N element injection region to form a P element injection region, wherein the injection energy is 50–100 keV and the injection dose is 5e¹⁴–8e¹⁴ cm⁻¹. -2 .

[0026] In one embodiment of the present invention, B element is injected into the P-well injection region to form a B element injection region, including:

[0027] A P+ implantation region is formed by photolithography. A self-aligned process is then used to implant boron (B) into this P+ implantation region to form a boron implantation region. The implantation energy is 300–500 keV, and the implantation dose is 1e15–3e15 cm⁻¹. -2 .

[0028] In one embodiment of the present invention, injecting Al element into the B element injection region to form an Al element injection region includes:

[0029] Al element was injected into the B element injection region using a self-aligned process to form an Al element injection region, wherein the injection energy was 50–100 keV and the injection dose was 5e¹⁴–8e¹⁴ cm⁻¹. -2 .

[0030] In one embodiment of the present invention, C and Ge elements are implanted in the source ohmic contact region to form a surface modulation layer, comprising:

[0031] A self-aligned process is used to implant C and Ge elements into the source ohmic contact region to form a surface modulation layer. The implantation energy is 50–100 keV, and the implantation dose is 1e14–3e14 cm⁻¹. -2 .

[0032] In one embodiment of the present invention, a source electrode is fabricated on the surface modulation layer, comprising:

[0033] Source ohmic contact metal Ni is deposited on the surface modulation layer, followed by annealing to form the source.

[0034] One embodiment of the present invention provides a SiC MOSFET device, fabricated using the SiC MOSFET device fabrication method described in any of the above embodiments, wherein the SiC MOSFET device comprises:

[0035] N-type substrate layer;

[0036] An N-type epitaxial layer is located on the N-type substrate layer;

[0037] Two P-well injection regions are located at both ends of the N-type epitaxial layer, respectively;

[0038] Two N-element injection regions are located within the P-well injection region, respectively;

[0039] Two P-element injection regions are located within the N-element injection regions, and the P-element injection regions are located on the remaining N-element injection regions;

[0040] Two B-element injection regions are located within the P-well injection region, and the N-element injection region and the P-element injection region are located between the two B-element injection regions, with the bottom of the B-element injection region located within the N-type epitaxial layer.

[0041] Two Al element injection regions are located on the remaining B element injection regions, respectively;

[0042] A gate oxide layer is located on a portion of the P-element implantation region, the P-well implantation region, and the N-type epitaxial layer;

[0043] A polycrystalline silicon layer is located on the gate oxide layer;

[0044] Two surface modulation layers are located on the remaining Al element injection regions, respectively;

[0045] Two sources are located on the surface modulation layer, respectively;

[0046] The drain is located on the back side of the N-type substrate.

[0047] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0048] 1. The N+ injection region of the present invention uses a mixture of nitrogen (N) and phosphorus (P) elements for injection to form a surface P element injection region, so as to reduce the contact resistance of the N-type ohmic contact; the bottom N element injection region is formed to reduce the sheet resistance of the injection region.

[0049] 2. The P+ injection region of the present invention is formed by a mixture of aluminum (Al) and boron (B) elements to form a surface Al element injection region, so as to reduce the contact resistance of the P-type ohmic contact; and a bottom B element injection region is formed to reduce the sheet resistance of the injection region.

[0050] 3. The present invention introduces a C / Ge surface modulation layer in the source contact hole through ion implantation, which can solve the requirement of Ni metal forming excellent ohmic contact with both N-type and P-type SiC.

[0051] 4. The technical solution of the present invention reduces the source ohmic contact resistance and the body sheet resistance, thereby reducing the on-resistance of the PiN diode formed by the source and drain, and improving the freewheeling capability of the diode when it is used as a body diode. Attached Figure Description

[0052] Figure 1This is a schematic flowchart illustrating a method for fabricating a SiC MOSFET device according to an embodiment of the present invention.

[0053] Figures 2a-2i This is a schematic diagram illustrating a method for fabricating a SiC MOSFET device according to an embodiment of the present invention.

[0054] Figure 3 This is a schematic diagram of the structure of a SiC MOSFET device provided in an embodiment of the present invention. Detailed Implementation

[0055] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0056] It should be noted that, in this embodiment, "up," "down," "left," and "right" refer to the positional relationship of the Schottky diode structure when it is in the illustrated state, "length" refers to the lateral dimension of the Schottky diode when it is in the illustrated state, and "depth" refers to the longitudinal dimension of the Schottky diode when it is in the illustrated state.

[0057] Example 1

[0058] Please see Figure 1 And Figure 2, Figure 1 This is a schematic flowchart of a method for fabricating a SiC MOSFET device according to an embodiment of the present invention. Figures 2a-2i This is a schematic diagram illustrating a process for fabricating a SiC MOSFET device according to an embodiment of the present invention. The embodiment of the present invention provides a method for fabricating a SiC MOSFET device, which includes:

[0059] Step 1, please refer to Figure 2a N-type substrate layer 1 was selected.

[0060] Specifically, N-type substrate 1 is selected and cleaned using the RCA cleaning standard.

[0061] Furthermore, the N-type substrate layer 1 is an N-type 4H-SiC substrate layer.

[0062] Step 2, please refer to Figure 2b An N-type epitaxial layer 2 is formed on an N-type substrate layer 1.

[0063] Specifically, an N-type epitaxial layer 2 is epitaxially grown on the surface of an N-type substrate layer 1 using a chemical vapor deposition (CVD) process.

[0064] Furthermore, the N-type epitaxial layer 2 is an N-type 4H-SiC epitaxial layer.

[0065] Step 3, please refer to Figure 2c Ions are implanted at both ends of the N-type epitaxial layer 2 to form P-well implantation regions 3.

[0066] Specifically, Al ions are implanted at both ends of the N-type epitaxial layer 2 using the ion implantation method to form a P-well implantation region 3.

[0067] Furthermore, the P-well implantation region was subjected to four Al ion implantations at an ambient temperature of 650℃, using implantation energies of 450keV, 300keV, 200keV, and 120keV respectively, resulting in an implantation dose of 7.97 × 10⁻⁶. 13 cm -2 4.69×10 13 cm -2 3.27×10 13 cm -2 and 2.97×10 13 cm -2 Aluminum ions are injected into the P-well injection region to form P-well injection region 3.

[0068] Step 4, please refer to Figure 2d N element is injected into the P-well injection region 3 to form the N element injection region 4.

[0069] Specifically, a self-aligned process is used to implant N element into the P-well implantation region 3 to form the N element implantation region 4, wherein the implantation energy is 100–200 keV and the implantation dose is 1e¹⁵–3e¹⁵ cm⁻¹. -2 .

[0070] Step 5, please refer to Figure 2d P element is injected into N element injection region 4 to form P element injection region 5. P element injection region 5 is located on the remaining N element injection region 4. N element injection region 4 and P element injection region 5 together form N+ injection region.

[0071] Specifically, a self-aligned process is used to inject P element into the N element injection region 4 to form the P element injection region 5, wherein the injection energy is 50-100 keV and the injection dose is 5e14-8e14 cm⁻¹. -2 .

[0072] Step 6, please refer to Figure 2e B element is injected into P well injection region 3 to form B element injection region 6. N element injection region 4 and P element injection region 5 are located between the two B element injection regions 6, and B element injection region 6 is injected into N-type epitaxial layer 2.

[0073] Specifically, a P+ implantation region is formed by photolithography, and a B element is implanted into the P+ implantation region using a self-aligned process to form a B element implantation region 6. The implantation energy is 300–500 keV, and the implantation dose is 1e15–3e15 cm⁻¹. -2 .

[0074] Step 7, please refer to Figure 2e Al element is injected into B element injection region 6 to form Al element injection region 7. Al element injection region 7 is located on the remaining B element injection region 6. B element injection region 6 and Al element injection region 7 together form P+ injection region.

[0075] Specifically, Al element is injected into the B element injection region 6 using a self-aligned process to form the Al element injection region 7, wherein the injection energy is 50–100 keV and the injection dose is 5e¹⁴–8e¹⁴ cm⁻¹. -2 .

[0076] Step 8, please refer to Figure 2f A gate oxide layer 8 is formed on the P-element implantation region 5, the P-well implantation region 3, and the N-type epitaxial layer 2.

[0077] Preferably, the gate oxide layer 8 is made of silicon dioxide (SiO2) or aluminum oxide (Al2O3).

[0078] Step 9, please refer to Figure 2f A polysilicon layer 9 is prepared on the gate oxide layer 8 to form the gate.

[0079] Step 10, please refer to Figure 2g Photolithography is used to form the source ohmic contact region, and C and Ge elements are implanted in the source ohmic contact region to form a surface modulation layer 10, which is located on the remaining Al element implantation region 7.

[0080] Specifically, a source ohmic contact region is formed by photolithography, and C and Ge elements are implanted into the source ohmic contact region using a self-aligned process to form a surface modulation layer 10. The implantation energy is 50–100 keV, and the implantation dose is 1e14–3e14 cm⁻¹. -2 .

[0081] Step 11, please refer to Figure 2h Source electrode 11 is fabricated on surface modulation layer 10.

[0082] Specifically, source ohmic contact metal Ni is deposited on the surface modulation layer 10, followed by annealing to form source 11.

[0083] Preferably, the thickness of the source ohmic contact metal Ni is 200 nm.

[0084] Preferably, the annealing temperature is 1000℃ and the annealing time is 3 minutes.

[0085] Step 12, please refer to Figure 2i Drain 12 is fabricated on the back side of N-type substrate 1.

[0086] Specifically, a Ti / Ni drain is formed on the back side of the N-type substrate layer 1 using magnetron sputtering or electron beam evaporation.

[0087] Step 13: Perform rapid thermal annealing on the entire sample at a temperature of 1000℃ for 3 minutes.

[0088] Step 14: Form an Al gate on the polysilicon layer 9 using magnetron sputtering or electron beam evaporation.

[0089] 1. The N+ injection region of the present invention uses a mixture of nitrogen (N) and phosphorus (P) elements for injection to form a surface P element injection region, so as to reduce the contact resistance of the N-type ohmic contact; the bottom N element injection region is formed to reduce the sheet resistance of the injection region.

[0090] 2. The P+ injection region of the present invention is formed by a mixture of aluminum (Al) and boron (B) elements to form a surface Al element injection region, so as to reduce the contact resistance of the P-type ohmic contact; and a bottom B element injection region is formed to reduce the sheet resistance of the injection region.

[0091] 3. The present invention introduces a C / Ge surface modulation layer in the source contact hole through ion implantation, which can solve the requirement of Ni metal forming excellent ohmic contact with both N-type and P-type SiC.

[0092] 4. The technical solution of the present invention reduces the source ohmic contact resistance and the body sheet resistance, thereby reducing the on-resistance of the PiN diode formed by the source and drain, and improving the freewheeling capability of the diode when it is used as a body diode.

[0093] Example 2

[0094] Please see Figure 3 , Figure 3 This is a schematic diagram of a SiC MOSFET device provided in an embodiment of the present invention. Based on Embodiment 1, the present invention also provides a SiC MOSFET device, which is fabricated using the SiC MOSFET device fabrication method described in Embodiment 1. This SiC MOSFET device includes:

[0095] N-type substrate layer 1;

[0096] N-type epitaxial layer 2 is located on N-type substrate layer 1;

[0097] Two P-well injection regions 3 are located at both ends of the N-type epitaxial layer 2;

[0098] Two N-element injection regions 4 are located within the P-well injection region 3;

[0099] Two P-element injection regions 5 are located within N-element injection regions 4, and the P-element injection regions 5 are located on the remaining N-element injection regions 4;

[0100] Two B-element injection regions 6 are located within the P-well injection region 3, and the N-element injection region 4 and the P-element injection region 5 are located between the two B-element injection regions 6, with the bottom of the B-element injection region 6 located within the N-type epitaxial layer 2.

[0101] Two Al element injection regions 7 are located on the remaining B element injection regions 6;

[0102] Gate oxide layer 8 is located on part of the P-element implantation region 5, P-well implantation region 3 and N-type epitaxial layer 2;

[0103] Polysilicon layer 9 is located on gate oxide layer 8;

[0104] Two surface modulation layers 10 are located on the remaining Al element injection region 7, respectively;

[0105] Two sources 11 are located on the surface modulation layer 10;

[0106] Drain 12 is located on the back side of N-type substrate 1.

[0107] 1. The N+ injection region of the present invention uses a mixture of nitrogen (N) and phosphorus (P) elements for injection to form a surface P element injection region, so as to reduce the contact resistance of the N-type ohmic contact; the bottom N element injection region is formed to reduce the sheet resistance of the injection region.

[0108] 2. The P+ injection region of the present invention is formed by a mixture of aluminum (Al) and boron (B) elements to form a surface Al element injection region, so as to reduce the contact resistance of the P-type ohmic contact; and a bottom B element injection region is formed to reduce the sheet resistance of the injection region.

[0109] 3. The present invention introduces a C / Ge surface modulation layer in the source contact hole through ion implantation, which can solve the requirement of Ni metal forming excellent ohmic contact with both N-type and P-type SiC.

[0110] 4. The technical solution of the present invention reduces the source ohmic contact resistance and the body sheet resistance, thereby reducing the on-resistance of the PiN diode formed by the source and drain, and improving the freewheeling capability of the diode when it is used as a body diode.

[0111] In the description of this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0112] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or data point described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or data points described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0113] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A method of fabricating a SiC MOSFET device, characterized by, The preparation method comprises: selecting an N-type substrate layer (1); forming an N-type epitaxial layer (2) on the N-type substrate layer (1); injecting ions at both ends of the N-type epitaxial layer (2) to form P-well injection regions (3); injecting N elements into the P-well injection regions (3) to form N element injection regions (4); injecting P elements into the N element injection regions (4) to form P element injection regions (5), which are located on the remaining N element injection regions (4); injecting B elements into the P-well injection regions (3) to form B element injection regions (6), wherein the N element injection regions (4) and the P element injection regions (5) are located between two B element injection regions (6), and the B element injection regions (6) are injected into the N-type epitaxial layer (2); injecting Al elements into the B element injection regions (6) to form Al element injection regions (7), which are located on the remaining B element injection regions (6); forming a gate oxide layer (8) on part of the P element injection regions (5), the P-well injection regions (3), and the N-type epitaxial layer (2); preparing a polysilicon layer (9) on the gate oxide layer (8) to form a gate electrode; forming a source electrode ohmic contact region by photolithography, and injecting C and Ge elements into the source electrode ohmic contact region to form a surface modulation layer (10), which is located on the remaining Al element injection regions (7); preparing a source electrode (11) on the surface modulation layer (10); preparing a drain electrode (12) on the back of the N-type substrate layer (1).

2. The method of fabricating a SiC MOSFET device according to claim 1, wherein, The materials of the N-type substrate layer (1) and the N-type epitaxial layer (2) are both 4H-SiC.

3. The method of fabricating a SiC MOSFET device of claim 1, wherein, The method for injecting ions at both ends of the N-type epitaxial layer (2) to form P-well injection regions (3) comprises: injecting Al ions at both ends of the N-type epitaxial layer (2) by ion implantation to form P-well injection regions (3).

4. The method of fabricating a SiC MOSFET device of claim 1, wherein, The method for injecting N elements into the P-well injection regions (3) to form N element injection regions (4) comprises: The N element injection region (4) is formed by injecting N element into the P well injection region (3) by using a self-alignment process, wherein the injection energy is 100-200 keV, and the injection dose is 1e15-3e15 cm -2 .

5. The method of fabricating a SiC MOSFET device according to claim 4, wherein, The method for injecting P elements into the N element injection regions (4) to form P element injection regions (5) comprises A self-aligned process is used to implant P element into the N element implantation region (4) to form a P element implantation region (5), wherein the implantation energy is 50-100 keV, and the implantation dose is 5e14-8e14 cm -2 .

6. The method of fabricating a SiC MOSFET device of claim 1, wherein, The method for injecting B elements into the P-well injection regions (3) to form B element injection regions (6) comprises: The P+ implantation region is formed by photoetching, and B element implantation region (6) is formed by implanting B element in the P+ implantation region by self-alignment process, wherein the implantation energy is 300-500 keV, and the implantation dose is 1e15-3e15 cm -2 .

7. The method of fabricating a SiC MOSFET device according to claim 6, wherein, The method for injecting Al elements into the B element injection regions (6) to form Al element injection regions (7) comprises: An Al element implantation region (7) is formed by implanting Al element into the B element implantation region (6) by using a self-alignment process, wherein the implantation energy is 50-100 keV, and the implantation dose is 5e14-8e14 cm -2 .

8. The method of fabricating a SiC MOSFET device of claim 1, wherein, The method for injecting C and Ge elements into the source electrode ohmic contact region to form a surface modulation layer (10) comprises: C and Ge elements are injected in the source ohmic contact region by using a self-alignment process to form a surface modulation layer (10), the injection energy is 50-100 keV, and the injection dose is 1e14-3e14 cm -2 .

9. The method of fabricating a SiC MOSFET device of claim 1, wherein, The method for preparing a source electrode (11) on the surface modulation layer (10) comprises: depositing a source electrode ohmic contact metal Ni on the surface modulation layer (10), and then performing annealing treatment to form a source electrode (11).

10. A SiC MOSFET device prepared by the preparation method of any one of claims 1 to 9, the SiC MOSFET device comprising: an N-type substrate layer (1); an N-type epitaxial layer (2) located on the N-type substrate layer (1); two P-well injection regions (3) respectively located in both ends of the N-type epitaxial layer (2); two N element implantation regions (4) are located in the P well implantation region (3) respectively; two P element implantation regions (5) are located in the N element implantation region (4) respectively, and the P element implantation region (5) is located on the remaining N element implantation region (4); two B element implantation regions (6) are located in the P well implantation region (3) respectively, the N element implantation region (4) and the P element implantation region (5) are located between the two B element implantation regions (6), and the bottom of the B element implantation region (6) is located in the N type epitaxial layer (2); two Al element implantation regions (7) are located on the remaining B element implantation region (6) respectively; a gate oxide layer (8) is located on part of the P element implantation region (5), the P well implantation region (3) and the N type epitaxial layer (2); a polysilicon layer (9) is located on the gate oxide layer (8); two surface modulation layers (10) are located on the remaining Al element implantation region (7) respectively; two sources (11) are located on the surface modulation layer (10) respectively; a drain (12) is located on the back of the N type substrate layer (1).

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