Shielded semiconductor package with open terminal and method of fabrication via two-step process

Abstract

This application relates to shielded semiconductor packages having open terminals and methods of fabrication via a two-step process. A semiconductor device has a substrate including a terminal and an insulating layer formed over the terminal. An electrical component is disposed over the substrate. An encapsulant is deposited over the electrical component and the substrate. A portion of the insulating layer over the terminal is exposed from the encapsulant. A shield layer is formed over the encapsulant and the terminal. A portion of the shield layer is removed to expose the portion of the insulating layer. The portion of the insulating layer is removed to expose the terminal. The portion of the shield layer and the portion of the insulating layer can be removed by laser ablation.

Description

[0001] This application is a divisional application of the national patent application number 201911380906.X, which was filed on December 27, 2019, and is entitled "Shielded Semiconductor Package with Open Terminals and Method for Manufacturing via a Two-Step Process". Technical Field

[0002] The present invention relates generally to semiconductor devices, and more particularly to semiconductor packages having electromagnetic interference (EMI) shielding and one or more open terminals or sockets. Background Technology

[0003] Semiconductor devices are commonly found in modern electronic products. They perform a wide variety of functions, such as signal processing, high-speed computing, transmitting and receiving electromagnetic signals, controlling electronic devices, converting sunlight into electricity, and creating visual images for television displays. Semiconductor devices are used in communications, power conversion, networking, computers, entertainment, and consumer products. They are also found in military applications, aerospace, automotive, industrial controllers, and office equipment.

[0004] Semiconductor devices are generally susceptible to electromagnetic interference (EMI), radio frequency interference (RFI), harmonic distortion, or other inter-device interference, such as capacitive, inductive, or conductive coupling, also known as crosstalk, which can interfere with their operation. High-speed switching in digital circuits also generates interference.

[0005] A conductive layer is typically formed over a semiconductor package to shield the electronic components within the package from EMI and other interference. The shielding layer absorbs EMI before signals can strike the semiconductor chip and discrete components within the package, which could otherwise cause device malfunction. Shielding layers are also formed over packages containing components expected to generate EMI to protect nearby devices from malfunction.

[0006] One problem with existing semiconductor packaging shielding methods is that the shielding layer formed on top of the package completely covers the top of the package. Many semiconductor packages require open areas with exposed sockets or terminals that allow connections to adjacent semiconductor devices. Unfortunately, conventional shielding completely covers the package and can short-circuit any exposed terminals or sockets together. Therefore, there is a need for semiconductor devices that have both EMI shielding and exposed terminals or sockets, and for methods of fabricating such devices. Attached Figure Description

[0007] Figure 1a-1k The illustration shows a semiconductor package with exposed terminals and electromagnetic interference (EMI) shielding. Figures 2a-2gThe illustration shows an alternative configuration for the exposed terminals; and Figures 3a-3e The illustrations depict various embodiments of integrating a package into an electronic device and connecting it to the package via exposed terminals. Detailed Implementation

[0008] The invention is described in one or more embodiments with reference to the accompanying drawings, wherein like numerals denote like or similar elements. Although the invention has been described according to the best mode for carrying out the objectives of the invention, those skilled in the art will appreciate that it is intended to cover alternatives, modifications, and equivalents that may be included within the spirit and scope of the invention as defined by the appended claims and their equivalents, as supported by the following disclosure and the accompanying drawings. As used herein, the term “semiconductor chip” refers to both the singular and plural forms of the word, and therefore can refer to both a single semiconductor device and multiple semiconductor devices.

[0009] Semiconductor devices are typically manufactured using two complex processes: front-end fabrication and back-end fabrication. Front-end fabrication involves forming multiple dies on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components that are electrically connected to form a functional circuit. Active electrical components, such as transistors and diodes, have the ability to control the flow of current. Passive electrical components, such as capacitors, inductors, and resistors, create the voltage and current relationships necessary to perform the circuit's function.

[0010] Back-end manufacturing refers to the dicing or dicing of finished wafers into individual semiconductor dies, and the packaging of these dies for structural support, electrical interconnection, and environmental isolation. To dice semiconductor dies, the wafer is scribed and broken along non-functional areas (called serrations or cuts). The wafer is diced using a laser cutting tool or saw blade. After dicing, the individual semiconductor dies are mounted onto a package substrate, which includes pins or contact pads for interconnection with other system components. Contact pads formed on top of the semiconductor dies are then connected to contact pads within the package. Electrical connections can be made using conductive layers, bumps, pillar bumps, conductive paste, or wire bonding. A sealant or other molding compound is deposited on top of the package to provide physical support and electrical isolation. The finished package is then inserted into an electrical system, enabling the functionality of the semiconductor device for use with other system components.

[0011] Figure 1a-1k The illustration shows a method for forming a semiconductor package with shielded and exposed terminals using a two-step partial shield removal process. Figure 1aA partial cross-sectional view of substrate 100, which serves as the basis for the package formation process, is shown. The illustrated portion of substrate 100 includes spaces for forming two packages separated by saw marks 101. However, substrate 100 as a whole will typically include spaces for forming hundreds, thousands, or even more packages in parallel.

[0012] Substrate 100 is formed of a base insulating material 102, wherein a conductive layer 104 is formed above the outer surface of the substrate and interleaved between layers of the insulating material. The conductive layer 104 includes contact pads, conductive traces, and conductive vias configured as needed to achieve desired signal routing. Portions of the conductive layer 104 may be electrically common or electrically isolated depending on the design and function of the formed device. The conductive layer 104 is formed using PVD, CVD, electrolytic plating, electrodeless plating, or other suitable metal deposition processes. The conductive layer 104 may be one or more layers of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag), or other suitable electrically conductive materials.

[0013] The conductive layer 104 includes terminals 110 for external interconnection in the final package. The terminals 110 are formed on the top surface of the substrate 100 and will remain exposed in the final package for electrical connection to another external device or package.

[0014] The substrate 100 can also be any suitable laminated insert, PCB, wafer form, strip insert, lead frame, or other type of substrate. The substrate 100 may include one or more laminated layers of pre-impregnated (prepreg treated) polytetrafluoroethylene (PTFE), FR-4, FR-1, CEM-1, or CEM-3 (which has a combination of phenolic cotton paper, epoxy resin, resin, glass fabric, frosted glass, polyester, and other reinforcing fibers or fabrics). The insulating material 102 comprises one or more layers of silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), tantalum pentoxide (Ta2O5), alumina (Al2O3), solder resist, polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), and other materials with similar insulating and structural properties. The substrate 100 may also be a multilayer flexible laminate, ceramic, copper-clad laminate, glass, or semiconductor wafer, which includes an active surface containing one or more transistors, diodes, and other circuit elements to realize analog or digital circuits.

[0015] Solder resist or passivation layers 106 and 108 are formed above the top and bottom surfaces of the substrate 100 for physical protection of the exposed contact pads. Passivation layer 106 is formed of any suitable material for passivation or solder resist layers, including those mentioned above with respect to insulating material 102 (e.g., polyimide).

[0016] exist Figure 1b In this embodiment, a semiconductor chip 114 is flip-chip mounted to the top surface of a substrate 100. The semiconductor chip 114 includes contact pads 116 for electrical interconnection and is mounted to the substrate 100 using solder bumps 118 that flow back between the contact pads 116 and the contact pads of the conductive layer 104. In other embodiments, other interconnection structures, such as pillar bumps, conductive pillars, or bonding wires, are used. Openings are formed in the passivation layer 106 to expose the contact pads for connecting the semiconductor chip 114.

[0017] Semiconductor chip 114 is packaged together with discrete passive component 122 and any other desired electrical components by placing the components on substrate 100. Similar to semiconductor chip 114, component 122 is mounted to contact pads of conductive layer 104 through openings in passivation layer 106. Any electrical component or combination of electrical components can be placed on substrate 100 for any desired purpose.

[0018] Solder material disposed between components 122 is reflowed to connect those components. In some embodiments, the solder material for the discrete passive components 122 is solder paste printed onto the substrate 100 before the component surfaces are mounted to the substrate. Components disposed on the substrate 100 may include system-in-package (SiP) modules. Components mounted to the substrate 100 may include semiconductor chips, semiconductor packages, discrete active or passive components, or any other suitable electrical components.

[0019] Figure 1c A substrate 100 is shown having semiconductor wafers 114 and components 122 disposed in a mold 160. The mold 160 shapes deposited sealant into the desired shape of a semiconductor package. The mold 160 includes an extension 162 that extends to and contacts a passivation layer 106 above a terminal 110 to substantially prevent molding compound from extending over the terminal. In other embodiments, other methods are used to leave the terminal 110 free of molding compound. In one embodiment, molding compound is deposited using a mask over the terminal 110. In another embodiment, molding compound is deposited over the entire substrate 100 including the terminal 110 and then removed over the terminal using laser drilling, mechanical drilling, chemical etching, or another suitable process.

[0020] In embodiments where the opening 168 extends across the entire length or width of each package, a trench can be created across the entire width or length of the substrate 100 using a saw blade after the sealant 166 is deposited. The passivation layer 106 retains a cover over the terminals 110, protecting them during the molding process and any subsequent sealant removal processes that may be used. In some embodiments (where the sealant 166 is deposited over the terminals 110 and then removed), the passivation layer 106 functions as an etch-stop layer.

[0021] Figure 1d The diagram illustrates a sealant 166 deposited on a substrate 100 above semiconductor wafers 114 and components 122 using paste printing, compression molding, transfer molding, liquid sealant molding, vacuum lamination, spin coating, or another suitable coater. The sealant 166 may be a polymer composite material, such as epoxy resin, epoxy acrylate, or a polymer with or without fillers. The sealant 166 is non-conductive, provides structural support, and environmentally protects the semiconductor device from external elements and contaminants. The sealant 166 includes an opening 168 formed above terminals 110, wherein an extension 162 of the mold 160 blocks the sealant.

[0022] The substrate 100 with sealant 166 is removed from the mold 160, and if used, is divided by sawing through slits 101 to form individual packages 170 using a laser cutting tool, saw blade, waterjet cutting tool or other suitable device. Figure 1e The illustration shows a perspective view of the segmented package 170, illustrating the positions of the terminals 110 and the opening 168 relative to the package as a whole. The opening 168 extends only above the terminals 110 and a small periphery of the terminals. In other embodiments, the terminals 110 may be located at other points on the substrate 100, such as... Figures 2a-2g As illustrated in the figure, opening 168 moves accordingly.

[0023] exist Figure 1f and 1g In this configuration, a semiconductor package 170 is placed on a carrier 180 having optional heat release, ultraviolet (UV) release, adhesive, or other suitable interface layer 182. The carrier 180 is a panel of glass, aluminum, steel, copper, polymer, silicon, or another suitable material, possessing sufficient rigidity to support multiple packages 170 to be processed together. Only two packages 170 are illustrated, but typically hundreds, thousands, or more packages are processed at once. In some embodiments, the carrier 180 is... Figures 1a-1d The same carrier is used in the processing steps. Package 170 can remain in place after splitting, rather than being set on a different carrier for the application of EMI shielding.

[0024] Conductive material is sputtered over package 170 to form a conformal shielding layer 190. Shielding layer 190 is formed by any suitable metal deposition technique, such as chemical vapor deposition, physical vapor deposition, other sputtering methods, spraying, or electroplating. Shielding layer 190 completely covers the sealant 166 and the exposed top and sides of substrate 100, including terminals 110. Terminals 110 remain covered by passivation layer 106 and do not directly physically contact shielding layer 190. Passivation layer 106 remains disposed between terminals 110 and shielding layer 190. In some embodiments, a portion of conductive layer 104 in substrate 100 is exposed on one side of the substrate to physically contact shielding layer 190 and serves to electrically connect the shielding layer to a ground voltage node. Shielding layer 190 covers each exposed surface of package 170. Typically, only the bottom surface remains uncovered by shielding layer 190 because the bottom surface of package 170 is in contact with carrier 180 or interface layer 182.

[0025] exist Figure 1h In this process, laser 200 is used to perform laser ablation to remove a portion of the shielding layer 190 above terminal 110. Laser 200 is a diode-pumped solid-state (DPSS) laser, an excited-state focused laser (with ArF, KrF, XeCl, XeF, or another suitable exciton), an ultraviolet, visible, or infrared laser, a yttrium aluminum garnet (YAG) laser doped with neodymium, erbium, ytterbium, or another suitable material, or a CO2 laser with μm, ns, ps, or fs pulses. Various lenses can be used, such as focusing, collimating, apochromatic, or achromatic lenses. Mirrors, scanners, slits, filters, or other suitable devices can be used to guide or modulate the optical signal from laser 200. Figure 1h In this process, a scanner 202 is used to guide the laser 200 over the surface area of ​​the terminal 110.

[0026] Energy emitted by laser 200 strips the shielding layer 190 from above terminal 110, but leaves the passivation layer 106 covering the terminal. In some embodiments, a metal stripping process is used to remove the shielding layer 190, thereby defocusing the beam from laser 200 and stripping the desired portion of the shielding layer. Metal stripping is a form of laser ablation. After the stripping process removes the shielding layer 190 above terminal 110, soft laser ablation is performed using a laser 200 set at a low power level as a cleaning process to remove any remaining metal residue. Any suitable stripping, shadowing, lift-off, or ablation technique can be used to partially remove the shielding layer 190. In other embodiments, methods other than laser ablation are used to remove the shielding layer 190 above terminal 110, such as chemical etching or mechanical polishing.

[0027] Figure 1iA perspective view is shown, with the shielding layer 190 removed above the terminal 110. The terminal 110 remains covered by the passivation layer 106. The shielding layer 190 remains fully covered by the side surfaces of the substrate 100 and the sealant 166, as well as the top surface of the sealant.

[0028] exist Figure 1j In this configuration, laser 200 is used to form openings in passivation layer 106 and expose terminals 110 for subsequent interconnection. Laser 200 is used in conjunction with... Figure 1h The same laser used for partially removing the shielding layer 190 is used, but may be reconfigured to have a different frequency or power output if necessary. In other embodiments, different lasers are used. Scanner 202 moves the laser beam from laser 200 across terminal 110 to expose the terminal for subsequent electrical interconnection.

[0029] Figure 1k The illustration shows a perspective view in which terminal 110 is exposed through an opening in passivation layer 106. Shielding layer 190 completely covers the top and all side surfaces of sealant 166, including within opening 168 and the side surfaces of substrate 100, while exposing terminal 110 for electrical interconnection.

[0030] The passivation layer 106 is held above the substrate 100 and can function as a solder resist layer. Openings in the passivation layer 106 can be smaller than, larger than, or the same size as the corresponding terminals 110. Package 170 is removed from the carrier 180, which separates portions of the shielding layer 190 between packages. Package 170 can be mounted onto the substrate of a larger electronic device using pick-and-place operations, packaged in tapes and reels for delivery, or otherwise configured.

[0031] Except for the open socket or terminal area with exposed terminals 110, the semiconductor package 170 is completely shielded by a shielding layer 190. The shielding layer 190 effectively blocks electromagnetic noise radiation generated by components within the package 170 and prevents malfunctions in nearby devices, and vice versa.

[0032] Figures 2a-2g The illustration shows alternative, non-limiting locations for terminals or sockets on the package. Figure 2a A package 210 having terminals 110 as described above is shown, and an additional terminal 212 on the opposite side of the package. The terminal 212 extends parallel to the terminal 110 on the opposite side of the package 210. Figure 2b A package 220 with terminal 222 is shown. Terminal 222 is formed in the middle of package 220 and surrounded by a ring of sealant 166, rather than being located at the edge of the package as terminal 110 is.

[0033] Figure 2cA package 230 with terminals 232 is shown, the terminals 232 being continuously formed around the package to surround the remainder of the sealant 166. Figure 2d In the package 240, a terminal 242 is formed only along the middle portion of one of the package edges, while... Figure 2e In the package 250, terminals 252 and 254 are formed at both ends of the edge without extending to the middle. Figure 2f A package 260 with a terminal 262 formed at the left end of the package edge is shown, and Figure 2g The package 270 has a terminal 272 formed at the right end of the edge.

[0034] Terminals can be formed at any location within the package and then exposed via the two-step laser process disclosed above. Any of the above terminal locations can be combined. The semiconductor wafer and other components for the package are disposed in the remaining area of ​​the sealant 166.

[0035] Figures 3a-3e The illustration shows the shielded encapsulation described above (e.g., having a shielded enclosure from...). Figure 1k The shielding layer 190 and the package 170 are incorporated into the electronic device. Figure 3a The illustration shows a partial cross-section of a package 170 mounted on a PCB or other substrate 282, which is a part of an electronic device. Bumps 284 are formed on a conductive layer 104 on the side of the substrate 100 opposite to the semiconductor wafer 114. The conductive bumps 284 can be present at any stage of the manufacturing process (e.g., during...). Figure 1c Before molding, in Figure 1e The package 170 is formed (either before or after the formation of the shielding layer 190). Bumps 284 are reflowed onto the conductive layer 283 of the PCB 282 to physically attach and electrically connect the package 170 to the PCB. In other embodiments, thermoforming or other suitable attachment and connection methods are used. In some embodiments, an adhesive or underfill layer is used between the package 170 and the PCB 282. The semiconductor wafer 114 is electrically coupled to the conductive layer 283 via bumps 118, conductive layer 104, and bumps 284.

[0036] A second semiconductor package 280 is disposed on a substrate 282 adjacent to package 170. Package 280 is illustrated as a mirror image of package 170. However, any suitable package configuration having any desired electrical components or combinations thereof can be disposed on substrate 282 and connected to package 270 via terminals 110. Package 280 has exposed terminals 281 disposed adjacent to terminals 110 of package 170. A board-to-board (B2B) connector 286 is mounted to terminals 110 and 281 to electrically connect package 170 and package 280.

[0037] B2B connector 286 is a PCB or other suitable substrate or insert with conductive layer 287 for routing electrical signals between packages. B2B connector 286 is mechanically and electrically connected to terminals 110 and 281 via solder bumps 288 that flow back between the B2B connector and the terminals. B2B connector 286 provides a direct electrical connection between two packages without signal routing through PCB 282, which reduces the signal routing requirements of electrical components and provides faster and more direct signal transmission.

[0038] Figure 3b Packages 170 and 280 are illustrated, each having a ribbon cable connector 292 mounted to terminals 110 and 281, respectively. A ribbon cable or flexible PCB 294 is connected to one of the connectors 292 at each end. Any suitable interconnect structure or connection mechanism can be used to connect package 170 to another location within the electronics via terminal 110.

[0039] Terminal 110 also allows for more flexible use of package 170 because the terminals on substrate 100 can be used to integrate the package into electronic devices instead of using contact pads on the bottom of substrate 100. Figure 3c In this configuration, package 170 is disposed on substrate 300 but not electrically connected to the substrate. Substrate 300 may be a structural part of the electronic device to which package 280 is mounted, such as the housing of a mobile phone. PCB or flexible PCB 302 holds other circuit components that implement other functionalities of the electronic device and is mounted to substrate 300 adjacent to package 170. PCB 302 and package 170 may be directly mounted to substrate 300 using adhesive, screwed on using a lifter (which keeps package 170 and PCB 302 separate from substrate 300), or attached by any other suitable mechanism. B2B connector 286 or another interconnect structure is used to connect package 170 to PCB 302 to integrate the functionality of semiconductor chip 114 with, for example, the functionality of semiconductor chip 304.

[0040] exist Figure 3d In this configuration, a PCB 310 with socket pins 312 formed thereon is mounted onto terminal 110. The socket pins 312 can be used for a variety of purposes, such as testing package 170, allowing configuration via jumpers, or connecting package 170 to another socket via a ribbon cable.

[0041] Figure 3e The illustration shows an electronic device 340, which includes a PCB 282 (with multiple semiconductor packages mounted on the surface of the PCB) and a package 170 having socket pins 312. Depending on the application, the electronic device 340 may have one type of semiconductor package or multiple types of semiconductor packages.

[0042] Electronic device 340 may be a standalone system that uses a semiconductor package to perform one or more electrical functions. Alternatively, electronic device 340 may be a sub-component of a larger system. For example, electronic device 340 may be part of a tablet computer, cellular phone, digital camera, communication system, or other electronic device. Electronic device 340 may also be a graphics card, network interface card, or another signal processing card inserted into a computer. Semiconductor packages may include microprocessors, memory, ASICs, logic circuits, analog circuits, RF circuits, discrete active or passive devices, or other semiconductor chips or electrical components.

[0043] exist Figure 3e In this PCB 282, a general-purpose substrate is provided for the structural support and electrical interconnection of semiconductor packages mounted on the PCB. Conductive signal traces 283 are formed on or within the surface of the PCB 282 using evaporation, electroplating, electrodeless plating, screen printing, or other suitable metal deposition processes. The signal traces 283 provide electrical communication between the semiconductor package, mounted components, and other external systems or components. The traces 283 also provide power and ground connections to the semiconductor package as needed.

[0044] In some embodiments, the semiconductor device has two package levels. The first-level package is a technique for mechanically and electrically attaching a semiconductor die to an intermediate substrate. The second-level package involves mechanically and electrically attaching the intermediate substrate to PCB 282. In other embodiments, the semiconductor device may have only a first-level package, where the die is directly mechanically and electrically mounted to PCB 282.

[0045] For illustrative purposes, several types of first-level packages, including wire bond packages 346 and flip chips 348, are shown on PCB 282. Additionally, several types of second-level packages (including ball grid array (BGA) 350, bump chip carrier (BCC) 352, land surface grid array (LGA) 356, multi-chip module (MCM) 358, quad flat no-lead (QFN) package 360, quad flat package 362, and embedded wafer-level ball grid array (eWLB) 364) are shown mounted on PCB 282 along with package 170. Conductive traces 283 electrically couple various packages and components disposed on PCB 282 to package 170, thereby making the components within package 170 available to other components on the PCB. Furthermore, socket pins 312 remain exposed for connection via test equipment, etc. In other embodiments, some of the other packages of the electronic device 340 are connected to the package 170 via terminal 110 (or via socket 312 or via another interconnection structure).

[0046] Depending on system requirements, any combination of semiconductor packages configured with first-level and second-level package styles, along with other electronic components, can be connected to PCB 282. In some embodiments, electronics 340 includes a single attached semiconductor package, while other embodiments require multiple interconnected packages. By combining one or more semiconductor packages over a single substrate, manufacturers can incorporate pre-fabricated components into electronics and systems. Because semiconductor packages include complex functionality, electronics can be manufactured using less expensive components and streamlined manufacturing processes. The resulting devices are less likely to fail and less expensive to manufacture, resulting in lower costs for consumers.

[0047] Although one or more embodiments of the invention have been illustrated in detail, those skilled in the art will appreciate that changes and modifications may be made to those embodiments without departing from the scope of the invention as set forth in the following claims.

Claims

1. A semiconductor device, comprising substrate; A first terminal is formed above the substrate, wherein the first terminal is used for external interconnection in the final package; An insulating layer formed above the substrate includes an opening in the insulating layer above the first terminal; A sealant is disposed above the first portion of the insulating layer, while a second portion of the top surface of the insulating layer around the opening of the insulating layer remains exposed outside the sealant, wherein the top surface of the insulating layer is exactly opposite to the substrate and is in physical contact with the sealant within the first portion of the insulating layer; as well as An electromagnetic interference shielding layer is formed over the substrate, the insulating layer and the sealant, the electromagnetic interference shielding layer being in physical contact with a second portion of the insulating layer, wherein an opening of the electromagnetic interference shielding layer is formed over the first terminal.

2. The semiconductor device of claim 1, further comprising a semiconductor package disposed adjacent to the substrate, wherein the semiconductor package is connected to the first terminal.

3. The semiconductor device of claim 2, further comprising a ribbon cable or flexible printed circuit board coupled between the first terminal and the semiconductor package.

4. The semiconductor device of claim 2, further comprising a board-to-board connector coupled between the first terminal and the semiconductor package.

5. The semiconductor device of claim 1, further comprising a second terminal formed above the substrate and a second opening formed through an insulating layer above the second terminal.

6. The semiconductor device of claim 5, wherein the opening of the electromagnetic interference shielding layer is formed above the second terminal.

7. The semiconductor device of claim 1, further comprising an interconnect structure disposed above the first terminal.

8. The semiconductor device of claim 7, further comprising a semiconductor package connected to the substrate via the interconnect structure and the first terminal.

9. The semiconductor device of claim 7, wherein the interconnect structure comprises a ribbon cable connector.

10. The semiconductor device of claim 1, further comprising a socket disposed above the first terminal.

11. A semiconductor device, comprising: substrate; A first contact pad formed on the substrate for external interconnection in the final package; An insulating layer formed on the substrate has an opening formed in the insulating layer above the first contact pad; A sealant is formed on a first portion of the insulating layer, wherein a second portion of the top surface of the insulating layer is exposed from the sealant around the first contact pad, and wherein the top surface of the insulating layer is exactly opposite to the substrate and is in physical contact with the sealant within the first portion of the insulating layer; as well as An electromagnetic interference shielding layer is formed over the insulating layer and the sealant, wherein a portion of the electromagnetic interference shielding layer is in physical contact with a second portion of the insulating layer, and the electromagnetic interference shielding layer includes an opening over the first contact pad.

12. The semiconductor device of claim 11, further comprising a second contact pad formed on the substrate and a second opening formed in an insulating layer above the second contact pad.

13. The semiconductor device according to claim 12, wherein, The openings of the electromagnetic interference shielding layer are formed above the first contact pad and the second contact pad.

14. The semiconductor device of claim 11, further comprising an interconnect structure disposed on the first contact pad, wherein the interconnect structure extends outside the occupied area of ​​the substrate.

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