Semiconductor package structure
By employing an independent routing channel design in the semiconductor packaging structure, the problem of insufficient flexibility in integrating different components in the existing packaging structure is solved, thereby enhancing the flexibility and adaptability of the channel design.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- MEDIATEK INC
- Filing Date
- 2021-11-19
- Publication Date
- 2026-08-04
AI Technical Summary
Existing semiconductor packaging structures lack flexibility in integrating different components, making it difficult to meet the diverse needs of channel design.
The semiconductor packaging structure design includes front and rear redistribution layers, a stacked structure, a first IP core, and a second IP core. The IP cores are electrically coupled to the redistribution layer through independent routing channels, ensuring that the signals of different IP cores pass through different routing channels and providing additional routing channel design flexibility.
It improves the flexibility of channel design, ensures that the signal transmission of different IP cores does not interfere with each other, and enhances the adaptability of the channel design of the packaging structure.
Smart Images
Figure CN115547981B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to semiconductor packaging technology, and more particularly to a semiconductor packaging structure. Background Technology
[0002] With the increasing demand for more features and smaller devices, package-on-package (PoP) technology, which vertically stacks two or more packages, is becoming increasingly popular. PoP technology reduces the line length between different components, such as controllers and storage devices. This provides better electrical performance because shorter interconnect wiring results in faster signal propagation and reduces noise and crosstalk defects.
[0003] While existing semiconductor packaging structures are generally sufficient, they are not satisfactory in every aspect. For example, meeting the channel requirements for integrating different components into a single package is a challenge. Therefore, further improvements to semiconductor packaging structures are needed to provide flexibility in channel design. Summary of the Invention
[0004] According to some embodiments, a semiconductor package structure is provided. The semiconductor package structure includes a front redistribution layer, a stack structure, a rear redistribution layer, a first IP core, and a second IP core. The stack structure is disposed above the front redistribution layer and includes a first semiconductor die and a second semiconductor die above the first semiconductor die. The rear redistribution layer is disposed above the stack structure. The first IP core is disposed in the stack structure and electrically coupled to the front redistribution layer through a first trace channel. The second IP core is disposed in the stack structure and electrically coupled to the rear redistribution layer through a second trace channel, wherein the second trace channel is separate from the first trace channel and electrically insulated from the front redistribution layer.
[0005] According to some embodiments, a semiconductor wiring structure is provided. The semiconductor wiring structure includes a first package structure, a first wiring channel, and a second wiring channel. The first package structure has a front side and a rear side, and includes a stacked structure having a first IP core and a second IP core. The first wiring channel electrically couples the first IP core to a first rewiring layer on the front side of the first package structure. The second wiring channel independently and electrically couples the second IP core to a second rewiring layer on the rear side of the first package structure, wherein the second wiring channel is separate from the first wiring channel and electrically insulated from the first rewiring layer.
[0006] These and other objects of the invention will undoubtedly become apparent to those skilled in the art after reading the following detailed description of the preferred embodiments shown in the various accompanying drawings. Attached Figure Description
[0007] The invention is illustrated by way of example and not limitation in the accompanying drawings, in which similar reference numerals indicate similar elements. When a particular feature, structure, or characteristic is described in connection with an embodiment, it should be understood that implementing such a feature, structure, or characteristic in connection with other embodiments is within the knowledge of those skilled in the art, whether or not explicitly indicated.
[0008] Figure 1 This is a cross-sectional view of an exemplary semiconductor package structure according to some embodiments;
[0009] Figures 2A-2D This is a cross-sectional view of a stack structure in an exemplary semiconductor package structure according to some embodiments;
[0010] Figure 3 This is a cross-sectional view of an exemplary semiconductor package structure according to some embodiments;
[0011] Figure 4 This is a cross-sectional view of an exemplary semiconductor package structure according to some embodiments;
[0012] Figure 5 This is a cross-sectional view of an exemplary semiconductor package structure according to some embodiments;
[0013] Figure 6 These are cross-sectional views of exemplary semiconductor package structures according to some embodiments; and
[0014] Figure 7 This is a cross-sectional view of an exemplary semiconductor package structure according to some embodiments. Detailed Implementation
[0015] The following description represents the preferred mode for carrying out the invention. This description is intended to illustrate the general principles of the invention and should not be construed as limiting. The scope of the invention is determined by reference to the appended claims.
[0016] This invention will be described in conjunction with specific embodiments and with reference to certain accompanying drawings, but the invention is not limited thereto, only by the claims. The described drawings are merely illustrative and not restrictive. In the drawings, for illustrative purposes, the dimensions of some components may be exaggerated rather than drawn to scale. Dimensions and relative dimensions do not correspond to actual dimensions in the practice of this invention.
[0017] Semiconductor package structures and semiconductor wiring structures are described according to some embodiments of this disclosure. Semiconductor package structures provide separate routing channels for devices and IP cores (e.g., memory devices and memory IP cores), thereby increasing the flexibility of routing channel design.
[0018] Figure 1 This is a cross-sectional view of a semiconductor package structure 100 according to some embodiments of the present disclosure. Additional features may be added to the semiconductor package structure 100. For different embodiments, some features described below may be replaced or eliminated. For simplicity, only a portion of the semiconductor package structure 100 is shown.
[0019] like Figure 1 As shown, according to some embodiments, the semiconductor package structure 100 includes a first package structure 100a and a second package structure 100b stacked vertically. The first package structure 100a has a front side and a rear side opposite to the front side. The first package structure 100a has a first redistribution layer 102 on its front side and a second redistribution layer 124 on its rear side. Therefore, the first redistribution layer 102 can also be referred to as the front redistribution layer 102, and the second redistribution layer 124 can also be referred to as the rear redistribution layer 124.
[0020] The first redistribution layer 102 includes one or more conductive layers and passivation layers, wherein the one or more conductive layers may be disposed within the one or more passivation layers. The conductive layers may include metals, such as copper, titanium, tungsten, aluminum, or combinations thereof. In some embodiments, the passivation layer includes a polymer layer, such as polyimide (PI), polybenzoxazole (PBO), benzocyclobutene (BCB), epoxy resin, or combinations thereof. Alternatively, the passivation layer may include a dielectric layer, such as silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof. The material of the second redistribution layer 124 may be similar to that of the first redistribution layer 102, and will not be described further here.
[0021] like Figure 1 As shown, according to some embodiments, the first wiring layer 102 includes more conductive layers and passivation layers than the second wiring layer 124. The first wiring layer 102 may be thicker than the second wiring layer 124, but this disclosure is not limited thereto. For example, the second wiring layer 124 may be thicker than or substantially equal to the first wiring layer 102.
[0022] In some embodiments, the first package structure 100a includes a plurality of conductive structures 104 located below and electrically coupled to the first redistribution layer 102. In some embodiments, the conductive structures 104 include conductive materials, such as metal conductive structures 104 may include microbumps, controlled collapse chip connection (C4) bumps, ball grid array (BGA) balls, or combinations thereof.
[0023] In some embodiments, the first package structure 100a includes a stack structure comprising a first semiconductor die 106 and a second semiconductor die 112 vertically stacked above the first redistribution layer 102. According to some embodiments, the first semiconductor die 106 and the second semiconductor die 112 each independently encompass a system-on-a-chip (SoC), a logic device, a memory device, a radio frequency (RF) device, or any combination thereof. For example, the first semiconductor die 106 and the second semiconductor die 112 may each independently include a microcontroller unit (MCU) die, a microprocessor unit (MPU) die, a power management integrated circuit (PMIC) die, a global positioning system (GPS) device, a central processing unit (CPU) die, a graphics processing unit (GPU) die, an input / output (I / O) die, a dynamic random access memory (DRAM) IP core, static random access memory (SRAM), high-bandwidth memory (HBM), or any combination thereof.
[0024] Although there are two semiconductor dies, the first semiconductor die 106 and the second semiconductor die 112, in Figure 1 As shown, but possibly more than two semiconductor dies, a stacked structure may be used. For example, a stacked structure may include three semiconductor dies stacked vertically. Alternatively, a stacked structure may include four semiconductor dies, with two semiconductor dies stacked vertically above one semiconductor die, and another semiconductor die disposed above that semiconductor die and adjacent to the two semiconductor dies. In some embodiments, the stacked structure may also include one or more passive components (not shown), such as resistors, capacitors, inductors, or combinations thereof.
[0025] Reference Figure 1 The first semiconductor die 106 includes a plurality of vias 108 electrically coupled to the first redistribution layer 102. The vias 108 can be formed of a conductive material such as a metal. For example, the vias 108 can be formed of copper. Figure 1 In the first semiconductor die 106, the via 108 has substantially vertical sidewalls and extends from the top surface to the bottom surface of the first semiconductor die 106, but this disclosure is not limited thereto. The via 108 in the first semiconductor die 106 may have other configurations and numbers.
[0026] In some embodiments, the first package structure 100a includes a third rewiring layer 110 located between the first rewiring layer 102 and the second rewiring layer 124. For example... Figure 1As shown, the third wiring layer 110 can be disposed between the top surface of the first semiconductor die 106 and the bottom surface of the second semiconductor die 112, and can extend beyond the sidewalls of the first semiconductor die 106 and the second semiconductor die 112. The third wiring layer 110 can be electrically coupled to the first semiconductor die 106, the via 108 in the first semiconductor die 106, and the second semiconductor die 112.
[0027] The material of the third wiring layer 110 can be similar to that of the first wiring layer 102, and will not be described in detail here. Figure 1 As shown, the first rewiring layer 102 includes more conductive layers and passivation layers than the third rewiring layer 110, and the third rewiring layer 110 includes more conductive layers and passivation layers than the second rewiring layer 124, but this disclosure is not limited thereto. For example, the second rewiring layer 124 may include more conductive layers and passivation layers than the first rewiring layer 102 and the third rewiring layer 110.
[0028] By setting a third wiring layer 110, additional routing channels can be formed between the first semiconductor die 106 and the second semiconductor die 112. This improves layout flexibility and saves die bump fan-out width, as described below and in Figures 2A-2D As shown.
[0029] Figure 2A This is a cross-sectional view of a stack structure 200a in a semiconductor package structure 100 according to some embodiments. For simplicity, only a portion of the stack structure 200a is shown. In some embodiments, the stack structure 200a includes a first semiconductor die 106 and a second semiconductor die 112.
[0030] The first semiconductor die 106 has an active surface 106a and a backside surface 106b opposite to the active surface 106a. The second semiconductor die 112 has an active surface 112a and a backside surface 112b opposite to the active surface 112a. The first semiconductor die 106 and the second semiconductor die 112 can be stacked face-to-face (FtF). That is, the active surface 112a of the second semiconductor die 112 is close to the active surface 106a of the first semiconductor die 106.
[0031] Reference Figure 2A The first intellectual property (IP) core 101 and the second IP core 103 can be disposed on the active surface 106a of the first semiconductor die 106. In some embodiments, the first IP core 101 is used to control the second package structure 100b (e.g., Figure 1As shown), the second IP core 103 is used to control other components electrically coupled to the first rewiring layer 102.
[0032] According to some embodiments, since the third wiring layer 110 is disposed between the first semiconductor die 106 and the second semiconductor die 112, additional routing paths can be formed between them. Therefore, signals from the first IP core 101 and signals from the second IP core 103 can pass through different routing paths, such as path 101P and path 103P respectively. Specifically, the routing path of the first IP core 101 (represented by path 101P) can pass through the third wiring layer 110 (e.g., ...). Figure 1 As shown), the routing channel of the second IP core 103 (represented by path 103P) can pass through the via 108 in the first semiconductor die 106 and the first redistribution layer 102 (as shown). Figure 1 (As shown).
[0033] That is, compared to the first IP core 101 and the second IP core 103, whose routing paths both pass through the first redistribution layer 102, this invention provides separate routing paths for the first IP core 101 and the second IP core 103. In this way, these routing paths can be optimized individually to meet different routing requirements. Furthermore, the routing path of the first IP core 101 does not affect the routing path of the second IP core 103, thereby increasing the flexibility of routing design.
[0034] like Figure 2A As shown, the first IP core 101 and the second IP core 103 are arranged separately side by side, but this disclosure is not limited thereto. For example, according to some other embodiments, the first IP core 101 may be placed within the second IP core 103. Alternatively, the first IP core 101 and the second IP core 103 may be located near different edges of the first semiconductor die 102. Furthermore, there may be more than two IP cores.
[0035] Figure 2B This is a cross-sectional view of a stack structure 200b in a semiconductor package structure 100 according to some embodiments. For simplicity, only a portion of the stack structure 200b is shown. The stack structure 200b may include... Figure 2A The stack structure 200a shown contains the same or similar components, and for simplicity, those components will not be discussed in detail. In the following embodiment, the first IP core 101 is disposed on the active surface 112a of the second semiconductor die 112, while the second IP core 103 is disposed on the active surface 106a of the first semiconductor die 106.
[0036] like Figure 2BAs shown, signals from the first IP core 101 and signals from the second IP core 103 can use different routing paths, such as path 101P and path 103P respectively. Specifically, the routing path of the first IP core 101 (represented by path 101P) can pass through the third wiring layer 110 (e.g., Figure 1 As shown), the routing channel of the second IP core 103 (represented by path 103P) can pass through the via 108 in the first semiconductor die 106 and the first redistribution layer 102 (as shown). Figure 1 (As shown).
[0037] Figure 2C This is a cross-sectional view of a stack structure 200c in a semiconductor package structure 100 according to some embodiments. For simplicity, only a portion of the stack structure 200c is shown. The stack structure 200c may include... Figure 2A The components shown in the stack structure 200a are the same as or similar to those in the stack structure, and for simplicity, those components will not be discussed in detail. In the following embodiments, the first semiconductor die 106 and the second semiconductor die 112 may be face-to-back (FtB) stacked. That is, the active surface 112a of the second semiconductor die 112 is close to the rear surface 106b of the first semiconductor die 106.
[0038] like Figure 2C As shown, the first IP core 101 and the second IP core 103 are disposed on the active surface 106a of the first semiconductor die 106. Signals from the first IP core 101 and signals from the second IP core 103 can pass through different routing paths. For example, they are indicated by path 101P and path 103P, respectively. Specifically, the routing path of the first IP core 101 (represented by path 101P) can pass through the via 108 and the third redistribution layer 110 in the first semiconductor die 106 (e.g., via 108 and via 103). Figure 1 As shown), and the routing channel of the second IP core 103 (represented by path 103P) can pass through the first rewiring layer 102 (as shown). Figure 1 (As shown).
[0039] Figure 2D This is a cross-sectional view of a stack structure 200d in a semiconductor package structure 100 according to some embodiments. For simplicity, only a portion of the stack structure 200d is shown. The stack structure 200d may include... Figure 2A The stack structure 200a shown contains the same or similar components, and for simplicity, those components will not be discussed in detail. In the following embodiment, the first IP core 101 is disposed on the active surface 112a of the second semiconductor die 112, while the second IP core 103 is disposed on the active surface 106a of the first semiconductor die 106.
[0040] like Figure 2D As shown, signals from the first IP core 101 and signals from the second IP core 103 can use different routing paths, such as path 101P and path 103P respectively. Specifically, the routing path of the first IP core 101 (represented by path 101P) can pass through the third wiring layer 110 (e.g., Figure 1 As shown), the routing path of the second IP core 103 (represented by path 103P) can pass through the first rewiring layer 102 (as shown). Figure 1 (As shown).
[0041] Reference Figure 1 According to some embodiments, a plurality of conductive structures 114 are formed between the third wiring layer 110 and the second semiconductor die 112. The conductive structures 114 can electrically couple the second semiconductor die 112 to the third wiring layer 110. Depending on the routing channel design and the location of the IP core, the routing channel may also include the conductive structures 114.
[0042] In some embodiments, the conductive structure 114 includes a conductive material, such as a metal. The conductive structure 114 may include microbumps, controlled-collapse chip connection (C4) bumps, ball grid array (BGA) balls, or combinations thereof.
[0043] In some embodiments, an underfill material 116 is formed between the second semiconductor die 112 and the third redistribution layer 110, filling the gaps between the conductive structures 114 to provide structural support. The underfill material 116 may surround each conductive structure 114. In some embodiments, the underfill material 116 is formed of a polymer, such as epoxy resin. After the conductive structures 114 are formed between the second semiconductor die 112 and the third redistribution layer 110, the underfill material 116 can be applied by capillary force. The underfill material 116 can then be cured by any suitable curing process.
[0044] like Figure 1 As shown, the first package structure 100a includes a molding material 118 surrounding the second semiconductor die 112 and the underfill material 116, and covering a portion of the top surface of the third redistribution layer 110. In some embodiments, the molding material 118 is adjacent to the sidewalls of the second semiconductor die 112 and the top surface of the third redistribution layer 110. The molding material 118 can protect the second semiconductor die 112 from environmental influences, thereby preventing damage to the second semiconductor die 112 due to, for example, stress, chemicals and / or moisture.
[0045] The molding material 118 may include non-conductive materials, such as moldable polymers, epoxy resins, resins, or combinations thereof. In some embodiments, the molding material 118 is applied in a liquid or semi-liquid form and then cured by any suitable curing process, such as a thermosetting process, a UV curing process, or a combination thereof. The molding material 118 may be shaped or molded using a mold (not shown).
[0046] The molding material 118 can then be partially removed using a planarization process such as chemical mechanical polishing (CMP) until the top surface of the second semiconductor die 112 is exposed. In some embodiments, the top surface of the molding material 118 and the top surface of the second semiconductor die 112 are substantially coplanar. Figure 1 As shown, the sidewalls of the molding material 118 can be coplanar with the sidewalls of the first semiconductor die 106.
[0047] In some embodiments, a plurality of conductive pillars 120 are formed adjacent to the stack structure (including the first semiconductor die 106 and the second semiconductor die 112) and the molding material 118. The conductive pillars 120 may include metal pillars, such as copper pillars. In some embodiments, the conductive pillars 120 are formed by an electroplating process or any other suitable process. Figure 1 As shown, the conductive post 120 may have substantially vertical sidewalls.
[0048] like Figure 1 As shown, the conductive post 120 can be disposed between the first rewiring layer 102 and the second rewiring layer 124, and can also be disposed on the top and bottom surfaces of the third rewiring layer 110. The conductive post 120 can be electrically coupled to the first rewiring layer 102, the second rewiring layer 124, and the third rewiring layer 110.
[0049] The position and number of conductive posts 120 can be adjusted according to the wiring design of the first package structure 100a. For example, in some other embodiments, the conductive posts 120 are disposed between the second redistribution layer 124 and the third redistribution layer 110, instead of between the first redistribution layer 102 and the third redistribution layer 110. The second redistribution layer 124 is electrically coupled to the third redistribution layer 110 through the conductive posts 120, and the third redistribution layer 110 is electrically coupled to the first redistribution layer 102 through the vias 108 in the first semiconductor die 106.
[0050] like Figure 1 As shown, four conductive posts 120 are disposed on opposite sides of the stack structure, but this disclosure is not limited thereto. For example, the number of conductive posts 120 on opposite sides of the stack structure may be different. Alternatively, the conductive posts 120 may be disposed on one side of the stack structure.
[0051] like Figure 1As shown, the first package structure 100a includes molding material 122 surrounding a stack structure (including a first semiconductor die 106 and a second semiconductor die 112), molding material 118, and conductive pillars 120. The molding material 122 can fill the conductive pillars 120 and the gaps between the stack structure and the conductive pillars 120.
[0052] like Figure 1 As shown, molding material 122 is adjacent to the sidewalls of the first semiconductor die 106 and molding material 118, and covers the top surface of the first redistribution layer 102, the bottom surface of the second redistribution layer 124, and the top and bottom surfaces of the third redistribution layer 110. Molding material 122 can protect the stack structure and conductive pillars 120 from environmental influences, thereby preventing damage to the stack structure and conductive pillars 120 due to, for example, stress, chemicals, and / or moisture.
[0053] In some embodiments, the molding material 122 comprises a non-conductive material, such as a moldable polymer, epoxy resin, resin, or a combination thereof. In some embodiments, the molding material 122 is applied in a liquid or semi-liquid form and then cured by any suitable curing process, such as a thermosetting process, a UV curing process, or a combination thereof. The molding material 122 may be shaped or molded using a mold (not shown).
[0054] The molding material 122 can then be partially removed using a planarization process such as chemical mechanical polishing (CMP) until the top surface of the conductive pillar 120 is exposed. In some embodiments, the top surfaces of the molding material 122 and the conductive pillar 120 are substantially coplanar, as shown in the figure. Figure 1 As shown, the sidewalls of the molding material 122 may be coplanar with at least one of the sidewalls of the first rewiring layer 102, the second rewiring layer 124, and the third rewiring layer 110.
[0055] like Figure 1 As shown, the second redistribution layer 124 can be disposed above the stack structure and cover the top surface of the second semiconductor die 112, the top surface of the conductive pillar 120 and the top surface of the molding material 122.
[0056] like Figure 1 As shown, according to some embodiments, a second package structure 100b is disposed above a first package structure 100a and electrically coupled to a second rewiring layer 124 via a plurality of conductive structures 126. In some embodiments, the conductive structures 126 comprise conductive materials, such as metals. The conductive structures 126 may include microbumps, controlled collapse chip connection (C4) bumps, ball grid array (BGA) balls, or combinations thereof.
[0057] like Figure 1As shown, according to some embodiments, the second packaging structure 100b includes a substrate 128. The substrate 128 may have a wiring structure therein. In some embodiments, the wiring structure of the substrate 128 includes a conductive layer, conductive vias, conductive pillars, etc., or combinations thereof. The wiring structure of the substrate 128 may be formed of a metal, such as copper, titanium, tungsten, aluminum, etc., or combinations thereof.
[0058] The wiring structure of substrate 128 can be disposed in an inter-metal dielectric (IMD) layer. In some embodiments, the IMD layer can be formed of an organic material (e.g., a polymer substrate), an organic material (e.g., silicon nitride, silicon oxide, silicon oxynitride, etc.), or a combination thereof. Any desired semiconductor component can be formed in and on substrate 128. However, for the sake of simplicity, only a flat substrate 128 is shown.
[0059] like Figure 1 As shown, according to some embodiments, the second package structure 100b includes semiconductor components 130 and 132 above a substrate 128. Semiconductor components 130 and 132 may include memory dies, such as dynamic random access memory (DRAM). For example, semiconductor components 130 and 132 may be double data rate (DDR) synchronous dynamic random access memory (SDRAM) dies for mobile systems. In embodiments where the second package structure 100b includes a memory device, the IP core for the second package structure 100b (e.g., first IP core 101) may be referred to as a memory IP core.
[0060] Semiconductor components 130 and 132 may include the same or different devices. In some embodiments, the second package structure 100b also includes one or more passive components (not shown), such as resistors, capacitors, inductors, or combinations thereof.
[0061] The first IP core 101 in the stack structure (e.g.) Figures 2A-2D (As shown) can be electrically coupled to the second package structure 100b through a first routing channel, which includes a third wiring layer 110, conductive pillars 120, and a second wiring layer 124. The second IP core 103 in the stack structure (as shown) Figures 2A-2D (As shown) can be electrically coupled to the conductive structure 104 through a second trace channel including a first redistribution layer 110. In an embodiment, depending on the location of the IP core, as described above, the first or second trace channel may further include vias 108 and / or conductive structures 114 in the first semiconductor die 106.
[0062] In other words, the routing path between the IP core and the second package structure 100b can be separated from other routing paths, such as the routing path between another IP core and the conductive structure 104. Specifically, according to some embodiments, the routing path between the IP core and the second package structure 100b is electrically insulated from the first redistribution layer 110. Therefore, different routing paths can be optimized separately, increasing the flexibility of channel design.
[0063] Figure 3 This is a cross-sectional view of a semiconductor package structure 300 according to some embodiments of the present disclosure. It should be noted that the semiconductor package structure 300 may include... Figure 1 The semiconductor package structure 100 shown contains the same or similar components. For simplicity, these components will not be discussed in detail. In the following embodiments, the wiring channels include conductive pillars 134 above the first semiconductor die 106 and adjacent to the second semiconductor die 112.
[0064] According to some embodiments, the conductive pillar 134 is electrically coupled to the second redistribution layer 124, the first semiconductor die 106, and the via 108 in the first semiconductor die 106. In an embodiment where the IP core for the second package structure 100b is formed at the bottom of the first semiconductor die 106, the wiring path between the IP core and the second package structure 100b may include the via 108, the conductive pillar 134, and the second redistribution layer 124 in the first semiconductor die 106. In an embodiment where the IP core for the second package structure 100b is formed at the top of the first semiconductor die 106, the wiring path between the IP core and the second package structure 100b includes the conductive pillar 134 and the second redistribution layer 124.
[0065] The conductive post 134 may comprise a metal post, such as a copper post. In some embodiments, the conductive post 134 is formed by an electroplating process or any other suitable process. The conductive post 134 may have substantially vertical sidewalls. Figure 3 As shown, the conductive post 134 may be surrounded by molding material 118. The conductive post 134 may have substantially vertical sidewalls and may extend from the bottom surface of molding material 118 to the top surface of molding material 118.
[0066] The position and number of conductive pillars 134 can be adjusted according to the wiring design of the first package structure 100a. For example, more than one conductive pillar 134 can be disposed above the first semiconductor die 106, and can be disposed on one side adjacent to or opposite to the second semiconductor die 112. Furthermore, the semiconductor package structure 300 may also include one or more redistribution layers, such as... Figure 1 The third wiring layer 110 in the process.
[0067] Figure 4This is a cross-sectional view of a semiconductor package structure 400 according to some embodiments of the present disclosure. It should be noted that the semiconductor package structure 400 may include, and Figure 1 The semiconductor package structure 100 shown contains the same or similar components. For simplicity, these components will not be discussed in detail. In the following embodiment, the wiring channel includes a via 136 in the second semiconductor die 112.
[0068] The via 136 can be electrically coupled to the second redistribution layer 124, the conductive structure 114, the first semiconductor die 106, and the via 108 in the first semiconductor die 106. In an embodiment where the IP core for the second package structure 100b is formed on the bottom of the first semiconductor die 106, the routing path between the IP core and the second package structure 100b may include the via 108, the conductive structure 114, the via 136, and the second redistribution layer 124 in the first semiconductor die 106. In an embodiment where the IP core for the second package structure 100b is formed on the top of the first semiconductor die 106, the routing path between the IP core and the second package structure 100b may include the conductive structure 114, the via 136, and the second redistribution layer 124.
[0069] In an embodiment where the IP core for the second package structure 100b is formed at the bottom of the second semiconductor die 112, the wiring channel between the IP core and the second package structure 100b may include a via 136 and a second redistribution layer 124. In an embodiment where the IP core for the second package structure 100b is formed at the top of the second semiconductor die 112, the wiring channel between the IP core and the second package structure 100b may include the second redistribution layer 124, and the via 136 may be omitted.
[0070] In these embodiments, the routing path between the second redistribution layer 124 and the IP core does not extend beyond the first semiconductor die 106 and the second semiconductor die 112. Specifically, the routing path between the second redistribution layer 124 and the IP core passes through the area shielded by the first semiconductor die 106 and / or the second semiconductor die 112.
[0071] The through-hole 136 can be formed of any conductive material, such as metal. For example, the through-hole 136 can be formed of copper. Figure 4 As shown, the via 136 may have substantially vertical sidewalls and may extend from the top surface of the second semiconductor die 112 to the bottom surface of the second semiconductor die 112, but this disclosure is not limited thereto. The via 136 in the second semiconductor die 112 may have other configurations.
[0072] The location and number of vias 136 can be adjusted according to the wiring design of the first package structure 100a. For example, more than one via 136 can be provided in the second semiconductor die 112. Alternatively, the semiconductor package structure 400 may also include one or more redistribution layers (e.g., Figure 1 The third wiring layer 110) and / or one or more conductive pillars (e.g. Figure 3 (Conductive post 134 in the middle).
[0073] Figure 5 This is a cross-sectional view of a semiconductor package structure 500 according to some embodiments of the present disclosure. It should be noted that the semiconductor package structure 500 may include... Figure 1 The semiconductor package structure 100 shown contains the same or similar components. For simplicity, these components will not be discussed in detail. In the following embodiment, a larger first semiconductor die 106 is disposed on a smaller second semiconductor die 112.
[0074] like Figure 5 As shown, the second semiconductor die 112 may include a plurality of vias 138, which can be electrically coupled to vias 108 in the first redistribution layer 102, the conductive structure 114, and the first semiconductor die 106. The vias 138 can be formed of any conductive material, such as a metal. For example, the vias 138 can be formed of copper. Figure 5 As shown, each of the vias 138 may have a substantially vertical sidewall and may extend from the top surface of the second semiconductor die 112 to the bottom surface of the second semiconductor die 112. However, the vias 138 in the second semiconductor die 112 may have other configurations and numbers.
[0075] The via 138 can be electrically coupled to the first redistribution layer 102, the conductive structure 114, the first semiconductor die 106, and the via 108 in the first semiconductor die 106. In an embodiment where the IP core for the second package structure 100b is formed at the bottom of the second semiconductor die 112, the wiring path between the IP core and the second package structure 100b may include the via 138 in the second semiconductor die 112, the conductive structure 114, the via 108 in the first semiconductor die 106, and the second redistribution layer 124. In an embodiment where the IP core for the second package structure 100b is formed at the top of the second semiconductor die 112, the wiring path between the IP core and the second package structure 100b may include the conductive structure 114, the via 108 in the first semiconductor die 106, and the second redistribution layer 124.
[0076] In an embodiment where the IP core for the second package structure 100b is formed at the bottom of the first semiconductor die 106, the wiring channel between the IP core and the second package structure 100b may include a via 108 and a second redistribution layer 124 in the first semiconductor die 106. In an embodiment where the IP core for the second package structure 100b is formed at the top of the first semiconductor die 106, the wiring channel between the IP core and the second package structure 100b may include the second redistribution layer 124, and the via 108 may be omitted.
[0077] In these embodiments, the routing path between the second redistribution layer 124 and the IP core does not extend beyond the first semiconductor die 106 and the second semiconductor die 112. Specifically, the routing path between the second redistribution layer 124 and the IP core passes through the area shielded by the first semiconductor die 106 and / or the second semiconductor die 112.
[0078] like Figure 5 As shown, the first package structure 100a may include one or more conductive pillars 140 below the first semiconductor die 106 and adjacent to the second semiconductor die 112. The conductive pillars 140 are optional. The conductive pillars 140 may include metal pillars, such as copper pillars. In some embodiments, the conductive pillars 140 are formed by an electroplating process or any other suitable process.
[0079] The conductive post 140 can be electrically coupled to the first redistribution layer 102, the first semiconductor die 106, and the via 108 of the first semiconductor die 106. (See reference...) Figure 5 Each conductive post 140 may have substantially vertical sidewalls. The conductive post 140 may be surrounded by molding material 118 and extend from the top surface of molding material 118 to the bottom surface of molding material 118.
[0080] The position and number of conductive posts 140 can be adjusted according to the wiring design of the first package structure 100a. For example... Figure 5 As shown, two conductive pillars 140 are disposed on opposite sides of the adjacent second semiconductor bare die 112, but this disclosure is not limited thereto. For example, the number of conductive pillars 140 on opposite sides of the stack structure may be different. Alternatively, the conductive pillars 140 may be disposed on one side of the stack structure.
[0081] Figure 6 This is a cross-sectional view of a semiconductor package structure 600 according to some embodiments of the present disclosure. It should be noted that the semiconductor package structure 600 may include... Figure 1The semiconductor package structure 100 shown contains the same or similar components. For simplicity, these components will not be discussed in detail. In the following embodiments, the stack structure includes a plurality of semiconductor components 142, 144, 146 located above the first semiconductor die 106 and adjacent to the second semiconductor die 112.
[0082] Semiconductor components 142, 144, and 146 may include active components. For example, semiconductor components 142, 144, and 146 may each independently include a system-on-a-chip (SoC), a logic device, a memory device, a radio frequency (RF) device, or any combination thereof. For example, semiconductor components 142, 144, and 146 may each independently include a microcontroller unit (MCU) device, a microprocessor unit (MPU) device, a power management integrated circuit (PMIC) device, a global positioning system (GPS) device, a central processing unit (CPU) die, a graphics processing unit (GPU) die, an input / output (I / O) die, a dynamic random access memory (DRAM) IP core, static random access memory (SRAM), high-bandwidth memory (HBM), or any combination thereof.
[0083] In some other embodiments, semiconductor components 142, 144, and 146 include passive components, such as resistors, capacitors, inductors, or combinations thereof. Semiconductor components 142, 144, and 146 may include the same or different means.
[0084] Semiconductor components 142, 144, and 146 may be electrically coupled to the first semiconductor die 106. Each of semiconductor components 142, 144, and 146 may be surrounded and covered by molding material 118. It should be noted that the positions and numbers of semiconductor components 142, 144, and 146, the first semiconductor die 106, and the second semiconductor die 112 are merely exemplary and this disclosure is not limited thereto.
[0085] For example, semiconductor components 142, 144, and 146 can be stacked vertically. Alternatively, the stack structure may include two semiconductor components stacked vertically. In some other embodiments, the stack structure may include four semiconductor components, with two semiconductor components stacked vertically above one semiconductor component, and another semiconductor component disposed above and adjacent to the two semiconductor components.
[0086] Based on the routing design of the first package structure 100a, the semiconductor package structure 600 may further include one or more redistribution layers (e.g., ...). Figure 1 The third wiring layer 110 in the middle), one or more conductive pillars (e.g. Figure 3 Conductive pillar 134 in the semiconductor chip and / or one or more vias in the semiconductor chip (e.g., conductive pillar 134) ... Figure 4 (Through hole 136 in the middle).
[0087] Figure 7 This is a cross-sectional view of a semiconductor package structure 700 according to some embodiments of the present disclosure. It should be noted that the semiconductor package structure 700 may include... Figure 6 The semiconductor package structure 600 shown contains the same or similar components. For simplicity, these components will not be discussed in detail. In the following embodiments, the stack structure includes a plurality of semiconductor components 142, 144, 146 below the first semiconductor die 106 and adjacent to the second semiconductor die 112.
[0088] Semiconductor components 142, 144, and 146 can be similar to Figure 6 The semiconductor components 142, 144, and 146 are not described in detail here. Semiconductor components 142, 144, and 146 are electrically coupled to the first semiconductor die 106. Each of the semiconductor components 142, 144, and 146 may be surrounded and covered by molding material 118. It should be noted that the number and position of the semiconductor components 142, 144, 146, the first semiconductor die 106, and the second semiconductor die 112 in this embodiment are illustrative only, and this disclosure is not limited thereto.
[0089] For example, semiconductor components 142, 144, and 146 can be stacked vertically. Alternatively, the stack structure may include two semiconductor components stacked vertically. In some other embodiments, the stack structure may include four semiconductor components, with two semiconductor components stacked vertically above one semiconductor component, and another semiconductor component disposed above and adjacent to the two semiconductor components.
[0090] According to the routing design of the first package structure 100a, the semiconductor package structure 700 may also include one or more redistribution layers (e.g., ...). Figure 1 The third wiring layer 110 in the middle), one or more conductive pillars (e.g. Figure 3 Conductive pillars 134 in the semiconductor die and / or one or more vias in the semiconductor die (e.g., conductive pillars 134) ... Figure 4 (Through hole 136 in the middle).
[0091] In summary, by incorporating one or more redistribution layers, one or more conductive pillars, and / or one or more vias in the semiconductor die within a package structure, a separate routing path can be established from an IP core in one package structure to another. Therefore, the routing path can be optimized individually, increasing the flexibility of channel design.
[0092] While the invention has been described by way of example and preferred embodiments, it should be understood that the invention is not limited to the disclosed embodiments. Rather, it is intended to cover various modifications and similar arrangements (which will be apparent to those skilled in the art). Therefore, the scope of the appended claims should be given the broadest interpretation to cover all such modifications and similar arrangements.
Claims
1. A semiconductor package structure, comprising: One front-side heavy wiring layer; A stack structure is disposed above the front redistribution layer and includes a first semiconductor die and a second semiconductor die located above the first semiconductor die; A secondary routing layer is placed on top of this stack structure; A first IP core is disposed in the stack structure and electrically coupled to the front redistribution layer through a first trace channel; as well as A second IP core is disposed in the stack structure and electrically coupled to the rear redistribution layer through a second trace channel, wherein the second trace channel is separate from the first trace channel and electrically insulated from the front redistribution layer; The second wiring channel includes: A conductive pillar is adjacent to the stack structure and electrically coupled to the rear redistribution layer; as well as A third wiring layer is located between the top surface of the first semiconductor die and the bottom surface of the second semiconductor die and is electrically coupled to the conductive pillar.
2. The semiconductor packaging structure as claimed in claim 1 further includes a packaging structure disposed above the rear redistribution layer and electrically coupled to the second IP core through the second trace channel.
3. The semiconductor packaging structure as claimed in claim 1, wherein the second wiring channel further includes a plurality of through-holes located in the first semiconductor die.
4. The semiconductor package structure of claim 1, further comprising a molding material surrounding the conductive pillar and the stack structure, wherein the sidewalls of the molding material are coplanar with the sidewalls of the third redistribution layer.
5. The semiconductor package structure of claim 1, wherein the second trace channel includes a second conductive post, the second conductive post being disposed above and adjacent to the first semiconductor die.
6. The semiconductor packaging structure of claim 5 further includes a molding material surrounding the second conductive pillar and the second semiconductor die, wherein the sidewalls of the molding material are coplanar with the sidewalls of the first semiconductor die.
7. The semiconductor package structure of claim 5, wherein the second wiring channel further includes a through-hole located in the first semiconductor die.
8. The semiconductor package structure of claim 1, wherein the second wiring channel includes a first via in the second semiconductor die.
9. The semiconductor package structure of claim 8, wherein the second wiring channel further includes a second via located in the first semiconductor die.
10. The semiconductor package structure of claim 1, wherein the second trace passes through a region shielded by the first semiconductor die and / or the second semiconductor die.
11. A semiconductor wiring structure, comprising: A first package structure having a front side and a rear side, and including a stack structure having a first IP core and a second IP core; A first routing channel electrically couples the first IP core to a first rewiring layer located on the front side of the first package structure; as well as A second trace independently electrically couples the second IP core to a second rewiring layer located on the rear side of the first package structure, wherein the second trace is separate from the first trace and electrically insulated from the first rewiring layer; The second wiring channel includes: A conductive pillar, adjacent to the stack structure and electrically coupled to the second wiring layer; and A third wiring layer is located between the top surface of a first semiconductor die and the bottom surface of a second semiconductor die and is electrically coupled to the conductive pillar. The stack structure includes a first semiconductor die and a second semiconductor die stacked vertically, and the first IP core and the second IP core are each independently disposed in the first semiconductor die or the second semiconductor die.
12. The semiconductor wiring structure of claim 11, further comprising a second packaging structure disposed on the second wiring layer, wherein the second packaging structure receives a control signal from the second IP core through the second wiring channel.
13. The semiconductor wiring structure of claim 11, wherein the second wiring channel includes a via located in the first semiconductor die and electrically coupling the second semiconductor die to the second rewiring layer.