Display substrate and manufacturing method thereof, and display device

Abstract

The embodiment of the present application provides a display substrate and a method for manufacturing the same, and a display device, wherein the display substrate includes a substrate, a first source and drain electrode layer, a second source and drain electrode layer, and a planarization layer. The first source and drain electrode layer is located on one side of the substrate; the second source and drain electrode layer is located on the side of the first source and drain electrode layer away from the substrate, and includes a first portion, a second portion, and a third portion, wherein the first portion is connected to the third portion through the second portion, and the first portion and the third portion are both arranged parallel to the substrate, the first portion is connected to the first source and drain electrode layer, and the second portion is at a preset angle to the substrate; the planarization layer is located on the side of the second source and drain electrode layer away from the substrate, and the planarization layer at least covers the edge area of ​​the third portion, and exposes part of the third portion, and the length of the exposed third portion along the direction parallel to the substrate is a preset length. By adopting the embodiment of the present application, the generation of a V-groove structure can be avoided, stress concentration can be weakened, and the risk of peeling and the generation of progressive black spots can be reduced.

Description

Technical Field

[0001] The present application relates to the field of display technology, and more specifically, to a display substrate and a manufacturing method thereof, and a display device. Background Art

[0002] The FOP (FPC On Panel) area is located in the non-display area of ​​the display substrate. The FOP area is located in the bending area. Due to stress concentration, there is a risk of film peeling. Under the action of stress, the TLD (insulating layer) may crack, and water vapor enters the water-absorbing PLN (planarization layer) film through the cracks, resulting in the generation of GDS (Growing dark spots). Summary of the invention

[0003] In view of the shortcomings of the existing methods, the present application proposes a display substrate and a manufacturing method thereof, and a display device to solve the technical problems existing in the related technologies that easily lead to the risk of film peeling and the generation of GDS (progressive black spots).

[0004] In a first aspect, an embodiment of the present application provides a display substrate, including a display area and a non-display area located at least on one side of the display area, wherein the non-display area includes:

[0005] substrate;

[0006] A first source and drain electrode layer, located on one side of the substrate;

[0007] A second source-drain electrode layer is located on a side of the first source-drain electrode layer away from the substrate, and includes a first portion, a second portion and a third portion, wherein the first portion is connected to the third portion through the second portion, the first portion and the third portion are both arranged parallel to the substrate, the first portion is connected to the first source-drain electrode layer, and the second portion is at a preset angle to the substrate;

[0008] The planarization layer is located on the side of the second source and drain electrode layer away from the substrate. The planarization layer at least covers the edge area of ​​the third portion and exposes a portion of the third portion. The length of the exposed third portion along the direction parallel to the substrate is a preset length.

[0009] In a possible implementation, the preset length is not less than 2 micrometers.

[0010] In a possible implementation, the second part includes a first sub-part and a second sub-part, and the third part includes a third sub-part and a fourth sub-part;

[0011] The third sub-portion and the fourth sub-portion are located on different sides of the center line of the first source-drain electrode layer, the third sub-portion is connected to the first portion through the first sub-portion, and the fourth sub-portion is connected to the first portion through the second sub-portion;

[0012] The planarization layer at least covers an edge region of the third sub-portion and exposes a portion of the third sub-portion, and the planarization layer at least covers an edge region of the fourth sub-portion and exposes a portion of the fourth sub-portion;

[0013] The exposed third sub-portion and the exposed fourth sub-portion are symmetrical with respect to a center line of the first source-drain electrode layer.

[0014] In a possible implementation manner, the third sub-portion covered by the planarization layer and the fourth sub-portion covered by the planarization layer are symmetrical about the center line of the first source and drain layer.

[0015] In a possible implementation, the method further includes:

[0016] The insulating layer is located on a side of the planarization layer away from the substrate and covers the exposed third portion. At a position where the insulating layer contacts the exposed third portion, a partial area of ​​the insulating layer is parallel to the substrate.

[0017] In a possible implementation, the method further includes:

[0018] The metal layer is located on a side of the insulating layer away from the substrate and is connected to the first portion through a via hole penetrating the insulating layer;

[0019] At a position where the insulating layer contacts the exposed third portion, a partial area of ​​the metal layer is parallel to the substrate direction.

[0020] In a possible implementation, the method further includes:

[0021] A passivation layer, located between the first source-drain electrode layer and the second source-drain electrode layer;

[0022] The interlayer dielectric layer is located on a side of the first source and drain electrode layer close to the substrate.

[0023] In a second aspect, an embodiment of the present application provides a display device, comprising a display substrate as described in any one of the first aspects.

[0024] In a third aspect, an embodiment of the present application provides a method for manufacturing a display substrate, comprising:

[0025] providing a substrate;

[0026] A first source-drain electrode layer, a second source-drain electrode layer and a planarization layer are sequentially formed on one side of the substrate by a patterning process;

[0027] Among them: the second source and drain layer is located on the side of the first source and drain layer away from the substrate, and includes a first part, a second part and a third part. The first part is connected to the third part through the second part. The first part and the third part are both arranged parallel to the substrate. The first part is connected to the first source and drain layer, and the second part is at a preset angle to the substrate; the planarization layer at least covers the edge area of ​​the third part and exposes part of the third part. Along the direction parallel to the substrate, the length of the exposed third part is a preset length.

[0028] In a possible implementation manner, after the planarization layer is formed, the method further includes:

[0029] An insulating layer and a metal layer are sequentially formed on a side of the planarization layer away from the substrate by a patterning process;

[0030] Before forming the first source and drain electrode layer on one side of the substrate, the method further includes:

[0031] An interlayer dielectric layer is formed on one side of the substrate by a patterning process;

[0032] After forming a first source and drain electrode layer on one side of the substrate, the method further includes:

[0033] A passivation layer is formed on the side of the first source and drain electrode layer away from the substrate through a patterning process.

[0034] The beneficial technical effects brought about by the technical solution provided by the embodiment of the present application include:

[0035] In the display substrate provided in the embodiment of the present application, part of the third portion of the second source and drain electrode layer is exposed through the planarization layer, and the length of the exposed third portion is a preset length, so that a flat area of ​​the preset length exists between the second portion of the second source and drain electrode layer and the planarization layer, thereby avoiding the generation of a V-shaped groove structure between the second portion and the planarization layer, which can not only ensure the coating of the side of the second source and drain electrode layer and avoid the generation of dark spots of residual silver precipitation at the anode, but also weaken stress concentration, thereby reducing the risk of peeling and the generation of progressive black spots (GDS).

[0036] Additional aspects and advantages of the present application will be partially given in the following description, which will become apparent from the following description, or will be understood through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0038] Figure 1 A cross-sectional schematic diagram of a display substrate in the related art;

[0039] Figure 2 A schematic cross-sectional view of a display substrate provided in an embodiment of the present application;

[0040] Figure 3 for Figure 1 A partial area enlarged schematic diagram;

[0041] Figure 4 for Figure 3 A partial area enlarged schematic diagram;

[0042] Figure 5 A schematic flow chart of a method for manufacturing a display substrate provided in an embodiment of the present application.

[0043] Reference numerals:

[0044] 10 - substrate, 20 - interlayer dielectric layer, 30 - first source and drain layer, 40 - passivation layer, 50 - second source and drain layer, 51 - first portion, 52 - second portion, 53 - third portion, 60 - planarization layer, 70 - insulating layer, 80 - metal layer. DETAILED DESCRIPTION

[0045] The present application is described in detail below, and examples of embodiments of the present application are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar components or components with the same or similar functions. In addition, if the detailed description of the known technology is unnecessary for the features of the present application shown, it will be omitted. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be interpreted as limiting the present application.

[0046] It will be understood by those skilled in the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those generally understood by those skilled in the art to which this application belongs. It should also be understood that terms such as those defined in general dictionaries should be understood to have meanings consistent with the meanings in the context of the relevant technology, and will not be interpreted with idealized or overly formal meanings unless specifically defined as here.

[0047] It will be understood by those skilled in the art that, unless expressly stated, the singular forms "one", "said", and "the" used herein may also include plural forms. It should be further understood that the term "comprising" used in the specification of the present application refers to the presence of the features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof. It should be understood that when we refer to an element as being "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be an intermediate element. In addition, the "connection" or "coupling" used herein may include wireless connection or wireless coupling. The term "and / or" used herein includes all or any unit and all combinations of one or more associated listed items.

[0048] The side of SD2 (second source and drain layer) in the FOP (FPC On Panel) area of ​​the non-display area of ​​the display substrate is exposed, and the Ag+ (silver ions) in the anode etching solution undergoes a substitution reaction with the exposed aluminum of SD2 (second source and drain layer), generating a large amount of Ag PT (Ag partical, silver impurities). The Ag PT (silver impurities) is dispersed in the solution and falls on the anode, causing the anode and cathode to overlap and cause dark spots.

[0049] It should be noted that there is no anode in the FOP area. When the AA area (display area) is subjected to anode etching, the etching solution contains silver ions, which replace the exposed side Al (aluminum) (the composition of the SD2 film layer is Ti / Al / Ti) of the SD2 (second source and drain layer) in the FOP area.

[0050] Since Ag (silver) is produced during the wet etching process, it will be randomly scattered on the screen with the liquid. There is no cathode and anode in the FOP area, and the cathode and anode overlap, that is, Ag (silver) falls on the anode in the light-emitting area. Even after the cathode is made, the cathode and anode are connected through Ag (silver), making them short (short-circuited) and producing dark spots.

[0051] In order to improve the dark spots of Ag (silver) precipitation, Figure 1 As shown, a planarization layer 60 is used to wrap the side of the second source-drain electrode layer 50 to prevent the side of the second source-drain electrode layer 50 from being exposed.

[0052] Although the planarization layer 60 can wrap the side of the second source-drain electrode layer 50, since the planarization layer 60 is close to the climbing area of ​​the second source-drain electrode layer 50 (i.e., the part of the second source-drain electrode layer 50 that has a certain inclination angle with the horizontal plane), a V-shaped groove structure (such as Figure 1The V-groove structure may cause stress concentration. After the insulating layer 70 and the metal layer 80 are subsequently manufactured, the insulating layer 70 and the metal layer 80 may be at risk of peeling. Furthermore, cracks may occur in the insulating layer 70 due to stress, and water vapor may enter the water-absorbing planarization layer 60 through the cracks, resulting in the generation of GDS (Growing dark spots). Progressive dark spots refer to black spots that may grow larger over time.

[0053] In addition, anode residue is easily generated at the V-groove structure, and the Ag (silver) of the anode residue migrates and overlaps with the adjacent Pin (pin), resulting in Pin Short (pin short circuit).

[0054] It should be noted that the Pin Short refers to the connection of the metal layer 80 (TMB) between Pins.

[0055] Figure 1 d0 is the length of the edge region of the second source / drain electrode layer 50 covered by the planarization layer 60 and the exposed portion of the second source / drain electrode layer 50 .

[0056] The present application provides a display substrate and a manufacturing method thereof, and a display device, aiming to solve the above technical problems of the related art.

[0057] The technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems are described in detail below with specific embodiments.

[0058] The embodiment of the present application provides a display substrate, including a display area and a non-display area located at least on one side of the display area. The specific area division of the display area and the non-display area is similar to the related art and will not be repeated here. Figure 2 As shown, the non-display area includes: a substrate 10 , a first source-drain electrode layer 30 , a second source-drain electrode layer 50 and a planarization layer 60 .

[0059] The first source-drain electrode layer 30 is located on one side of the substrate 10 .

[0060] The second source-drain electrode layer 50 is located on a side of the first source-drain electrode layer 30 away from the substrate 10, and includes a first portion 51, a second portion 52 and a third portion 53. The first portion 51 is connected to the third portion 53 through the second portion 52. The first portion 51 and the third portion 53 are both arranged parallel to the substrate 10. The first portion 51 is connected to the first source-drain electrode layer 30, and the second portion 52 is at a preset angle to the substrate 10.

[0061] The planarization layer 60 is located on the side of the second source and drain layer 50 away from the substrate 10. The planarization layer 60 at least covers the edge area of ​​the third portion 53 and exposes a portion of the third portion 53. The length of the exposed third portion 53 along the direction parallel to the substrate 10 is a preset length.

[0062] It should be noted that if Figure 2 As shown, the substrate 10 in the present application is located in the FOP (FPC On Panel) area of ​​the non-display area, and the FOP area is a bending area.

[0063] The substrate 10 is a flexible substrate.

[0064] In the display substrate provided in the embodiment of the present application, part of the third portion 53 of the second source / drain electrode layer 50 is exposed through the planarization layer 60, and the length of the exposed third portion 53 is a preset length, so that a flat area of ​​the preset length exists between the second portion 52 of the second source / drain electrode layer 50 and the planarization layer 60, thereby avoiding the generation of a V-shaped groove structure between the second portion 52 and the planarization layer 60, which can not only ensure the coating of the side of the second source / drain electrode layer 50 and avoid the generation of dark spots of silver precipitation of the anode residue, but also weaken stress concentration, thereby reducing the risk of peeling and the generation of progressive black spots (GDS). In addition, since the generation of the V-shaped groove structure between the second portion 52 and the planarization layer 60 is avoided, the generation of anode residue can be avoided, making it difficult for the anode to overlap with the adjacent pin, thereby avoiding pin short circuit.

[0065] In some embodiments, the predetermined length is not less than 2 microns.

[0066] Optionally, the preset length is 2 to 4 microns (including two end values ​​2 and 4).

[0067] In some embodiments, Figure 2 As shown, the second portion 52 includes a first sub-portion (the portion on the left side of the second portion 52 in the figure) and a second sub-portion (the portion on the right side of the second portion 52 in the figure), and the third portion 53 includes a third sub-portion (the portion on the left side of the third portion 53 in the figure) and a fourth sub-portion (the portion on the right side of the third portion 53 in the figure); the third sub-portion and the fourth sub-portion are located on opposite sides of the center line of the first source and drain layer 30, the third sub-portion is connected to the first portion 51 through the first sub-portion, and the fourth sub-portion is connected to the first portion 51 through the second sub-portion; the planarization layer 60 at least covers the edge area of ​​the third sub-portion and exposes part of the third sub-portion, and the planarization layer 60 at least covers the edge area of ​​the fourth sub-portion and exposes part of the fourth sub-portion; the exposed third sub-portion and the exposed fourth sub-portion are symmetrical about the center line of the first source and drain layer 30.

[0068] In some embodiments, Figure 2As shown, the third sub-portion covered by the planarization layer 60 and the fourth sub-portion covered by the planarization layer 60 are symmetrical about the center line of the first source and drain electrode layer 30 .

[0069] In some embodiments, Figure 2 As shown, the display substrate also includes an insulating layer 70, which is located on the side of the planarization layer 60 away from the substrate 10 and covers the exposed third portion 53. At the position where the insulating layer 70 contacts the exposed third portion 53, a partial area of ​​the insulating layer 70 is parallel to the direction of the substrate 10, that is, there is a horizontal portion of the insulating layer 70 at the position where the insulating layer 70 contacts the exposed third portion 53.

[0070] In some embodiments, Figure 2 As shown, the display substrate also includes a metal layer 80, which is located on a side of the insulating layer 70 away from the substrate 10 and is connected to the first portion 51 through a via hole penetrating the insulating layer 70; at the position where the insulating layer 70 contacts the exposed third portion 53, a partial area of ​​the metal layer 80 is parallel to the direction of the substrate 10, that is, there is a horizontal portion of the metal layer 80 at the position where the insulating layer 70 contacts the exposed third portion 53.

[0071] In the embodiment of the present application, the third portion 53 of the second source-drain electrode layer 50 is exposed through the planarization layer 60, and the length of the exposed third portion 53 is a preset length, that is, the side length (length in the horizontal direction) of the third portion 53 of the second source-drain electrode layer 50 is lengthened, so that the second portion 52 (i.e., the climbing area) of the second source-drain electrode layer 50 is staggered from the climbing areas of the insulating layer 70 and the metal layer 80, and the planarization layer 60 does not contact the climbing area of ​​the second source-drain electrode layer 50 (e.g., Figure 2 There is a planarization area of ​​length d1 between the planarization layer 60 and the climbing area of ​​the second source and drain electrode layer 50, so that a flat area (such as Figure 2 The V-shaped groove structure between the second portion 52 and the planarization layer 60 is avoided. This can not only ensure the coating of the side of the second source-drain electrode layer 50 and avoid the precipitation of dark spots of Ag (silver) residues from the anode, but also reduce stress concentration, thereby reducing the risk of peeling and progressive black spots (GDS). In addition, since the V-shaped groove structure between the second portion 52 and the planarization layer 60 is avoided, the anode residue can be avoided, making it difficult for the anode to overlap with the adjacent pin, thereby avoiding pin short circuit.

[0072] In one possible implementation, Figure 2As shown, the display substrate also includes: a passivation layer 40 and an interlayer dielectric layer 20, the passivation layer 40 is located between the first source and drain layer 30 and the second source and drain layer 50; the passivation layer 40 at least covers the edge area of ​​the first source and drain layer 30 and exposes a portion of the first source and drain layer 30; the interlayer dielectric layer 20 is located on the side of the first source and drain layer 30 close to the substrate 10.

[0073] Based on the same inventive concept, an embodiment of the present application provides a display device, including a display substrate provided in any of the above embodiments.

[0074] The display device may be an OLED display device, or may be a quantum dot light emitting diode (QLED) or a micro light emitting diode (Micro LED) display device, etc.

[0075] The display device provided in the embodiment of the present application has the same inventive concept and the same beneficial effects as the previous embodiments. The contents not shown in detail in the display device can be referred to the previous embodiments and will not be repeated here.

[0076] Based on the same inventive concept, the present application embodiment provides a method for manufacturing a display substrate, such as Figure 5 As shown, the basic production method of the display includes:

[0077] S1: providing a substrate;

[0078] S2: A first source-drain electrode layer, a second source-drain electrode layer and a planarization layer are sequentially manufactured on one side of the substrate through a patterning process; wherein: the second source-drain electrode layer is located on a side of the first source-drain electrode layer away from the substrate, and comprises a first portion, a second portion and a third portion, the first portion is connected to the third portion through the second portion, the first portion and the third portion are both arranged parallel to the substrate, the first portion is connected to the first source-drain electrode layer, and the second portion is at a preset angle to the substrate; the planarization layer at least covers an edge area of ​​the third portion and exposes a portion of the third portion, and the length of the exposed third portion along a direction parallel to the substrate is a preset length.

[0079] It should be noted that if Figure 3 and Figure 4 As shown, when manufacturing the second source-drain electrode layer, the third portion (long side d1') of the second source-drain electrode layer is lengthened. Figure 3 d0′ is the length of the long side of the second source / drain layer in the related art, and d1′ is greater than d0′.

[0080] In the related art, d0' is approximately 2 to 3 μm (micrometers).

[0081] Optionally, d1′ is 5 to 6 μm (micrometers), including two end values ​​of 5 and 6.

[0082] Alternatively, if Figure 2 As shown, the length of d2 is 2-3 μm (micrometers), and includes two end values ​​2 and 3. In this way, the third portion 53 (i.e., the lengthened portion) of the second source-drain electrode layer 50 can be further matched to ensure that the spacing between each PIN corner is guaranteed without V-shaped slope (the second source-drain electrode layer 50 does not need to be lengthened all the time); "lengthened" in this application means "widened" when viewed from a top view.

[0083] Alternatively, if Figure 2 As shown, the length of d2 is one tenth to one fifth of the length of the first source and drain electrode layer 30 .

[0084] Furthermore, the length d3 (width in top view) of the first source-drain electrode layer 30 (PAD) is 15 to 20 microns (including two end values ​​15 and 20), which can ensure the size of the overlapping hole so that the first source-drain electrode layer 30 and the second source-drain electrode layer 50 can be overlapped smoothly.

[0085] In the related art, the thickness of the first source-drain electrode layer 30 (PAD) is similar to that of the second source-drain electrode layer 50. Furthermore, the present application shortens the length (width in a top view) of the first source-drain electrode layer 30 and increases the thickness of the first source-drain electrode layer 30, that is, the thickness of the first source-drain electrode layer 30 (PAD) is greater than that of the second source-drain electrode layer 50, which can alleviate the increase in resistance of the first source-drain electrode layer 30 after shortening.

[0086] When the planarization layer is made, the edge area of ​​the third part of the second source-drain electrode layer is covered and part of the third part is exposed. After the length of the third part of the second source-drain electrode layer in the horizontal direction is lengthened, after the planarization layer 60 covers the edge of the third part of the second source-drain electrode layer, the exposed third part can have a preset length in the direction parallel to the substrate, thereby avoiding the generation of a V-shaped groove structure between the second part 52 and the planarization layer 60. In this way, the side of the second source-drain electrode layer 50 can be covered, and the generation of dark spots caused by the precipitation of Ag (silver) residues of the anode can be avoided, and stress concentration can be weakened, thereby reducing the risk of peeling and the generation of progressive black spots (GDS). In addition, since the generation of a V-shaped groove structure between the second part 52 and the planarization layer 60 is avoided, the generation of anode residues can be avoided, making it difficult for the anode to overlap with the adjacent pin, thereby avoiding pin short circuit.

[0087] In some embodiments, after the planarization layer is formed, the method further includes:

[0088] An insulating layer and a metal layer are sequentially formed on a side of the planarization layer away from the substrate by a patterning process;

[0089] Before forming the first source and drain electrode layer on one side of the substrate, the method further includes:

[0090] An interlayer dielectric layer is formed on one side of the substrate through a patterning process.

[0091] After forming a first source and drain electrode layer on one side of the substrate, the method further includes:

[0092] A passivation layer is formed on the side of the first source and drain electrode layer away from the substrate through a patterning process.

[0093] In the embodiments of the present application, the specific manufacturing methods of the insulating layer, the metal layer, the interlayer dielectric layer and the passivation layer are similar to those in the related art and will not be described in detail here.

[0094] By applying the embodiments of the present application, at least the following beneficial effects can be achieved:

[0095] In the embodiment of the present application, the third portion 53 of the second source-drain electrode layer 50 is exposed through the planarization layer 60, and the length of the exposed third portion 53 is a preset length, that is, the long side of the second source-drain electrode layer 50 is elongated, so that the climbing area of ​​the second source-drain electrode layer 50 is staggered with the climbing areas of the insulating layer 70 and the metal layer 80, and the planarization layer 60 does not contact the climbing area of ​​the second source-drain electrode layer 50, so that a flat area (such as Figure 2 The second source-drain electrode layer 50 can be covered with a dotted line, thereby preventing the formation of Ag (silver) precipitation dark spots, and preventing the formation of V-shaped groove structures, thereby reducing stress concentration, thereby reducing the risk of peeling and progressive black spots (GDS), and further, preventing the formation of anode residues, thereby preventing pin short circuits.

[0096] Those skilled in the art will appreciate that the various operations, methods, steps, measures, and schemes in the processes discussed in this application may be alternated, changed, combined, or deleted. Furthermore, other steps, measures, and schemes in the various operations, methods, and processes discussed in this application may also be alternated, changed, rearranged, decomposed, combined, or deleted. Furthermore, steps, measures, and schemes in the related art that are similar to those disclosed in this application may also be alternated, changed, rearranged, decomposed, combined, or deleted.

[0097] In the description of the present application, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0098] The terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise specified, "plurality" means two or more.

[0099] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0100] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0101] It should be understood that, although the steps in the flowchart of the accompanying drawings are displayed in sequence as indicated by the arrows, these steps are not necessarily executed in sequence in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least a part of the steps in the flowchart of the accompanying drawings may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but can be executed at different times, and their execution order is not necessarily sequential, but can be executed in turn or alternately with other steps or at least a part of the sub-steps or stages of other steps.

[0102] The above description is only a partial implementation method of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. A display substrate, comprising a display area and a non-display area located at at least one side of the display area, characterized in that: The non-display area includes: substrate; A first source-drain electrode layer, located on one side of the substrate; A second source-drain electrode layer, located on a side of the first source-drain electrode layer away from the substrate, comprises a first portion, a second portion and a third portion, wherein the first portion is connected to the third portion through the second portion, the first portion and the third portion are both arranged parallel to the substrate, the first portion is connected to the first source-drain electrode layer, and the second portion is at a preset angle to the substrate; a planarization layer, located on a side of the second source-drain electrode layer away from the substrate, the planarization layer at least covering an edge region of the third portion and exposing a portion of the third portion, and the length of the exposed third portion along a direction parallel to the substrate is a preset length; The preset length is not less than 2 microns.

2. The display substrate according to claim 1, characterized in that: The second part includes a first sub-part and a second sub-part, and the third part includes a third sub-part and a fourth sub-part; The third sub-portion and the fourth sub-portion are located on different sides of the center line of the first source-drain electrode layer, the third sub-portion is connected to the first portion through the first sub-portion, and the fourth sub-portion is connected to the first portion through the second sub-portion; The planarization layer at least covers an edge region of the third sub-portion and exposes a portion of the third sub-portion, and the planarization layer at least covers an edge region of the fourth sub-portion and exposes a portion of the fourth sub-portion; The exposed third sub-portion and the exposed fourth sub-portion are symmetrical about a center line of the first source-drain layer.

3. The display substrate according to claim 2, characterized in that: The third sub-portion covered by the planarization layer and the fourth sub-portion covered by the planarization layer are symmetrical about a center line of the first source-drain layer.

4. The display substrate according to claim 1, characterized in that: Also includes: The insulating layer is located on a side of the planarization layer away from the substrate and covers the exposed third portion. At a position where the insulating layer contacts the exposed third portion, a partial area of ​​the insulating layer is parallel to the substrate.

5. The display substrate according to claim 4, characterized in that: Also includes: a metal layer, located on a side of the insulating layer away from the substrate and connected to the first portion through a via hole penetrating the insulating layer; At a position where the insulating layer contacts the exposed third portion, a partial area of ​​the metal layer is parallel to the substrate direction.

6. The display substrate according to any one of claims 1 to 5, characterized in that: Also includes: A passivation layer, located between the first source-drain electrode layer and the second source-drain electrode layer; The interlayer dielectric layer is located on a side of the first source-drain electrode layer close to the substrate.

7. A display device, characterized in that: It comprises the display substrate as claimed in any one of claims 1 to 6.

8. A method for manufacturing a display substrate, characterized in that: include: providing a substrate; A first source-drain electrode layer, a second source-drain electrode layer and a planarization layer are sequentially formed on one side of the substrate by a patterning process; Wherein: the second source-drain electrode layer is located on a side of the first source-drain electrode layer away from the substrate, and comprises a first portion, a second portion and a third portion, the first portion is connected to the third portion through the second portion, the first portion and the third portion are both arranged parallel to the substrate, the first portion is connected to the first source-drain electrode layer, and the second portion is at a preset angle to the substrate; the planarization layer at least covers an edge region of the third portion and exposes a portion of the third portion, and the length of the exposed third portion along a direction parallel to the substrate is a preset length; The preset length is not less than 2 microns.

9. The manufacturing method according to claim 8, characterized in that: After the planarization layer is formed, the method further comprises: An insulating layer and a metal layer are sequentially formed on a side of the planarization layer away from the substrate by a patterning process; Before forming the first source-drain electrode layer on one side of the substrate, the method further comprises: forming an interlayer dielectric layer on one side of the substrate by a patterning process; After forming a first source and drain electrode layer on one side of the substrate, the method further includes: A passivation layer is formed on the side of the first source and drain electrode layer away from the substrate through a patterning process.

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