Active element substrate, capacitor device, and method for manufacturing active element substrate
By integrating thin-film transistors and using buffer layer doping to reduce resistivity, the problem of high production costs in electronic devices has been solved, enabling a low-cost and high-efficiency manufacturing process and improving component performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- AU OPTRONICS CORP
- Filing Date
- 2022-10-09
- Publication Date
- 2026-06-19
AI Technical Summary
Manufacturing active or passive components with different characteristics in existing electronic devices requires multiple deposition and doping processes, resulting in high production costs and long production times.
By integrating a first thin-film transistor and a second thin-film transistor on a substrate, and using hydrogen from the first buffer layer to dope the first metal oxide layer to reduce resistivity, while employing a low-temperature process to form gate dielectric layers with different oxygen concentrations, the manufacturing process is simplified.
This technology enables low-cost production of active component substrates, improves production efficiency, and enhances component performance by controlling the characteristics of the gate dielectric layer with different oxygen concentrations.
Smart Images
Figure CN115548031B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to an active element substrate, a capacitor device, and a method for manufacturing the active element substrate. Background Technology
[0002] Generally speaking, an electronic device typically contains many active or passive components for different purposes. To manufacture active or passive components with different characteristics, multiple deposition and doping processes are often required, which results in high production costs and long production times for electronic devices. Summary of the Invention
[0003] The present invention provides an active component substrate and a method for manufacturing the same. The active component substrate integrates a first thin-film transistor and a second thin-film transistor, and has the advantage of low production cost.
[0004] The present invention provides a capacitor device that can reduce the resistivity of the first metal oxide layer by doping the first metal oxide layer with hydrogen in the first buffer layer.
[0005] At least one embodiment of the present invention provides an active element substrate. The active element substrate includes a substrate and a first thin-film transistor and a second thin-film transistor disposed on the substrate. The first thin-film transistor includes a first metal oxide layer, a first gate, a first source, and a first drain. A first gate dielectric layer and a second gate dielectric layer are located between the first gate and the first metal oxide layer. The first source and the first drain are electrically connected to the first metal oxide layer. The second thin-film transistor includes a second metal oxide layer, a second gate, a second source, and a second drain. The second gate dielectric layer is located between the second gate and the second metal oxide layer, and the second metal oxide layer is located between the first gate dielectric layer and the second gate dielectric layer. The first gate and the second gate belong to the same patterned layer. The second source and the second drain are electrically connected to the second metal oxide layer.
[0006] At least one embodiment of the present invention provides a capacitor device. The capacitor device includes a substrate, a first buffer layer, a first metal oxide layer, a first dielectric layer, and a second metal oxide layer. The first buffer layer is located on the substrate and contains hydrogen. The first metal oxide layer contacts the upper surface of the first buffer layer. The first dielectric layer is located on the first metal oxide layer. The second metal oxide layer is located on the first dielectric layer and at least partially overlaps the first metal oxide layer. The resistivity of the first metal oxide layer is different from the resistivity of the second metal oxide layer.
[0007] At least one embodiment of the present invention provides an active element substrate. The active element substrate includes a substrate and a first thin-film transistor and a second thin-film transistor disposed on the substrate. The first thin-film transistor includes a first metal oxide layer, a first gate, a first source, and a first drain. A first gate dielectric layer, a second gate dielectric layer, a third gate dielectric layer, and a fourth gate dielectric layer are located between the first gate and the first metal oxide layer. The first source and the first drain are electrically connected to the first metal oxide layer. The second thin-film transistor includes a second metal oxide layer, a second gate, a second source, and a second drain. A third gate dielectric layer and a fourth gate dielectric layer are located between the second gate and the second metal oxide layer. The second metal oxide layer is located between the second gate dielectric layer and the third gate dielectric layer. The oxygen concentration of the second gate dielectric layer and the third gate dielectric layer is higher than the oxygen concentration of the first gate dielectric layer. The second source and the second drain are electrically connected to the second metal oxide layer.
[0008] At least one embodiment of the present invention provides a method for manufacturing an active element substrate, comprising: forming a first metal oxide layer on a substrate; forming a first gate dielectric layer on the first metal oxide layer; forming a second gate dielectric layer on the first gate dielectric layer, wherein the fabrication process temperature for forming the second gate dielectric layer is lower than the fabrication process temperature for forming the first gate dielectric layer, and the oxygen concentration of the second gate dielectric layer is higher than the oxygen concentration of the first gate dielectric layer; forming a second metal oxide layer on the second gate dielectric layer; and forming a third gate dielectric layer on the second metal oxide layer, wherein the fabrication process temperature for forming the third gate dielectric layer is lower than the fabrication process temperature for forming the first gate dielectric layer. The fabrication process temperature of the first gate dielectric layer is as follows, and the oxygen concentration of the third gate dielectric layer is higher than that of the first gate dielectric layer; a fourth gate dielectric layer is formed on the third gate dielectric layer; a first gate and a second gate are formed on the fourth gate dielectric layer, wherein the first gate dielectric layer, the second gate dielectric layer, the third gate dielectric layer and the fourth gate dielectric layer are located between the first gate and the first metal oxide layer, and the third gate dielectric layer and the fourth gate dielectric layer are located between the second gate and the second metal oxide layer; a first source and a first drain electrically connected to the first metal oxide layer are formed; a second source and a second drain electrically connected to the second metal oxide layer are formed. Attached Figure Description
[0009] Figure 1 This is a cross-sectional schematic diagram of an active element substrate according to an embodiment of the present invention;
[0010] Figures 2A to 2F yes Figure 1 A cross-sectional schematic diagram of the manufacturing method of the active component substrate;
[0011] Figure 3 This is a cross-sectional schematic diagram of an active element substrate according to an embodiment of the present invention;
[0012] Figure 4 This is a cross-sectional schematic diagram of an active element substrate according to an embodiment of the present invention;
[0013] Figure 5 This is a cross-sectional schematic diagram of a capacitor device according to an embodiment of the present invention;
[0014] Figures 6A to 6D yes Figure 5 A cross-sectional schematic diagram of the manufacturing method of the capacitor device;
[0015] Figure 7 This is a cross-sectional schematic diagram of an active element substrate according to an embodiment of the present invention;
[0016] Figures 8A to 8D yes Figure 7 A cross-sectional schematic diagram of the manufacturing method of the active component substrate;
[0017] Figure 9 This is a cross-sectional schematic diagram of an active element substrate according to an embodiment of the present invention;
[0018] Figures 10A to 10B yes Figure 9 A cross-sectional schematic diagram of the manufacturing method of the active component substrate.
[0019] Symbol Explanation
[0020] 10A, 10B, 10C, 10E, 10F: Active component substrates
[0021] 10D: Capacitor Device
[0022] 100:Substrate
[0023] 110: First Buffer Layer
[0024] 120: Second Buffer Layer
[0025] 122: First oxygen-containing structure
[0026] 124: Second oxygen-containing structure
[0027] 130, 133: First gate dielectric layer
[0028] 132, 133a: First dielectric structure
[0029] 133b, 134: Second dielectric structure
[0030] 135, 140: Second gate dielectric layer
[0031] 135a: Third dielectric structure
[0032] 135b: Fourth dielectric structure
[0033] 140: Second gate dielectric layer
[0034] 143: Third gate dielectric layer
[0035] 143a: Fifth dielectric structure
[0036] 143b: Sixth dielectric structure
[0037] 145: Fourth gate dielectric layer
[0038] 145a: Seventh dielectric structure
[0039] 145b: Eighth dielectric structure
[0040] 150: Interlayer dielectric layer
[0041] BG1: First bottom gate
[0042] BG2: Second bottom gate
[0043] CE1,CE1',OS1,OS1': First metal oxide layer
[0044] CE2,CE2',OS2,OS2': Second metal oxide layer
[0045] ch1: First Channel Area
[0046] ch2: Second Channel Area
[0047] D1: First drain electrode
[0048] D2: Second drain electrode
[0049] dr1: First drain region
[0050] dr2 second drain region
[0051] dp1: First doped region
[0052] dp2: Second doped region
[0053] G1: First gate
[0054] G2: Second gate
[0055] g1a, g1b, g2a, g2b: Resistance gradient region
[0056] ND: Normal direction
[0057] P: Doping fabrication process
[0058] S1: First Source
[0059] S2: Second source pole
[0060] sr1: First source region
[0061] sr2: Second source pole region
[0062] T1: First thin-film transistor
[0063] T2: Second thin-film transistor
[0064] V1: First contact hole
[0065] V2: Second contact hole
[0066] V3: Third contact hole
[0067] V4: Fourth contact hole
[0068] V5: Fifth contact hole
[0069] V6: Sixth contact hole Detailed Implementation
[0070] Figure 1 This is a cross-sectional schematic diagram of an active element substrate according to an embodiment of the present invention. Please refer to... Figure 1 The active element substrate 10A includes a substrate 100, a first thin-film transistor T1, and a second thin-film transistor T2.
[0071] The substrate 100 may be made of glass, quartz, organic polymer, or opaque / reflective materials (e.g., conductive materials, metals, wafers, ceramics, or other suitable materials) or other suitable materials. If conductive materials or metals are used, an insulating layer (not shown) is applied to the substrate 100 to prevent short circuits. In some embodiments, the substrate 100 is a flexible substrate, and the material of the substrate 100 may be, for example, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyester (PES), polymethyl methacrylate (PMMA), polycarbonate (PC), polyimide (PI), or metal foil or other flexible materials.
[0072] In some embodiments, a first buffer layer 110 is located on the substrate 100 and contains hydrogen. For example, the material of the first buffer layer 110 includes hydrogen-containing silicon nitride (or hydrogenated silicon nitride) or other suitable materials. A second buffer layer 120 is located on the first buffer layer 110 and contains oxygen. For example, the second buffer layer 120 includes an oxygen-containing insulating material such as oxides or oxynitrides, such as silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide, or other suitable materials.
[0073] In some embodiments, a first buffer layer 110 is blanketed onto a substrate 100, while a second buffer layer 120 is patterned but does not cover a portion of the first buffer layer 110. In some embodiments, the second buffer layer 120 includes a first oxygen-containing structure 122 and a second oxygen-containing structure 124. In some embodiments, the first oxygen-containing structure 122 and the second oxygen-containing structure 124 are separated from each other. In some embodiments, the thickness of the first buffer layer 110 is 300 angstroms to 6000 angstroms. In some embodiments, the thickness of the second buffer layer 120 is 200 angstroms to 6000 angstroms.
[0074] A first thin-film transistor T1 and a second thin-film transistor T2 are located on the substrate 100. In some embodiments, the first thin-film transistor T1 and the second thin-film transistor T2 are located on the second buffer layer 120. The first thin-film transistor T1 includes a first metal oxide layer OS1, a first gate G1, a first source S1, and a first drain D1. The second thin-film transistor T2 includes a second metal oxide layer OS2, a second gate G2, a second source S2, and a second drain D2.
[0075] A first metal oxide layer OS1 is located on a first oxygen-containing structure 122, and the first oxygen-containing structure 122 is located between the first metal oxide layer OS1 and the first buffer layer 110. The first metal oxide layer OS1 contacts the top surface of the first oxygen-containing structure 122. The first buffer layer 110 and the first oxygen-containing structure 122 are located between the first metal oxide layer OS1 and the substrate 100. A first gate dielectric layer 130 and a second gate dielectric layer 140 are located on the first metal oxide layer OS1.
[0076] The first metal oxide layer OS1 includes a first source region sr1, a first drain region dr1, and a first channel region ch1 located between the first source region sr1 and the first drain region dr1. In this embodiment, the first source region sr1, the first drain region dr1, and the first channel region ch1 are all located between the second buffer layer 120 and the first gate dielectric layer 130. The distance between the first channel region ch1 and the substrate 100 is substantially equal to the distance between the first source region sr1 and the substrate 100 and the distance between the first drain region dr1 and the substrate 100.
[0077] In some embodiments, the first oxygen-containing structure 122 beneath the first metal oxide layer OS1 replenishes oxygen in the first metal oxide layer OS1, thereby increasing the resistivity of the first metal oxide layer OS1. In this embodiment, the first oxygen-containing structure 122 beneath the first source region sr1, the first drain region dr1, and the first channel region ch1 has a substantially uniform thickness.
[0078] Table 1 shows the sheet resistance R of the first source region sr1 and the first drain region dr1 in some embodiments. n+ And the threshold voltage Vth of the first thin-film transistor T1, wherein the first metal oxide layer OS1 (taking indium gallium zinc oxide as an example) is formed on the second buffer layer 120 (taking silicon oxynitride as an example) of different thicknesses.
[0079] Table 1
[0080] The thickness of the second buffer layer <![CDATA[R n+ (ohm / sq)]]> Vth(V) Example 1 50nm 759.1～773.5 0.22～0.28 Example 2 85nm 847.6～977 0.3～0.32 Example 3 150nm 1628.6～2138.5 0.33～0.35
[0081] As shown in Table 1, the thickness of the oxygen-containing layer beneath the first metal oxide layer OS1 affects the sheet resistance R of the first source region sr1 and the first drain region dr1. n+ And the threshold voltage Vth of the first thin-film transistor T1. The thicker the oxygen-containing layer beneath the first metal oxide layer OS1, the higher the R... n+ And the higher Vth is.
[0082] In some embodiments, the first gate dielectric layer 130 includes a first dielectric structure 132 and a second dielectric structure 134. The first dielectric structure 132 is located above the first oxygen-containing structure 122 and covers the first metal oxide layer OS1. The second dielectric structure 134 is located above the second oxygen-containing structure 124 and is located between the second dielectric structure 134 and the first buffer layer 110.
[0083] The second metal oxide layer OS2 is located on the second dielectric structure 134 and contacts the top surface, side surface, and side surface of the second dielectric structure 134, as well as the top surface of the first buffer layer 110. The second gate dielectric layer 140 is located on the first dielectric structure 132 and the second metal oxide layer OS2. The second metal oxide layer OS2 is located between the second dielectric structure 134 and the second gate dielectric layer 140 of the first gate dielectric layer 130, and between the first buffer layer 110 and the second gate dielectric layer 140. The first buffer layer 110, the second oxygen-containing structure 124, and the second dielectric structure 134 are located between the second metal oxide layer OS2 and the substrate 100.
[0084] The second metal oxide layer OS2 includes a second drain region dr2, a second source region sr2, a second channel region ch2, a resistive gradient region g2a located between the second drain region dr2 and the second channel region ch2, and a resistive gradient region g2b located between the second source region sr2 and the second channel region ch2. The second channel region ch2 contacts the top surface of the second dielectric structure 134, and the resistive gradient regions g2a and g2b contact the side surfaces of the second dielectric structure 134 and the second oxygen-containing structure 124. The second drain region dr2 and the second source region sr2 contact the top surface of the first buffer layer 110. The distance between the second channel region ch2 and the substrate 100 is greater than the distance between the second drain region dr2 and the substrate 100, and the distance between the second source region sr2 and the substrate 100.
[0085] In some embodiments, the second oxygen-containing structure 124 and the second dielectric structure 134 beneath the second metal oxide layer OS2 replenish oxygen to the second metal oxide layer OS2, thereby increasing the resistivity of the second metal oxide layer OS2.
[0086] The overall thickness of the second oxygen-containing structure 124 and the second dielectric structure 134 affects their ability to replenish oxygen in the second metal oxide layer OS2. Below the second channel region ch2, the overall thickness of the second oxygen-containing structure 124 and the second dielectric structure 134 is relatively large, thus the resistivity of the second channel region ch2 is relatively large. Below the resistance gradient regions g2a and g2b, the overall thickness of the second oxygen-containing structure 124 and the second dielectric structure 134 gradually decreases, thus the resistivity of the resistance gradient regions g2a and g2b also gradually decreases. Below the second drain region dr2 and the second source region sr2, there is no second oxygen-containing structure 124 and the second dielectric structure 134, and the second drain region dr2 and the second source region sr2 have lower resistivity than the second channel region ch2, the resistance gradient regions g2a and g2b. In some embodiments, the oxygen concentration in the second channel region ch2 is greater than the oxygen concentration in the resistance gradient regions g2a and g2b, and the oxygen concentration in the resistance gradient regions g2a and g2b is greater than the oxygen concentration in the second drain region dr2 and the second source region sr2.
[0087] In some embodiments, the materials of the first metal oxide layer OS1 and the second metal oxide layer OS2 include quaternary metal compounds such as indium gallium tin zinc oxide (IGTZO), indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), aluminum zinc tin oxide (AZTO), and indium tungsten zinc oxide (IWZO), or oxides composed of ternary metals containing any three of gallium (Ga), zinc (Zn), indium (In), tin (Sn), aluminum (Al), and tungsten (W), or lanthanide rare earth doped metal oxides (e.g., Ln-IZO). In some embodiments, the first metal oxide layer OS1 and the second metal oxide layer OS2 comprise the same material. In other embodiments, the first metal oxide layer OS1 and the second metal oxide layer OS2 comprise different materials. In some embodiments, the carrier mobility of the second channel region ch2 of the second metal oxide layer OS2 is different from (greater than or less than) the carrier mobility of the first channel region ch1 of the first metal oxide layer OS1.
[0088] In some embodiments, both the first gate dielectric layer 130 and the second gate dielectric layer 140 comprise an oxygen-containing insulating material such as an oxide or oxynitride, for example, silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide, or other suitable materials. In some embodiments, the thickness of the first gate dielectric layer 130 is 100 angstroms to 2000 angstroms. In some embodiments, the thickness of the second gate dielectric layer 140 is 400 angstroms to 3000 angstroms.
[0089] The first gate G1 and the second gate G2 are located on the second gate dielectric layer 140 and overlap the first channel region ch1 and the second channel region ch2, respectively. The first dielectric structure 132 and the second gate dielectric layer 140 are located between the first gate G1 and the first metal oxide layer OS1. The second gate dielectric layer 140 is located between the second gate G2 and the second metal oxide layer OS2. In this embodiment, the thickness of the insulating material between the first gate G1 and the first metal oxide layer OS1 is greater than the thickness of the insulating material between the second gate G2 and the second metal oxide layer OS2, thereby giving the first thin-film transistor T1 and the second thin-film transistor T2 different characteristics. For example, the first thin-film transistor T1 has a larger subthreshold swing and better long-term operational reliability; the second thin-film transistor T2 has a larger operating current and a smaller subthreshold swing, enabling high-speed switching.
[0090] The materials of the first gate G1 and the second gate G2 may include metals, such as chromium (Cr), gold (Au), silver (Ag), copper (Cu), tin (Sn), lead (Pb), hafnium (Hf), tungsten (W), molybdenum (Mo), neodymium (Nd), titanium (Ti), tantalum (Ta), aluminum (Al), zinc (Zn), or alloys of any combination of the above metals, or stacks of the above metals and / or alloys, but the present invention is not limited thereto. The first gate G1 and the second gate G2 may also use other conductive materials, such as metal nitrides, metal oxides, metal oxynitrides, stacks of metals and other conductive materials, or other materials with conductive properties.
[0091] An interlayer dielectric layer 150 is located on the second gate dielectric layer 140 and covers the first gate G1 and the second gate G2. In some embodiments, the material of the interlayer dielectric layer 150 includes silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, or other insulating materials.
[0092] The first contact hole V1 and the second contact hole V2 pass through the interlayer dielectric layer 150, the second gate dielectric layer 140, and the first dielectric structure 132. The first drain D1 and the first source S1 are located on the interlayer dielectric layer 150 and are respectively filled into the first contact hole V1 and the second contact hole V2 to electrically connect to the first metal oxide layer OS1. The first drain D1 and the first source S1 are respectively connected to the first drain region dr1 and the first source region sr1 of the first metal oxide layer OS1.
[0093] The third contact hole V3 and the fourth contact hole V4 pass through the interlayer dielectric layer 150 and the second gate dielectric layer 140. The second drain D2 and the second source S2 are located on the interlayer dielectric layer 150 and are respectively filled into the third contact hole V3 and the fourth contact hole V4 to electrically connect to the second metal oxide layer OS2. The second drain D2 and the second source S2 are respectively connected to the second drain region dr2 and the second source region sr2 of the second metal oxide layer OS2.
[0094] The materials of the first drain D1, the first source S1, the second drain D2, and the second source S2 may include metals, such as chromium, gold, silver, copper, tin, lead, hafnium, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc (or any combination of the above metals or a stack of the above metals and / or alloys, but the present invention is not limited thereto). The first drain D1, the first source S1, the second drain D2, and the second source S2 may also use other conductive materials, such as metal nitrides, metal oxides, metal oxynitrides, stacks of metals and other conductive materials, or other materials with conductive properties.
[0095] Figures 2A to 2F yes Figure 1 A cross-sectional schematic diagram of the manufacturing method of the active element substrate 10A.
[0096] Please refer to Figure 2A A first buffer layer 110 is formed on the substrate 100. A second buffer layer 120 is formed on the first buffer layer 110. A first metal oxide layer OS1' is formed on the second buffer layer 120. The method for forming the first metal oxide layer OS1' includes a photolithography etching process, wherein the etching process can be dry etching or wet etching.
[0097] Please refer to Figure 2B A first gate dielectric layer 130 is formed on the second buffer layer 120 and the first metal oxide layer OS1', forming a blanket-covered first gate dielectric layer 130.
[0098] Please refer to Figure 2C The first gate dielectric layer 130 and the second buffer layer 120 are patterned to expose the first buffer layer 110. The method for patterning the first gate dielectric layer 130 and the second buffer layer 120 includes, for example, a photolithography etching process, wherein the etching process can be dry etching or wet etching. The patterned second buffer layer 120 includes a first oxygen-containing structure 122 and a second oxygen-containing structure 124. The patterned first gate dielectric layer 130 includes a first dielectric structure 132 and a second dielectric structure 134. A first metal oxide layer OS1' is located between the first oxygen-containing structure 122 and the first dielectric structure 132.
[0099] Please refer to Figure 2D A second metal oxide layer OS2' is formed on the second dielectric structure 134 and the second oxygen-containing structure 124, and a portion of the second metal oxide layer OS2' contacts the top surface of the first buffer layer 110.
[0100] Please refer to Figure 2E A blanket-covered second gate dielectric layer 140 is formed on the first buffer layer 110, the first oxygen-containing structure 122, the first dielectric structure 132, and the second metal oxide layer OS2'. A first gate G1 and a second gate G2 are formed on the second gate dielectric layer 140. In some embodiments, the method of forming the first gate G1 and the second gate G2 includes: forming a conductive material layer (not shown) on the second gate dielectric layer 140; forming a patterned photoresist (not shown) on the aforementioned conductive material layer; using the patterned photoresist as a mask, etching the conductive material layer to form the first gate G1 and the second gate G2, wherein the etching process can be dry etching or wet etching; and finally, removing the patterned photoresist.
[0101] Next, using the first gate G1 and the second gate G2 as masks, a doping process P is performed on the first metal oxide layer OS1' and the second metal oxide layer OS2' to form a first metal oxide layer OS1 including a first source region sr1, a first drain region dr1, and a first channel region ch1, and a second metal oxide layer OS2 including a second source region sr2, a second drain region dr2, a resistance gradient region g2a, a resistance gradient region g2b, and a second channel region ch2. In some embodiments, the doping process P is, for example, a hydrogen plasma fabrication process or other suitable fabrication process.
[0102] In this embodiment, the second dielectric structure 134 and the second oxygen-containing structure 124 provide oxygen during the fabrication process, thereby increasing the resistivity of the resistance gradient region g2a, the resistance gradient region g2b, and the second channel region ch2. In some embodiments, the first buffer layer 110 provides hydrogen during the fabrication process, thereby reducing the resistivity of the second source region sr2 and the second drain region dr2. In some embodiments, the resistivity of the first drain region dr1 and the first source region sr2 is different from the resistivity of the second drain region dr2 and the second source region sr2. For example, the resistivity of the second drain region dr2 and the second source region sr2 is less than the resistivity of the first drain region dr1 and the first source region sr2.
[0103] In this embodiment, the first gate G1 and the second gate G2 belong to the same patterning layer, and the first metal oxide layer OS1 and the second metal oxide layer OS2 can be doped by the same doping process P, thus saving the manufacturing cost of the first thin film transistor and the second thin film transistor.
[0104] Please refer to Figure 2F An interlayer dielectric layer 150 is formed on the second gate dielectric layer 140. Next, an etching process is performed to form the first contact hole V1, the second contact hole V2, the third contact hole V3, and the fourth contact hole V4.
[0105] Finally, please return to Figure 1A first drain D1, a first source S1, a second drain D2, and a second source S2 are formed on the interlayer dielectric layer 150 and respectively filled into the first contact hole V1, the second contact hole V2, the third contact hole V3, and the fourth contact hole V4. At this point, the active device substrate 10A is substantially complete. In some embodiments, the method for forming the first source S1, the first drain D1, the second source S2, and the second drain D2 includes: forming a conductive material layer (not shown) on the interlayer dielectric layer 150; forming a patterned photoresist (not shown) on the aforementioned conductive material layer; using the patterned photoresist as a mask, etching the conductive material layer to form the first source S1, the first drain D1, the second source S2, and the second drain D2; and finally, removing the patterned photoresist. In other words, the first source S1, the first drain D1, the second source S2, and the second drain D2 belong to the same patterned layer.
[0106] Figure 3 This is a schematic cross-sectional view of an active element substrate according to an embodiment of the present invention. It should be noted that... Figure 3 The embodiments follow Figures 1 to 2F The component reference numerals and partial contents of the embodiments are described below, wherein the same or similar reference numerals are used to represent the same or similar components, and descriptions of the same technical content are omitted. For explanations of the omitted parts, please refer to the foregoing embodiments, and will not be repeated here.
[0107] Figure 3 Active component substrate 10B and Figure 1 The main difference between the active element substrate 10A and the active element substrate 10B is that the active element substrate 10B also includes a first bottom gate BG1 and a second bottom gate BG2.
[0108] Please refer to Figure 3 A first bottom gate BG1 and a second bottom gate BG2 are located between the first buffer layer 110 and the substrate 100. A first metal oxide layer OS1 is located between the first gate G1 and the first bottom gate BG1. A second metal oxide layer OS2 is located between the second gate G2 and the second bottom gate BG2. In some embodiments, the width of the first bottom gate BG1 is greater than the width of the first gate G1, and the width of the second bottom gate BG2 is greater than the width of the second gate G2. Therefore, in the normal direction ND of the top surface of the substrate 100, the first bottom gate BG1 overlaps a portion of the first source region sr1 and a portion of the first drain region dr1, and the second bottom gate BG2 overlaps a portion of the second source region sr2 and a portion of the second drain region dr2.
[0109] Figure 4 This is a schematic cross-sectional view of an active element substrate according to an embodiment of the present invention. It should be noted that... Figure 4 The embodiments follow Figures 1 to 2FThe component reference numerals and partial contents of the embodiments are described below, wherein the same or similar reference numerals are used to represent the same or similar components, and descriptions of the same technical content are omitted. For explanations of the omitted parts, please refer to the foregoing embodiments, and will not be repeated here.
[0110] Figure 4 Active component substrate 10C and Figure 1 The main difference between the active element substrate 10A and the active element substrate 10C is that the first metal oxide layer OS1 contacts the top and side surfaces of the first oxygen-containing structure 122, while the second metal oxide layer OS2 does not contact the second oxygen-containing structure 124.
[0111] Please refer to Figure 4 A first metal oxide layer OS1 is located on the first oxygen-containing structure 122 and the first buffer layer 110. The first metal oxide layer OS1 contacts the top surface, the side surface, and the top surface of the first buffer layer 110 of the first oxygen-containing structure 122. The first oxygen-containing structure 122 and the first buffer layer 110 are located between the first metal oxide layer OS1 and the substrate 100, and the first oxygen-containing structure 122 is located between the first metal oxide layer OS1 and the first buffer layer 110.
[0112] The first metal oxide layer OS1 includes a first source region sr1, a first drain region dr1, a resistive gradient region g1a located between the first drain region dr1 and the first channel region ch1, and a resistive gradient region g1b located between the first source region sr1 and the first channel region ch1. In this embodiment, the first channel region ch1 contacts the top surface of the first oxygen-containing structure 122, the resistive gradient regions g1a and g1b contact the side surfaces of the first oxygen-containing structure 122, and the first drain region dr1 and the first source region sr1 contact the top surface of the first buffer layer 110. The distance between the first channel region ch1 and the substrate 100 is greater than the distance between the first drain region dr1 and the substrate 100 and the distance between the first source region sr1 and the substrate 100.
[0113] The thickness of the first oxygen-containing structure 122 affects its ability to replenish oxygen in the first metal oxide layer OS1. Below the first channel region ch1, the thickness of the first oxygen-containing structure 122 is larger, resulting in a higher resistivity in the first channel region ch1. Below the resistance gradient regions g1a and g1b, the thickness of the first oxygen-containing structure 122 gradually decreases, thus the resistivity of the resistance gradient regions g1a and g1b also gradually decreases. The first drain region dr1 and the first source region sr1 do not have the first oxygen-containing structure 122 below them, and the first drain region dr1 and the first source region sr1 have lower resistivity than the first channel region ch1, the resistance gradient regions g1a, and the resistance gradient regions g1b. In some embodiments, the oxygen concentration in the first channel region ch1 is greater than the oxygen concentrations in the resistivity gradient regions g1a and g1b, and the oxygen concentrations in the resistivity gradient regions g1a and g1b are greater than the oxygen concentrations in the first drain region dr1 and the first source region sr1. In some embodiments, the first buffer layer 110 provides hydrogen during the fabrication process, thereby reducing the resistivity of the first drain region dr1 and the first source region sr1. In some embodiments, when the first metal oxide layer OS1 and the second metal oxide layer OS2 are made of the same material, the resistivity of the first drain region dr1 and the first source region sr1 is different from the resistivity of the second drain region dr2 and the second source region sr2. For example, the resistivity of the first drain region dr1 and the first source region sr1 is less than the resistivity of the second drain region dr2 and the second source region sr2.
[0114] In some embodiments, a first gate dielectric layer 130 is blanketed over a first metal oxide layer OS1 and a second oxygen-containing structure 124. The first gate dielectric layer 130 covers the top surface and sidewalls of the second oxygen-containing structure 124.
[0115] The second metal oxide layer OS2 is located on the first gate dielectric layer 130 and contacts the top surface of the first gate dielectric layer 130. The first buffer layer 110, the second oxygen-containing structure 124, and the first gate dielectric layer 130 are located between the second metal oxide layer OS2 and the substrate 100. The second oxygen-containing structure 124 and the first gate dielectric layer 130 are located between the second metal oxide layer OS2 and the first buffer layer 110. The first gate dielectric layer 130 has protrusions corresponding to the second oxygen-containing structure 124, and the second metal oxide layer OS2 covers the aforementioned protrusions of the first gate dielectric layer 130, such that the distance between the second channel region ch2 and the substrate 100 is greater than the distance between the second drain region dr2 and the substrate 100 and the distance between the second source region sr2 and the substrate 100.
[0116] The second gate dielectric layer 140 is located on the first gate dielectric layer 130 and the second metal oxide layer OS2. The second metal oxide layer OS2 is located between the first gate dielectric layer 130 and the second gate dielectric layer 140.
[0117] In this embodiment, the second channel region ch2, the resistance gradient region g2a, the resistance gradient region g2b, the second drain region dr2, and the second source region sr2 are all in contact with the top surface of the first gate dielectric layer 130.
[0118] In some embodiments, the second oxygen-containing structure 124 and the first gate dielectric layer 130 beneath the second metal oxide layer OS2 replenish oxygen to the second metal oxide layer OS2. Oxygen elements in the second oxygen-containing structure 124 and the first gate dielectric layer 130 diffuse into the second metal oxide layer OS2, increasing the resistivity of the second metal oxide layer OS2. The overall thickness of the second oxygen-containing structure 124 and the first gate dielectric layer 130 affects their ability to replenish oxygen to the second metal oxide layer OS2. Below the second channel region ch2, the overall thickness of the second oxygen-containing structure 124 and the first gate dielectric layer 130 is relatively large, therefore the resistivity of the second channel region ch2 is relatively large; below the resistance gradient regions g2a and g2b, the overall thickness of the second oxygen-containing structure 124 and the first gate dielectric layer 130 gradually decreases, therefore the resistivity of the resistance gradient regions g2a and g2b also gradually decreases. The second drain region dr2 and the second source region sr2 do not have a second oxygen-containing structure 124 below them, and the second drain region dr2 and the second source region sr2 have lower resistivity than the second channel region ch2, the resistivity gradient region g2a, and the resistivity gradient region g2b. In some embodiments, the oxygen concentration in the second channel region ch2 is greater than the oxygen concentration in the resistivity gradient region g2a and the oxygen concentration in the resistivity gradient region g2b, and the oxygen concentration in the resistivity gradient region g2a and the oxygen concentration in the resistivity gradient region g2b is greater than the oxygen concentration in the second drain region dr2 and the oxygen concentration in the second source region sr2.
[0119] Figure 5 This is a schematic cross-sectional view of a capacitor device according to an embodiment of the present invention. It should be noted that... Figure 5 The embodiments follow Figures 1 to 2F The component reference numerals and partial contents of the embodiments are described below, wherein the same or similar reference numerals are used to represent the same or similar components, and descriptions of the same technical content are omitted. For explanations of the omitted parts, please refer to the foregoing embodiments, and will not be repeated here.
[0120] Please refer to Figure 5The capacitor device 10D includes a substrate 100, a first buffer layer 110, a first metal oxide layer CE1, a first gate dielectric layer 130 (also referred to as a first dielectric layer), and a second metal oxide layer CE2. In this embodiment, the capacitor device 10D further includes a second gate dielectric layer 140 (also referred to as a second dielectric layer), an interlayer dielectric layer 150, a first electrode E1, and a second electrode E2.
[0121] A first buffer layer 110 is located on the substrate 100 and contains hydrogen. A first metal oxide layer CE1 contacts the upper surface of the first buffer layer 110. A first gate dielectric layer 130 is located on the first metal oxide layer CE1. A second metal oxide layer CE2 is located on the first gate dielectric layer 130 and at least partially overlaps the first metal oxide layer CE1. The resistivity of the first metal oxide layer CE1 is different from the resistivity of the second metal oxide layer CE2. For example, the first metal oxide layer CE1 and the second metal oxide layer CE2 may be made of different materials or have different doping concentrations. In this embodiment, the first metal oxide layer CE1 includes a first doped region dp1 that does not overlap with the second metal oxide layer CE2 in the normal direction ND and a second doped region dp2 that overlaps with the second metal oxide layer CE2 in the normal direction ND. The hydrogen concentration in the first doped region dp1 is different from the hydrogen concentration in the second doped region dp2.
[0122] The second gate dielectric layer 140 is located on the second metal oxide layer OS2. The interlayer dielectric layer 150 is located on the second gate dielectric layer 140. The fifth contact hole V5 passes through the interlayer dielectric layer 150, the second gate dielectric layer 140, and the first gate dielectric layer 130. The sixth contact hole V6 passes through the interlayer dielectric layer 150 and the second gate dielectric layer 140.
[0123] The first electrode E1 and the second electrode E2 are located on the interlayer dielectric layer 150, wherein the first electrode E1 and the second electrode E2 are electrically connected to the first metal oxide layer CE1 and the second metal oxide layer CE2, respectively. For example, the first electrode E1 fills the fifth contact hole V5 and contacts the first doped region dp1 of the first metal oxide layer CE1; the second electrode E2 fills the sixth contact hole V6 and contacts the second metal oxide layer CE2. In some embodiments, the first electrode E1 is electrically connected to one of the first thin-film transistor T1 and the second thin-film transistor T2 (see reference). Figure 1 , Figure 3 or Figure 4 And the second electrode E4 is electrically connected to the other of the first thin-film transistor T1 and the second thin-film transistor T2 (see reference). Figure 1 , Figure 3 or Figure 4In some embodiments, the metal oxide layer in the capacitor device 10D can be formed using the same deposition process as the metal oxide layer in the thin-film transistor, and the metal oxide layer in the capacitor device 10D can be doped using the same doping process as the metal oxide layer in the thin-film transistor. Therefore, the production cost of the capacitor device 10D can be reduced.
[0124] Figures 6A to 6D yes Figure 5 A cross-sectional schematic diagram of the manufacturing method of the capacitor device 10D.
[0125] Please refer to Figure 6A A first buffer layer 110 is formed on the substrate 100. A first metal oxide layer CE1' is formed on the first buffer layer 110. A first gate dielectric layer 130 is formed on the first buffer layer 110.
[0126] In some embodiments, before forming the first metal oxide layer CE1', a second buffer layer (not shown) is formed on the first buffer layer 110, and the second buffer layer is patterned by an etching process to expose the first buffer layer 110 so that the subsequently formed first metal oxide layer CE1' can contact the first buffer layer 110.
[0127] In some embodiments, hydrogen elements in the first buffer layer 110 diffuse into the first metal oxide layer CE1', thereby reducing the resistivity of the first metal oxide layer CE1'. In some embodiments, the first metal oxide layer CE1' and the first metal oxide layer OS1' are formed simultaneously (see reference). Figure 2A and Figure 2B In other words, the first metal oxide layer CE1' and the first metal oxide layer OS1' belong to the same patterning layer.
[0128] Please refer to Figure 6B A second metal oxide layer CE2' is formed on the first gate dielectric layer 130, and the second metal oxide layer CE2' overlaps a portion of the first metal oxide layer CE1'. In some embodiments, the second metal oxide layer CE2' and the second metal oxide layer OS2' are formed simultaneously (see reference). Figure 2D In other words, the second metal oxide layer CE2' and the second metal oxide layer OS2' belong to the same patterning layer.
[0129] Please refer to Figure 6CA second gate dielectric layer 140 is formed on the second metal oxide layer CE2' and the first gate dielectric layer 130. Next, a doping fabrication process P is performed on the first metal oxide layer CE1' and the second metal oxide layer CE2' to obtain the first metal oxide layer CE1 and the second metal oxide layer CE2. In this embodiment, the second metal oxide layer CE2 partially obscures the first metal oxide layer CE1, resulting in the first metal oxide layer CE1 having a first doped region dp1 and a second doped region dp2 with different doping concentrations. In this embodiment, the doping fabrication process P is a hydrogen plasma fabrication process or other suitable fabrication process. In this embodiment, the hydrogen concentration of the first doped region dp1 is greater than the hydrogen concentration of the second doped region dp2. In some embodiments, Figure 6C The doping process of P and Figure 2E The doping fabrication process P belongs to the same fabrication process, thereby saving manufacturing costs. In other words, the first metal oxide layer CE1', the first metal oxide layer OS1', the second metal oxide layer CE2', and the second metal oxide layer OS2' can be doped simultaneously through a single doping fabrication process P.
[0130] Please refer to Figure 6D An interlayer dielectric layer 150 is formed on the second gate dielectric layer 140. Next, an etching process is performed to form the fifth contact hole V5 and the sixth contact hole V6. In some embodiments, the fabrication process for forming the fifth contact hole V5 and the sixth contact hole V6 is the same as the fabrication process for forming the first contact holes V1 to the fourth contact holes V4 (see reference). Figure 2F This saves manufacturing costs. In other words, the first contact hole V1 to the sixth contact hole V6 can be formed simultaneously using the same photomask.
[0131] Finally, please return to Figure 5 A first electrode E1 and a second electrode E2 are formed on the interlayer dielectric layer 150. At this point, the capacitor device 10D is substantially complete. In some embodiments, the first electrode E1, the second electrode E2, the first source S1, the first drain D1, the second source S2, and the second drain D2 (see reference) Figure 1 They belong to the same patterned layer. It can also be said that the first electrode E1, the second electrode E2, the first source S1, the first drain D1, the second source S2, and the second drain D2 are formed simultaneously.
[0132] Figure 7 This is a schematic cross-sectional view of an active element substrate according to an embodiment of the present invention. It should be noted that... Figure 7 The embodiments follow Figures 1 to 2FThe component reference numerals and partial contents of the embodiments are described below, wherein the same or similar reference numerals are used to represent the same or similar components, and descriptions of the same technical content are omitted. For explanations of the omitted parts, please refer to the foregoing embodiments, and will not be repeated here.
[0133] Please refer to Figure 7 The active element substrate 10E includes a substrate 100, a first thin-film transistor T1, and a second thin-film transistor T2.
[0134] In some embodiments, the active element substrate 10E further includes a first buffer layer 110 and a second buffer layer 120. In some embodiments, the first buffer layer 110 is blanketed on the substrate 100, and the second buffer layer 120 is blanketed on the first buffer layer 110. In some embodiments, the thickness of the first buffer layer 110 is 200 angstroms to 3000 angstroms, and the thickness of the second buffer layer 120 is 200 angstroms to 3000 angstroms.
[0135] A first thin-film transistor T1 and a second thin-film transistor T2 are located on the substrate 100. In some embodiments, the first thin-film transistor T1 and the second thin-film transistor T2 are located on the second buffer layer 120. The first thin-film transistor T1 includes a first metal oxide layer OS1, a first gate G1, a first source S1, and a first drain D1. The second thin-film transistor T2 includes a second metal oxide layer OS2, a second gate G2, a second source S2, and a second drain D2.
[0136] The first metal oxide layer OS1 is located on the second buffer layer 120 and contacts the top surface of the second buffer layer 120. The first gate dielectric layer 133 is located on the first metal oxide layer OS1. The second gate dielectric layer 135 is located on the first gate dielectric layer 133. The first buffer layer 110 and the second buffer layer 120 are located between the first metal oxide layer OS1 and the substrate 100.
[0137] The first metal oxide layer OS1 includes a first source region sr1, a first drain region dr1, and a first channel region ch1 located between the first source region sr1 and the first drain region dr1. In this embodiment, the first source region sr1, the first drain region dr1, and the first channel region ch1 are all located between the second buffer layer 120 and the first gate dielectric layer 133.
[0138] The second metal oxide layer OS2 is located on the second gate dielectric layer 135 and contacts the top surface of the second gate dielectric layer 135. The third gate dielectric layer 143 is located on the second gate dielectric layer 135. The fourth gate dielectric layer 145 is located on the third gate dielectric layer 143. The second metal oxide layer OS2 is located between the second gate dielectric layer 135 and the third gate dielectric layer 143. The first buffer layer 110, the second buffer layer 120, the first gate dielectric layer 133, and the second gate dielectric layer 135 are located between the second metal oxide layer OS2 and the substrate 100.
[0139] The second metal oxide layer OS2 includes a second source region sr2, a second drain region dr2, and a second channel region ch2 located between the second source region sr2 and the second drain region dr2. In this embodiment, the second source region sr2, the second drain region dr2, and the second channel region ch2 are all located between the second gate dielectric layer 135 and the third gate dielectric layer 143.
[0140] In some embodiments, the second buffer layer 120, the first gate dielectric layer 133, the second gate dielectric layer 135, and the third gate dielectric layer 143 contain oxygen. For example, the second buffer layer 120, the first gate dielectric layer 133, the second gate dielectric layer 135, and the third gate dielectric layer 143 comprise oxygen-containing insulating materials such as oxides or oxynitrides, for example, silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide, or other suitable materials. In some embodiments, the material of the fourth gate dielectric layer 145 includes silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, or other suitable materials.
[0141] In some embodiments, the second buffer layer 120 and / or the first gate dielectric layer 133 replenish oxygen to the first metal oxide layer OS1, thereby increasing the resistivity of the first metal oxide layer OS1. In some embodiments, the second gate dielectric layer 135 and / or the third gate dielectric layer 143 replenish oxygen to the second metal oxide layer OS2, thereby increasing the resistivity of the second metal oxide layer OS2.
[0142] In some embodiments, the oxygen concentration of the second gate dielectric layer 135 and the oxygen concentration of the third gate dielectric layer 143 are higher than the oxygen concentration of the first gate dielectric layer 133. Therefore, the second gate dielectric layer 135 and the third gate dielectric layer 143 have better oxygen replenishment capabilities, which can prevent the second thin film transistor T2 from failing due to the low resistivity of the second channel region ch2 of the second metal oxide layer OS2. Therefore, the second metal oxide layer OS2 can be formed using a material with high carrier mobility.
[0143] In some embodiments, the thickness of the second buffer layer 120 is 1,000 to 4,000 angstroms. In some embodiments, the thickness of the first gate dielectric layer 135, the second gate dielectric layer 135, the third gate dielectric layer 143, and the fourth gate dielectric layer 145 is 200 to 500 angstroms.
[0144] In some embodiments, the materials of the first metal oxide layer OS1 and the second metal oxide layer OS2 include quaternary metal compounds such as indium gallium tin zinc oxide (IGTZO), indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), aluminum zinc tin oxide (AZTO), and indium tungsten zinc oxide (IWZO), or oxides composed of ternary metals containing any three of gallium (Ga), zinc (Zn), indium (In), tin (Sn), aluminum (Al), and tungsten (W), or lanthanide rare earth doped metal oxides (e.g., Ln-IZO). In some embodiments, the first metal oxide layer OS1 and the second metal oxide layer OS2 comprise the same material. In other embodiments, the first metal oxide layer OS1 and the second metal oxide layer OS2 comprise different materials. In some embodiments, the carrier mobility of the first channel region ch1 of the first metal oxide layer OS1 is different from (greater than or less than) the carrier mobility of the second channel region ch2 of the second metal oxide layer OS2.
[0145] The first gate G1 and the second gate G2 are located on the fourth gate dielectric layer 145 and overlap the first channel region ch1 and the second channel region ch2, respectively. The first gate dielectric layer 133, the second gate dielectric layer 135, the third gate dielectric layer 143, and the fourth gate dielectric layer 145 are located between the first gate G1 and the first metal oxide layer OS1. The third gate dielectric layer 143 and the fourth gate dielectric layer 145 are located between the second gate G2 and the second metal oxide layer OS2.
[0146] The thickness of the insulating material between the first gate G1 and the first metal oxide layer OS1 is greater than the thickness of the insulating material between the second gate G2 and the second metal oxide layer OS2. Therefore, the first thin-film transistor T1 and the second thin-film transistor T2 have different characteristics. For example, the first thin-film transistor T1 has a larger subthreshold swing and better long-term operational reliability; the second thin-film transistor T2 has a larger operating current and a smaller subthreshold swing, enabling high-speed switching.
[0147] An interlayer dielectric layer 150 is located on the fourth gate dielectric layer 145 and covers the first gate G1 and the second gate G2. In some embodiments, the material of the interlayer dielectric layer 150 includes silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, or other insulating materials.
[0148] The first contact hole V1 and the second contact hole V2 pass through the interlayer dielectric layer 150, the first gate dielectric layer 133, the second gate dielectric layer 135, the third gate dielectric layer 143, and the fourth gate dielectric layer 145. The first drain D1 and the first source S1 are located on the interlayer dielectric layer 150 and are respectively filled into the first contact hole V1 and the second contact hole V2 to electrically connect to the first metal oxide layer OS1. The first drain D1 and the first source S1 are respectively connected to the first drain region dr1 and the first source region sr1 of the first metal oxide layer OS1.
[0149] The third contact hole V3 and the fourth contact hole V4 pass through the interlayer dielectric layer 150, the third gate dielectric layer 143, and the fourth gate dielectric layer 145. The second drain D2 and the second source S2 are located on the interlayer dielectric layer 150 and are respectively filled into the third contact hole V3 and the fourth contact hole V4 to electrically connect to the second metal oxide layer OS2. The second drain D2 and the second source S2 are respectively connected to the second drain region dr2 and the second source region sr2 of the second metal oxide layer OS2.
[0150] Figures 8A to 8D yes Figure 7 A cross-sectional schematic diagram of the manufacturing method of the active element substrate 10E.
[0151] Please refer to Figure 8A A first metal oxide layer OS1' is formed on the substrate. In this embodiment, the first metal oxide layer OS1' is formed on the second buffer layer 120. In some embodiments, the fabrication process temperature for forming the first metal oxide layer OS1' is room temperature to 300 degrees Celsius.
[0152] Please refer to Figure 8B A first gate dielectric layer 133 is formed on top of a first metal oxide layer OS1'. A second gate dielectric layer 135 is formed on top of the first gate dielectric layer 133. In some embodiments, the fabrication process temperature for forming the second gate dielectric layer 135 is lower than the fabrication process temperature for forming the first gate dielectric layer 133. For example, the fabrication process temperature for forming the second gate dielectric layer 135 is 200 to 300 degrees Celsius, and the fabrication process temperature for forming the first gate dielectric layer 133 is 300 to 400 degrees Celsius. In some embodiments, the first gate dielectric layer 133 and the second gate dielectric layer 135 comprise the same material (e.g., both are silicon oxide); however, because the fabrication process temperature for forming the second gate dielectric layer 135 is lower, more oxygen can be stored in the second gate dielectric layer 135, resulting in a higher oxygen concentration in the second gate dielectric layer 135 than in the first gate dielectric layer 133.
[0153] A second metal oxide layer OS2' is formed on the second gate dielectric layer 135. In some embodiments, the fabrication process temperature for forming the second metal oxide layer OS2' is 200 degrees Celsius to 300 degrees Celsius. In some embodiments, the first metal oxide layer OS1' and the second metal oxide layer OS2' comprise the same material (e.g., both are indium gallium zinc oxide). Due to the lower fabrication process temperature for forming the second metal oxide layer OS2', the carrier mobility of the second metal oxide layer OS2' is lower than that of the first metal oxide layer OS1', but this invention is not limited thereto. In other embodiments, the second metal oxide layer OS2' and the first metal oxide layer OS1' comprise different materials, and the carrier mobility of the second metal oxide layer OS2' is higher than that of the first metal oxide layer OS1'.
[0154] Please refer to Figure 8C A third gate dielectric layer 143 is formed on top of the second metal oxide layer OS2'. In some embodiments, the fabrication temperature for forming the third gate dielectric layer 143 is lower than the fabrication temperature for forming the first gate dielectric layer 133. For example, the fabrication temperature for forming the third gate dielectric layer 143 is 200 to 300 degrees Celsius. In some embodiments, the first gate dielectric layer 133 and the third gate dielectric layer 143 comprise the same material (e.g., both are silicon oxide); however, because the fabrication temperature for forming the third gate dielectric layer 143 is lower, more oxygen can be stored in the third gate dielectric layer 143, resulting in a higher oxygen concentration in the third gate dielectric layer 143 than in the first gate dielectric layer 133.
[0155] A fourth gate dielectric layer 145 is formed on the third gate dielectric layer 143. In some embodiments, the fabrication process temperature for forming the fourth gate dielectric layer 145 is between 200 degrees Celsius and 400 degrees Celsius.
[0156] A first gate G1 and a second gate G2 are formed on the fourth gate dielectric layer 145. Next, using the first gate G1 and the second gate G2 as masks, a doping process P is performed on the first metal oxide layer OS1' and the second metal oxide layer OS2' to form a first metal oxide layer OS1 including a first source region sr1, a first drain region dr1, and a first channel region ch1, and a second metal oxide layer OS2 including a second source region sr2, a second drain region dr2, and a second channel region ch2. In some embodiments, the doping process P is, for example, a hydrogen plasma fabrication process or other suitable fabrication process.
[0157] The second buffer layer 120, the first gate dielectric layer 133, the second gate dielectric layer 135, and the third gate dielectric layer 143 provide oxygen during the fabrication process, thereby increasing the resistivity of the first metal oxide layer OS1 and the second metal oxide layer OS2.
[0158] In this embodiment, due to the high oxygen concentration in the second gate dielectric layer 135 and the third gate dielectric layer 143, more oxygen can be provided to the second metal oxide layer OS2, thereby preventing the second channel region ch2 of the second metal oxide layer OS2 from becoming a conductor due to excessively high carrier mobility. In some embodiments, the resistivity of the first channel region ch1 is different from the resistivity of the second channel region ch2. In some embodiments, the resistivity of the first drain region dr1 and the first source region sr2 is different from the resistivity of the second drain region dr2 and the second source region sr2.
[0159] In this embodiment, the first gate G1 and the second gate G2 belong to the same patterning layer, and the first metal oxide layer OS1 and the second metal oxide layer OS2 can be doped by the same doping process P, thus saving the manufacturing cost of the first thin film transistor and the second thin film transistor.
[0160] Please refer to Figure 8D An interlayer dielectric layer 150 is formed on the fourth gate dielectric layer 145. Next, an etching process is performed to form the first contact hole V1, the second contact hole V2, the third contact hole V3, and the fourth contact hole V4.
[0161] Finally, please return to Figure 7 A first drain D1, a first source S1, a second drain D2, and a second source S2 are formed on the interlayer dielectric layer 150 and respectively filled into the first contact hole V1, the second contact hole V2, the third contact hole V3, and the fourth contact hole V4. At this point, the active element substrate 10E is substantially completed.
[0162] Figure 9 This is a schematic cross-sectional view of an active element substrate according to an embodiment of the present invention. It should be noted that... Figure 9 The embodiments follow Figures 7 to 8D The component reference numerals and partial contents of the embodiments are described below, wherein the same or similar reference numerals are used to represent the same or similar components, and descriptions of the same technical content are omitted. For explanations of the omitted parts, please refer to the foregoing embodiments, and will not be repeated here.
[0163] Figure 9 Active component substrate 10F and Figure 7The main difference between the active element substrate 10E and the active element substrate 10F is that the first gate dielectric layer 133 of the active element substrate 10F includes a first dielectric structure 133a and a second dielectric structure 133b, the second gate dielectric layer 135 includes a third dielectric structure 135a and a fourth dielectric structure 135b, the third gate dielectric layer 143 includes a fifth dielectric structure 143a and a sixth dielectric structure 143b, and the fourth gate dielectric layer 145 includes a seventh dielectric structure 145a and an eighth dielectric structure 145b.
[0164] The first gate G1 overlaps with the first dielectric structure 133a, the third dielectric structure 135a, the fifth dielectric structure 143a, and the seventh dielectric structure 145a. The first dielectric structure 133a, the third dielectric structure 135a, the fifth dielectric structure 143a, and the seventh dielectric structure 145a are located between the first gate G1 and the first channel region ch1.
[0165] The second gate G2 overlaps with the second dielectric structure 133b, the fourth dielectric structure 135b, the sixth dielectric structure 143b, and the eighth dielectric structure 145b. The sixth dielectric structure 143b and the eighth dielectric structure 145b are located between the second gate G2 and the second channel region ch2. The second dielectric structure 133b and the fourth dielectric structure 135b are located between the second metal oxide layer OS2 and the second buffer layer 120.
[0166] The interlayer dielectric layer 150 contacts the sidewalls of the first dielectric structure 133a, the second dielectric structure 133b, the third dielectric structure 135a, the fourth dielectric structure 135b, the fifth dielectric structure 143a, the sixth dielectric structure 143b, the seventh dielectric structure 145a, the eighth dielectric structure 145b, the first source region sr1, the first drain region dr1, the second source region sr2, the second drain region dr2, and the top surface of the second buffer layer 120.
[0167] Figures 10A to 10B yes Figure 9 A cross-sectional schematic diagram of the manufacturing method of the active element substrate 10F.
[0168] Please refer to Figure 10A , continuing Figure 8C The fabrication process uses the first gate G1, the second gate G2, and the second metal oxide layer OS2 as a mask to etch the first gate dielectric layer 133, the second gate dielectric layer 135, the third gate dielectric layer 143, and the fourth gate dielectric layer 145. In some embodiments, the aforementioned etching process also removes a portion of the second buffer layer 120. Figure 8C The doping process P can be performed before or after the aforementioned etching process. This invention does not limit the order of the doping process P and the aforementioned etching process.
[0169] In this embodiment, the sidewalls of the first dielectric structure 133a, the third dielectric structure 135a, the fifth dielectric structure 143a, and the seventh dielectric structure 145a are aligned with the sidewalls of the first gate G1, the sidewalls of the sixth dielectric structure 143b and the eighth dielectric structure 145b are aligned with the sidewalls of the second gate G2, and the sidewalls of the second dielectric structure 133b and the fourth dielectric structure 135b are aligned with the sidewalls of the second metal oxide layer OS2.
[0170] Please refer to Figure 10B An interlayer dielectric layer 150 is formed on the second buffer layer 120, the first metal oxide layer OS1, and the second metal oxide layer OS2. The interlayer dielectric layer 150 directly contacts the first source region sr1, the first drain region dr1, the second source region sr2, and the second drain region dr2. In some embodiments, the interlayer dielectric layer 150 contains hydrogen, and the hydrogen in the interlayer dielectric layer 150 diffuses into the first source region sr1, the first drain region dr1, the second source region sr2, and the second drain region dr2 to reduce the resistivity of the first source region sr1, the first drain region dr1, the second source region sr2, and the second drain region dr2.
[0171] Next, an etching process is performed to form the first contact hole V1, the second contact hole V2, the third contact hole V3, and the fourth contact hole V4.
[0172] Finally, please return to Figure 9 A first drain D1, a first source S1, a second drain D2, and a second source S2 are formed on the interlayer dielectric layer 150 and respectively filled into the first contact hole V1, the second contact hole V2, the third contact hole V3, and the fourth contact hole V4. At this point, the active element substrate 10F is substantially completed.
Claims
1. A method for manufacturing an active component substrate, comprising: A blanket-covered first buffer layer is formed on the substrate; A second cushioning layer is formed on top of the first cushioning layer, covered with a blanket. A first metal oxide layer is formed on the second buffer layer, the first buffer layer, and the substrate; A first gate dielectric layer is formed on the first metal oxide layer, and the fabrication process temperature for forming the first gate dielectric layer is 300 degrees Celsius to 400 degrees Celsius. A second gate dielectric layer is formed on top of the first gate dielectric layer. The fabrication process temperature for forming the second gate dielectric layer is 200 degrees Celsius to 300 degrees Celsius. The fabrication process temperature for forming the second gate dielectric layer is lower than the fabrication process temperature for forming the first gate dielectric layer, and the oxygen concentration of the second gate dielectric layer is higher than the oxygen concentration of the first gate dielectric layer. A second metal oxide layer is formed on the second gate dielectric layer, and the fabrication process temperature for forming the second metal oxide layer is 200 degrees Celsius to 300 degrees Celsius. A third gate dielectric layer is formed on the second metal oxide layer, wherein the fabrication process temperature for forming the third gate dielectric layer is lower than the fabrication process temperature for forming the first gate dielectric layer, and the oxygen concentration of the third gate dielectric layer is higher than the oxygen concentration of the first gate dielectric layer. A fourth gate dielectric layer is formed on the third gate dielectric layer; A first gate and a second gate belonging to the same patterned layer are formed on the fourth gate dielectric layer, wherein the first gate dielectric layer, the second gate dielectric layer, the third gate dielectric layer and the fourth gate dielectric layer are located between the first gate and the first metal oxide layer, and the third gate dielectric layer and the fourth gate dielectric layer are located between the second gate and the second metal oxide layer. Using the first gate and the second gate as masks, a doping process is performed on the first metal oxide layer and the second metal oxide layer to form a first metal oxide layer including a first source region, a first drain region and a first channel region, and a second metal oxide layer including a second source region, a second drain region and a second channel region. An interlayer dielectric layer is formed on the first gate, the second gate, the second buffer layer, the first metal oxide layer, and the second metal oxide layer; An etching process is performed on the interlayer dielectric layer to form the first contact hole, the second contact hole, the third contact hole, and the fourth contact hole; A first source and a first drain are formed by electrically connecting the first metal oxide layer through the second contact hole and the first contact hole, respectively, to form a first thin film transistor; as well as A second source and a second drain are formed by electrically connecting the second metal oxide layer through the fourth contact hole and the third contact hole, respectively, to form a second thin film transistor.
2. The method for manufacturing an active element substrate as claimed in claim 1, wherein the fabrication process temperature for forming the third gate dielectric layer is 200 degrees Celsius to 300 degrees Celsius.
3. The method for manufacturing an active element substrate as claimed in claim 1, wherein the fabrication process temperature for forming the fourth gate dielectric layer is 200 degrees Celsius to 400 degrees Celsius, wherein the first gate dielectric layer includes a first dielectric structure and a second dielectric structure, the second gate dielectric layer includes a third dielectric structure and a fourth dielectric structure, the third gate dielectric layer includes a fifth dielectric structure and a sixth dielectric structure, the fourth gate dielectric layer includes a seventh dielectric structure and an eighth dielectric structure, and the first gate is superimposed on the first dielectric structure, the third dielectric structure, the fifth dielectric structure, and the fourth gate dielectric layer. A seventh dielectric structure is provided, wherein the sidewalls of the first, third, fifth, and seventh dielectric structures are aligned with the sidewalls of the first gate. The first, third, fifth, and seventh dielectric structures are located between the first gate and the first channel region. The second gate overlaps the second, fourth, sixth, and eighth dielectric structures. The sidewalls of the sixth and eighth dielectric structures are aligned with the sidewalls of the second gate. The structure is located between the second gate and the second channel region. The second dielectric structure and the fourth dielectric structure are located between the second metal oxide layer and the second buffer layer. The sidewalls of the second dielectric structure and the fourth dielectric structure are aligned with the sidewalls of the second metal oxide layer. The interlayer dielectric layer directly contacts the sidewalls of the first dielectric structure, the second dielectric structure, the third dielectric structure, the fourth dielectric structure, the fifth dielectric structure, the sixth dielectric structure, the seventh dielectric structure, and the eighth dielectric structure. The first source region, the first drain region, the second source region, the second drain region, and the top surface of the second buffer layer are connected. The interlayer dielectric layer directly contacts the first gate, the second gate, the second buffer layer, the first source region, the first drain region, the second source region, and the second drain region. The interlayer dielectric layer contains hydrogen, and the hydrogen in the interlayer dielectric layer diffuses into the first source region, the first drain region, the second source region, and the second drain region to reduce the resistivity of the first source region, the first drain region, the second source region, and the second drain region.
4. The method for manufacturing an active element substrate as described in claim 1, wherein, The fabrication process temperature for forming the first metal oxide layer is between room temperature and 300 degrees Celsius.