Semiconductor device
By setting P-type isolation pillars in the high and low voltage junction termination regions, high-voltage devices can be fabricated, solving the problem of excessively large PN junction isolation area, increasing the density of integrated circuits and reducing costs.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- WUXI NCE POWER
- Filing Date
- 2021-03-15
- Publication Date
- 2026-06-12
Smart Images
Figure CN115548089B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a semiconductor device, and more particularly to a power semiconductor device that is easy to integrate. Background Technology
[0002] With the rapid development of integrated circuit technology, integrated circuits are increasingly moving towards higher density, higher performance, and higher reliability.
[0003] High density requires integrated circuits to integrate a variety of different circuits and devices, making full use of the limited area of the integrated circuit to achieve as many functions as possible. For integrated circuits, especially analog integrated circuits, the inside of the chip is generally divided into high-voltage regions, low-voltage regions, and high-low junction termination regions that isolate the high-voltage and low-voltage regions. Some more complex analog circuits, due to the different operating voltages in each region, may divide the entire chip into even more voltage operating regions, and appropriate isolation needs to be set between different voltage operating regions.
[0004] Currently, commonly used isolation technologies for single-chip integrated circuits include PN junction isolation and SOI isolation. Among them, PN junction isolation is the most widely used isolation technology in power integrated circuits because it achieves the best trade-off between cost and performance. However, when PN junction isolation is used for higher voltage isolation, it often requires a larger area to withstand the high voltage, which contradicts the need for high-density development of integrated circuits. Summary of the Invention
[0005] The purpose of this invention is to overcome the contradiction between the excessive area occupied by PN junction isolation in the prior art and the need for high-density integrated circuit development, and to provide a novel semiconductor device. The device of this invention can make full use of the area of the high and low voltage junction termination regions to fabricate various power devices, improve the utilization rate of chip area, increase the density of integrated circuits, and thus reduce the cost of integrated circuits.
[0006] To achieve the above technical objectives, the technical solution adopted by this invention is as follows:
[0007] An embodiment of the present invention provides a semiconductor device comprising: a P-type substrate, an N-type doped epitaxial layer on the P-type substrate, a high-voltage region and a low-voltage region on the N-type doped epitaxial layer, a high-low voltage junction termination region between the high-voltage region and the low-voltage region, a first P-type isolation pillar between the low-voltage region and the high-low voltage junction termination region, a second P-type isolation pillar between the high-voltage region and the high-low voltage junction termination region, the second P-type isolation pillar being connected to the first P-type isolation pillar, the first P-type isolation pillar and the second P-type isolation pillar forming one or more closed regions, and a high-voltage device disposed in the closed region.
[0008] The high-voltage device is one or more of the following: JFET device, LDMOS device, LIGBT device, and power diode device.
[0009] Embodiments of the present invention also provide a method for fabricating a semiconductor device, comprising the following steps:
[0010] Step 1: Select a P-type substrate material, implant boron ions using a mask window, and anneal to form a P-type buried layer;
[0011] Step 2: An N-type doped epitaxial layer is grown on the P-type substrate. Due to the high temperature, the P-type buried layer diffuses upward. Using a mask window, a P-type deep well is selectively implanted by ion implantation and then annealed.
[0012] Step 3: Grow a layer of silicon nitride on the silicon surface, use a mask window to etch the field oxide layer area, and oxidize and grow the field oxide layer in the area where there is no silicon nitride covering the surface.
[0013] Step 4: Grow a gate oxide layer and deposit gate polysilicon on the device surface, and use a mask window to etch away the excess gate oxide layer and gate polysilicon.
[0014] Step 5: Using a mask window, heavily doped N-type high-concentration contacts and P-type high-concentration contacts are implanted to form the gate, source, and drain;
[0015] Step 6: Deposit an insulating dielectric layer, then selectively etch through-holes on the insulating dielectric layer, followed by depositing and selectively etching the metal to form the source metal, drain metal, and gate metal;
[0016] An embodiment of the present invention also provides a method for fabricating a semiconductor device, comprising the following steps:
[0017] Step 1: Select a P-type substrate material, implant boron ions using a mask window, and anneal to form a P-type buried layer;
[0018] Step 2: An N-type doped epitaxial layer is grown on the P-type substrate. Due to the high temperature, the P-type buried layer diffuses upward. Using a mask window, a P-type deep well is selectively implanted by ion implantation and then annealed.
[0019] Step 3: Selectively etch longitudinal trenches on the N-type doped epitaxial layer, grow an oxide layer in the longitudinal trenches, and deposit polysilicon to fill the trenches to form gate polysilicon;
[0020] Step 4: Grow a layer of silicon nitride on the silicon surface, use a mask window to etch the field oxide layer area, and oxidize and grow the field oxide layer in the area where there is no silicon nitride covering the surface.
[0021] Step 5: Using a mask window, heavily doped N-type high-concentration contacts and P-type high-concentration contacts are implanted to form the gate, source, and drain;
[0022] Step 6: Deposit an insulating dielectric layer, then selectively etch through-holes on the insulating dielectric layer, followed by depositing and selectively etching the metal to form the source metal, drain metal, and gate metal.
[0023] In the two fabrication methods described above, in step two, during ion implantation, P-type regions and P-type deep traps are selectively implanted and then annealed.
[0024] Compared with the prior art, the main advantages of the present invention are as follows:
[0025] Integrated circuits, especially power integrated circuits, often require the integration of power devices to meet the demands of high-voltage, high-current applications. Traditional integrated circuits typically have separate low-voltage and high-voltage regions, as well as high- and low-voltage junction termination regions responsible for isolating the high- and low-voltage regions. If the voltage difference between the high- and low-voltage regions is too large, the high- and low-voltage junction termination regions may occupy a significant area to withstand the voltage. This invention fully utilizes the area of the high- and low-voltage junction termination regions to fabricate various power semiconductor devices, eliminating the need for additional chip area and improving chip area utilization, thereby reducing the cost of integrated circuits. Attached Figure Description
[0026] Appendix Figure 1 This is a schematic diagram of the layout of the present invention;
[0027] Appendix Figure 2 This is a cross-sectional view along AA' of the first type of structure in the present invention where the high-voltage device is a JFET and no P-type region is provided;
[0028] Appendix Figure 3 This is a second cross-sectional view along AA' when the high-voltage device in the structure of this invention is a JFET;
[0029] Appendix Figure 4 This is a third cross-sectional view along AA' when the high-voltage device in the structure of this invention is a JFET;
[0030] Appendix Figure 5 This is a fourth cross-sectional view along AA' when the high-voltage device in the structure of this invention is a JFET;
[0031] Appendix Figure 6 This is a three-dimensional structural diagram of the fifth type along AA' when the high-voltage device in the structure of this invention is a JFET;
[0032] Appendix Figure 7 This is a three-dimensional structural diagram of the sixth type along AA' when the high-voltage device in the structure of this invention is a JFET;
[0033] Appendix Figure 8 This is a cross-sectional view along AA' when the high-voltage device in the structure of this invention is an LDMOS;
[0034] Appendix Figure 9 This is a cross-sectional view along AA' when the high-voltage device in the structure of this invention is a LIGBT;
[0035] Appendix Figure 10 This is a cross-sectional view along AA' when the high-voltage device in the structure of this invention is a power diode;
[0036] Appendix Figure 11 This is a cross-sectional view of the structure after the P-type embedded layer is injected in the manufacturing method of the present invention;
[0037] Appendix Figure 12 This is a cross-sectional view of the structure after the formation of the P-type buried layer, the P-type region, and the P-type deep well in the manufacturing method of the present invention.
[0038] Appendix Figure 13 This is a cross-sectional view of the structure after the field oxide layer is formed in the manufacturing method of the present invention;
[0039] Appendix Figure 14 This is a cross-sectional view of the gate polysilicon after it has been formed in the fabrication method of the present invention;
[0040] Appendix Figure 15 This is a cross-sectional view of the N-type high-concentration contact and the P-type high-concentration contact formed in the manufacturing method of the present invention.
[0041] Appendix Figure 16 This is a cross-sectional view of the trench gate JFET fabrication method of the present invention after the longitudinal trench is formed;
[0042] Appendix Figure 17 This is a cross-sectional view of the trench gate JFET fabrication method of the present invention after the formation of the field oxide layer;
[0043] Appendix Figure 18 This is a cross-sectional view of the trench gate JFET fabrication method of the present invention after forming N-type high-concentration contacts and P-type high-concentration contacts;
[0044] Appendix Figure 19 This is the layout structure of the present invention, which contains a single high-voltage device;
[0045] Appendix Figure 20 This is the layout structure of the present invention, which contains multiple high-voltage devices;
[0046] Explanation of reference numerals in the attached figures: 001—P-type substrate; 002—P-type buried layer; 003—P-type region; 004—P-type deep well; 005—N-type high-concentration contact; 006—P-type high-concentration contact; 008—N-type doped epitaxial layer; 010—Gate oxide layer; 011—Source metal; 012—Gate polysilicon; 013—Drain metal; 014—Gate metal; 015—Emitter metal; 016—Collector metal; 017—Anode metal; 018—Cathode metal; 020—Vertical trench; 110—High voltage region; 120—High-low voltage junction termination region; 130a—First P-type isolation pillar; 130b—Second P-type isolation pillar; 140—Low voltage region; I—First high voltage device; II—Second high voltage device; III—Third high voltage device. Detailed Implementation
[0047] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.
[0048] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other. The present invention will now be described in detail with reference to the accompanying drawings and embodiments.
[0049] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.
[0050] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of the invention described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.
[0051] Embodiments of the present invention provide a semiconductor device structure, with reference to Figure 1A P-type substrate 001 is provided, and an N-type doped epitaxial layer 008 is provided on the P-type substrate 001. A high-voltage region 110 and a low-voltage region 140 are provided on the N-type doped epitaxial layer 008. A high-low voltage junction termination region 120 is provided between the high-voltage region 110 and the low-voltage region 140. A first P-type isolation pillar 130a is provided between the low-voltage region 140 and the high-low voltage junction termination region 120. A second P-type isolation pillar 130b is provided between the high-voltage region 110 and the high-low voltage junction termination region 120. The second P-type isolation pillar 130b is connected to the first P-type isolation pillar 130a. The first P-type isolation pillar 130a and the second P-type isolation pillar 130b form one or more closed regions. High-voltage devices are provided in each closed region.
[0052] exist Figure 1 In the example shown, the first P-type isolation post 130a and the second P-type isolation post 130b form three enclosed regions, and the three enclosed regions are respectively equipped with a first high-voltage device I, a second high-voltage device II, and a third high-voltage device III; Figure 19 In the example shown, the first P-type isolation post 130a and the second P-type isolation post 130b form a closed area, in which a first high-voltage device I is disposed; Figure 20 In the example shown, the first P-type isolation post 130a and the second P-type isolation post 130b form four closed areas, and the four closed areas are respectively provided with a first high-voltage device I, a second high-voltage device II, a third high-voltage device III and a fourth high-voltage device IV;
[0053] The high-voltage devices I, II, and III mentioned above can be one of JFET, LDMOS, LIGBT, or high-voltage power diode. Among them, JFET devices have various structures. The high-voltage devices in this embodiment can be of the same type or different types.
[0054] The area of different high-voltage devices can be varied according to actual needs, and the area of the enclosed area isolated by the P-type isolation column can be varied according to the area of the high-voltage device.
[0055] In one embodiment, such as Figure 2As shown, the high-voltage device is a JFET device, including a P-type substrate 001. The first P-type isolation pillar 130a and the second P-type isolation pillar 130b each include a P-type buried layer 002 and a P-type deep well 004 arranged sequentially from bottom to top. The P-type buried layer 002 is located at the junction of the N-type doped epitaxial layer 008 and the P-type substrate 001, and the P-type buried layer 002 is led to the surface through the P-type deep well 004. The P-type deep well 004 of the first P-type isolation pillar 130a is connected to the gate metal 014 through a P-type high-concentration contact 006. The N-type doped epitaxial layer 008 region between the first P-type isolation pillar 130a and the second P-type isolation pillar 130b... The region serves as the drift region of the high-voltage device. On the side of the drift region closest to the gate metal 014, an N-type high-concentration contact 005 is provided, connected to the source metal 011. On the other side away from the gate metal 014, an N-type high-concentration contact 005 is provided, connected to the drain metal 013. A field oxide layer is provided above the N-type doped epitaxial layer 008. Above the field oxide layer, on the side closest to the source metal 011 towards the center, a gate polysilicon 012 is provided. A gate oxide layer 010 is provided between the gate polysilicon 012 and the field oxide layer. An island-shaped P-type buried layer 002 is also provided at the junction of the N-type doped epitaxial layer 008 and the P-type substrate 001 below the gate polysilicon 012.
[0056] In one embodiment, such as Figure 3 As shown, the high-voltage device is a JFET device, including a P-type substrate 001. The first P-type isolation pillar 130a and the second P-type isolation pillar 130b each include a P-type buried layer 002, a P-type region 003, and a P-type deep well 004 arranged sequentially from bottom to top. The P-type buried layer 002 is located at the junction of the N-type doped epitaxial layer 008 and the P-type substrate 001, and is led to the surface through the P-type region 003 and the P-type deep well 004. The P-type deep well 004 of the first P-type isolation pillar 130a is connected to the gate metal 014 through a P-type high-concentration contact 006. The N-type doped epitaxial layer 008 region between the first P-type isolation pillar 130a and the second P-type isolation pillar 130b serves as a high-concentration contact. The drift region of the voltage device has an N-type high-concentration contact 005 connected to the source metal 011 on the side near the gate metal 014 and an N-type high-concentration contact 005 connected to the drain metal 013 on the other side away from the gate metal 014. A field oxide layer is provided above the N-type doped epitaxial layer 008. A gate polysilicon 012 is provided above the field oxide layer on the side of the source metal 011 facing towards the middle. A gate oxide layer 010 is provided between the gate polysilicon 012 and the field oxide layer. An island-shaped P-type buried layer 002 is also provided at the junction of the N-type doped epitaxial layer 008 and the P-type substrate 001 below the gate polysilicon 012. A P-type region 003 is provided above the island-shaped P-type buried layer 002.
[0057] In one embodiment, such as Figure 4As shown, the high-voltage device is a JFET device, including a P-type substrate 001. The first P-type isolation pillar 130a and the second P-type isolation pillar 130b each include a P-type buried layer 002, a P-type region 003, and a P-type deep well 004 arranged sequentially from bottom to top. The P-type buried layer 002 is located at the junction of the N-type doped epitaxial layer 008 and the P-type substrate 001, and is led to the surface through the P-type region 003 and the P-type deep well 004. The P-type deep well 004 of the first P-type isolation pillar 130a is connected to the gate metal 014 through a P-type high-concentration contact 006. The N-type doped epitaxial layer 008 between the first P-type isolation pillar 130a and the second P-type isolation pillar 130b... The epitaxial layer 008 region serves as the drift region of the high-voltage device. In the drift region, an N-type high-concentration contact 005 is provided on the side near the gate metal 014, connected to the source metal 011. On the other side away from the gate metal 014, an N-type high-concentration contact 005 is provided, connected to the drain metal 013. A field oxide layer is provided above the N-type doped epitaxial layer 008. Above the field oxide layer, on the side near the source metal 011 towards the center, a gate polysilicon 012 is provided. A gate oxide layer 010 is provided between the gate polysilicon 012 and the field oxide layer. The P-type buried layer 002 and the P-type region 003 of the first P-type isolation pillar 130a extend laterally towards the center to below the gate polysilicon 012.
[0058] In one embodiment, such as Figure 5 As shown, the high-voltage device is a JFET device, including a P-type substrate 001. The first P-type isolation pillar 130a and the second P-type isolation pillar 130b each include a P-type buried layer 002, a P-type region 003, and a P-type deep well 004 arranged sequentially from bottom to top. The P-type buried layer 002 is located at the junction of the N-type doped epitaxial layer 008 and the P-type substrate 001, and is led to the surface through the P-type region 003 and the P-type deep well 004. The P-type deep well 004 of the first P-type isolation pillar 130a is connected to the gate metal 014 through a P-type high-concentration contact 006. The N-type doped epitaxial layer 008 region between the first P-type isolation pillar 130a and the second P-type isolation pillar 130b serves as a high-concentration contact. The drift region of the voltage device has an N-type high-concentration contact 005 connected to the source metal 011 on the side near the gate metal 014, and an N-type high-concentration contact 005 connected to the drain metal 013 on the other side away from the gate metal 014. A field oxide layer is provided above the N-type doped epitaxial layer 008. A longitudinal trench 020 is provided on the side of the drift region near the source metal 011 towards the middle. A gate polysilicon 012 wrapped by an oxide layer is provided in the longitudinal trench 020. An island-shaped P-type buried layer 002 is also provided at the junction of the N-type doped epitaxial layer 008 and the P-type substrate 001 below the gate polysilicon 012. A P-type region 003 is provided above the island-shaped P-type buried layer 002.
[0059] In one embodiment, such as Figure 6 As shown, the high-voltage device is a JFET device, including a P-type substrate 001. The first P-type isolation pillar 130a and the second P-type isolation pillar 130b each include a P-type buried layer 002, a P-type region 003, and a P-type deep well 004 arranged sequentially from bottom to top. The P-type buried layer 002 is located at the junction of the N-type doped epitaxial layer 008 and the P-type substrate 001, and is led to the surface through the P-type region 003 and the P-type deep well 004. The P-type deep well 004 of the first P-type isolation pillar 130a is connected to the gate metal 014 through a P-type high-concentration contact 006. The first P-type isolation pillar 130a and the second P-type isolation pillar 130b... The N-type doped epitaxial layer 008 region between the N-type isolation pillars 130b serves as the drift region of the high-voltage device. In the drift region, an N-type high-concentration contact 005 is provided on the side near the gate metal 014, connecting to the source metal 011. On the other side away from the gate metal 014, an N-type high-concentration contact 005 is provided, connecting to the drain metal 013. A field oxide layer is provided above the N-type doped epitaxial layer 008. A longitudinal trench 020 is provided on the side of the drift region near the source metal 011 towards the center. A gate polysilicon 012 encased in an oxide layer is provided within the longitudinal trench 020. The longitudinal trenches 020 are spaced apart in the Y direction.
[0060] In one embodiment, such as Figure 7 As shown, the high-voltage device is a JFET device, including a P-type substrate 001. The first P-type isolation pillar 130a and the second P-type isolation pillar 130b each include a P-type buried layer 002, a P-type region 003, and a P-type deep well 004 arranged sequentially from bottom to top. The P-type buried layer 002 is located at the junction of the N-type doped epitaxial layer 008 and the P-type substrate 001, and is led to the surface through the P-type region 003 and the P-type deep well 004. The P-type deep well 004 of the first P-type isolation pillar 130a is connected to the gate metal 014 through a P-type high-concentration contact 006. The first P-type isolation pillar 130a and the second P-type isolation pillar 130b... The N-type doped epitaxial layer 008 region between the pillar 130b serves as the drift region of the high-voltage device. In the drift region, an N-type high-concentration contact 005 is provided on the side near the gate metal 014, which is connected to the source metal 011. On the other side away from the gate metal 014, an N-type high-concentration contact 005 is provided, which is connected to the drain metal 013. A field oxide layer is provided above the N-type doped epitaxial layer 008. In the drift region, on the side near the source metal 011 towards the middle, from the junction of the N-type doped epitaxial layer 008 and the P-type substrate 001, P-type buried layer 002, P-type region 003 and P-type deep well 004 are sequentially provided along the Y direction at intervals.
[0061] It should be noted that, in Figure 6 and Figure 7Gate metal 014, source metal 011, and drain metal 013 are not shown; please refer to [the provided text]. Figures 2-5 ;
[0062] In one embodiment, such as Figure 8 As shown, the high-voltage device is an LDMOS device, including a P-type substrate 001. The first P-type isolation pillar 130a and the second P-type isolation pillar 130b each include a P-type buried layer 002, a P-type region 003, and a P-type deep well 004 arranged sequentially from bottom to top. The P-type buried layer 002 is located at the junction of the N-type doped epitaxial layer 008 and the P-type substrate 001. The P-type buried layer 002 is led to the surface through the P-type region 003 and the P-type deep well 004. The surface of the P-type deep well 004 of the first P-type isolation pillar 130a is provided with a P-type high-concentration contact 006 and an N-type high-concentration contact 005, and is connected to the source metal... The N-type doped epitaxial layer 008 region between the first P-type isolation pillar 130a and the second P-type isolation pillar 130b serves as the drift region of the high-voltage device. A field oxide layer is provided above the N-type doped epitaxial layer 008. The gate polysilicon 012 extends from the N-type high-concentration contact 005 on the surface of the P-type deep well 004 of the first P-type isolation pillar 130a toward the middle to one end above the field oxide layer of the drift region. A gate oxide layer 010 is also provided below the gate polysilicon 012. An N-type high-concentration contact 005 is provided on the other side of the drift region away from the source metal 011 and is connected to the drain metal 013.
[0063] In one embodiment, such as Figure 9 As shown, the high-voltage device is a LIGBT device, including a P-type substrate 001. The first P-type isolation pillar 130a and the second P-type isolation pillar 130b each include a P-type buried layer 002, a P-type region 003, and a P-type deep well 004 arranged sequentially from bottom to top. The P-type buried layer 002 is located at the interface between the N-type doped epitaxial layer 008 and the P-type substrate 001, and is led to the surface through the P-type region 003 and the P-type deep well 004. The surface of the P-type deep well 004 of the first P-type isolation pillar 130a is provided with a P-type high-concentration contact 006 and an N-type high-concentration contact 005, which are connected to the emitter metal. 015 are connected; the N-type doped epitaxial layer 008 region between the first P-type isolation pillar 130a and the second P-type isolation pillar 130b serves as the drift region of the high-voltage device; a field oxide layer is provided above the N-type doped epitaxial layer 008; the gate polysilicon 012 extends from the N-type high-concentration contact 005 on the surface of the P-type deep well 004 of the first P-type isolation pillar 130a toward the middle to one end above the field oxide layer of the drift region, and a gate oxide layer 010 is also provided below the gate polysilicon 012; an N-type high-concentration contact 005 is provided on the other side of the drift region away from the emitter metal 015 and connected to the collector metal 016;
[0064] In one embodiment, such as Figure 10As shown, the high-voltage device is a power diode device, including a P-type substrate 001. The first P-type isolation pillar 130a and the second P-type isolation pillar 130b each include a P-type buried layer 002, a P-type region 003, and a P-type deep well 004 arranged sequentially from bottom to top. The P-type buried layer 002 is located at the junction of the N-type doped epitaxial layer 008 and the P-type substrate 001. The P-type buried layer 002 is led to the surface through the P-type region 003 and the P-type deep well 004. A P-type high-concentration contact 006 is provided on the surface of the P-type deep well 004 of the first P-type isolation pillar 130a and connected to the anode metal 017. The N-type doped epitaxial layer 008 region between the first P-type isolation pillar 130a and the second P-type isolation pillar 130b serves as the drift region of the high-voltage device. An N-type high-concentration contact 005 is provided on the other side of the drift region away from the anode metal 017 and connected to the cathode metal 018.
[0065] like Figures 11-15 As shown, embodiments of the present invention also provide a method for fabricating a semiconductor device, comprising the following steps:
[0066] Step 1: Select a P-type substrate 001 material, implant boron ions using a mask window, and anneal to form a P-type buried layer 002;
[0067] Step 2: An N-type doped epitaxial layer 008 is grown on the P-type substrate 001. The P-type buried layer 002 diffuses upward due to high temperature. Using a mask window, P-type regions 003 and P-type deep wells 004 are selectively implanted by ion implantation and then annealed.
[0068] Step 3: Grow a layer of silicon nitride on the silicon surface, use a mask window to etch the field oxide layer area, and oxidize and grow the field oxide layer in the area where there is no silicon nitride covering the surface.
[0069] Step 4: Grow a gate oxide layer 010 and deposit gate polysilicon 012 on the device surface, and use a mask window to etch away the excess gate oxide layer 010 and gate polysilicon 012.
[0070] Step 5: Using a mask window, heavily doped N-type high-concentration contacts 005 and P-type high-concentration contacts 006 are implanted to form the gate, source, and drain, respectively.
[0071] Step 6: Deposit an insulating dielectric layer, then selectively etch through-holes on the insulating dielectric layer, then deposit and selectively etch metal to form source metal 011, drain metal 013, and gate metal 014.
[0072] Optionally, refer to Figure 2 The P-type deep well 004 can be directly connected to the P-type buried layer 002. In the above embodiment, the P-type region 003 is no longer injected during device fabrication.
[0073] like Figures 16-18 As shown, embodiments of the present invention also provide a method for fabricating a semiconductor device, comprising the following steps:
[0074] Step 1: Select a P-type substrate 001 material, implant boron ions using a mask window, and anneal to form a P-type buried layer 002;
[0075] Step 2: An N-type doped epitaxial layer 008 is grown on the P-type substrate 001. The P-type buried layer 002 diffuses upward due to high temperature. Using a mask window, P-type regions 003 and P-type deep wells 004 are selectively implanted by ion implantation and then annealed.
[0076] Step 3: Selectively etch vertical trenches 020 on the N-type doped epitaxial layer 008, grow an oxide layer in the vertical trenches 020, and deposit polysilicon to fill the trenches to form gate polysilicon 012.
[0077] Step 4: Grow a layer of silicon nitride on the silicon surface, use a mask window to etch the field oxide layer area, and oxidize and grow the field oxide layer in the area where there is no silicon nitride covering the surface.
[0078] Step 5: Using a mask window, heavily doped N-type high-concentration contacts 005 and P-type high-concentration contacts 006 are implanted to form the gate, source, and drain, respectively.
[0079] Step 6: Deposit an insulating dielectric layer, then selectively etch through-holes on the insulating dielectric layer, followed by depositing and selectively etching metal to form source metal 011, drain metal 013, and gate metal 014.
[0080] Optionally, refer to Figure 2 The P-type deep well 004 can be directly connected to the P-type buried layer 002. In the above embodiment, the P-type region 003 is no longer injected during device fabrication.
[0081] Finally, it should be noted that the above specific embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to examples, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.
Claims
1. A semiconductor device, comprising: A P-type substrate (001) is provided with an N-type doped epitaxial layer (008) on the P-type substrate (001). A high-voltage region (110) and a low-voltage region (140) are provided on the N-type doped epitaxial layer (008). A high-low voltage junction termination region (120) is provided between the high-voltage region (110) and the low-voltage region (140). The first P-type isolation pillar (130a) is provided between the low-voltage region (140) and the high-low voltage junction termination region (120). A second P-type isolation pillar (130b) is provided between the high-voltage region (110) and the high-low voltage junction termination region (120). The second P-type isolation pillar (130b) is connected to the first P-type isolation pillar (130a). The first P-type isolation pillar (130a) and the second P-type isolation pillar (130b) form one or more closed regions. A high-voltage device is disposed in the closed region. The high-voltage device is a LIGBT device, including a P-type substrate (001). The first P-type isolation pillar (130a) and the second P-type isolation pillar (130b) each include a P-type buried layer (002), a P-type region (003), and a P-type deep well (004) arranged sequentially from bottom to top. The P-type buried layer (002) is located at the junction of the N-type doped epitaxial layer (008) and the P-type substrate (001). The P-type buried layer (002) is led to the surface through the P-type region (003) and the P-type deep well (004). The surface of the P-type deep well (004) of the first P-type isolation pillar (130a) is provided with a P-type high-concentration contact (006) and an N-type high-concentration contact (005) and is connected to the emitter gold. The N-type doped epitaxial layer (008) region between the first P-type isolation pillar (130a) and the second P-type isolation pillar (130b) serves as the drift region of the high-voltage device; a field oxide layer is provided above the N-type doped epitaxial layer (008); the gate polysilicon (012) extends from the N-type high-concentration contact (005) on the surface of the P-type deep well (004) of the first P-type isolation pillar (130a) towards the middle to one end above the field oxide layer of the drift region, and a gate oxide layer (010) is also provided below the gate polysilicon (012); an N-type high-concentration contact (005) is provided on the other side of the drift region away from the emitter metal (015) and connected to the collector metal (016).