GaN HEMT device structure with gate protection function and manufacturing method thereof

Abstract

The application provides a GaN HEMT device structure with a gate protection function, which comprises a GaN HEMT device, a first nucleation layer, a PN diode formed on the first nucleation layer, and a first nucleation layer formed on the GaN HEMT device; wherein the PN diode comprises a p+ type GaN layer and an n+ type GaN layer formed on a first region and a second region of the first nucleation layer respectively, and a cathode and an anode formed on the GaN HEMT device, the cathode being connected with the p+ type GaN layer, and the anode being connected with the n+ type GaN layer; the first region and the second region are opposite along a first direction, and the first direction represents a horizontal direction on a paper plane; and the breakdown voltage of the PN diode is less than the breakdown voltage of the GaN HEMT device. The technical scheme provided by the application solves the problem that the gate of a traditional structure GaN HEMT device is easily broken down, and achieves the technical effect of protecting the GaN HEMT device from being damaged.

Description

Technical Field

[0001] This invention relates to the field of semiconductor devices, and more particularly to a GaN HEMT device structure with gate protection function and its fabrication method. Background Technology

[0002] Gallium nitride (GaN), as a prominent representative of third-generation semiconductor materials, differs from traditional silicon-based power devices. High Electron Mobility Transistors (HEMTs) based on GaN utilize the polarization effect of GaN to accumulate a two-dimensional electron gas at the AlGaN / GaN heterojunction interface, forming a lateral conductive channel. The two-dimensional electron gas in the conductive channel possesses excellent electrical properties, such as high electron mobility, making AlGaN / GaN HEMT devices promising for applications in high-frequency and high-power power devices.

[0003] Among the existing solutions for realizing the enhancement mode of gallium nitride devices, pGaN gate-enhanced gallium nitride high mobility transistors (pGaN gate HEMTs) have great commercial value due to their good balance between performance, reliability and cost.

[0004] However, for pGaN-gate GaN HEMTs, under DC static gate stress, high-energy electrons accelerate in the depleted p-GaN layer, generating defect energy levels that convert the Schottky gate into an ohmic-like gate. Ultimately, excessive current density at the gate leads to breakdown. Developing a novel GaN HEMT device that can prevent gate breakdown has become a key technical challenge for those skilled in the art. Summary of the Invention

[0005] This invention provides a GaN HEMT device structure with gate protection function and its fabrication method to solve the problem of how to protect the gate of traditional GaN HEMT devices from easy breakdown.

[0006] According to a first aspect of the present invention, a GaN HEMT device structure with gate protection function is provided, comprising:

[0007] GaN HEMT devices;

[0008] A first nucleation layer; the first nucleation layer is formed on the GaN HEMT device; and

[0009] A PN diode formed on the first nucleation layer;

[0010] The PN diode includes: a p+ type GaN layer and an n+ type GaN layer respectively formed on a first region and a second region on the first nucleation layer; and a cathode and an anode formed on the GaN HEMT device, wherein the cathode is connected to the p+ type GaN layer and the anode is connected to the n+ type GaN layer; the first region and the second region are opposite to each other along a first direction, wherein the first direction characterizes the direction in which the anode of the PN diode points to the cathode or the direction in which the cathode points to the anode;

[0011] The breakdown voltage of the PN diode is lower than that of the GaN HEMT device.

[0012] Optionally, the GaN HEMT device includes:

[0013] A substrate and a second nucleation layer, a buffer layer, a first channel layer, and a barrier layer sequentially formed on the substrate along a direction away from the substrate;

[0014] A source, a gate, and a drain are formed on the barrier layer; the source, the gate, and the drain are arranged along the first direction; wherein the gate includes a p-GaN layer and a gate metal layer formed at the top of the p-GaN layer; wherein the gate metal layer serves as the anode of the PN diode; the cathode is formed on the barrier layer; and

[0015] A passivation layer formed on the barrier layer and filling the gap between the source, the drain and the gate.

[0016] Optionally, the GaN HEMT device further includes:

[0017] Source metal interconnect layer, gate metal interconnect layer and drain metal interconnect layer are respectively formed at the top of the source, the gate and the drain; the anode is connected to the n+ type GaN layer through the gate metal interconnect layer;

[0018] An isolation layer; the isolation layer is formed in the barrier layer and the first channel layer on the side of the source and the drain away from the gate; and

[0019] A gate field plate; the gate field plate is formed on the passivation layer at the top of the gate and connected to the gate.

[0020] Optionally, the structure of the GaN HEMT device with gate protection function further includes:

[0021] A cathode metal interconnect layer is formed at the top of the cathode; the cathode is connected to the p+ type GaN layer through the cathode metal interconnect layer; and

[0022] A passivation layer is formed in the gap between the cathode metal interconnect layer and the adjacent source electrode, and in the gap between the drain electrode and the adjacent drain electrode.

[0023] Optionally, the first nucleation layer and the second nucleation layer are made of AlN, the first channel layer is made of GaN, and the barrier layer is made of AlGaN.

[0024] According to a second aspect of the present invention, a method for fabricating a GaN HEMT device structure with gate protection function is provided, comprising:

[0025] Provide a substrate;

[0026] A second nucleation layer, a buffer layer, a first channel layer, a barrier layer, and a p-GaN layer are sequentially formed on the substrate along a direction away from the substrate, and an isolation layer is formed thereon; the p-GaN layer covers a portion of the barrier layer; the isolation layer is formed in the barrier layer and the first channel layer on both sides of the p-GaN layer along a first direction;

[0027] This forms the source, drain, and cathode.

[0028] A gate and an anode are formed; the gate includes the p-GaN layer and a gate metal layer formed on top of the p-GaN layer; and the gate metal layer serves as the anode;

[0029] A passivation layer is deposited at the top of the gate;

[0030] A first nucleation layer is formed; the first nucleation layer is formed on the passivation layer at the top of the gate; and

[0031] A p+GaN channel layer and an n+GaN channel layer are formed in the nodular region of the first nucleation layer; a GaN HEMT device, the first nucleation layer, and a PN diode are formed.

[0032] The breakdown voltage of the PN diode is lower than that of the GaN HEMT device.

[0033] Optionally, forming a p+GaN channel layer and an n+GaN channel layer in the nodular region of the first nucleation layer includes:

[0034] A second channel layer is formed; the second channel layer is formed on the nodular region and the non-nodular region of the first nucleation layer;

[0035] P+ ions are implanted in a first region of the nodule region to form the p+GaN channel layer, and n+ ions are implanted in a second region of the nodule region to form the n+GaN channel layer; and

[0036] A layer of photoresist is coated on the surface of the second channel layer, the photoresist is exposed and developed to form a patterned photoresist, and the second channel layer in the non-nodular region is etched using the patterned photoresist as a mask.

[0037] Optionally, the fabrication method of the GaN HEMT device structure with gate protection function further includes:

[0038] A source metal interconnect layer, a gate metal interconnect layer, a drain metal interconnect layer, and a cathode metal interconnect layer are formed at the top of the source, the gate, the drain, and the cathode, respectively, and a gate field plate is formed on the passivation layer at the top of the gate; wherein, the gate field plate connects the gate metal interconnect layer and the n+GaN channel layer.

[0039] Optionally, forming the gate and anode specifically includes:

[0040] The passivation layer is deposited on the surface of the barrier layer; the passivation layer fills the voids between the source, the drain, the p-GaN layer, and the cathode;

[0041] Etching the passivation layer at the top of the p-GaN layer forms a gate cavity; and

[0042] The gate metal layer is deposited in the gate cavity to form the gate and the anode.

[0043] According to a third aspect of the present invention, a method for fabricating an electronic device is provided, comprising: a method for fabricating a GaN HEMT device structure with gate protection function as described in any of the second aspects of the present invention.

[0044] According to a fourth aspect of the present invention, an electronic device is provided, the electronic device having a GaN HEMT device structure with gate protection function according to the first aspect of the present invention.

[0045] This invention provides a GaN HEMT device structure with gate protection function. By connecting a PN diode to the gate of the GaN HEMT device, since the breakdown voltage of the connected PN diode is lower than that of the original GaN HEMT device, the PN diode can be ensured to break down first when a destructive voltage is present. This prevents the gate of the GaN HEMT device from being subjected to destructive voltage and thus avoids breakdown. This solves the problem that the gate of traditional GaN HEMT devices is easily broken down, achieving the technical effect of protecting the GaN HEMT device and improving its performance. Attached Figure Description

[0046] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0047] Figure 1 This is a schematic flowchart of a method for fabricating a GaN HEMT device structure with gate protection function according to an embodiment of the present invention;

[0048] Figure 2 This is a schematic diagram of a device structure fabricated at different process stages according to a method for fabricating a GaN HEMT device structure with gate protection function, provided in an embodiment of the present invention. Figure 1 ;

[0049] Figure 3 This is a schematic diagram of a device structure fabricated at different process stages according to a method for fabricating a GaN HEMT device structure with gate protection function, provided in an embodiment of the present invention. Figure 2 ;

[0050] Figure 4 This is a schematic diagram of a device structure fabricated at different process stages according to a method for fabricating a GaN HEMT device structure with gate protection function, provided in an embodiment of the present invention. Figure 3 ;

[0051] Explanation of reference numerals in the attached figures:

[0052] 101-Substrate;

[0053] 102 - Second nucleation layer;

[0054] 103 - Buffer layer;

[0055] 104 - First channel layer;

[0056] 105 - Barrier layer;

[0057] 106 - Isolation layer;

[0058] 107-p-GaN layer;

[0059] 108-Source;

[0060] 109-Drain;

[0061] 110 - Cathode;

[0062] 111 - Gate metal layer;

[0063] 112 - First nucleation layer;

[0064] 113-p+GaN channel layer;

[0065] 114-n+GaN channel layer;

[0066] 115 - Gate field plate;

[0067] 116 - Cathode metal interconnect layer;

[0068] 117 - Gate metal interconnect layer;

[0069] 118-Passivation layer. Detailed Implementation

[0070] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0071] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0072] Gallium nitride (GaN), as a prominent representative of third-generation semiconductor materials, differs from traditional silicon-based power devices. High Electron Mobility Transistors (HEMTs) based on GaN utilize the polarization effect of GaN to accumulate a two-dimensional electron gas at the AlGaN / GaN heterojunction interface, forming a lateral conductive channel. The two-dimensional electron gas in the conductive channel possesses excellent electrical properties, including high electron mobility, making AlGaN / GaN HEMT devices promising for applications in high-frequency and high-power power devices. Among the existing methods for realizing enhancement-mode GaN devices, pGaN gate-enhanced GaN high-mobility transistors (pGaN gate HEMTs) have significant commercial value due to their excellent balance between performance, reliability, and cost.

[0073] However, for pGaN-gate GaN HEMTs, under DC static gate stress, high-energy electrons accelerate in the depleted p-GaN layer, generating defect levels that convert the Schottky gate into an ohmic-like gate. Ultimately, the gate breaks down due to excessively high current density. Specifically, when a large voltage or continuous electrical stress is applied between the gate and source of a GaN HEMT, carrier injection and tunneling occur between the gate metal and GaN. Due to the weak avalanche performance of GaN material and the very thin thickness of the pGaN and AlGaN stack, the gate region of HEMTs is prone to breakdown.

[0074] To address the gate breakdown problem in traditional GaN HEMTs, the inventors of this application propose a novel GaN HEMT device with gate protection. This novel GaN HEMT device connects a GaN-based avalanche PN diode to the gate of the GaN HEMT, wherein the breakdown voltage of the diode is slightly lower than the gate breakdown voltage. This ensures that the PN junction undergoes avalanche breakdown and conduction before the gate experiences destructive breakdown, thus preventing the gate from being subjected to destructive voltage.

[0075] It is evident that the technical solution provided in this application solves the gate breakdown problem of traditional GaN HEMTs.

[0076] The technical solution of the present invention will be described in detail below with reference to specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0077] Please refer to Figure 4 According to an embodiment of the present invention, a GaN HEMT device structure with gate protection function is provided, comprising:

[0078] GaN HEMT devices;

[0079] A first nucleation layer 112; the first nucleation layer 112 is formed on the GaN HEMT device; and

[0080] A PN diode formed on the first nucleation layer 112;

[0081] The PN diode includes: a p+ type GaN layer and an n+ type GaN layer formed on a first region and a second region respectively on the first nucleation layer 112; and a cathode 110 and an anode formed on the GaN HEMT device, wherein the cathode 110 is connected to the p+ type GaN layer and the anode is connected to the n+ type GaN layer; the first region and the second region are arranged sequentially along a first direction, wherein the first direction represents the direction in which the anode of the PN diode points to the cathode or the direction in which the cathode points to the anode; that is, the stacking direction of the GaN HEMT device and the first nucleation layer on the paper plane is perpendicular to the stacking direction of the GaN HEMT device and the first nucleation layer.

[0082] The breakdown voltage of the PN diode is lower than that of the GaN HEMT device.

[0083] The first region refers to the P-type region of the PN diode; the second region refers to the N-type region of the PN diode.

[0084] This invention provides a GaN HEMT device structure with gate protection function. By connecting a PN diode to the gate of the GaN HEMT device, the breakdown voltage of the connected PN diode is lower than that of the original GaN HEMT device, thus ensuring that the PN diode is broken down first, thereby protecting the GaN HEMT device and solving the problem that the gate of traditional GaN HEMT devices is easily broken down.

[0085] As can be seen, the technical solution provided by the present invention solves the problem that the gate of traditional GaN HEMT devices is easily broken down by introducing a PN diode into the gate of the GaN HEMT device, thereby achieving the technical effect of improving device performance.

[0086] In one embodiment, the GaN HEMT device includes:

[0087] The substrate 101 and a second nucleation layer 102, a buffer layer 103, a first channel layer 104, and a barrier layer 105 are sequentially formed on the substrate 101 along a direction away from the substrate 101; the material of the first nucleation layer 102 and the second nucleation layer 102 is AlN, the material of the first channel layer 104 is GaN, and the material of the barrier layer 105 is AlGaN; of course, it can also be other materials of the corresponding structural layers, and the present invention is not limited thereto. Any implementation of the material of the corresponding structural layer is within the protection scope of the present invention.

[0088] A source 108, a gate, and a drain 109 are formed on the barrier layer 105; the source 108, the gate, and the drain 109 are arranged along the first direction; wherein, the gate includes: a p-GaN layer 107 and a gate metal layer 111 formed at the top of the p-GaN layer 107; wherein, the gate metal layer 111 also serves as the anode of the PN diode; the cathode 110 is formed on the barrier layer 105 in the GaN HEMT device; and

[0089] A passivation layer 118 is formed on the barrier layer 105 and fills the gap between the source 108, the drain 109 and the gate.

[0090] As can be seen, the integration of the PN diode and GaN HEMT device on the GaN HEMT device by sharing the gate metal layer 111 solves the problem that the gate of the GaN HEMT device is easily broken down.

[0091] In one embodiment, the GaN HEMT device further includes:

[0092] A source metal interconnect layer, a gate metal interconnect layer 117, and a drain metal interconnect layer are respectively formed at the top of the source 108, the gate, and the drain 109; the anode is connected to the n+ type GaN layer through the gate metal interconnect layer 117.

[0093] Isolation layer 106; the isolation layer 106 is formed in the barrier layer 105 and the first channel layer 104 on the side of the source 108 and the drain 109 away from the gate; and

[0094] Gate field plate 115; the gate field plate 115 is formed on the passivation layer 118 at the top of the gate and connected to the gate.

[0095] In one embodiment, the structure of the GaN HEMT device with gate protection function further includes:

[0096] A cathode metal interconnect layer 116 is formed at the top of the cathode 110; the cathode 110 is connected to the p+ type GaN layer through the cathode metal interconnect layer 116; and

[0097] A passivation layer 118 is formed in the gap between the cathode metal interconnect layer 116 and the adjacent source 108, and in the gap between the drain 109 and the adjacent drain 109, forming a GaNHEMT device with gate protection function, such as... Figure 4 As shown.

[0098] Please refer to Figure 1-4 According to another embodiment of the present invention, a method for fabricating a GaN HEMT device structure with gate protection function is also provided, wherein the flowchart of the method for fabricating a GaN HEMT device structure with gate protection function is shown below. Figure 1 As shown, the method specifically includes steps S11-S17:

[0099] S11: Provide a substrate 101;

[0100] S12: A second nucleation layer 102, a buffer layer 103, a first channel layer 104, a barrier layer 105, and a p-GaN layer 107 are sequentially formed on the substrate 101 in a direction away from the substrate 101, and an isolation layer 106 is formed; the p-GaN layer 107 covers a portion of the barrier layer 105; the isolation layer 106 is formed in the barrier layer 105 and the first channel layer 104 on both sides of the p-GaN layer 107 along a first direction; in one embodiment, the isolation layer 106 is formed by implanting ions at corresponding positions.

[0101] The device formed after step S12 is as follows Figure 2 As shown;

[0102] S13: Forms source 108, drain 109 and cathode 110;

[0103] S14: Forming a gate and an anode; the gate includes the p-GaN layer 107 and a gate metal layer 111 formed on the top of the p-GaN layer 107; and the gate metal layer 111 serves as the anode;

[0104] In one embodiment, step S14, forming the gate and the anode, specifically includes: S141-S143:

[0105] S141: Deposit the passivation layer 118 on the surface of the barrier layer 105; the passivation layer 118 fills the gap between the source 108, the drain 109, the p-GaN layer 107 and the cathode 110;

[0106] S142: Etching the passivation layer 118 at the top of the p-GaN layer 107 to form a gate cavity; and

[0107] S143: Deposit the gate metal layer 111 in the gate cavity to form the gate and the anode.

[0108] S15: Deposit a passivation layer 118 at the top of the gate;

[0109] S16: Forming a first nucleation layer 112; the first nucleation layer 112 is formed on the passivation layer 118 at the top of the gate. The device after step S16 is as follows: Figure 3 As shown; and

[0110] S17: Form p+GaN channel layer 113 and n+GaN channel layer 114 in the nodal region of the first nucleation layer 112; form a GaN HEMT device, the first nucleation layer 112 and a PN diode;

[0111] The breakdown voltage of the PN diode is lower than that of the GaN HEMT device.

[0112] In one embodiment, step S17, forming a p+GaN channel layer 113 and an n+GaN channel layer 114 in the nodular region of the first nucleation layer 112, includes steps S171-S173:

[0113] S171: Formation of a second channel layer; the second channel layer is formed on the nodular region and the non-nodular region of the first nucleation layer 112;

[0114] S172: P+ ions are implanted in the first region of the nodule region to form the p+GaN channel layer 113, and n+ ions are implanted in the second region of the nodule region to form the n+GaN channel layer 114; and

[0115] S173: Coat a layer of photoresist on the surface of the second channel layer, expose and develop the photoresist to form a patterned photoresist, and use the patterned photoresist as a mask to etch the second channel layer in the non-nodular region.

[0116] In one embodiment, the method for fabricating a GaN HEMT device structure with gate protection function further includes:

[0117] S18: A source metal interconnect layer, a gate metal interconnect layer 117, a drain metal interconnect layer, and a cathode metal interconnect layer 116 are formed at the top of the source 108, the gate, the drain 109, and the cathode 110, respectively. A gate field plate 115 is formed on the passivation layer 118 at the top of the gate. The gate field plate 115 connects the gate metal interconnect layer 117 and the n+GaN channel layer 114. The device after step S18 is as follows: Figure 4 As shown.

[0118] The method for fabricating a GaN HEMT device structure with gate protection provided in this application involves fabricating a PN diode onto the GaN HEMT device. Utilizing the characteristic that the PN diode is more prone to avalanche breakdown and conduction than the GaN HEMT device, the PN diode conducts first when encountering a destructive voltage. Therefore, the gate of the GaN HEMT device is not subjected to a destructive voltage, thereby protecting the GaN HEMT device.

[0119] In addition, according to other embodiments of the present invention, a method for fabricating an electronic device is also provided, comprising: a method for fabricating a GaN HEMT device structure with gate protection function as described in any of the foregoing embodiments of the present invention.

[0120] Secondly, according to an embodiment of the present invention, an electronic device is also provided, the electronic device comprising the GaN HEMT device structure with gate protection function described in the foregoing embodiments of the present invention.

[0121] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for fabricating a GaN HEMT device structure with gate protection function, characterized in that, include: Provide a substrate; A second nucleation layer, a buffer layer, a first channel layer, a barrier layer, and a p-GaN layer are sequentially formed on the substrate along a direction away from the substrate, and an isolation layer is formed thereon; the p-GaN layer covers a portion of the barrier layer; the isolation layer is formed in the barrier layer and the first channel layer on both sides of the p-GaN layer along a first direction; This forms the source, drain, and cathode. A gate and an anode are formed; the gate includes the p-GaN layer and a gate metal layer formed on top of the p-GaN layer; and the gate metal layer serves as the anode; A passivation layer is deposited at the top of the gate; The first nucleation layer is formed; The first nucleation layer is formed on the passivation layer at the top of the gate; as well as A p+GaN channel layer and an n+GaN channel layer are formed in the nodal region of the first nucleation layer to form a GaN HEMT device, the first nucleation layer, and a PN diode. The breakdown voltage of the PN diode is lower than that of the GaN HEMT device.

2. The method for fabricating a GaN HEMT device structure with gate protection function according to claim 1, characterized in that, The formation of p+GaN channel layers and n+GaN channel layers in the nodular region of the first nucleation layer includes: A second channel layer is formed; the second channel layer is formed on the nodular region and the non-nodular region of the first nucleation layer; P+ ions are implanted in a first region of the nodule region to form the p+GaN channel layer, and n+ ions are implanted in a second region of the nodule region to form the n+GaN channel layer; and A layer of photoresist is coated on the surface of the second channel layer, the photoresist is exposed and developed to form a patterned photoresist, and the second channel layer in the non-nodular region is etched using the patterned photoresist as a mask.

3. The method for fabricating a GaN HEMT device structure with gate protection function according to claim 2, characterized in that, Also includes: A source metal interconnect layer, a gate metal interconnect layer, a drain metal interconnect layer, and a cathode metal interconnect layer are formed at the source, the gate, the drain, and the cathode, respectively, and a gate field plate is formed on the passivation layer at the top of the gate; wherein, the gate field plate connects the gate metal interconnect layer and the n+GaN channel layer.

4. The method for fabricating a GaN HEMT device structure with gate protection function according to claim 3, characterized in that, The formation of the gate and anode specifically includes: The passivation layer is deposited on the surface of the barrier layer; the passivation layer fills the voids between the source, the drain, the p-GaN layer, and the cathode; Etching the passivation layer at the top of the p-GaN layer forms a gate cavity; and The gate metal layer is deposited in the gate cavity to form the gate and the anode.

5. A method for manufacturing an electronic device, characterized in that, include: A method for fabricating a GaN HEMT device structure with gate protection function as described in any one of claims 1 to 4.

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