A metallized heterojunction cell and method of making the same
By depositing TCO and Cu films on the back of heterojunction solar cells and employing laser grooving and low-temperature silver paste printing techniques, the problem of high production costs for heterojunction solar cells has been solved, achieving cost reduction and stable performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- JETION SOLAR HLDG
- Filing Date
- 2022-10-20
- Publication Date
- 2026-06-19
AI Technical Summary
Heterojunction solar cells have high production costs, especially due to the large consumption of low-temperature silver paste and TCO target materials, which affects their mass production development.
A transparent conductive oxide (TCO), a Cu film, and another layer of transparent conductive oxide (TCO) are deposited on the back side of the heterojunction cell to reduce the consumption of TCO and Ag. Metal grid lines are formed by laser grooving and low-temperature silver paste printing to conduct current.
It effectively reduces battery costs while maintaining stable battery performance, reduces TCO film and Ag consumption, and improves battery efficiency and conductivity.
Smart Images
Figure CN115548140B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to batteries, specifically a metallized heterojunction battery and its preparation method. Background Technology
[0002] The rapid development of the photovoltaic industry chain in recent years is essentially driven by technology to reduce costs and improve efficiency. Currently, the trend towards monocrystalline silicon is established, the efficiency improvement progress of p-type cells is slowing down, while n-type cells have great potential for efficiency enhancement. Looking ahead, we believe the most anticipated transformation in the photovoltaic industry lies in the shift from p-type to n-type cells in the cell manufacturing process. Among these, heterojunction and tunnel-tunnel junction cells, with their high efficiency and significant cost reduction potential, are becoming important development directions for the photovoltaic industry.
[0003] Heterojunction solar cells use an n-type monocrystalline silicon wafer as a substrate. An intrinsic amorphous silicon thin film and an n-type amorphous silicon layer are sequentially deposited on the front side of the texturized and cleaned n-type silicon wafer to form an n-n+ heterojunction. An intrinsic amorphous silicon thin film and a p-type amorphous silicon layer are sequentially deposited on the back side to form a p-n heterojunction. Transparent conductive oxide (TCO) films are then deposited on both sides of the doped amorphous silicon thin film. Finally, metal electrodes are formed on the top layers on both sides using screen printing, resulting in a symmetrical heterojunction solar cell.
[0004] Heterojunction solar cells have attracted widespread attention due to their excellent conversion efficiency and simple process steps. Currently, heterojunction solar cells are in a stage of rapid development, but their high production cost seriously hinders their mass production. Low-temperature silver paste and TCO target materials account for a significant portion of their production cost. Therefore, reducing the consumption of low-temperature silver paste and TCO target materials can effectively reduce the cost of heterojunction solar cells and promote their mass production. Summary of the Invention
[0005] To address the shortcomings of the prior art, this invention provides a metallized heterojunction battery and its fabrication method. This invention utilizes a back-side deposition of a transparent conductive oxide (TCO) layer, a Cu film, and another transparent conductive oxide (TCO) layer to reduce the consumption of TCO and Ag, thereby reducing battery costs and ensuring stable battery performance.
[0006] To achieve the above technical objectives, the present invention adopts the following technical solution: a metallized heterojunction solar cell, comprising a silicon wafer, the silicon wafer having a front side and a back side, the front side being sequentially deposited with a front amorphous silicon layer, a front transparent conductive oxide film, and a front gate line, the back side being sequentially deposited with a back amorphous silicon layer, a back first transparent conductive oxide film, a back copper film, and a back second transparent conductive oxide film, the back second transparent conductive oxide film being provided with a back main gate line.
[0007] Furthermore, the silicon wafer is an n-type monocrystalline silicon wafer or a p-type monocrystalline silicon wafer.
[0008] Furthermore, the front amorphous silicon layer is n-type amorphous silicon, and the back amorphous silicon layer is p-type amorphous silicon.
[0009] Furthermore, one end of the back main gate line is connected to the back copper film, and the other end extends outward after passing through the back second transparent conductive oxide film.
[0010] A method for fabricating a metallized heterojunction solar cell, comprising the following steps:
[0011] S1. A front amorphous silicon layer is deposited on the front side of the silicon wafer that has been texturized and cleaned in sequence, and a back amorphous silicon layer is deposited on the back side. A front transparent conductive oxide film is then deposited on the front amorphous silicon layer.
[0012] S2. Sequentially deposit the first transparent conductive oxide film, the copper film, and the second transparent conductive oxide film on the back side outside the amorphous silicon layer on the back side;
[0013] S3. Laser grooving is performed on the second transparent conductive oxide film on the back side;
[0014] S4. Screen printing and silver paste curing are performed on the front transparent conductive oxide film and the back second transparent conductive oxide film to obtain the front gate line and the back main gate line;
[0015] S5, photothermal treatment.
[0016] Furthermore, in step S1, the thickness of the front transparent conductive oxide film is 70-120 nm.
[0017] Further, in step S2, the thickness of the first transparent conductive oxide film on the back side is 2-5 nm, the thickness of the copper film on the back side is 1-10 μm, and the thickness of the second transparent conductive oxide film on the back side is 2-10 nm.
[0018] Further, step S3 includes the following sub-step: slotting the second transparent conductive oxide film on the back side to expose the copper film on the back side, and the exposed shape is the shape of the main gate line on the back side.
[0019] Further, step S4 includes the following sub-steps: screen printing the front main grid and fine grid and the back main grid of the monocrystalline silicon wafer after step S3. The screen printing process uses low-temperature silver paste printing. Then, the screen-printed monocrystalline silicon wafer is sent into a curing oven for curing at a temperature of 180-250°C.
[0020] In summary, the present invention has achieved the following technical effects:
[0021] This invention deposits a TCO2 film, a Cu metal film, and a TCO3 film on the back of the battery to collect current and reduce reflection; after laser grooving on the film, Ag metal main grid lines are printed at the grooving positions to conduct current.
[0022] The silicon wafer of this invention can be either n-type or p-type, and is not limited to n-type, thus offering better adaptability;
[0023] This invention designs a structure for the TCO film layer and metallization on the back of the battery. Compared with conventional heterojunction batteries, the metallization scheme prepared using the structure of this invention can effectively reduce the consumption of TCO film and Ag, thereby significantly reducing battery costs. Attached Figure Description
[0024] Figure 1 This is a schematic diagram of the metallization structure of an n-type heterojunction battery provided in an embodiment of the present invention;
[0025] Figure 2 This is a schematic diagram of the metallization structure of a p-type heterojunction battery provided in an embodiment of the present invention;
[0026] Figure 3 This is a schematic diagram of a conventional heterojunction solar cell. Detailed Implementation
[0027] The present invention will be further described in detail below with reference to the accompanying drawings.
[0028] This specific embodiment is merely an explanation of the present invention and is not intended to limit the invention. After reading this specification, those skilled in the art can make modifications to this embodiment without contributing any inventive step, but such modifications are protected by patent law as long as they are within the scope of the claims of the present invention.
[0029] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.
[0030] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.
[0031] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.
[0032] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "over," and "on top" of the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.
[0033] Example:
[0034] A metallized heterojunction solar cell includes a silicon wafer 1, which is an n-type monocrystalline silicon wafer or a p-type monocrystalline silicon wafer. Figure 1 The silicon wafer 1 shown is an n-type monocrystalline silicon wafer, such as Figure 2 The silicon wafer 1 shown is a p-type monocrystalline silicon wafer.
[0035] The silicon wafer 1 has a front side and a back side. The front side is sequentially deposited with a front amorphous silicon layer 2, a front transparent conductive oxide film 3, and a front gate line 4. The back side is sequentially deposited with a back amorphous silicon layer 5, a back first transparent conductive oxide film 6, a back copper film 7, and a back second transparent conductive oxide film 8. The back second transparent conductive oxide film 8 is provided with a back main gate line 9.
[0036] In this embodiment, both the front amorphous silicon layer 2 and the back amorphous silicon layer 5 are made of a-Si amorphous silicon. The front amorphous silicon layer 2 is n-type amorphous silicon, and the back amorphous silicon layer 5 is p-type amorphous silicon.
[0037] Combination Figure 1This is a schematic diagram of the bonding structure between an n-type monocrystalline silicon wafer and a-Si amorphous silicon. When silicon wafer 1 is an n-type monocrystalline silicon wafer, the front a-Si amorphous silicon layer is n-type, and the back a-Si amorphous silicon layer is p-type. Figure 2 This diagram illustrates the combined structure of a p-type monocrystalline silicon wafer and a-Si amorphous silicon. When silicon wafer 1 is a p-type monocrystalline silicon wafer, the front a-Si amorphous silicon layer is n-type, and the back a-Si amorphous silicon layer is p-type. Therefore, silicon wafer 1 in this cell can be either n-type or p-type, and is not limited to n-type.
[0038] In this embodiment, the front transparent conductive oxide film 3, the back first transparent conductive oxide film 6, and the back second transparent conductive oxide film 8 are all TCO (transparent conductive oxide) layers. In this document, the front transparent conductive oxide film 3 is referred to as TCO1, the back first transparent conductive oxide film 6 as TCO2, and the back second transparent conductive oxide film 8 as TCO3. TCO1, TCO2, and TCO3 can all be ITO (indium tin oxide), IWO (indium tungsten oxide), ICO (indium cerium oxide), or AZO (aluminum-doped zinc oxide) films. Different types of target materials can be used for the TCO films, with TCO films being the optimal choice for optical, electrical, and cost performance.
[0039] Combination Figure 1 and Figure 2 The front gate line 4 is an Ag metal gate line, and the back main gate line 9 is an Ag metal main gate line. One end of the back main gate line 9 is connected to the back copper film 7, and the other end passes through the back second transparent conductive oxide film 8 and extends to the outside as the back main gate line.
[0040] The copper film 7 on the back side, as a Cu metal film layer, can effectively increase conductivity, reduce the film thickness of TCO2 and TCO3 and the consumption of the back main gate line 9, thereby reducing costs.
[0041] A method for fabricating a metallized heterojunction solar cell includes the following steps:
[0042] S1. A front amorphous silicon layer 2 is deposited on the front side of the silicon wafer 1 that has been texturized and cleaned in sequence, and a back amorphous silicon layer 5 is deposited on the back side. A front transparent conductive oxide film 3 is deposited on the front amorphous silicon layer 2.
[0043] In step S1, the thickness of the front transparent conductive oxide film 3, i.e., TCO1, is 70-120 nm, which can be optimally adjusted according to the electrical properties and film color.
[0044] S2. Sequentially deposit a first transparent conductive oxide film 6, a copper film 7, and a second transparent conductive oxide film 8 on the back side outside the amorphous silicon layer 5.
[0045] Among them, a TCO2 film, a Cu metal film, and a TCO3 film are sequentially deposited after the amorphous silicon layer 5 on the back side, which serve to collect current and reduce reflection.
[0046] In step S2, the first transparent conductive oxide film 6 on the back side, namely the TCO2 film layer, is deposited using PVD or RPD equipment. The thickness of the TCO2 film is 2-5 nm, and the target material is an ITO target material.
[0047] Cu metal films were deposited on TCO2 films using PVD equipment, with a film thickness of 1-10 μm, and Cu was used as the target material.
[0048] A TCO3 film with a thickness of 2-10 nm was deposited on a Cu metal film. The target material was ITO or AZO.
[0049] S3. Laser grooving is performed on the second transparent conductive oxide film 8 on the back side;
[0050] Step S3 includes the following sub-steps: slotting the second transparent conductive oxide film 8 on the back side to expose the copper film 7 on the back side, and the exposed shape is the shape of the back main gate line 9; that is, using a laser to slot the back main gate, removing the TCO3 film layer on the outer surface of the Cu metal film layer, and printing Ag metal main gate lines at the slotted position after laser slotting on the TCO3 film layer for current conduction.
[0051] S4. Screen printing and silver paste curing are performed on the front transparent conductive oxide film 3 and the back second transparent conductive oxide film 8 to obtain the front grid line 4 and the back main grid line 9.
[0052] Step S4 includes the following sub-steps: screen printing the front main grid and fine grid and the back main grid of the single crystal silicon wafer after step S3. The screen printing process uses low-temperature silver paste printing. Commercial silver paste can be used, such as silver paste from Crystal Silver manufacturer.
[0053] Then, the screen-printed monocrystalline silicon wafers are sent to a curing oven for curing at a temperature of 180-250℃.
[0054] S5, photothermal treatment;
[0055] In step S5, photothermal treatment using either electrical injection or optical injection can effectively improve efficiency. After treatment, an I-V test is performed to obtain battery performance data. The I-V test uses a long pulse and nonlinear scanning method to eliminate the capacitance effect and employs instruments from manufacturers such as Weixin for measurement.
[0056] Example 1:
[0057] Batteries fabricated using metallization schemes for heterojunctions, such as Figure 1As shown, the structure includes an n-type single-crystal silicon wafer; after a back-side amorphous silicon layer is deposited, a TCO2 film, a Cu metal film, and a TCO3 film are deposited sequentially, serving to collect current and reduce reflection; after laser grooving on the films, Ag metal main gate lines are printed at the grooving locations to conduct current. The metallization scheme prepared using the structure of this invention can effectively reduce the consumption of TCO film and Ag.
[0058] A metallization scheme and preparation method suitable for heterojunctions, specifically including the following steps:
[0059] S1. A TCO1 thin film is deposited on the front side of the original silicon wafer that has undergone texturing, cleaning and front and back a-Si amorphous silicon layer deposition processes in sequence.
[0060] The thickness of the TCO1 film on the front side is 100 nm.
[0061] S2. Sequentially deposit a TCO2 film, a Cu film, and a TCO3 film on the back a-Si amorphous silicon layer.
[0062] A TCO2 film with a thickness of 2 nm was deposited using PVD or RPD equipment, with an ITO target. A Cu metal film with a thickness of 6 μm was deposited on the TCO2 film using PVD equipment, with a Cu target. A TCO3 film with a thickness of 10 nm was deposited on the Cu metal film, with an ITO target.
[0063] S3. Laser grooving is performed on the TCO3 film layer on the back side;
[0064] The back main gate is slotted using a laser to remove the TCO3 thin film on the outer surface of the Cu metal film layer;
[0065] S4. Screen printing and silver paste curing are performed to obtain Ag metal grid lines;
[0066] After step S3, the monocrystalline silicon wafer is screen printed with the front main grid and fine grid and the back main grid. The screen printing paste is low temperature silver paste. Then the screen-printed monocrystalline silicon wafer is sent into a curing oven for curing. The curing conditions are 200℃ and 30min.
[0067] S5. Light injection yields the metallized heterojunction solar cell:
[0068] Photothermal treatment using light injection can effectively improve efficiency. After the treatment is completed, I-V testing is performed to obtain battery performance data.
[0069] Example 2:
[0070] Batteries fabricated using metallization schemes for heterojunctions, such as Figure 2As shown, the structure includes a p-type single-crystal silicon wafer; after a back-side amorphous silicon layer is deposited, a TCO2 film, a Cu metal film, and a TCO3 film are sequentially deposited, serving to collect current and reduce reflection; after laser grooving on the films, Ag metal main gate lines are printed at the grooving locations to conduct current. The metallization scheme prepared using the structure of this invention can effectively reduce the consumption of TCO film and Ag.
[0071] A metallization scheme and preparation method suitable for heterojunctions, specifically including the following steps:
[0072] S1. A TCO1 thin film is deposited on the front side of the original silicon wafer that has undergone texturing, cleaning and front and back a-Si amorphous silicon layer deposition processes in sequence.
[0073] The front-side TCO1 film thickness is 70nm;
[0074] S2. Sequentially deposit a TCO2 film, a Cu film, and a TCO3 film on the back a-Si amorphous silicon layer.
[0075] A TCO2 film with a thickness of 5 nm was deposited using PVD or RPD equipment, with an ITO target. A Cu metal film with a thickness of 10 μm was deposited on the TCO2 film using PVD equipment, with a Cu target. A TCO3 film with a thickness of 2 nm was deposited on the Cu metal film, with an ITO target.
[0076] S3. Laser grooving is performed on the TCO3 film layer on the back side;
[0077] The back main gate is slotted using a laser to remove the TCO3 thin film on the outer surface of the Cu metal film layer;
[0078] S4. Screen printing and silver paste curing are performed to obtain Ag metal grid lines;
[0079] After step S3, the monocrystalline silicon wafer is screen printed with the front main grid and fine grid and the back main grid. The screen printing paste is low temperature silver paste. Then the screen-printed monocrystalline silicon wafer is sent into a curing oven for curing. The curing conditions are 250℃ and 30min.
[0080] S5. Light injection yields the heterojunction solar cell with the aforementioned metallization scheme:
[0081] Photothermal treatment using light injection can effectively improve efficiency. After the treatment is completed, I-V testing is performed to obtain battery performance data.
[0082] Example 3:
[0083] Batteries fabricated using metallization schemes for heterojunctions, such as Figure 1As shown, the structure includes an n-type single-crystal silicon wafer; after a back-side amorphous silicon layer is deposited, a TCO2 film, a Cu metal film, and a TCO3 film are deposited sequentially, serving to collect current and reduce reflection; after laser grooving on the films, Ag metal main gate lines are printed at the grooving locations to conduct current. The metallization scheme prepared using the structure of this invention can effectively reduce the consumption of TCO film and Ag.
[0084] A metallization scheme and preparation method suitable for heterojunctions, specifically including the following steps:
[0085] (1) A TCO1 thin film is deposited on the front side of the original silicon wafer that has undergone texturing, cleaning and front and back a-Si amorphous silicon layer deposition processes in sequence.
[0086] The front-side TCO1 film thickness is 120nm;
[0087] (2) A TCO2 film, a Cu film, and a TCO3 film are sequentially deposited on the back a-Si amorphous silicon layer.
[0088] A TCO2 film with a thickness of 3 nm was deposited using PVD or RPD equipment, with ITO as the target material. A Cu metal film with a thickness of 1 μm was deposited on the TCO2 film using PVD equipment, with Cu as the target material. A TCO3 film with a thickness of 6 nm was deposited on the Cu metal film, with AZO as the target material.
[0089] (3) Laser grooving of the TCO3 film layer on the back side;
[0090] The back main gate is slotted using a laser to remove the TCO3 thin film on the outer surface of the Cu metal film layer;
[0091] (4) Screen printing and silver paste curing to obtain Ag metal grid lines;
[0092] After step S3, the monocrystalline silicon wafer is screen printed with the front main grid and fine grid and the back main grid. The screen printing paste is low temperature silver paste. Then the screen-printed monocrystalline silicon wafer is sent into a curing oven for curing. The curing conditions are 180℃ and 30min.
[0093] (5) Light injection yields the heterojunction solar cell with the metallization scheme described above:
[0094] Photothermal treatment using light injection can effectively improve efficiency. After the treatment is completed, I-V testing is performed to obtain battery performance data.
[0095] Comparative example:
[0096] Conventional heterojunction solar cells, such as Figure 3As shown, it includes an n-type monocrystalline silicon wafer; an a-Si(i) amorphous silicon layer, an a-Si(p+) amorphous silicon layer, a TCO(ITO) film layer and an Ag metal gate line sequentially deposited on the front side of the monocrystalline silicon wafer; and an a-Si(i) amorphous silicon layer, an a-Si(n+) amorphous silicon layer, a TCO(ITO) film layer and an Ag metal gate line sequentially deposited on the back side of the monocrystalline silicon wafer.
[0097] The fabrication method of the above-mentioned conventional heterojunction structure solar cell specifically includes the following steps:
[0098] (1) Texturing and cleaning n-type monocrystalline silicon wafers to form a clean surface with a texture size of 5μm.
[0099] (2) Amorphous silicon thin film deposition is performed on the n-type single crystal silicon wafer after texturing in step (1) using a PECVD equipment. On the front side, an a-Si(i) intrinsic amorphous silicon film with a thickness of 5 nm and an a-Si(p+)p-type doped amorphous silicon film with a thickness of 10 nm and a doping concentration of 2% are deposited sequentially. On the back side, an a-Si(i) intrinsic amorphous silicon film with a thickness of 5 nm and an a-Si(n+)n-type doped amorphous silicon film with a thickness of 7 nm and a doping concentration of 2% are deposited sequentially.
[0100] (3) Use an RPD device to deposit a double-sided TCO film on the n-type single crystal silicon wafer in step (2), with a deposition thickness of 100 nm;
[0101] (4) Use screen printing to print Ag metal grid lines on the n-type monocrystalline silicon wafer in step (3), and then perform electrical performance testing after drying and curing.
[0102] Performance testing:
[0103] Cells prepared using the metallization schemes for heterojunctions obtained in Examples 1, 2, and 3, and a conventional heterojunction structure cell prepared in the comparative example were used. The cell size was 210 mm × 105 mm. The Eta (efficiency), Voc (open-circuit voltage), Isc (short-circuit current), FF (fill factor), and slurry cost were measured respectively, and the results are shown in Table 1.
[0104] Table 1. Performance test results of batteries fabricated using metallization schemes for heterojunctions and batteries with conventional heterojunction structures.
[0105]
[0106] Note: 1. The baseline in the table is represented by "-".
[0107] As shown in Table 1, using the comparative example as a benchmark, Example 1 shows a 0.083% improvement in Eta (efficiency). This is mainly due to the improved series resistance resulting from the copper plating technology on the back side, which in turn increases Isc, leading to a 0.035A increase in Isc compared to the comparative example. The 0.073% increase in Eta and the 0.035A increase in Isc are significant improvements for a battery. Furthermore, the copper plating on the back side reduces the consumption of TCO film and Ag, resulting in a decrease in target material cost of RMB 0.082 / piece and slurry cost of RMB 0.56 / piece, respectively. Therefore, Example 1 demonstrates a good improvement in both Eta (efficiency) and Isc (short-circuit current) while reducing costs. It is evident that Example 1 is superior to the comparative example.
[0108] Although the Eta (efficiency) of Example 2 decreased, the decrease was only -0.44%. Given the 0.032A increase in Isc and the significant cost reductions of 0.082 yuan / piece and 0.56 yuan / piece respectively, the slight decrease in conversion efficiency is negligible. Therefore, considering the present invention's aim of cost reduction, a significant cost reduction is preferable to a slight decrease in conversion efficiency; that is, the solution in Example 2 is superior to the comparative example.
[0109] In Example 3, Eta (efficiency) was improved by 0.053%, and Isc (short-circuit current) was improved by 0.030A. This was mainly due to the improved series resistance resulting from the copper plating technology on the back side, which in turn increased Isc. Therefore, Example 3 showed a good improvement in both Eta (efficiency) and Isc (short-circuit current). The cost of the target material and the paste decreased by RMB 0.082 / piece and RMB 0.56 / piece, respectively, making Example 3 superior to the comparative example in terms of Eta, Isc, and cost.
[0110] The fill factor (FF) represents the battery performance. As shown in Table 1, the FF of Example 2 is slightly lower than that of the comparative example. However, given the significant cost reduction, this slight decrease in fill factor is negligible. The FF of Examples 1 and 3 are still superior to that of the comparative example.
[0111] The Voc (open circuit voltage) of Examples 1, 2, and 3 all showed a slight decrease compared to the comparative example. Given the significant reduction in cost, the slight decrease in open circuit voltage can be ignored.
[0112] In summary, both Example 1 and Example 3 show improved battery efficiency (Eta), while the decrease in battery efficiency in Example 2 is negligible. Because this battery technology reduces ITO (TCO) usage by 75% and lowers Ag consumption, the target material cost decreases by 0.082 yuan / piece. Simultaneously, the fine grid on the back of the battery is replaced with copper plating, reducing silver paste usage and lowering the total paste cost by 0.56 yuan / piece. The significant reduction in target material and paste costs, coupled with almost unchanged or even improved battery efficiency, demonstrates the economic feasibility of this solution.
[0113] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention shall fall within the scope of the technical solution of the present invention.
Claims
1. A metallated heterojunction cell, characterized by: The device includes a silicon wafer (1), which has a front side and a back side. The front side is sequentially deposited with a front amorphous silicon layer (2), a front transparent conductive oxide film (3), and a front gate line (4). The back side is sequentially deposited with a back amorphous silicon layer (5), a back first transparent conductive oxide film (6), a back copper film (7), and a back second transparent conductive oxide film (8). The back second transparent conductive oxide film (8) is provided with a back main gate line (9). One end of the back main gate line (9) is connected to the back copper film (7), and the other end extends outward after passing through the back second transparent conductive oxide film (8). The thickness of the front transparent conductive oxide film (3) is 120 nm, the thickness of the back first transparent conductive oxide film (6) is 2 nm, the thickness of the back second transparent conductive oxide film (8) is 2 nm, and the thickness of the back copper film (7) is 1 μm.
2. A metalized heterojunction cell according to claim 1, wherein: The silicon wafer (1) is an n-type monocrystalline silicon wafer or a p-type monocrystalline silicon wafer.
3. A metalized heterojunction cell according to claim 2, wherein: The front amorphous silicon layer (2) is n-type amorphous silicon, and the back amorphous silicon layer (5) is p-type amorphous silicon.
4. A method of fabricating a metalized heterojunction cell, the method comprising: The method is used to prepare a metallized heterojunction solar cell as described in claim 1, and the method includes the following steps: S1. A front amorphous silicon layer (2) is deposited on the front side of the silicon wafer (1) that has been texturized and cleaned in sequence, and a back amorphous silicon layer (5) is deposited on the back side. A front transparent conductive oxide film (3) is deposited on the front amorphous silicon layer (2). S2. Sequentially deposit the first transparent conductive oxide film (6), the copper film (7), and the second transparent conductive oxide film (8) on the back side outside the amorphous silicon layer (5). S3. Laser grooving is performed on the second transparent conductive oxide film (8) on the back side; S4. The front transparent conductive oxide film (3) and the back second transparent conductive oxide film (8) are screen printed and silver paste is cured to obtain the front gate line (4) and the back main gate line (9). S5, photothermal treatment.
5. The method of claim 4, wherein: In step S1, the thickness of the front transparent conductive oxide film (3) is 70-120 nm.
6. The method of claim 4, wherein: In step S2, the thickness of the first transparent conductive oxide film (6) on the back side is 2-5 nm, the thickness of the copper film (7) on the back side is 1-10 μm, and the thickness of the second transparent conductive oxide film (8) on the back side is 2-10 nm.
7. The method of claim 4, wherein: Step S3 includes the following sub-step: slotting the second transparent conductive oxide film (8) on the back side to expose the copper film (7) on the back side, and the exposed shape is the shape of the main gate line (9) on the back side.
8. The method of claim 4, wherein: Step S4 includes the following sub-steps: screen printing the front main grid and fine grid and the back main grid of the monocrystalline silicon wafer after step S3. The screen printing process uses low-temperature silver paste printing. Then, the screen-printed monocrystalline silicon wafer is sent into a curing oven for curing at a temperature of 180-250℃.