Control method of phase-locked loop circuit, frequency generation device, and readable storage medium

Abstract

The application discloses a control method of a phase-locked loop circuit, a frequency generating device and a readable storage medium. The phase-locked loop circuit comprises a phase discriminator, a filter and a voltage-controlled oscillator connected in sequence. The method comprises the following steps: acquiring a current control voltage corresponding to a current frequency and a target control voltage corresponding to a target frequency according to the corresponding relationship between the frequency and the control voltage, wherein the control voltage is the output voltage of the filter, and the current frequency and the target frequency are the output frequencies of the phase-locked loop circuit; determining a preset voltage by using the target control voltage and the current control voltage; and inputting the preset voltage to a capacitor in the filter. In the foregoing manner, the frequency locking time can be reduced, and fast locking can be realized.

Description

Technical Field

[0001] This application relates to the field of communication technology, and in particular to control methods, frequency generating devices, and readable storage media for phase-locked loop circuits. Background Technology

[0002] The frequency generator is one of the core components of communication equipment, providing the equipment with the ability to receive local oscillator signals and transmit carrier signals.

[0003] A frequency generator typically includes a loop filter, a voltage-controlled oscillator (VCO), and a phase detector. The phase detector identifies the phase difference between the local oscillator signal and the output signal of the VCO and outputs an error voltage. This error voltage, after passing through the loop filter, becomes the voltage control voltage (CV) of the VCO to achieve frequency locking, thereby locking the frequency of the VCO's output signal to the frequency required by the frequency generation unit.

[0004] Currently, the commonly used external fast-locking scheme for phase-locked loops is based on an external switching circuit. The initial preset voltage is configured to the loop filter capacitor through software, so that the voltage at the beginning of the loop operation is close to the voltage of the locked state, thereby reducing the locking time. The preset voltage is usually set by frequency band. Summary of the Invention

[0005] This application mainly provides a control method for a phase-locked loop circuit, which can solve the problem of long frequency lock-in time in the prior art.

[0006] To address the aforementioned technical problems, the first aspect of this application provides a control method for a phase-locked loop (PLL) circuit. The PLL circuit includes a phase detector, a filter, and a voltage-controlled oscillator (VCO) connected in sequence. The method includes: obtaining a current control voltage corresponding to a current frequency and a target control voltage corresponding to a target frequency based on the correspondence between frequency points and control voltages; wherein the control voltage is the output voltage of the filter, and the current frequency and the target frequency are the output frequencies of the PLL circuit; determining a preset voltage using the target control voltage and the current control voltage; and inputting the preset voltage to a capacitor in the filter.

[0007] Optionally, determining the preset voltage using the target control voltage and the current control voltage includes: using the sum of a preset multiple of the difference between the target control voltage and the current control voltage and the target control voltage as the preset voltage.

[0008] Optionally, determining the preset voltage using the target control voltage and the current control voltage includes: calculating the preset voltage according to the following formula: V = CV next +(CV next -CV prep )·e, where V represents the preset voltage, CV nextThe target control voltage, CV prep represents the current control voltage, and e represents the preset multiple.

[0009] Optionally, 0.1 ≤ e ≤ 0.25.

[0010] Optionally, the method further includes: detecting at least two frequency points and corresponding control voltages; and using the at least two frequency points and corresponding control voltages to fit a correspondence between the frequency points and the control voltages.

[0011] Optionally, detecting the control voltage corresponding to at least two of the frequency points includes: acquiring at least two of the frequency points and the corresponding control voltage at preset intervals.

[0012] Optionally, the step of fitting the correspondence between each frequency point and the control voltage using the at least two frequency points and the corresponding control voltage includes: fitting the correspondence between each frequency point and the control voltage using the following formula:

[0013]

[0014] Optionally, f represents the frequency point to be fitted, CV represents the control voltage corresponding to the frequency point to be fitted, f1 and f2 represent two adjacent frequency points, and CV1 and CV2 are the control voltages corresponding to the adjacent frequency points f1 and f2, respectively.

[0015] Optionally, the preset interval frequency is 10MHz.

[0016] To address the aforementioned technical problems, a second aspect of this application provides a frequency generating device, comprising: a phase detector, a filter, and a voltage-controlled oscillator connected in sequence; a preset voltage configuration circuit connected to the filter for providing a preset voltage to the capacitor of the filter; and a processor connected to the preset voltage configuration circuit for determining the preset voltage using the control method of the phase-locked loop circuit provided in the first aspect, and controlling the preset voltage configuration circuit to configure the preset voltage.

[0017] To address the aforementioned technical problems, a third aspect of this application provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the control method for the phase-locked loop circuit provided in the first aspect.

[0018] The beneficial effects of this application are as follows: Unlike the prior art, the control method of the phase-locked loop circuit in this application obtains the current control voltage corresponding to the current frequency and the target control voltage corresponding to the target frequency based on the correspondence between frequency and control voltage. Here, the control voltage is the output voltage of the filter, and the current frequency and target frequency are the output frequencies of the phase-locked loop circuit. Then, the preset voltage is determined using the target control voltage and the current control voltage. Finally, the preset voltage is input to the capacitor in the filter. This allows the charging and discharging requirements of the capacitor to be determined based on the target control voltage and the current control voltage, thereby determining the magnitude of the preset voltage according to the target control voltage and the current control voltage. This achieves dynamic setting of the preset voltage, reducing the influence of capacitor dielectric absorption, thereby reducing the capacitor charging and discharging time, and ultimately effectively reducing the lock-in time. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort, wherein:

[0020] Figure 1 This is a schematic diagram of the circuit structure of one embodiment of a phase-locked loop circuit;

[0021] Figure 2 This is a flowchart illustrating an embodiment of the control method for the phase-locked loop circuit of this application;

[0022] Figure 3 This is a comparative schematic diagram of the polar molecular dielectric inside the capacitor of this application before and after polarization;

[0023] Figure 4 This application describes the relationship between the internal electric field strength of the capacitor and time t during capacitor discharge.

[0024] Figure 5 This application describes the relationship between the internal electric field strength of the capacitor and time t during capacitor charging.

[0025] Figure 6 This is a flowchart illustrating an embodiment of the method for obtaining the correspondence between frequency points and control voltages in this application.

[0026] Figure 7 This is a circuit structure diagram of an embodiment of the frequency generating device of this application;

[0027] Figure 8 This is a schematic block diagram of the circuit structure of an embodiment of the computer-readable storage medium of this application. Detailed Implementation

[0028] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0029] The terms "first" and "second" in this application are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features shown. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to such processes, methods, products, or apparatus.

[0030] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0031] Please see Figure 1 , Figure 1 This is a schematic diagram of the circuit structure of an embodiment of a phase-locked loop (PLL) circuit. The PLL circuit 80 includes a phase detector 81, a filter 82, a voltage-controlled oscillator (VCO) 83, and a preset voltage configuration circuit 84. The phase detector 81, filter 82, and VCO 83 are connected in sequence. The preset voltage configuration circuit 84 is connected to the filter 82 and is used to provide a preset voltage to the capacitor of the filter 82.

[0032] Specifically, the phase detector 81 is used to receive the reference signal and the output signal of the voltage-controlled oscillator 83, and compares the phase of the reference signal and the output signal of the voltage-controlled oscillator 83 to generate an error voltage corresponding to the phase difference between the two signals. The filter 82 is used to filter out high-frequency components and noise in the error voltage and output a control voltage to control the frequency of the output signal of the voltage-controlled oscillator 83 to approach the frequency of the input signal until the frequency difference is eliminated and locked.

[0033] To achieve rapid locking and reduce locking time, one approach is to use a preset voltage configuration circuit 84 to provide a preset voltage to the filter 82 during frequency switching. This ensures that the initial operating voltage of the circuit is close to the voltage at the locked state, thereby reducing the locking time. Generally, the preset voltage is set as a fixed value for each frequency band. However, our researchers have found through long-term studies that within a small frequency band, the locking time at some frequencies can be as long as 6.5ms, and the effect of reducing the locking time is not significant.

[0034] Please see Figure 2 , Figure 2 This is a schematic flowchart illustrating an embodiment of the control method for the phase-locked loop (PLL) circuit of this application. The PLL circuit includes a phase detector, a filter, and a voltage-controlled oscillator connected in sequence. This embodiment includes the following steps:

[0035] S11, based on the correspondence between frequency point and control voltage, obtain the current control voltage corresponding to the current frequency and the target control voltage corresponding to the target frequency.

[0036] Among them, the control voltage is the output voltage of the filter when the frequency is locked, and the current frequency and the target frequency are the output frequencies of the phase-locked loop circuit.

[0037] Since each frequency point of the phase-locked loop circuit has a corresponding control voltage, the frequency point and control voltage correspondence provided in this application include each frequency point and the corresponding control voltage.

[0038] Here, the current frequency is the current output frequency of the phase-locked loop (PLL); the current control voltage is the control voltage corresponding to the current frequency; the target frequency is the output frequency that the PLL circuit will lock onto after frequency switching; and the target control voltage is the control voltage corresponding to the target frequency. After knowing the current frequency and the target frequency, the corresponding current control voltage and target control voltage can be obtained through the correspondence between frequency points and control voltages.

[0039] Specifically, when the phase-locked loop circuit needs to switch from the current frequency to the target frequency, a certain locking time is required. In order to shorten the locking time, this application calculates a preset voltage using the current control voltage and the target control voltage, and provides the preset voltage to the capacitor of the filter to speed up the locking.

[0040] S12, using the target control voltage and the current control voltage, determine the preset voltage.

[0041] Optionally, the preset voltage is the sum of a preset multiple of the difference between the target control voltage and the current control voltage and the target control voltage.

[0042] Specifically, during the investigation of lock-in time, the researchers of this application discovered over a long period of time that when the dielectric of the capacitor in the filter is a polar molecule, the polar molecule is prone to polarization under the action of an electric field, which leads to a slower electric field response speed and thus a longer lock-in time.

[0043] Please see Figure 3 , Figure 3 This is a comparative schematic diagram showing the polar molecules in the capacitor before and after polarization. Because polar molecules undergo reorientation and polarization under the influence of an applied electric field, polarization charges appear on the dielectric surface. These charges generate an internal electric field, resulting in a slow electric field response in this type of dielectric. Based on this characteristic, a dynamically set preset voltage can effectively reduce the influence of the internal electric field, thereby reducing the lock-in time.

[0044] Please see Figure 4 and Figure 5 , Figure 4 This represents the relationship between the internal electric field strength of the capacitor and time t during capacitor discharge. Figure 5 The relationship between the electric field strength inside the capacitor and time t during charging. Figure 4 In the diagram, T1 represents the lockout time at a low preset voltage, T2 represents the lockout time when the preset voltage is the control voltage, and T3 represents the lockout time at a high preset voltage. The following conclusions can be drawn: when the control voltage at the target frequency is lower than the control voltage at the current frequency, the capacitor needs to discharge; when the preset voltage is lower than the target control voltage, the lockout time is the shortest.

[0045] exist Figure 5 In the diagram, T1 represents the lockout time at a high preset voltage, T2 represents the lockout time when the preset voltage is the control voltage, and T3 represents the lockout time at a low preset voltage. The following conclusions can be drawn: when the control voltage at the target frequency is higher than the control voltage at the current frequency, the capacitor needs to be charged; when the preset voltage is higher than the target control voltage, the lockout time is the shortest.

[0046] In this embodiment, when calculating the preset voltage according to the "preset multiple of the difference between the target control voltage and the current control voltage and the sum of the target control voltage", the preset voltage that is greater than or less than the target control voltage can be automatically configured according to the relationship between the target control voltage and the current control voltage, which is quick and convenient.

[0047] The preset voltage can be calculated according to the following formula (1):

[0048] V = CV next +(CV next -CV pre )·e (1)

[0049] Where V represents the preset voltage, CV next Indicates the target control voltage, CVpre This indicates the current control voltage, and 'e' indicates the preset multiple.

[0050] This embodiment can detect the target control voltage CV. next and the current control voltage CV pre Then, directly set the target control voltage CV next and the current control voltage CV pre Substituting into formula (1), the preset voltage V can be calculated.

[0051] Optionally, 0.1 ≤ e ≤ 0.25.

[0052] Unlike existing technologies, this embodiment detects the current frequency and target frequency when frequency switching is detected. It can obtain the current control voltage corresponding to the current frequency and the target control voltage corresponding to the target frequency through the correspondence between frequency point and control voltage. Then, it calculates the value of the preset voltage according to the above formula (1). This realizes the dynamic determination of the preset voltage based on the current control voltage and the target control voltage, which is suitable for the charging and discharging process of the capacitor, so as to reduce the influence of the electric field in the capacitor dielectric and realize the rapid locking of frequency.

[0053] S13 inputs the preset voltage to the capacitor in the filter.

[0054] After determining the preset voltage, the preset voltage is configured to the capacitor in the filter so that the operating voltage of the loop is close to the target control voltage, thereby speeding up frequency locking.

[0055] Optionally, the dielectric of the capacitor is a polar molecule.

[0056] Please refer to the table below, which compares the locking time of each frequency point after improvement using the method described above in this application with that before improvement. In the table, R represents the receiving frequency and T represents the transmitting frequency. It can be seen from the table that the locking time of each frequency point is significantly reduced after improvement. In the obtained test results, the maximum improvement is 2.4ms, which shows a good improvement effect.

[0057] 350 480 4.8 2.5 480 350 5.2 2.9 350 419.999 5.2 3.9 419.999 350 5.2 2.9 420 480 4.8 2.5 480 420 5.3 2.9 420 419.999 4.9 3.7 419.999 420 5.4 3.1

[0058] Please see Figure 6 , Figure 6 This is a flowchart illustrating an embodiment of obtaining the correspondence between frequency points and control voltages according to this application. This embodiment includes the following steps:

[0059] S21, detect at least two frequency points and their corresponding control voltages.

[0060] This step detects two or more frequency points and their corresponding control voltages, and then uses the detected frequency points and their corresponding control voltage data to fit the data of each frequency point.

[0061] Optionally, at least two frequency points and their corresponding control voltages are acquired at each preset interval frequency.

[0062] For example, the preset interval frequency can be 10MHz, 20MHz, 30MHz, etc. Those skilled in the art can select an appropriate interval frequency according to the accuracy requirements. If a high-accuracy fitting result is to be obtained, a lower interval frequency can be selected as the preset interval frequency. If the sampling frequency points are to be reduced, a higher interval frequency can be selected as the preset interval frequency. Those skilled in the art can determine the specific preset interval frequency according to the requirements, and there are no further restrictions here.

[0063] S22, using at least two frequency points and their corresponding control voltages, fit the relationship between the frequency points and the control voltages.

[0064] This step uses at least two frequency points and the corresponding control voltages obtained in step S21 to fit the correspondence between frequency points and control voltages, so that in step S11, the corresponding current control voltage can be obtained according to the current frequency, and the corresponding target control voltage can be obtained according to the target frequency.

[0065] Optionally, the correspondence between each frequency point and the control voltage can be obtained by fitting the following formula:

[0066]

[0067] Where f represents the frequency point to be fitted, CV represents the control voltage corresponding to the frequency point to be fitted, f1 and f2 represent two adjacent frequency points, and CV1 and CV2 are the control voltages corresponding to the adjacent frequency points f1 and f2, respectively.

[0068] Specifically, (f1,CV1) and (f2,CV2) are two adjacent frequency points and their corresponding control voltages among the at least two frequency points detected in step S21, and f is the frequency point to be fitted between f1 and f2.

[0069] The linear fitting method described in this embodiment can obtain the correspondence between each frequency point and the control voltage by detecting the corresponding voltage control voltage at a finite number of frequency points. This method involves little computation and is convenient and fast.

[0070] Alternatively, in addition to the linear fitting method described above, the least squares method or other nonlinear fitting methods can be used to fit the correspondence between each frequency point and the corresponding control voltage to obtain a more accurate fitting result.

[0071] It is understandable that there are various ways to obtain the correspondence between each frequency point and the control voltage through curve fitting, and those skilled in the art can choose for themselves, which will not be elaborated here.

[0072] Please see Figure 7 , Figure 7 This is a schematic diagram of the circuit structure of an embodiment of the frequency generating device of this application. The frequency generating device 70 of this embodiment includes: a phase detector 71, a filter 72, a voltage-controlled oscillator 73, a preset voltage configuration circuit 74, and a processor 75. The phase detector 71, the filter 72, and the voltage-controlled oscillator 73 are connected in sequence. The preset voltage configuration circuit 74 is connected to the filter 72 and is used to provide a preset voltage to the capacitor of the filter 72. The processor 75 is connected to the preset voltage configuration circuit 74 and is used to determine the preset voltage and control the preset voltage configuration circuit 74 to configure the preset voltage.

[0073] Specifically, the phase detector 71 is used to receive the reference signal and the output signal of the voltage-controlled oscillator 73 (e.g., YTO / VCO), and compares the phase of the reference signal and the output signal of the voltage-controlled oscillator 73 to generate an error voltage corresponding to the phase difference between the two signals. The filter 72 is used to filter out high-frequency components and noise in the error voltage and output a control voltage to control the frequency of the output signal of the voltage-controlled oscillator 73 to approach the frequency of the input signal until the frequency difference is eliminated and locked. The preset voltage configuration circuit 74 provides a preset voltage to the filter 72 so that the initial operating voltage of the circuit is close to the voltage of the locked state, thereby reducing the lock-in time.

[0074] The processor 75 is connected to the preset voltage configuration circuit 74, used to determine the preset voltage and control the preset voltage configuration circuit 74 to configure the preset voltage so that the preset voltage is provided to the capacitor of the filter 72. When the capacitor dielectric of the filter 72 is a polar molecule, the frequency lock time can be effectively shortened. The processor 75 is used to implement the following method:

[0075] Based on the correspondence between frequency and control voltage, the current control voltage corresponding to the current frequency and the target control voltage corresponding to the target frequency are obtained; where the control voltage is the output voltage of filter 72, and the current frequency and target frequency are the output frequencies of the phase-locked loop circuit; using the target control voltage and the current control voltage, the preset voltage is determined; and the preset voltage is input to the capacitor in filter 72.

[0076] Understandably, the processor 75 in this embodiment is also used to implement the steps of the control method for the phase-locked loop circuit in the above embodiments of this application. For a description of each step of the processing, please refer to the description of each step in the control method embodiment for the phase-locked loop circuit in the above embodiments of this application, which will not be repeated here.

[0077] This application may also include a digital-to-analog converter 76 (DAC), a processor 75 connected to the DAC 76, and the DAC 76 connected to the filter 72. After the processor 75 calculates the preset voltage, it sends the digital signal to the DAC 76 to convert it into an analog signal and send it to the filter 72, thus configuring the preset voltage to the capacitor of the filter 72.

[0078] In the various embodiments of this application, the control method and frequency generating device of the disclosed phase-locked loop circuit can be implemented in other ways. For example, the embodiments of the frequency generating device described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the mutual coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, devices, or units, and may be electrical, mechanical, or other forms.

[0079] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment, depending on actual needs.

[0080] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0081] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium.

[0082] See Figure 8 , Figure 8 This is a schematic block diagram of a circuit structure of an embodiment of a computer-readable storage medium according to this application. The computer storage medium 1000 stores a computer program 1001, which, when executed, implements the following method:

[0083] Based on the correspondence between frequency and control voltage, obtain the current control voltage corresponding to the current frequency and the target control voltage corresponding to the target frequency; where the control voltage is the output voltage of the filter, and the current frequency and target frequency are the output frequencies of the phase-locked loop circuit; use the target control voltage and the current control voltage to determine the preset voltage; input the preset voltage to the capacitor in the filter.

[0084] Based on the correspondence between frequency and control voltage, obtain the current control voltage corresponding to the current frequency and the target control voltage corresponding to the target frequency; where the control voltage is the output voltage of the filter, and the current frequency and target frequency are the output frequencies of the phase-locked loop circuit; use the target control voltage and the current control voltage to determine the preset voltage; input the preset voltage to the capacitor in the filter.

[0085] Understandably, the computer program 1001 in this embodiment is also used to implement the steps of the control method for the phase-locked loop circuit in the above embodiments of this application. For a description of each step of the processing execution, please refer to the description of each step in the control method embodiment for the phase-locked loop circuit in the above embodiments of this application, which will not be repeated here.

[0086] The computer storage medium 1000 can be any medium capable of storing program code, such as a USB flash drive, external hard drive, read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk.

[0087] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A control method for a phase-locked loop circuit, characterized in that, The phase-locked loop circuit includes a phase detector, a filter, and a voltage-controlled oscillator connected in sequence. The dielectric of the capacitor in the filter is a polar molecule. The method includes: Based on the correspondence between frequency points and control voltages, the current control voltage corresponding to the current frequency and the target control voltage corresponding to the target frequency are obtained; wherein, the control voltage is the output voltage of the filter, the current frequency and the target frequency are the output frequencies of the phase-locked loop circuit, the current frequency is the current output frequency of the phase-locked loop circuit, and the target frequency is the output frequency to be locked by the phase-locked loop circuit after frequency switching; A preset voltage is defined as the sum of a preset multiple of the difference between the target control voltage and the current control voltage and the target control voltage; wherein, when the target control voltage is lower than the current control voltage, the preset voltage is lower than the target control voltage; and when the target control voltage is higher than the current control voltage, the preset voltage is higher than the target control voltage. The preset voltage is input to the capacitor in the filter.

2. The method according to claim 1, characterized in that, Determining a preset voltage using the target control voltage and the current control voltage includes: The preset voltage is calculated according to the following formula: in, This refers to the preset voltage. This refers to the target control voltage. This indicates the current control voltage. This indicates the preset multiple.

3. The method according to claim 2, characterized in that, 0.1≤e≤0.25。 4. The method according to claim 1, characterized in that, The method further includes: Detect at least two frequency points and their corresponding control voltages; Using the at least two frequency points and their corresponding control voltages, a correspondence between the frequency points and the control voltages is fitted to obtain the relationship between them.

5. The method according to claim 4, characterized in that, The detection of control voltages corresponding to at least two of the frequency points includes: At least two frequency points and their corresponding control voltages are obtained at each preset interval frequency.

6. The method according to claim 4, characterized in that, The step of fitting the correspondence between the frequency points and the control voltage using the at least two frequency points and the corresponding control voltage includes: The correspondence between each frequency point and the control voltage is obtained by fitting the following formula: in, Indicates the frequency points to be fitted. This represents the control voltage corresponding to the frequency point to be fitted. , Indicates two adjacent frequency points, , Adjacent frequency points , The corresponding control voltage.

7. The method according to claim 5, characterized in that, The preset interval frequency is 10MHz.

8. A frequency generating device, characterized in that, The device includes: A phase detector, a filter, and a voltage-controlled oscillator are connected in sequence. A preset voltage configuration circuit, connected to the filter, is used to provide a preset voltage to the capacitor of the filter; A processor, connected to the preset voltage configuration circuit, is configured to determine the preset voltage according to any one of claims 1-7, and control the preset voltage configuration circuit to configure the preset voltage.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps of the method as described in any one of claims 1-7.

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