A method and apparatus for detecting the minimum code weight of an LDPC code

Abstract

The application discloses a minimum code weight detection method and device for an LDPC code, and the method comprises the following steps: acquiring equivalent channel transmission coding bit prior information, and generating an input signal of low-density parity-check code (LDPC) iterative decoding; performing layered scheduling and minimum sum decoding on the input signal of the LDPC iterative decoding, calculating the posterior information of all coding bits after each iteration, and sequentially obtaining the current intermediate result of the LDPC iterative decoding; performing preset improved ANC algorithm processing and minimum code weight detection on the current intermediate result, obtaining the minimum code weight detection result of the current iteration in the current search, and obtaining the minimum code weight detection result of all iterations in the current search after a preset iteration stop condition is reached. Thus, the problems in the prior art, such as the increase in the complexity of calculation when noise is introduced, the large number of decoding iteration times in the iterative decoding process and the small search range, the reduction in the efficiency of code word search, and the increase in the system complexity, are solved.

Description

Technical Field

[0001] This application relates to the field of digital information transmission technology, and in particular to a method and apparatus for detecting the minimum code weight of LDPC (Low-Density Parity-Check Code). Background Technology

[0002] LDPC is a class of linear block codes based on sparse parity-check matrices. It was first proposed by R.G. Gallager in 1962. The main feature of LDPC codes is that their parity-check matrix H is sparse. Using MP (Message Passing) decoding algorithm, especially BP (Belief Propagation) decoding algorithm, the performance can approach the Shannon limit. Therefore, it is widely used in the field of channel coding in digital communication systems.

[0003] In related technologies, by flipping the sign bit of the LLR (Log likelihood Ratio) soft information of one or more random coded bits in an all-zero codeword, the difference in LLR before and after the flip is adjusted to control the strength of the equivalent impulse noise. This ensures that the result of BP decoding of the LLR vector of the coded bits in the equivalent channel deviates exactly from the all-zero codeword. Equivalent impulse noise of the same strength is introduced sequentially or randomly into all coded bits to achieve local search for the vicinity of the all-zero codeword in the codeword space.

[0004] However, the main problems with traditional ANC (Approximately Nearest Codeword) algorithms and their minimum code weight detection methods are as follows:

[0005] 1. When introducing noise, it is necessary to simulate the equivalent channel transmission. Impulse noise is superimposed on the input symbols of the equivalent channel transmission module to obtain the output symbols of the equivalent channel transmission, which has high computational complexity.

[0006] 2. For the output symbols transmitted through the equivalent channel, it is necessary to calculate the prior information (i.e., the initial log-likelihood ratio) of the all-zero codeword encoding bits of the equivalent channel, which has high computational complexity.

[0007] 3. In the iterative decoding process, the BP decoding algorithm, which is suitable for practical decoding, is usually used, but it has high computational complexity;

[0008] 4. During iterative decoding, a flooding scheduling strategy is usually adopted, which results in slow bit error propagation for minimum code weight detection and a large number of decoding iterations required.

[0009] 5. Local search uses traversal search, and the search range of the codeword space is limited by the number of erased bits, especially the number of bits to be traversed and searched in the erased bits, resulting in a small search range;

[0010] 6. In addition, for structured LDPC codes, including common quasi-cyclic structures, Raptor-like structures, and variable node punched structures, traditional minimum code weight detection algorithms lack post-processing.

[0011] In summary, the traditional ANC algorithm and its minimum code weight detection method need further optimization. Summary of the Invention

[0012] This application provides a method and apparatus for detecting the minimum code weight of LDPC codes, in order to solve the problems in related technologies, such as increased computational complexity when noise is introduced, and reduced efficiency of codeword search and increased system complexity due to the large number of decoding iterations and small search range during iterative decoding.

[0013] The first aspect of this application provides a minimum code weight detection method for LDPC codes, comprising the following steps: acquiring prior information of coded bits transmitted through an equivalent channel, generating an input signal for LDPC iterative decoding; performing hierarchical scheduling and minimum sum decoding on the input signal of the LDPC iterative decoding, and calculating the posterior information of all coded bits after each iteration to obtain the current intermediate result of the LDPC iterative decoding; processing the current intermediate result with a preset improved ANC algorithm and performing minimum code weight detection to obtain the minimum code weight detection result of the current iteration of the search, and obtaining the minimum code weight detection results of all iterations of the current search after reaching a preset iteration stopping condition.

[0014] Optionally, in one embodiment of this application, the step of obtaining the prior information of the coded bits transmitted through the equivalent channel and generating the input signal for the low-density parity-check code (LDPC) iterative decoding includes: converting a pre-defined length of all-zero codeword into prior information of the coded bits required by the LDPC decoder; initializing the prior information of the coded bits; performing sign bit flipping and amplification on the prior information of the random single coded bits of the all-zero codeword to obtain the prior information vector of the coded bits of the all-zero codeword after sign bit flipping, which is used as the input signal for the LDPC iterative decoding.

[0015] Optionally, in one embodiment of this application, the step of performing a preset improved ANC algorithm processing and minimum code weight detection on the current intermediate result to obtain the minimum code weight detection result of the current iteration of the search includes: sorting the posterior information of the encoded bits of the current intermediate result according to the absolute value of the log-likelihood ratio, rearranging the corresponding columns of the parity check matrix according to the sorting result, and obtaining a column-order rearranged parity check matrix; performing semi-Gaussian elimination, block processing, and decision processing on the column-order rearranged parity check matrix to obtain a matrix block and decision column-order rearranged parity check matrix; and combining the matrix block and the decision column-order rearranged parity check matrix to perform a non-traversal search and code word space solution on the codeword space composed of multiple encoded bit variables to be searched, and obtaining a non-all-zero legal codeword that conforms to the parity check matrix.

[0016] Optionally, in one embodiment of this application, the method further includes: post-processing the minimum code weight detection results of all iterations of the current search to update the minimum code weight detection statistics of the LDPC code.

[0017] A second aspect of this application provides an LDPC code minimum code weight detection device, comprising: a generation module, configured to acquire prior information of coded bits transmitted in an equivalent channel and generate an input signal for low-density parity-check code (LDPC) iterative decoding; a processing module, configured to perform hierarchical scheduling and minimum sum decoding on the input signal of the LDPC iterative decoding, and calculate the posterior information of all coded bits after each iteration to obtain the current sub-intermediate result of the LDPC iterative decoding; and a detection module, configured to perform a preset improved ANC algorithm processing and minimum code weight detection on the current sub-intermediate result to obtain the minimum code weight detection result of the current iteration of the search, and obtain the minimum code weight detection results of all iterations of the current search after reaching a preset iteration stop condition.

[0018] Optionally, in one embodiment of this application, the generation module includes: a conversion unit, used to convert a preset length of all-zero codeword into prior information of the encoded bits required by the LDPC decoder; and an acquisition unit, used to initialize the prior information of the encoded bits, perform sign bit flipping and amplification on the prior information of a random single encoded bit of the all-zero codeword, and obtain the prior information vector of the encoded bits of the all-zero codeword after sign bit flipping, as the input signal for the LDPC iterative decoding.

[0019] Optionally, in one embodiment of this application, the detection module includes: a sorting unit, used to sort the posterior information of the encoded bits of the current intermediate result according to the absolute value of the log-likelihood ratio, and rearrange the corresponding columns of the parity check matrix according to the sorting result to obtain a column-order rearranged parity check matrix; a processing unit, used to perform semi-Gaussian elimination, block processing and decision processing on the column-order rearranged parity check matrix to obtain a column-order rearranged parity check matrix of matrix block and decision; and a calculation unit, used to combine the matrix block and the column-order rearranged parity check matrix of decision to perform non-traversal search and codeword space solution on the codeword space composed of multiple encoded bit variables to be searched to obtain non-all-zero legal codewords that conform to the parity check matrix.

[0020] Optionally, in one embodiment of this application, it further includes: an update module, used to post-process the minimum code weight detection results of all iterations of the current search and update the minimum code weight detection statistics of the LDPC code.

[0021] A third aspect of this application provides an electronic device, including: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the LDPC code minimum code weight detection method as described in the above embodiments.

[0022] A fourth aspect of this application provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the LDPC code minimum code weight detection method described above.

[0023] This application's embodiments can directly obtain the prior information of the coded bits transmitted through the equivalent channel, generate the input signal for low-density parity-check (LDPC) iterative decoding, and thus perform hierarchical scheduling and minimum sum decoding. After each iteration, the posterior information of all coded bits is calculated, and the current intermediate result of LDPC iterative decoding is obtained sequentially. An improved ANC algorithm and minimum code weight detection are then performed to obtain the minimum code weight detection result for the current iteration. After the iteration stopping condition is met, the minimum code weight detection results for all iterations of the current search are obtained. This effectively expands the codeword search space, simplifies the decoding algorithm, reduces the required number of decoding iterations, and significantly improves codeword search efficiency and the versatility of minimum code weight detection. Therefore, it solves the problems in related technologies, such as increased computational complexity due to the introduction of noise, and the problems of numerous decoding iterations and small search ranges during iterative decoding, which reduce codeword search efficiency and increase system complexity.

[0024] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0025] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein:

[0026] Figure 1 This is a flowchart of a minimum code weight detection method for LDPC codes provided according to an embodiment of this application;

[0027] Figure 2 This is a schematic diagram of the base matrix of a specific embodiment of QC (Quasi Cyclic)-LDPC in this application;

[0028] Figure 3 This is a schematic diagram of the LDPC code minimum code weight detection device according to an embodiment of this application;

[0029] Figure 4 This is a schematic diagram of the structure of an electronic device according to an embodiment of this application. Detailed Implementation

[0030] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this application, and should not be construed as limiting this application.

[0031] The following describes the LDPC code minimum code weight detection method and apparatus according to embodiments of this application with reference to the accompanying drawings. Addressing the problems mentioned in the background art, such as increased computational complexity due to the introduction of noise, and the large number of decoding iterations and small search range during iterative decoding, which reduces codeword search efficiency and increases system complexity, this application provides an LDPC code minimum code weight detection method. In this method, prior information of the coded bits transmitted through the equivalent channel can be directly obtained to generate the input signal for low-density parity-check code LDPC iterative decoding, thereby performing hierarchical scheduling and minimum sum decoding. After each iteration, the posterior information of all coded bits is calculated to sequentially obtain the current intermediate result of the LDPC iterative decoding. An improved ANC algorithm is then applied, and minimum code weight detection is performed to obtain the minimum code weight detection result for the current iteration. After the iteration stopping condition is met, the minimum code weight detection results for all iterations of the current search are obtained. This effectively expands the codeword search space, simplifies the decoding algorithm, reduces the required number of decoding iterations, significantly improves codeword search efficiency, and enhances the versatility of minimum code weight detection. This solves the problems in related technologies, such as increased computational complexity when introducing noise, and the large number of decoding iterations and small search range during iterative decoding, which reduces the efficiency of codeword search and increases system complexity.

[0032] In the embodiments of this application, for ease of description, the basic concepts and symbols of this application are first defined, and the following content is all described based on the defined basic concepts and symbols.

[0033] 1. Checksum Matrix and Lifting

[0034] (1) Parity-check matrix H: This is one way to describe LDPC codes. For a linear block code defined by a parity-check matrix H of size (m, n), the parity bit length is m, the information bit length is k = nm, and the code bit length is n. For any code bit vector x of length n, if xH T If the value is 0, then the code is valid.

[0035] (2) Basis matrix B: For QC-LDPC code, its parity check matrix H is obtained by lifting the basis matrix B. In the widely used 5G-NR and Wi-Fi standards, the element values ​​of the basis matrix B are only 0 or 1. Therefore, in this embodiment, only the case where the element values ​​of the basis matrix B are 0 or 1 is considered.

[0036] (3) Lifting factor z: When the basis matrix B of the QC-LDPC code is lifted to obtain the parity check matrix H, each element in the basis matrix is ​​lifted to a matrix of size z×z corresponding to the position in the parity check matrix. That is, for a code of size m z ×n z Given a base matrix B, the size of the boosted parity-check matrix is ​​m×n, where m=m z ×z, n=n z ×z. Elements with a value of 0 in the basis matrix are promoted to a z-order all-zero matrix, while elements with a value of 1 are promoted to a z-order cyclically shifted square matrix.

[0037] (4) Offset address: Represents the number of bits that the non-zero elements in each row of the cyclic shift matrix are cyclically shifted to the right relative to the identity matrix. When the lifting factor z is given, the offset address of each non-zero element in the base matrix can uniquely determine the parity check matrix H. The non-zero elements of the base matrix B are replaced with the offset address values ​​to obtain the lifting matrix A (also known as the offset address matrix).

[0038] (5) Tanner Graph and Nodes: A Tanner graph is a way to visualize the constraints represented by the parity check matrix H. It is a bipartite graph. Parity check nodes in a Tanner graph correspond to row constraints in the parity check matrix H, and variable nodes correspond to column constraints. The connections between nodes indicate that the corresponding row and column parity check matrix elements are non-zero, and are called edges in the Tanner graph. In the following description, "coded bits" and "variable nodes" can be considered equivalent.

[0039] (6) Punched variable nodes: These represent variable nodes whose corresponding constraint relationships are preserved but do not participate in transmission. Punching technology can improve the code rate and enhance the threshold performance of iterative decoding. After decoding, all variable nodes can be restored to obtain the complete encoded bit vector. Therefore, for LDPC codes with punctured corresponding variable nodes, minimum code weight detection requires post-processing.

[0040] 2. Log-BP decoding and related message passing decoding algorithms

[0041] The following definition applies to LDPC codes with a parity-check matrix H of size m×n:

[0042] (1) BP algorithm: The BP algorithm is an MPA (Message Passing Algorithm). Its core idea is to perform confidence propagation and message passing based on the constraint relationship between the target variables (such as the variable nodes of the LDPC code and the "edge" implicit variables of the parity check matrix) (such as the row constraints and column constraints of the LDPC code).

[0043] (2) Target Variables and Constraints of LDPC Codes: In the BP algorithm of LDPC codes, each non-zero element (i.e., "edge") in the parity check matrix can be regarded as a hidden variable. For example, the non-zero element in the i-th row and j-th column of the parity check matrix H corresponds to the variable e(i, j). Each row and each column are regarded as a constraint relationship (including row constraints and column constraints), that is, variables in the same row or column satisfy a constraint equation. In the BP decoder, each constraint relationship corresponds to a computation unit. Among them, the row constraint is a CNU (Check-Node Unit), and the column constraint is a VNU (Variable-Node Unit). There are m CNUs and n VNUs. Messages are passed between variables through these computation units.

[0044] (3) LLR: Log-likelihood ratio, is the specific form of message transmission in the BP decoder. For variable e(i, j), The larger the absolute value of LLR, the higher the confidence level of the variable's value (i.e., the smaller the uncertainty of the variable itself). A positive LLR indicates that the variable is more likely to take the value 0, while a negative LLR indicates that the variable is more likely to take the value 1.

[0045] (4) Row operations: Definition In the k-th iteration, the extrinsic information passed from the i-th check node to the j-th variable node serves as prior information for column operations; define... In the k-th iteration, the extrinsic information passed from the j-th variable node to the i-th check node is used as prior information for row operations. Row operations utilize row constraints to perform confidence propagation, with the prior information passed from the variable nodes as input. Output is external information External information is fed back to column operations as prior information for column operations.

[0046] (5) SPA (Sum-Product Algorithm) and MSA (Min-Sum Algorithm): Both are specific message passing algorithms for row operations.

[0047] In the SPA algorithm, the row operation update formula is:

[0048]

[0049] in, P i\j This represents the set of column indices corresponding to all non-zero elements in the i-th row of the parity check matrix, excluding the j-th column.

[0050] In the MSA algorithm, the row operation update formula is:

[0051]

[0052] (6) Column operations: Column operations use column constraints (i.e., variable node constraints) to perform confidence propagation operations. The input is the coded bit prior information LLR transmitted in the equivalent channel. ch (j) and the prior information transmitted by the verification node Output is external information External information is fed back to row operations as prior information for row operation input. The specific operations are as follows:

[0053]

[0054] Among them, LLR ch (j) represents the prior information from the j-th coded bit of the equivalent channel, Q j Q represents the set of row indices corresponding to all non-zero elements in the j-th column of the parity check matrix. j\i This represents the set of row indices corresponding to all non-zero elements in the j-th column of the parity check matrix, excluding the i-th row.

[0055] (7) Flooding scheduling and hierarchical scheduling: Both are scheduling methods that determine the order of row and column operations during a single iteration of BP operation. Simply put, a single BP iteration requires one operation on each CNU. In the flooding scheduling mode, all row operations are performed consecutively, and all column operations are performed consecutively. In the hierarchical scheduling mode, after each row operation, a column operation is performed on the column with non-zero elements in the corresponding row of the parity check matrix. Due to the sparsity of the LDPC code parity check matrix, the number of column operations is small, and the complexity of column operations is much lower than that of row operations. Therefore, hierarchical scheduling effectively improves the message passing efficiency during iterative decoding with a very small complexity cost, and significantly reduces the number of iterations required for iterative decoding.

[0056] 3. Traditional ANC Algorithm and its Minimum Code Weight Detection Method

[0057] The following definition applies to LDPC codes with a parity-check matrix H of size m×n:

[0058] (1) The idea of ​​traditional ANC algorithm: For LDPC codes, the size of its codeword space increases exponentially with the increase of code length, and it is impossible to detect the minimum code distance by exhaustive search. Therefore, a simple idea is to perform a small-range local search in the vicinity of the all-zero codeword. The ANC algorithm, namely the approximate nearest neighbor codeword algorithm, introduces impulse noise to make the received signal deviate from the initial codeword (usually the all-zero codeword). After iterative BP decoding, it can obtain a legal codeword that is close to the all-zero codeword under the Hamming metric. Among these legal codewords, the codeword with the smallest code weight is further identified.

[0059] (2) Introducing Impulse Noise: The simplest and most direct way to introduce impulse noise is to use additive white Gaussian noise. Since message passing in BP decoding usually adopts the LLR form, the equivalent of impulse noise superposition can be achieved directly by changing the LLR value of the bit. According to previous experiments, good results can be obtained by introducing impulse noise equivalently to a single coded bit. Without loss of generality, assume that an all-zero codeword is sent, and the LLR of each coded bit is +1, that is, the transmitted LLR vector X = (+1, +1, ..., +1). Assume that an LLR of size A is added to the i-th bit. i If the pulse is constant and other bits remain unchanged, then the initial LLR vector received by BP decoding is Y = (+1, +1, ..., +1, 1-A). i (+1, ..., +1). Gradually increase A. i The noise can be gradually increased by increasing the size of the noise until the decoding result of the iterative decoding deviates from the original all-zero codeword. Although only impulse noise is superimposed at one bit position and the superimposed impulse noise at that position is maintained, the noise at a single position will be transmitted to each position through the operation unit and operation process of the iterative BP decoding, which will have a significant impact on the decoding result. Therefore, it is not necessary to superimpose impulse noise at multiple bit positions.

[0060] (3) Half-Gaussian elimination: After introducing noise, the decoding result of BP is the posterior information LLR of each encoded bit. Based on the decoding result, the absolute values ​​(i.e., confidence levels) of the posterior information LLR of each bit are sorted from low to high. At the same time, the corresponding columns in the parity check matrix H are rearranged to obtain matrix X. The rank of the matrix after half-Gaussian elimination of X is N. e And determine or preset the number of bits to be further traversed and searched as N. d In subsequent processing, the nN with the highest confidence level e -N d Each bit will be hard-determined based on the sign of the LLR, with the middle N bits... d The bits will be traversed, and in each traversal, the equation will be solved using Gaussian back substitution to obtain the N with the lowest confidence. e The result of bits.

[0061] (4) Erase bits: In matrix X, the first N bits... e +N d The bits corresponding to the columns (i.e., those with lower confidence) are the erase bits, followed by nN. e -N d The bits corresponding to the columns (those with higher confidence) are non-erasable bits.

[0062] Specifically, Figure 1 This is a flowchart illustrating a minimum code weight detection method for LDPC codes provided in an embodiment of this application.

[0063] like Figure 1 As shown, the minimum code weight detection method for LDPC codes includes the following steps:

[0064] In step S101, the prior information of the coded bits transmitted in the equivalent channel is obtained, and the input signal for low-density parity-check code (LDPC) iterative decoding is generated.

[0065] It is understood that the embodiments of this application can obtain the prior information of the coded bits transmitted in the equivalent channel in the following steps, and generate the input signal for the low-density parity check code LDPC iterative decoding, thereby effectively reducing the computational complexity, improving the computational efficiency, and improving the feasibility of minimum code weight detection.

[0066] In one embodiment of this application, obtaining the prior information of the coded bits transmitted through the equivalent channel and generating the input signal for low-density parity-check code (LDPC) iterative decoding includes: converting a pre-defined length of all-zero codeword into the prior information of the coded bits required by the LDPC decoder; initializing the prior information of the coded bits; performing sign bit flipping and amplification on the prior information of the random single coded bits of the all-zero codeword to obtain the coded bit prior information vector of the all-zero codeword after sign bit flipping, which serves as the input signal for LDPC iterative decoding.

[0067] In actual implementation, the embodiments of this application can initialize and obtain the equivalent channel transmitted coded bit prior information LLR. ch (j) serves as the input signal for LDPC iterative decoding. For example, referring to the traditional ANC algorithm, a codeword of length n with all zeros can be directly converted into the prior information of the encoded bits required by the LDPC decoder. Without loss of generality, all prior information of the encoded bits is initialized to LLR. ch (j) = +1, and the prior information of the random single coded bit of the all-zero codeword is flipped and amplified to obtain the prior information vector LLR of the coded bit of the all-zero codeword after the sign bit is flipped. ch = (+1, +1, ..., 1-A) i (1, +1, ..., +1) are used as input signals for LDPC iterative decoding, thereby effectively reducing computational complexity, simplifying the decoding algorithm, and improving computational efficiency.

[0068] For example, A j =3, that is, the equivalent channel transmitted prior information of the coded bits (LLR) of the inverted coded bits (assuming to be the j-th bit). ch (j) = -2, which means that the initialization method proposed in this application embodiment can well approximate the effect of impulse noise, and there is no need to superimpose impulse noise at multiple bit positions.

[0069] In step S102, the input signal of LDPC iterative decoding is hierarchically scheduled and minimum sum decoding is performed, and after each iteration, the posterior information of all encoded bits is calculated to obtain the current intermediate result of LDPC iterative decoding.

[0070] It is understood that the embodiments of this application can perform hierarchical scheduling and minimum sum decoding on the input signal of LDPC iterative decoding, and calculate the a posteriori information of all encoded bits after each iteration, thereby obtaining the current intermediate result of LDPC iterative decoding. For example, the nth intermediate result of LDPC iterative decoding, i.e., the a posteriori information of encoded bits of the nth iteration, can be obtained sequentially. When the iterative decoding verification is successful or the number of iterations reaches the maximum value, the current search ends, and the minimum code weight detection results of all iterations of the current search are post-processed in the following steps, thereby reducing the number of decoding iterations and improving codeword search efficiency.

[0071] In some embodiments, the decoding order of hierarchical scheduling is random. Under the condition of ensuring the same LDPC iterative decoding input signal, the minimum code weight detection result is random, which improves the minimum code weight detection efficiency of multiple repeated searches.

[0072] For example, assuming the maximum number of iterations is preset to 10, further, for the intermediate results of the 1st to 6th iterations of LDPC iterative decoding, there is no need to perform the subsequent processing of minimum code weight detection in the following steps, which further reduces the complexity of minimum code weight detection. The reason is that only after multiple iterations can the error at a single bit position be fully propagated to other bit positions, and the efficiency of minimum code weight detection in the following steps can be significantly improved.

[0073] Therefore, assuming the maximum number of iterations is preset to 10, since the embodiments of this application benefit from hierarchical scheduling and MSA decoding algorithm, the LDPC decoding scheduling strategy and decoding algorithm proposed in the embodiments of this application for minimum code weight detection can significantly reduce the complexity and number of iterations of LDPC decoding.

[0074] In step S103, the current intermediate result is processed by a preset improved ANC algorithm and the minimum code weight is detected to obtain the minimum code weight detection result of the current iteration of the search. After the preset iteration stopping condition is reached, the minimum code weight detection results of all iterations of the current search are obtained.

[0075] It is understood that the embodiments of this application can perform improved ANC algorithm processing and minimum code weight detection on the current intermediate result in the following steps to obtain the minimum code weight detection result of the current iteration of the current search. After the iteration stopping condition is reached, for example, when the number of searches reaches the maximum value or the search results meet the requirements, the minimum code weight detection result of all iterations of the current search is obtained, thereby effectively reducing the computational complexity, reducing the number of decoding iterations, reducing system complexity, improving codeword search efficiency, and improving the versatility of minimum code weight detection.

[0076] In one embodiment of this application, the current intermediate result is processed by a preset improved ANC algorithm and minimum code weight detection to obtain the minimum code weight detection result of the current iteration of the search. This includes: sorting the posterior information of the encoded bits of the current intermediate result according to the absolute value of the log-likelihood ratio; rearranging the corresponding columns of the parity check matrix according to the sorting result to obtain a column-ordered parity check matrix; performing semi-Gaussian elimination, block processing, and decision processing on the column-ordered parity check matrix to obtain a column-ordered parity check matrix of matrix block and decision; and combining the column-ordered parity check matrix of matrix block and decision, performing a non-traversal search and code space solution on the codeword space composed of multiple encoded bit variables to be searched to obtain a non-all-zero legal codeword that conforms to the parity check matrix.

[0077] In some embodiments, the present application embodiments may sort the posterior information of the encoded bits of the nth iteration decoding according to the absolute value of the log-likelihood ratio, and rearrange the corresponding columns of the parity check matrix according to the sorting result to obtain the parity check matrix X with column order rearrangement.

[0078] Furthermore, embodiments of this application can perform semi-Gaussian elimination on the column-ordered parity-check matrix, followed by block processing and decision-making, to obtain a column-ordered parity-check matrix with matrix block processing and decision-making, wherein N e +N d N erase bits d There are N erased bits (i.e. encoded bit variables) to be searched. e Let N be the rank of the matrix after half-Gaussian elimination. d This is the preset number of bits to traverse.

[0079] For example, the parity check matrix X after column reordering is:

[0080]

[0081] As shown in the above formula, the parity check matrix X, after column reordering, is divided into the first N columns. e Column, middle N d Columns, and the following nN e +N d The column is divided into three parts, and then divided into the first N rows. e row and after mN e The column-ordered parity check matrix X is divided into two parts, thus dividing it into 6 sub-matrices. Using the traditional ANC algorithm, hard decision can be made on the corresponding encoded bits of sub-matrices X3 and Y3, which facilitates the non-traversal search in the following steps.

[0082] Furthermore, embodiments of this application can combine matrix partitioning and the column order rearrangement of the decision check matrix to perform N... dThe codeword space is composed of 10 encoded bit variables to be searched. A non-traversal search and codeword space solution are performed to obtain a non-all-zero valid codeword that conforms to the parity check matrix. This is the minimum code weight detection result of this iteration of the search.

[0083] For example, the parity check matrix X after column reordering is:

[0084]

[0085] As shown in the above equation, a non-ergodic search is performed on the corresponding bits of submatrices X2 and Y2, i.e., within the allowed maximum... Under the premise of bit-level errors, a search is performed in a finite subspace. For all-zero codeword input, the improved ANC algorithm proposed in this application has a search range of length N. d And the number of bits that are 1 is no more than All the codewords of the given bits can reduce the search complexity from a traversal search method. Reduced to approximately This can significantly increase N d This expands the search scope within the codeword space.

[0086] Furthermore, combining the nN obtained in the above steps e -N d The coded bit decision result and the non-traversal search N d Taking the values ​​of each encoded bit, we perform Gaussian back substitution to solve the equations, yielding the residual N corresponding to submatrices X1 and Y1. e The least reliable bit value is selected to obtain the codeword space solution.

[0087] Furthermore, in this embodiment of the application, the codeword validity can be judged from the non-traversal search and codeword space solution results, and the valid codeword search results, including the punched bit positions, can be recorded to obtain the non-all-zero valid codewords that conform to the parity check matrix, which is the minimum code weight detection result of this iteration of the search.

[0088] For example, suppose the parameters in the embodiments of this application... The non-traversal search strategy proposed in the embodiments of this application can be used, and the search complexity is similar to that of the traditional ANC algorithm. d =10, The search range increases by orders of magnitude.

[0089] In summary, the embodiments of this application can effectively expand the codeword search space, simplify the decoding algorithm, reduce the number of decoding iterations required, and significantly improve the codeword search efficiency and the versatility of minimum code weight detection by improving the traditional ANC algorithm.

[0090] Optionally, in one embodiment of this application, the method further includes: post-processing the minimum code weight detection results of all iterations of the current search to update the minimum code weight detection statistics of the LDPC code.

[0091] As one possible implementation, this application embodiment can post-process the minimum code weight detection results of all iterations of the current search. For example, it can post-process structured LDPC codes, including but not limited to common quasi-cyclic structures, Raptor-like structures, variable node punched structures, etc., and update the minimum code weight detection statistics of LDPC codes. When the number of search attempts reaches the maximum value or the search results meet the requirements, the search ends; otherwise, it returns to the initialization processing stage. Thus, this application embodiment can further reduce system complexity by introducing post-processing steps, which helps to accelerate the hardware of minimum code weight detection and improves the versatility of minimum code weight detection.

[0092] In some embodiments, for non-all-zero legal codewords in the minimum code weight detection result, when the LDPC code is a QC-LDPC code, the z coded bits corresponding to each column of the base matrix in the non-all-zero legal codeword are cyclically shifted by the same size to obtain a set of z non-zero legal codewords with quasi-cyclic shift characteristics and the same minimum code weight. When the LDPC code is an LDPC code with punctured variable nodes, the minimum code weight detection result before and after puncturing is obtained according to the position of the punctured bits in the minimum code weight detection result, which helps to detect the minimum code weight and the corresponding legal codeword more quickly and accurately.

[0093] Therefore, the embodiments of this application can perform minimum code weight detection on LDPC codes with any given parity check matrix, and are particularly suitable for QC-LDPC and LDPC codes with variable node punching features.

[0094] For example, embodiments of this application can utilize the structural characteristics of LDPC codes in 5G-NR (5G New Radio) and Wi-Fi standards, employing the proposed improved ANC algorithm and its minimum code weight detection method to perform quasi-cyclic correction and variable node puncturing correction, thereby increasing the length N of the search bit in the erased bits. d It is permissible to allow The algorithm searches within the space of bit errors and significantly increases the search range of nearest neighbor codewords while controlling the complexity of the search operation, which helps to detect the minimum code weight and the corresponding legal codeword more quickly and accurately.

[0095] For example, such as Figure 2 The diagram shown is a schematic representation of the base matrix of a QC-LDPC code according to a specific embodiment of this application. In this embodiment, m can be set... z =12, n z=24, lift factor z=54, parity check matrix size is 648×1296, no punched variable nodes. Figure 2 Let A be the lifting matrix corresponding to the base matrix of the LDPC code. Zero elements represent the zero elements of the base matrix, and the values ​​of non-zero elements represent the offset addresses of the non-zero elements of the base matrix. For example, if the value of an element in the lifting matrix is ​​1, it means that the element is lifted to a z-order identity matrix, and if it is k (2≤k≤54), it means that it is lifted to a z-order cyclic shift matrix with an offset address of k-1.

[0096] Furthermore, according to the definition of the lifting matrix A, the 12×24 basis matrix can be lifted to a parity check matrix H of size 648×1296. Traditional ANC algorithms and their minimum code weight detection methods have difficulty searching for all z sets of legal codewords with the same minimum code weight that satisfy the quasi-cyclic shift feature of a legal codeword with a non-zero minimum code weight. Therefore, the search results of the ANC algorithm and its minimum code weight detection method can be improved by using the post-processing of the quasi-cyclic feature proposed in the embodiments of this application, which makes the search results more consistent with the theoretical results.

[0097] The LDPC code minimum code weight detection method proposed in this application can directly obtain the prior information of the coded bits transmitted in the equivalent channel, generate the input signal for low-density parity-check code LDPC iterative decoding, and perform hierarchical scheduling and minimum sum decoding. After each iteration, the posterior information of all coded bits is calculated to obtain the current intermediate result of LDPC iterative decoding. An improved ANC algorithm is then applied for processing and minimum code weight detection to obtain the minimum code weight detection result for the current iteration. After the iteration stopping condition is met, the minimum code weight detection results for all iterations of the current search are obtained. This effectively expands the codeword search space, simplifies the decoding algorithm, reduces the required number of decoding iterations, and significantly improves codeword search efficiency and the versatility of minimum code weight detection. Therefore, it solves the problems in related technologies, such as increased computational complexity due to the introduction of noise, and the problems of a large number of decoding iterations and a small search range during iterative decoding, which reduce codeword search efficiency and increase system complexity.

[0098] Next, the LDPC code minimum code weight detection device according to the embodiments of this application is described with reference to the accompanying drawings.

[0099] Figure 3 This is a block diagram of the LDPC code minimum code weight detection device according to an embodiment of this application.

[0100] like Figure 3 As shown, the LDPC code minimum code weight detection device 10 includes: a generation module 100, a processing module 200, and a detection module 300.

[0101] Specifically, the generation module 100 is used to obtain the prior information of the coded bits transmitted in the equivalent channel and generate the input signal for low-density parity-check code (LDPC) iterative decoding.

[0102] The processing module 200 is used to perform hierarchical scheduling and minimum sum decoding on the input signal of LDPC iterative decoding, and after each iteration, calculates the a posteriori information of all encoded bits to obtain the current intermediate result of LDPC iterative decoding.

[0103] The detection module 300 is used to process the current intermediate result with the improved ANC algorithm and perform minimum code weight detection to obtain the minimum code weight detection result of the current iteration of the search. After reaching the preset iteration stopping condition, the minimum code weight detection results of all iterations of the current search are obtained.

[0104] Optionally, in one embodiment of this application, the generation module 100 includes a conversion unit and an acquisition unit.

[0105] The conversion unit is used to convert a preset length of all-zero codeword into prior information of the encoded bits required by the LDPC decoder.

[0106] The acquisition unit is used to initialize the prior information of the encoded bits, perform sign bit flipping and amplification on the prior information of the random single encoded bit of the all-zero codeword, and obtain the prior information vector of the encoded bits of the all-zero codeword after sign bit flipping, which serves as the input signal for LDPC iterative decoding.

[0107] Optionally, in one embodiment of this application, the detection module 300 includes: an arrangement unit, a processing unit, and a calculation unit.

[0108] The permutation unit is used to sort the posterior information of the encoded bits of the current intermediate result according to the absolute value of the log-likelihood ratio, and rearrange the corresponding columns of the parity check matrix according to the sorting result to obtain the parity check matrix with column order rearrangement.

[0109] The processing unit is used to perform semi-Gaussian elimination, block processing, and decision processing on the column-order rearranged parity check matrix to obtain the column-order rearranged parity check matrix after matrix block and decision.

[0110] The computational unit is used to combine the matrix block and the column order rearrangement of the judgment to perform non-traversal search and codeword space solution on the codeword space composed of multiple coded bit variables to be searched, so as to obtain the non-all-zero legal codeword that conforms to the parity check matrix.

[0111] Optionally, in one embodiment of this application, the apparatus 10 of this application embodiment further includes an update module.

[0112] The update module is used to post-process the minimum code weight detection results of all iterations of this search and update the minimum code weight detection statistics of the LDPC code.

[0113] It should be noted that the foregoing explanation of the LDPC code minimum code weight detection method embodiment also applies to the LDPC code minimum code weight detection device of this embodiment, and will not be repeated here.

[0114] The LDPC code minimum code weight detection device proposed in this application can acquire the prior information of the coded bits transmitted through the equivalent channel, generate the input signal for low-density parity-check code LDPC iterative decoding, and perform hierarchical scheduling and minimum sum decoding. After each iteration, it calculates the posterior information of all coded bits, sequentially obtains the current intermediate result of LDPC iterative decoding, and performs improved ANC algorithm processing and minimum code weight detection to obtain the minimum code weight detection result of the current iteration. After reaching the iteration stopping condition, it obtains the minimum code weight detection results of all iterations of the current search, thereby effectively expanding the codeword search space, simplifying the decoding algorithm, reducing the number of decoding iterations required, and significantly improving the codeword search efficiency and the versatility of minimum code weight detection. This solves the problems in related technologies, such as increased computational complexity when noise is introduced, and the problems of a large number of decoding iterations and a small search range during iterative decoding, which reduce the efficiency of codeword search and increase system complexity.

[0115] Figure 4 A schematic diagram of the structure of an electronic device provided in an embodiment of this application. The electronic device may include:

[0116] The memory 401, the processor 402, and the computer program stored on the memory 401 and capable of running on the processor 402.

[0117] When the processor 402 executes the program, it implements the LDPC code minimum code weight detection method provided in the above embodiments.

[0118] Furthermore, electronic devices also include:

[0119] Communication interface 403 is used for communication between memory 401 and processor 402.

[0120] The memory 401 is used to store computer programs that can run on the processor 402.

[0121] The memory 401 may include high-speed RAM memory, and may also include non-volatile memory, such as at least one disk storage device.

[0122] If the memory 401, processor 402, and communication interface 403 are implemented independently, then the communication interface 403, memory 401, and processor 402 can be interconnected via a bus to complete communication between them. The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of representation, Figure 4 The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.

[0123] Optionally, in a specific implementation, if the memory 401, processor 402, and communication interface 403 are integrated on a single chip, then the memory 401, processor 402, and communication interface 403 can communicate with each other through an internal interface.

[0124] Processor 402 may be a central processing unit (CPU), an application specific integrated circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of this application.

[0125] This application also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the LDPC code minimum code weight detection method described above.

[0126] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0127] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "N" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0128] Any process or method described in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or N executable instructions for implementing custom logic functions or processes, and the scope of the preferred embodiments of this application includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the functions involved, as should be understood by those skilled in the art to which embodiments of this application pertain.

[0129] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a ordered list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a processor-included system, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include: an electrical connection having one or more wires (electronic device), a portable computer disk drive (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and programmable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Alternatively, the computer-readable medium may be paper or other suitable media on which the program can be printed, since the program can be obtained electronically by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in a computer memory.

[0130] It should be understood that the various parts of this application can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiments, the N steps or methods can be implemented using software or firmware stored in memory and executed by a suitable instruction execution system. If implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0131] Those skilled in the art will understand that all or part of the steps of the methods in the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, the program includes one or a combination of the steps of the method embodiments.

[0132] Furthermore, the functional units in the various embodiments of this application can be integrated into a processing module, or each unit can exist physically separately, or two or more units can be integrated into a module. The integrated module can be implemented in hardware or as a software functional module. If the integrated module is implemented as a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium.

[0133] The storage medium mentioned above can be a read-only memory, a disk, or an optical disk, etc. Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of this application.

Claims

1. A method for detecting the minimum code weight of a low-density parity-check (LDPC) code, characterized in that, Includes the following steps: Obtain the prior information of the coded bits transmitted in the equivalent channel to generate the input signal for low-density parity-check code (LDPC) iterative decoding; The input signal of the LDPC iterative decoding is subjected to hierarchical scheduling and minimum sum decoding. After each iteration, the posterior information of all encoded bits is calculated to obtain the current intermediate result of the LDPC iterative decoding. as well as The current intermediate result is processed by a preset improved approximate nearest neighbor codeword ANC algorithm and minimum code weight detection is performed to obtain the minimum code weight detection result of the current iteration of the search. After the preset iteration stopping condition is reached, the minimum code weight detection results of all iterations of the current search are obtained. The step of processing the current intermediate result using a pre-defined improved ANC algorithm and performing minimum code weight detection to obtain the minimum code weight detection result for the current iteration of the search includes: The posterior information of the encoded bits of the current intermediate result is sorted according to the absolute value of the log-likelihood ratio, and the corresponding columns of the parity check matrix are rearranged according to the sorting result to obtain the parity check matrix with column order rearranged. The column-order rearranged parity check matrix is ​​subjected to semi-Gaussian elimination, block processing, and decision processing to obtain a column-order rearranged parity check matrix with matrix block processing and decision processing. Combining the matrix block division and the column-order rearranged parity-check matrix of the decision, a non-traversal search and codeword space solution are performed on the codeword space composed of multiple coded bit variables to be searched, resulting in non-all-zero valid codewords that conform to the parity-check matrix; wherein, The search range of the non-traversal search is of length [length missing]. And the number of bits that are 1 is no more than All codewords of position; among them The preset number of traversed bits; wherein, the codeword space solution includes: performing Gaussian back substitution on the encoded bit values ​​and decision results obtained by the non-traversal search to solve for the values ​​of the remaining encoded bits.

2. The method according to claim 1, characterized in that, The step of obtaining the prior information of the coded bits transmitted in the equivalent channel and generating the input signal for low-density parity-check code (LDPC) iterative decoding includes: Convert a pre-defined all-zero codeword into prior information of the encoded bits required by the LDPC decoder; The prior information of the encoded bits is initialized, and the prior information of the random single encoded bit of the all-zero codeword is flipped and amplified to obtain the prior information vector of the encoded bits of the all-zero codeword after the sign bit is flipped, which is used as the input signal of the LDPC iterative decoding.

3. The method according to any one of claims 1-2, characterized in that, Also includes: Post-process the minimum code weight detection results of all iterations of this search to update the minimum code weight detection statistics of the LDPC code.

4. A device for detecting the minimum code weight of a low-density parity-check (LDPC) code, characterized in that, include: The generation module is used to obtain the prior information of the coded bits transmitted in the equivalent channel and generate the input signal for low-density parity-check code (LDPC) iterative decoding. The processing module is used to perform hierarchical scheduling and minimum sum decoding on the input signal of the LDPC iterative decoding, and after each iteration, calculate the posterior information of all encoded bits to obtain the current intermediate result of the LDPC iterative decoding in sequence. as well as The detection module is used to process the current intermediate result using a preset improved approximate nearest neighbor codeword (ANC) algorithm and to detect the minimum code weight, so as to obtain the minimum code weight detection result of the current iteration of the current search, and after reaching the preset iteration stopping condition, to obtain the minimum code weight detection results of all iterations of the current search. The detection module includes: The sorting unit is used to sort the posterior information of the encoded bits of the current intermediate result according to the absolute value of the log-likelihood ratio, and rearrange the corresponding columns of the parity check matrix according to the sorting result to obtain the parity check matrix with column order rearrangement. The processing unit is used to perform semi-Gaussian elimination, block processing and decision processing on the column-rearranged parity matrix to obtain a column-rearranged parity matrix with matrix block and decision. The calculation unit is used to combine the matrix block division and the column order rearrangement of the judgment into a parity check matrix to perform a non-traversal search and codeword space solution on the codeword space composed of multiple coded bit variables to be searched, so as to obtain a non-all-zero valid codeword that conforms to the parity check matrix; wherein, The search range of the non-traversal search is of length [length missing]. And the number of bits that are 1 is no more than All codewords of position; among them The preset number of traversed bits; wherein, the codeword space solution includes: performing Gaussian back substitution on the encoded bit values ​​and decision results obtained by the non-traversal search to solve for the values ​​of the remaining encoded bits.

5. The apparatus according to claim 4, characterized in that, The generation module includes: The conversion unit is used to convert a pre-defined all-zero codeword into prior information of the encoded bits required by the LDPC decoder. The acquisition unit is used to initialize the prior information of the encoded bits, perform sign bit flipping and amplification on the prior information of the random single encoded bit of the all-zero codeword, and obtain the prior information vector of the encoded bits of the all-zero codeword after sign bit flipping, which serves as the input signal for the LDPC iterative decoding.

6. The apparatus according to any one of claims 4-5, characterized in that, Also includes: Post-process the minimum code weight detection results of all iterations of this search to update the minimum code weight detection statistics of the LDPC code.

7. An electronic device, characterized in that, include: The memory, the processor, and the computer program stored in the memory and executable on the processor, the processor executing the program to implement the LDPC code minimum code weight detection method as described in any one of claims 1-3.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that, The program is executed by the processor to implement the LDPC code minimum code weight detection method as described in any one of claims 1-3.

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