Pixel structure and image sensor

Abstract

The application provides a pixel structure and an image sensor, which comprises: a pixel signal generation circuit for generating a signal voltage and a reset voltage; a voltage storage circuit comprising a signal voltage sampling capacitor and a reset voltage sampling capacitor, one end of the signal voltage sampling capacitor being electrically connected to an output end of the pixel signal generation circuit through a transfer transistor, the other end of the signal voltage sampling capacitor being electrically connected to a first reference voltage; one end of the reset voltage sampling capacitor being electrically connected to one end of the signal voltage sampling capacitor through another transfer transistor, the other end of the reset voltage sampling capacitor being electrically connected to a second reference voltage; and a signal reading circuit electrically connected to an output end of the voltage storage circuit. The pixel structure provided by the application can reduce the leakage current in the pixel structure.

Description

Technical Field

[0001] This invention belongs to the field of electronic circuit technology, and specifically relates to a pixel structure and image sensor. Background Technology

[0002] Image sensors are finding increasingly wide applications due to their low power consumption, simple power supply, high integration, and low cost. An image sensor generates images representing objects, and the pixel array, composed of pixel structures, is the core component of an image sensor.

[0003] In a global shutter pixel structure, the reset voltage and signal voltage are stored on the sampling capacitor in the pixel structure's voltage storage circuit and held for a period of time before being read out line by line. However, leakage current can occur in the sampling capacitor during this process, affecting the accuracy of the sampled voltage and creating spatial noise in the image sensor. Summary of the Invention

[0004] The purpose of this invention is to provide a pixel structure and image sensor that can reduce parasitic leakage current in the global shutter pixel structure and improve the performance of the image sensor.

[0005] To achieve the above objectives, the present invention provides a pixel structure comprising at least:

[0006] The pixel signal generation circuit generates signal voltage and reset voltage;

[0007] A voltage storage circuit includes a signal voltage sampling capacitor and a reset voltage sampling capacitor. One end of the signal voltage sampling capacitor is electrically connected to the output terminal of the pixel signal generation circuit through a transmission transistor, and the other end of the signal voltage sampling capacitor is electrically connected to a first reference voltage. One end of the reset voltage sampling capacitor is electrically connected to one end of the signal voltage sampling capacitor through another transmission transistor, and the other end of the reset voltage sampling capacitor is electrically connected to a second reference voltage.

[0008] The signal reading circuit is electrically connected to the output terminal of the voltage storage circuit.

[0009] In one embodiment of the present invention, the first reference voltage is greater than the minimum signal voltage and less than the maximum signal voltage, wherein the minimum signal voltage is the value of the signal voltage when shooting an oversaturated bright spot, and the maximum signal voltage is the value of the signal voltage when shooting a completely dark black spot.

[0010] In one embodiment of the present invention, the second reference voltage is equal to the reset voltage.

[0011] In one embodiment of the present invention, the first reference voltage is equal to the median of the signal voltage in a specific region of the previous frame image.

[0012] In one embodiment of the present invention, the first reference voltage includes two levels, wherein the first reference voltage of one level is equal to the sum of three-quarters of the maximum signal voltage and one-quarter of the minimum signal voltage, and the first reference voltage of the other level is equal to the sum of one-quarter of the maximum signal voltage and three-quarters of the minimum signal voltage.

[0013] In one embodiment of the present invention, the first reference voltage is equal to the second reference voltage, and is also equal to the median of the maximum and minimum values ​​of the maximum signal voltage, the minimum signal voltage, and the reset voltage.

[0014] In one embodiment of the present invention, the pixel structure further includes a dual-conversion gain circuit, and the dual-conversion gain circuit includes a gain capacitor, which is electrically connected to the ungrounded end of the floating diffusion region node capacitor in the pixel signal generation circuit through a switching transistor.

[0015] In one embodiment of the present invention, the voltage storage circuit includes a first voltage storage circuit and a second voltage storage circuit. The first voltage storage circuit stores the reset voltage and the signal voltage in high-gain mode, and the second voltage storage circuit stores the reset voltage and the signal voltage in low-gain mode.

[0016] In one embodiment of the present invention, the signal voltage sampling capacitor and the reset voltage sampling capacitor are linear capacitors.

[0017] In one embodiment of the present invention, the linear capacitor includes:

[0018] Substrate;

[0019] A gate oxide layer is disposed on the substrate;

[0020] A gate electrode is disposed on the gate oxide layer and forms the upper plate of the linear capacitor;

[0021] An electrode doped region is disposed in the substrate covered by the gate oxide layer. The doping type of the electrode doped region is the same as that of the source doped region and the drain doped region, forming the lower electrode of the linear capacitor.

[0022] The present invention also provides an image sensor comprising the pixel structure described in any of the above claims.

[0023] In summary, the pixel structure and image sensor provided by this invention can reduce leakage current between the upper and lower plates of the sampling capacitor, thereby improving the performance of the image sensor. Attached Figure Description

[0024] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 This is a structural block diagram of a pixel structure in this invention.

[0026] Figure 2 This is a circuit diagram of a pixel structure in this invention.

[0027] Figure 3 This is a circuit diagram of the pixel structure with equipotential sampling capacitors in this invention.

[0028] Figure 4 This is a circuit diagram of the pixel structure with a dual-conversion gain circuit in this invention.

[0029] Figure 5 This is a circuit diagram of the pixel structure with two voltage storage circuits and a signal reading circuit in this invention.

[0030] Figure 6 This is a structural diagram of a linear capacitor in this invention. Detailed Implementation

[0031] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Preferred embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the disclosure of this application.

[0032] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application.

[0033] In the description of this invention, it should be understood that the terms "center," "upper," "lower," "front," "rear," "left," and "right," etc., indicating orientation or positional relationships, are based on the orientation or positional relationships shown in the accompanying drawings and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0034] Complementary Metal Oxide Semiconductor (CMOS) image sensors consist of pixel arrays composed of numerous pixel units, which are the core components of the image sensor that enable light sensing. In CMOS image sensors, exposure time is typically controlled by an electronic shutter. Based on their operating principles, electronic shutters are divided into rolling shutters and global shutters. With a rolling shutter, the exposure time of each row is gradually staggered, which can easily cause motion distortion when photographing fast-moving objects. With a global shutter, all pixel rows are exposed simultaneously, and the charge signal is simultaneously stored in the pixel unit's storage node before being output line by line. Even when photographing fast-moving objects, motion distortion does not occur. Therefore, global shutter pixels are widely used in industrial monitoring, intelligent transportation, automotive, and other product fields.

[0035] Since the global shutter pixels need to store the voltage signal on the storage node for a certain period of time before reading it out, the storage node voltage must remain constant during this time. However, leakage current always exists on the storage node, including leakage current at the sampling capacitor plates, PN junctions, transistors, etc., causing changes in the storage voltage value. Furthermore, the difference in leakage current between each node by orders of magnitude further exacerbates the non-uniformity of the light response within the array, increasing the spatial noise of the image sensor. Simultaneously, with product iterations, there is a demand to reduce pixel size while suppressing temporal noise, necessitating the use of high-density sampling capacitors. These high-density capacitors are achieved by converting the planar structure to a slotted structure or using a thinner dielectric layer between the plates, but these improvements all make the leakage current between the plates increasingly significant.

[0036] Please see Figure 1 As shown, this application provides a pixel structure in an image sensor. The pixel structure forms a pixel unit and includes a pixel signal generation circuit 100, a voltage storage circuit 200, and a signal readout circuit 300. The pixel signal generation circuit 100 converts an optical signal into an electrical signal, generating a reset voltage and a signal voltage. The voltage storage circuit 200 stores the generated reset voltage and signal voltage. Under the control of a row selection signal, the signal readout circuit 300 reads the reset voltage and signal voltage stored in the voltage storage circuit 200.

[0037] Please see Figure 2As shown, in one embodiment of the present invention, the pixel signal generation circuit 100 includes a photodiode PD, a first transmission transistor M1, a reset transistor M2, a first-stage source follower M3, a first row selection transistor M4, and a floating diffusion region node capacitor Cfd. The connection relationships of the photodiode PD, the first transmission transistor M1, the reset transistor M2, the first-stage source follower M3, the first row selection transistor M4, and the floating diffusion region node capacitor Cfd are as follows: Figure 2 As shown.

[0038] For details, please refer to Figure 2 As shown, in one embodiment of the present invention, a photodiode PD can convert an optical signal into an electrical signal. A first transmission transistor M1 is electrically connected to the cathode of the photodiode PD, and its gate is electrically connected to the transmission signal TX. When the first transmission transistor M1 is turned on in response to the transmission signal TX, electrons generated after photoelectric conversion in the photodiode PD are emitted and can be temporarily stored in the floating diffusion region node capacitor Cfd or transmitted to the voltage storage circuit 200. The floating diffusion region node capacitor Cfd is electrically connected to the output terminal of the first transmission transistor M1, which also effectively reduces pixel thermal noise and dark current.

[0039] Please see Figure 2 As shown, in one embodiment of the present invention, the output terminal of the reset transistor M2 is electrically connected to the common terminal of the first transmission transistor M1 and the floating diffusion region node capacitor Cfd. The other terminal of the reset transistor M2 is electrically connected to the power supply voltage VDD_PIXEL, and the gate of the reset transistor M2 is electrically connected to the reset signal RX. When the reset transistor M2 is turned on in response to the reset signal RX, the signal at the connection point between the output terminal of the reset transistor M2 and the gate terminal of the first-stage source follower M3 is reset to the power supply voltage VDD_PIXEL at the other terminal of the reset transistor M2. Then, the reset signal RX is turned off. Due to the channel charge injection effect and clock feedthrough, and because there is no path to ground at the connection point between the reset transistor M2 and the gate terminal of the first-stage source follower M3, the connection point between the reset transistor M2 and the gate terminal of the first-stage source follower M3 will remain approximately lower than the voltage value at the other terminal of the reset transistor M2, and the reset voltage will be output.

[0040] Please see Figure 2As shown, in one embodiment of the present invention, the first-stage source follower M3 and the first row select transistor M4 are connected in series, with one end of the first-stage source follower M3 connected to a first fixed voltage VDD1, and one end of the first row select transistor M4 electrically connected to ground. The gate of the first-stage source follower M3 is electrically connected to the output of the reset transistor M2 and the output of the first transmission transistor M1, i.e., the common terminal of the reset transistor M2, the first transmission transistor M1, and the floating diffusion region node capacitor Cfd. The gate of the first row select transistor M4 is electrically connected to the first row select signal SEL1. The first-stage source follower M3 can act as a buffer amplifier, isolating the subsequent readout circuit with large parasitic capacitance from the sensitive node that generates the signal voltage. When the image sensor is working, the photodiode PD outputs an electrical signal after photoelectric conversion, and the first transmission transistor M1 selectively transfers the optical signal. When the first row select transistor M4 is turned on, the first-stage source follower M3 outputs a photoelectric signal, i.e., the signal voltage Vsig.

[0041] Please see Figure 2 As shown, in one embodiment of this application, the voltage storage circuit 200 includes a signal voltage sampling capacitor C1 and a reset voltage sampling capacitor C2. One end of the signal voltage sampling capacitor C1 is electrically connected to the output terminal of the pixel signal generation circuit 100, i.e., the common terminal of the first-stage source follower M3 and the first row selection transistor M4, via a second transmission transistor M5; the other end is connected to a first reference voltage V1. One end of the reset voltage sampling capacitor C2 is electrically connected to the common terminal of the signal voltage sampling capacitor C1 and the second transmission transistor M5 via a third transmission transistor M6; the other end is connected to a second reference voltage V2. In some embodiments, the first reference voltage V1 is equal to the second reference voltage V2. In other embodiments, the first reference voltage V1 is not equal to the second reference voltage V2, and the first reference voltage V1 and the second reference voltage V2 can be set according to specific circumstances. The gate of the second transmission transistor M5 is electrically connected to a first control signal S1, and the gate of the third transmission transistor M6 is electrically connected to a second control signal S2.

[0042] Please see Figure 2 As shown, in one embodiment of this application, when the second transmission transistor M5 closes in response to the first control signal S1 and the third transmission transistor M6 closes in response to the second control signal S2, the reset voltage Vrst can be stored in the upper plate of the signal voltage sampling capacitor C2. Then, when the second transmission transistor M5 closes in response to the first control signal S1 and the third transmission transistor M6 opens, the signal voltage Vsig can be stored in the upper plate of the signal voltage sampling capacitor C1.

[0043] Please see Figure 2As shown, in one embodiment of this application, the signal readout circuit 300 includes a second source follower M7 and a second row select transistor M8. The second source follower M7 and the second row select transistor M8 are connected in series, with one end of the second source follower M7 electrically connected to a second fixed voltage, and one end of the second row select transistor M8 serving as a signal output terminal. The gate of the second source follower M7 is electrically connected to the output terminal of the voltage storage circuit 200, i.e., the common terminal of the third transmission transistor M6 and the reset voltage sampling capacitor C2. The gate of the second row select transistor M8 receives a second row select signal SEL2. Responding to the second row select signal SEL2, the second row select transistor M8 reads out the reset voltage of the upper plate of the reset voltage sampling capacitor C2 and the signal voltage of the signal voltage sampling capacitor C1 during the readout phase.

[0044] Please see Figures 2 to 5 As shown in one embodiment of this application, the magnitudes of the first reference voltage V1 and the second reference voltage V2 can be adjusted according to the specific pixel structure in the image sensor to reduce the voltage difference between the upper and lower plates of the signal voltage sampling capacitor C1 and the reset voltage sampling capacitor C2. This reduces leakage current between the upper and lower plates of the signal voltage sampling capacitor C1 and the reset voltage sampling capacitor C2, thereby improving the performance of the image sensor.

[0045] Please see Figure 2 As shown, in one embodiment of this application, the first reference voltage V1 and the second reference voltage V2 have different values, and the first reference voltage V1 is related to the maximum signal voltage Vsig_max and the minimum signal voltage Vsig_min, while the second reference voltage V2 is equal to the reset voltage, i.e., V2 = Vrst.

[0046] For details, please refer to Figure 2 As shown, in one embodiment of this application, the reset voltage is a fixed value and is related to the power supply voltage VDD_PIXEL, the threshold voltages of the first transmission transistor M1, the reset transistor M2, the first source follower M3, the first row select transistor M4, the second transmission transistor M5, and the third transmission transistor M6, the voltage values ​​of the reset signal RX, the first row select signal SEL1, the first control signal S1, the second control signal S2, and the floating diffusion region node capacitance Cfd. In some embodiments, the reset voltage Vrst = 1.8V, then the second reference voltage is set to, for example, 1.8V. At this time, the voltage difference between the lower and upper plates of the reset voltage sampling capacitor C2 is 0, which can significantly reduce the voltage difference between the lower and upper plates of the reset voltage sampling capacitor C2, thereby eliminating the leakage current between the two plates of the reset voltage sampling capacitor C2.

[0047] Please see Figure 2As shown, in one embodiment of this application, the first reference voltage V1 is greater than the minimum signal voltage Vsig_min and less than the maximum signal voltage Vsig_max, i.e., Vsig_min ≤ V1 ≤ Vsig_max. Each frame includes pixel units with different brightness. When the brightness of the area captured by the pixel is different, the value of the signal voltage is also different. When capturing a brighter area, more electrons are generated in the photodiode PD, and the value of the signal voltage transmitted to the upper plate of the signal voltage sampling capacitor C1 is smaller. When capturing a darker area, fewer electrons are generated in the photodiode PD, and the value of the signal voltage transmitted to the upper plate of the signal voltage sampling capacitor C1 is larger. If a supersaturated bright spot is captured, the signal voltage is the minimum signal voltage Vsig_min, i.e., Vsig = Vsig_min. If a completely dark black spot is captured, the signal voltage is the maximum signal voltage Vsig_max, i.e., Vsig = Vsig_max. That is, the range of the signal voltage of the pixel units in the pixel unit array is Vsig_min ≤ Vsig ≤ Vsig_max. When the range of the first reference voltage V1 is set to Vsig_min ≤ V1 ≤ Vsig_max, the maximum voltage difference between the upper and lower plates of the signal voltage sampling capacitor C1 is Vsig_max - Vsig_min. In some embodiments, the first reference voltage V1 can also be set to the midpoint between the minimum signal voltage Vsig_min and the maximum signal voltage Vsig_max, i.e., V1 = (Vsig_max + Vsig_min) / 2. In a specific embodiment of this application, when Vsig_min = 0.8V and Vsig_max = 1.8V, then 0.8 ≤ V1 ≤ 1.8. And V1 = (Vsig_max + Vsig_min) / 2 = (1.8 + 0.8) / 2 = 1.3V. At this time, Vsig_max - V1 = 0.5V and Vsig_min - V1 = -0.5V, so the voltage difference between the upper and lower plates of the signal voltage sampling capacitor C1 does not exceed 0.5V. Compared to directly grounding the lower plate of the signal voltage sampling capacitor C1, electrically connecting the lower plate of the signal voltage sampling capacitor C1 to the first reference voltage V1 and setting the first reference voltage V1 to (Vsig_max-Vsig_min) / 2 can significantly reduce the difference between the upper and lower plates of the signal voltage sampling capacitor C1, thereby reducing the leakage current between the plates.

[0048] Please see Figure 2As shown, in one embodiment of this application, by electrically connecting the lower plate of the signal voltage sampling capacitor C1 to the first reference voltage V1 and electrically connecting the lower plate of the reset voltage sampling capacitor C2 to the second reference voltage V2, the voltage difference between the upper and lower plates of the signal voltage sampling capacitor C1 and the reset voltage sampling capacitor C2 is reduced, thereby reducing the leakage current between the upper and lower plates. In a specific embodiment of this application, the voltage difference between the upper and lower plates of the reset voltage sampling capacitor C2 is 0, completely eliminating the leakage current between the plates of the reset voltage sampling capacitor C2. The voltage difference between the upper and lower plates of the signal voltage sampling capacitor C1 does not exceed 0.5V, reducing the leakage current between the plates of the signal voltage sampling capacitor C1.

[0049] Please see Figure 2 As shown, in one embodiment of this application, the value of the first reference voltage V1 is a dynamic value. Since the captured image is a dynamic image, the signal voltage on the signal voltage sampling capacitor C1 is a changing value. At this time, the signal voltage of a specific region in the current frame image can be counted, and the median value Vsig_med of the signal voltage of the specific region in the current frame image can be obtained and transmitted to the register as the first reference voltage V1 of the signal voltage sampling capacitor C1 for the next frame.

[0050] Please see Figure 2As shown, in one embodiment of this application, two or more levels of the first reference voltage V1 can be set. When the signal voltage in a specific area of ​​the current frame image is different, different first reference voltages V1 are used during the next frame shooting. In a specific embodiment, for example, two levels of the first reference voltage V1 are set, namely, one-quarter of the maximum signal voltage Vsig_max and three-quarters of the minimum signal voltage Vsig_min, and the sum of three-quarters of the maximum signal voltage Vsig_max and one-quarter of the minimum signal voltage Vsig_min. At this point, the signal voltage in a specific region of the current frame image can be statistically analyzed, and the median value Vsig_med of the signal voltage in that specific region of the current frame image can be obtained. If Vsig_med ≤ (Vsig_max + Vsig_min) / 2, then the first reference voltage V1 of the signal voltage sampling capacitor C1 in the next frame is: V1 = Vsig_min + (Vsig_max - Vsig_min) × 1 / 4 = 3 / 4 × Vsig_min + 1 / 4 × Vsig_max; if Vsig_med > (Vsig_max + Vsig_min) / 2, then the first reference voltage V1 of the signal voltage sampling capacitor C1 in the next frame is: V1 = Vsig_min + (Vsig_max - Vsig_min) × 3 / 4 = 1 / 4 × Vsig_min + 3 / 4 × Vsig_max. Specifically, when the image is brighter, V1 is dynamically set to 3 / 4 × Vsig_min + 1 / 4 × Vsig_max; when the image is darker, V1 is dynamically set to 1 / 4 × Vsig_min + 3 / 4 × Vsig_max. Compared to a statically set value for the first reference voltage V1, dynamically adjusting the first reference voltage V1 based on changes in image brightness results in less parasitic leakage in the video image. Furthermore, compared to adjusting the first reference voltage V1 in real-time based on the median signal voltage of a specific region in the current frame, the process of adjusting the first reference voltage V1 is simplified.

[0051] Please see Figure 3As shown, in another embodiment of this application, the first reference voltage V1 is equal to the second reference voltage V2, and the lower plate of the signal voltage sampling capacitor C1 and the lower plate of the reset voltage sampling capacitor C2 can be electrically connected to the same potential VA. In this application, the values ​​of the first reference voltage V1 and the second reference voltage V2 are, for example, the median of the maximum and minimum values ​​of the maximum signal voltage Vsig_max, the minimum signal voltage Vsig_min, and the reset voltage Vrst. When the minimum signal voltage Vsig_min = 0.8V, the maximum signal voltage Vsig_max = 1.8V, and the reset voltage Vrst = 1.8V, the values ​​of the first reference voltage V1 and the second reference voltage V2 are: V1 = V2 = (1.8V + 0.8V) / 2 = 1.3V. At this time, the difference between the upper and lower plates of the reset voltage sampling capacitor C2 is 0.5V, and the maximum difference between the upper and lower plates of the signal voltage sampling capacitor C1 is 0.5V. This simplifies the pixel structure while reducing leakage current.

[0052] Please see Figure 4 As shown, in one embodiment of this application, the pixel structure further includes a dual-conversion gain (DCG) circuit, which includes a switching transistor M9 and a gain capacitor C0. One end of the gain capacitor C0 is electrically connected to the ungrounded end of the floating diffusion region node capacitor Cfd through the switching transistor M9, and the other end of the gain capacitor C0 is electrically connected to the ground terminal. The gate of the switching transistor M9 is electrically connected to the dual-conversion gain control signal DCG. When the switching transistor M9 is off, the pixel structure is in a high-gain mode, which is suitable for use in low-brightness environments. At this time, the values ​​of the first reference voltage V1 and the second reference voltage V2 can be set according to any of the above methods. That is, the reset voltage is the first reset voltage, and the value of the first reset voltage is... Figure 2 The reset voltages of the pixel structures are equal, i.e., Vrst1 = Vrst = 1.8V. The signal voltage range is Vsig = 0.8~1.8V, so the first reference voltage V1 = 1.3V and the second reference voltage V2 = 1.8V. When the switching transistor M9 responds to the double-conversion gain control signal DCG closing, the gain capacitor C0 is connected in the circuit, and the pixel structure is in low-gain mode, which is suitable for high-brightness environments. At this time, the capacitance of the floating diffusion region is equivalent to the floating diffusion region node capacitance Cfd + the gain capacitor C0. Due to the increased capacitance of the floating diffusion region, the change in capacitive coupling is relatively reduced when the reset transistor M2 is turned off, resulting in a higher reset voltage in low-gain mode. That is, the reset voltage at this time is related to the gain capacitor and each parasitic capacitance. The reset voltage is the second reset voltage, and the second reset voltage is greater than... Figure 2The reset voltage of the pixel structure is set, and the second reset voltage Vrst2 = 2.0V. At this time, the maximum signal voltage Vsig_max also increases to 2.0V. Therefore, in low-gain mode, the first reference voltage V1 = (Vsig_max + Vsig_min) / 2 = (0.8 + 2.0) / 2 = 1.4V, and the second reference voltage V2 = 2.0V can be configured. This reduces parasitic leakage current in both high-gain and low-gain modes of the pixel structure.

[0053] Please see Figure 5 As shown, in one embodiment of this application, corresponding to the dual-conversion gain circuit, the voltage storage circuit includes a first voltage storage circuit 201 and a second voltage storage circuit 202, and the signal reading circuit includes a first signal reading circuit 301 and a second signal reading circuit 302. The first voltage storage circuit 201 and the second voltage storage circuit 202 and... Figure 2 The voltage storage circuit 200 shown has the same structure as the first signal reading circuit 301 and the second signal reading circuit 302. Figure 2 The signal reading circuit 300 shown has the same structure, only the signals controlling each transistor switch are different.

[0054] For details, please refer to Figure 5 As shown, in one embodiment of the present invention, the first voltage storage circuit 201 includes a signal voltage sampling capacitor C1 and a reset voltage sampling capacitor C2. One end of the signal voltage sampling capacitor C1 is electrically connected to the output terminal of the pixel signal generation circuit 100, i.e., the common terminal of the first-stage source follower M3 and the first row selection transistor M4, via a second transmission transistor M5; the other end is connected to a first reference voltage V1. One end of the reset voltage sampling capacitor C2 is electrically connected to the common terminal of the signal voltage sampling capacitor C1 and the second transmission transistor M5 via a third transmission transistor M6; the other end is connected to a second reference voltage V2. The gate of the second transmission transistor M5 is electrically connected to a first control signal S1, and the gate of the third transmission transistor M6 is electrically connected to a second control signal S2. The first signal reading circuit 301 includes a second source follower M7 and a second row selection transistor M8. The second source follower M7 and the second row selection transistor M8 are connected in series, and one end of the second source follower M7 is electrically connected to a second fixed voltage VDD21; one end of the second row selection transistor M8 is a signal output terminal. The gate of the second source follower M7 is electrically connected to the output of the first voltage storage circuit 201, which is the common terminal of the third transmission transistor M6 and the reset voltage sampling capacitor C2. The gate of the second row select transistor M8 receives the second row select signal SEL2. In response to the second row select signal SEL2, the second row select transistor M8 reads out the reset voltage of the upper plate of the reset voltage sampling capacitor C2 and the signal voltage of the signal voltage sampling capacitor C1 during the readout phase.

[0055] Please see Figure 5 As shown, in one embodiment of the present invention, the second voltage storage circuit 202 includes a signal voltage sampling capacitor C3 and a reset voltage sampling capacitor C4. One end of the signal voltage sampling capacitor C3 is electrically connected to the output terminal of the pixel signal generation circuit 100, i.e., the common terminal of the first-stage source follower M3 and the first row selection transistor M4, via a fourth transmission transistor M10; the other end is connected to a third reference voltage V3. One end of the reset voltage sampling capacitor C4 is electrically connected to the common terminal of the signal voltage sampling capacitor C3 and the fourth transmission transistor M10 via a fifth transmission transistor M11; the other end is connected to the fourth reference voltage V4. The gate of the fourth transmission transistor M10 is electrically connected to a third control signal S3, and the gate of the fifth transmission transistor M11 is electrically connected to the fourth control signal S4. The second signal readout circuit 302 includes a third source follower M12 and a third row selection transistor M13. In this circuit, the third source follower M12 and the third row select transistor M13 are connected in series. One end of the third source follower M12 is electrically connected to the second fixed voltage VDD22, and one end of the third row select transistor M13 is the signal output terminal. The gate of the third source follower M12 is electrically connected to the output terminal of the second voltage storage circuit 202, which is the common terminal of the fifth transmission transistor M11 and the reset voltage sampling capacitor C4. The gate of the third row select transistor M13 receives the third row select signal SEL3. In response to the third row select signal SEL3, the third row select transistor M13 reads out the reset voltage of the upper plate of the reset voltage sampling capacitor C4 and the signal voltage of the signal voltage sampling capacitor C3 during the readout phase.

[0056] Please see Figure 5 As shown, in one embodiment of the present invention, the first voltage storage circuit 201 is used to store the reset voltage Vrst_h and the signal voltage Vsig_h in high-gain mode, and the second voltage storage circuit 202 is used to store the reset voltage Vrst_l and the signal voltage Vsig_l in low-gain mode. The reset voltage Vrst_h is stored on the upper plate of the reset voltage sampling capacitor C2, the signal voltage Vsig_h is stored on the upper plate of the signal voltage sampling capacitor C1, the reset voltage Vrst_l is stored on the upper plate of the reset voltage sampling capacitor C4, and the signal voltage Vsig_l is stored on the upper plate of the signal voltage sampling capacitor C3. (Reference) Figure 4 The pixel structure described herein includes the voltage of the lower plate of the capacitor in both high-gain and low-gain modes. A first reference voltage V1, a second reference voltage V2, a third reference voltage V3, and a fourth reference voltage V4 can be set, for example, V2 = 1.8V, V1 = 1.3V, V4 = 2.0V, and V3 = 1.4V, thereby reducing the voltage difference between the upper and lower plates of the four sampling capacitors and achieving lower parasitic leakage current.

[0057] Please see Figure 6As shown, the sampling capacitor provided in this application can be one or a combination of several of the following: MOM (Metal-Oxide-Metal), MIM (Metal-Insulator-Metal), MOS capacitor, etc. When using a MOS capacitor, a linear capacitor can be used, and the implementation method of the linear capacitor is as follows: Figure 6 As shown, the linear capacitor includes a substrate 401, an electrode doped region 402 disposed in the substrate 401, and a gate oxide layer 403 and a gate 404 disposed on the substrate 401. The electrode doped region 402 is formed in a channel between a source doped region 405 and a drain doped region 406, and the type of electrode doped region 402 is the same as that of the source doped region 405 and the drain doped region 406. An isolation structure 407 and another type of doped region 408 are also disposed on one side of the drain doped region 406. Based on a common MOS capacitor, the gate 404 is the upper electrode of the linear capacitor. By performing high-concentration ion implantation on the device channel region below the gate oxide layer 403, the impurity type of the implanted ions is the same as that of the source and drain regions, thereby forming the lower electrode of the MOS capacitor. For example, when the source doped region 405 and the drain doped region 406 are N-type doped, the electrode doped region 402 in the channel is also doped with N-type ions such as phosphorus or arsenic. This type of linear capacitor can maintain a very small change in capacitance value within the range of positive and negative power supply voltages, thereby improving the linearity of the sensitivity response.

[0058] It should be noted that this application does not limit the type of transistor used; it can be a thin-film transistor, a field-effect transistor, or other devices with the same characteristics. Since the source and drain of a transistor can be interchanged under certain conditions, there is no difference in the description of their connection relationship. Only a control signal needs to be applied to the gate to achieve conduction and turn-off.

[0059] In summary, the pixel structure provided by this invention includes a pixel signal generation circuit, a voltage storage circuit, and a signal readout circuit. The photodiode in the pixel signal converts the optical signal into an electrical signal and can temporarily store it in a floating diffusion region, forming a signal voltage. The voltage storage circuit includes a signal voltage sampling capacitor and a reset voltage sampling capacitor to store the signal voltage and reset voltage. Under the control of a row selection signal, the signal readout circuit reads the reset voltage and signal voltage stored in the voltage storage circuit.

[0060] The embodiments of the present invention disclosed above are merely illustrative of the invention. The embodiments do not exhaustively describe all details, nor do they limit the invention to the specific implementations described. Clearly, many modifications and variations can be made based on the content of this specification. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to better understand and utilize the invention. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A pixel structure, characterized in that, At least including: The pixel signal generation circuit generates signal voltage and reset voltage; A voltage storage circuit includes a signal voltage sampling capacitor and a reset voltage sampling capacitor. One end of the signal voltage sampling capacitor is electrically connected to the output terminal of the pixel signal generation circuit through a transmission transistor, and the other end of the signal voltage sampling capacitor is electrically connected to a first reference voltage. One end of the reset voltage sampling capacitor is electrically connected to one end of the signal voltage sampling capacitor through another transmission transistor, and the other end of the reset voltage sampling capacitor is electrically connected to a second reference voltage. The circuit reduces the voltage difference between the upper and lower plates of the signal voltage sampling capacitor and the reset voltage sampling capacitor by adjusting the magnitudes of the first and second reference voltages. The signal reading circuit is electrically connected to the output terminal of the voltage storage circuit.

2. A pixel structure according to claim 1, characterized in that, The first reference voltage is greater than the minimum signal voltage and less than the maximum signal voltage, wherein the minimum signal voltage is the value of the signal voltage when shooting an oversaturated bright spot, and the maximum signal voltage is the value of the signal voltage when shooting a completely dark black spot.

3. A pixel structure according to claim 1, characterized in that, The second reference voltage is equal to the reset voltage.

4. A pixel structure according to claim 1, characterized in that, The first reference voltage includes two settings, wherein the first reference voltage of one setting is equal to the sum of one-quarter of the maximum signal voltage and three-quarters of the minimum signal voltage, and the first reference voltage of the other setting is equal to the sum of three-quarters of the maximum signal voltage and one-quarter of the minimum signal voltage.

5. A pixel structure according to claim 1, characterized in that, The first reference voltage is equal to the second reference voltage, and is also equal to the median of the maximum and minimum values ​​of the maximum signal voltage, the minimum signal voltage, and the reset voltage.

6. A pixel structure according to claim 1, characterized in that, The pixel structure also includes a dual-conversion gain circuit, and the dual-conversion gain circuit includes a gain capacitor. The gain capacitor is electrically connected to the ungrounded end of the floating diffusion region node capacitor in the pixel signal generation circuit through a switching transistor.

7. A pixel structure according to claim 6, characterized in that, The voltage storage circuit includes a first voltage storage circuit and a second voltage storage circuit. The first voltage storage circuit stores the reset voltage and the signal voltage in high-gain mode, and the second voltage storage circuit stores the reset voltage and the signal voltage in low-gain mode.

8. A pixel structure according to claim 1, characterized in that, The signal voltage sampling capacitor and the reset voltage sampling capacitor are linear capacitors.

9. A pixel structure according to claim 8, characterized in that, The linear capacitor includes: Substrate; A gate oxide layer is disposed on the substrate; A gate electrode is disposed on the gate oxide layer and forms the upper plate of the linear capacitor; An electrode doped region is disposed in the substrate covered by the gate oxide layer. The doping type of the electrode doped region is the same as that of the source doped region and the drain doped region, forming the lower electrode of the linear capacitor.

10. An image sensor, characterized in that, Includes the pixel structure as described in any one of claims 1 to 9.

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