Power control circuit, pixel array and image sensor

Abstract

This invention provides a power control circuit, including a transconductance amplifier, a control switch, a drive unit, a sampling capacitor, and a voltage divider unit. The high impedance at the first terminal of the drive unit reduces power supply voltage noise. Furthermore, the control switch and sampling capacitor unit shield the power supply voltage noise at the third terminal of the drive unit, thereby significantly reducing the noise in the power supply voltage at the output of the power control circuit and minimizing the impact of power supply voltage noise on the image. This invention also provides a pixel array and an image sensor.

Description

Technical Field

[0001] This invention relates to the field of image sensor technology, and in particular to a power control circuit, a pixel array, and an image sensor. Background Technology

[0002] CMOS image sensors (CIS) are widely used in imaging fields such as video, surveillance, industrial manufacturing, automotive, and home appliances. With increasing application demands, CIS not only needs to achieve higher resolution, dynamic range, and frame rate within a reasonable power consumption range, but also increasingly higher requirements for image quality, including lower noise at lower illumination levels. When illumination is very low, the exposure and gain of the CIS need to be set very high to render more image details, at which point the noise ratio increases compared to the normal signal. Random line noise in the image is easily displayed at this time, affecting image quality. Line noise originates from pixel power supplies, readout operations of the analog-to-digital converter (ADC), and coupling of common bias signal lines. While layout design can eliminate or reduce parasitic noise on signal lines to reduce noise from common signal line coupling, pixel power supply noise is difficult to completely eliminate through external filtering.

[0003] Therefore, it is necessary to provide a novel power control circuit, pixel array, and image sensor to solve the aforementioned problems in the prior art. Summary of the Invention

[0004] The purpose of this invention is to provide a power control circuit, a pixel array, and an image sensor to reduce the impact of noise in the power supply voltage on the image.

[0005] To achieve the above objectives, the power control circuit of the present invention includes:

[0006] A transconductance amplifier used to output a drive voltage based on a reference voltage and a feedback voltage;

[0007] A control switch, one end of which is connected to the output terminal of the transconductance amplifier;

[0008] The drive unit has a first terminal connected to the power supply voltage and a third terminal connected to the other end of the control switch.

[0009] A sampling capacitor unit, with its first terminal connected to the third terminal of the driving unit and its second terminal grounded; and

[0010] The voltage divider unit has a first terminal connected to the second terminal of the drive unit, serving as the output terminal of the power control circuit. The second terminal is grounded, and the third terminal is connected to the transconductance amplifier. It is used for voltage division and to provide the feedback voltage to the transconductance amplifier.

[0011] The beneficial effects of the power control circuit are as follows: one end of the control switch is connected to the output terminal of the transconductance amplifier; the first end of the driving unit is connected to the power supply voltage; the third end of the driving unit is connected to the other end of the control switch; the first end of the sampling capacitor unit is connected to the third end of the driving unit; the second end of the sampling capacitor unit is grounded; the first end of the voltage divider unit is connected to the second end of the driving unit, serving as the output terminal of the power control circuit; the second end of the voltage divider unit is grounded; and the third end of the voltage divider unit is connected to the transconductance amplifier for voltage division and providing the feedback voltage to the transconductance amplifier. The high impedance of the first end of the driving unit reduces the noise of the power supply voltage. Furthermore, through the control switch and the sampling capacitor unit, the power supply voltage noise at the third end of the driving unit can be shielded, thereby greatly reducing the noise in the power supply voltage at the output terminal of the power control circuit and reducing the impact of the noise in the power supply voltage on the image.

[0012] Optionally, the transconductance amplifier includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor. The source of the first PMOS transistor and the source of the second PMOS transistor can be connected to a power supply voltage. The gate of the first PMOS transistor is connected to the drain of the first PMOS transistor and the gate of the second PMOS transistor. The drain of the first PMOS transistor is connected to the drain of the first NMOS transistor. The gate of the first NMOS transistor is used to receive the reference voltage. The drain of the second PMOS transistor is connected to one end of the control switch and the drain of the second NMOS transistor. The gate of the second NMOS transistor is used to receive the feedback voltage. The source of the first NMOS transistor is connected to the source of the second NMOS transistor.

[0013] Optionally, the transconductance amplifier further includes a current source, one end of which is connected to the source of the first NMOS transistor and the source of the second NMOS transistor, and the other end of which is grounded.

[0014] Optionally, the voltage divider unit includes a first resistor and a second resistor. One end of the first resistor is connected to the second end of the driving unit, and the other end of the first resistor is connected to the other end of the second resistor, serving as the output terminal of the voltage divider unit to output the feedback voltage. The other end of the second resistor is grounded.

[0015] Optionally, the driving unit is an NMOS transistor, with its drain connected to the power supply voltage and its source connected to the other end of the control switch.

[0016] Optionally, the sampling capacitor unit includes a sampling capacitor, one end of which is connected to the second end of the driving unit, and the other end is grounded.

[0017] The present invention also provides a pixel array, comprising:

[0018] At least one pixel unit for outputting a pixel signal after photosensitive processing; and

[0019] The power control circuit is connected to all the pixel units and is used to supply power to all the pixel units.

[0020] The beneficial effect of the pixel array is that, by employing the power control circuit, the impact of noise in the power supply voltage on the image is reduced.

[0021] The present invention also provides an image sensor, comprising:

[0022] The pixel array;

[0023] A decoding driving unit, connected to the pixel array, is used to drive the pixel array;

[0024] The slope generation unit is used to generate slope signals;

[0025] A readout circuit, connected to the ramp generating unit and the pixel array, is used to convert the pixel signal into a digital signal;

[0026] An output signal processing unit, connected to the readout circuit, is used to convert the digital signal into an image and output it; and

[0027] The timing control unit is connected to the decoding drive unit, the ramp generation unit, the readout circuit, and the output signal processing unit, and is used to send clock signals to the decoding drive unit, the ramp generation unit, the readout circuit, and the output signal processing unit.

[0028] The beneficial effect of the image sensor is that it uses a pixel array, which reduces the impact of noise in the power supply voltage on the image. Attached Figure Description

[0029] Figure 1 This is a schematic diagram of the image sensor structure in some embodiments of the present invention;

[0030] Figure 2 This is a circuit diagram of a pixel unit in some embodiments of the present invention;

[0031] Figure 3 This is a timing diagram of the pixel array in some embodiments of the present invention;

[0032] Figure 4 This is a schematic diagram of the power control circuit in some embodiments of the present invention;

[0033] Figure 5 This is a schematic diagram of an image from the prior art;

[0034] Figure 6 These are schematic diagrams of some embodiments of the present invention. Detailed Implementation

[0035] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions in the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without inventive effort are within the scope of protection of this invention. Unless otherwise defined, the technical or scientific terms used herein should have the ordinary meaning understood by those skilled in the art. The terms "comprising" and similar expressions used herein mean that the element or object preceding the word covers the element or object listed following the word and its equivalents, but do not exclude other elements or objects.

[0036] To address the problems existing in the prior art, embodiments of the present invention provide an image sensor. (Refer to...) Figure 1 The image sensor 100 includes a pixel array 101, a readout circuit 102, a decoding drive unit 103, a ramp generation circuit 104, an output signal processing unit 105, and a timing control unit 106.

[0037] Reference Figure 1 The pixel array 101 is used to output pixel signals after photosensitization; the row selection decoding driving unit 103 is connected to the pixel array 101 and is used to drive the pixel array 101; the ramp generation circuit 104 is used to generate ramp signals; the readout circuit 102 is connected to the pixel array 101 and the ramp generation circuit 104 and is used to convert the pixel signals into digital signals; the output signal processing unit 105 is connected to the readout circuit 102 to convert the digital signals into images and output them; the timing control unit 106 is connected to the decoding driving unit 103, the ramp generation circuit 104, the readout circuit 102 and the output signal processing unit 105 and is used to send clock signals to the decoding driving unit 103, the ramp generation circuit 104, the readout circuit 102 and the output signal processing unit. The decoding driving unit 103, the ramp generating circuit 104, the output signal processing unit 105, and the timing control unit 106 are all well-known technologies in the art, and will not be described in detail here.

[0038] In some embodiments, the pixel array includes at least one pixel unit and a power control circuit connected to all the pixel units for supplying power to all the pixel units.

[0039] Figure 2 This is a circuit diagram of a pixel unit in some embodiments of the present invention. (Refer to...) Figure 2 The pixel unit 1011 includes a reset transistor Mrst, an amplifying transistor Msf, a transmission transistor Mtg, a gating transistor Msel, and a photodiode PD. The drain of the reset transistor Mrst is connected to the output terminal of the power control circuit. The source of the reset transistor Mrst is connected to the gate of the amplifying transistor Msf and the drain of the transmission transistor Mtg. The gate of the reset transistor Mrst is used to receive a reset control signal RX. The source of the transmission transistor Mtg is connected to the negative terminal of the photodiode PD. The gate of the transmission transistor Mtg is used to receive a transmission control signal TX. The positive terminal of the photodiode PD is grounded. The drain of the amplifying transistor Msf is connected to the output terminal of the power control circuit. The source of the amplifying transistor Msf is connected to the drain of the gating transistor Msel. The gate of the gating transistor Msel is used to receive a gating control signal SEL. The source of the gating transistor Msel is connected to the readout circuit 102 to send the pixel signal to the readout circuit 102.

[0040] Reference Figure 2 The reset transistor Mrst, the amplification transistor Msf, the transmission transistor Mtg, and the gate transistor Msel are all NMOS transistors.

[0041] Reference Figure 2 The drain of the transmission transistor Mtg is connected to one end of the first connection line 10111, the gate of the transmission transistor Msf is connected to the other end of the first connection line 10111, the source of the reset transistor Mrst is connected to one end of the second connection line 10112, the other end of the second connection line 10112 is connected to the first connection line 10111, and the connection point between the second connection line 10112 and the first connection line 10111 is the floating diffusion region FD.

[0042] Figure 3 This is a timing diagram of the pixel array in some embodiments of the present invention. (Refer to...) Figure 2 and Figure 3 Rst represents the reset phase of the pixel unit 1011, Exp represents the exposure phase of the pixel unit 1011, Read represents the signal reading phase of the pixel unit 1011, SEL represents the gating control signal applied to the gate of the gating transistor Msel, RX represents the reset control signal applied to the gate of the reset transistor Mrst, and TX represents the transmission control signal applied to the gate of the transmission transistor Mtg.

[0043] Reference Figure 2 and Figure 3When the pixel unit 1011 is in the reset phase, the gating control signal SEL remains low, the reset control signal RX remains high, and the transmission control signal TX changes from high to low. When both the reset control signal RX and the transmission control signal TX are high, both the reset transistor Mrst and the transmission transistor Mtg are turned on, and the potential of the floating diffusion region FD is pulled high to the power supply voltage VDD to complete the reset.

[0044] Reference Figure 2 and Figure 3 After both the reset control signal RX and the transmission control signal TX change from high to low, the pixel unit 1011 enters the exposure stage from the reset stage. The gating control signal SEL remains low, the reset control signal RX remains low, and the transmission control signal TX remains low. When both the reset control signal RX and the transmission control signal TX are low, the reset transistor Mrst and the transmission transistor Mtg are both turned off, and the photodiode PD senses light and generates photoelectrons proportional to the light intensity.

[0045] Reference Figure 2 and Figure 3 After the selection control signal SEL changes from low to high, the selection transistor Msel is turned on, and the pixel unit 1011 enters the signal reading stage from the exposure stage. The reset control signal RX first changes from low to high to reset the floating diffusion region FD. At this time, the amplification transistor Msf is controlled by the potential of the floating diffusion region FD, and the source of the selection transistor Msel outputs the first reset potential. Then, the reset control signal RX changes from high to low. The transmission control signal TX changes from low to high, and the photoelectrons in the photodiode PD are transferred to the floating diffusion region FD. At this time, the amplification transistor Msf is controlled by the potential of the floating diffusion region FD, and the source of the selection transistor Msel outputs the second reset potential. Then, the transmission control signal TX changes from high to low.

[0046] In some embodiments, the readout circuit includes at least one readout unit, which includes a comparator and a counter. The counter is connected to the output of the comparator and is used to count the output signal of the comparator to output a digital signal.

[0047] Figure 4 This is a schematic diagram of a power control circuit in some embodiments of the present invention. (Refer to...) Figure 4 The power control circuit includes a transconductance amplifier 10, a control switch S0, a drive unit MQ, a sampling capacitor unit Cs, and a voltage divider unit 30.

[0048] In some embodiments, the transconductance amplifier is used to output a drive voltage based on a reference voltage and a feedback voltage. One end of the control switch is connected to the output terminal of the transconductance amplifier. The first terminal of the drive unit is connected to the power supply voltage, and the third terminal of the drive unit is connected to the other end of the control switch. The first terminal of the sampling capacitor unit is connected to the third terminal of the drive unit, and the second terminal of the sampling capacitor unit is grounded. The first terminal of the voltage divider unit is connected to the second terminal of the drive unit, serving as the output terminal of the power control circuit. The second terminal of the voltage divider unit is grounded, and the third terminal of the voltage divider unit is connected to the transconductance amplifier for voltage division and to provide the feedback voltage to the transconductance amplifier.

[0049] In some embodiments, the driving unit is composed of multiple MOS transistors, and the sampling capacitor unit includes at least one capacitor. When the sampling capacitor unit includes at least two capacitors, all capacitors are connected in series or in parallel to achieve the function of a single capacitor.

[0050] Reference Figure 4 The transconductance amplifier 10 includes a first PMOS transistor P1, a second PMOS transistor P2, a first NMOS transistor N1, and a second NMOS transistor N2. The source of the first PMOS transistor P1 and the source of the second PMOS transistor P2 can be connected to the power supply voltage VDD. The gate of the first PMOS transistor P1 is connected to the drain of the first PMOS transistor P1 and the gate of the second PMOS transistor P2. The drain of the first PMOS transistor P1 is connected to the drain of the first NMOS transistor N1. The gate of the first NMOS transistor N1 is used to receive the reference voltage VREF. The drain of the second PMOS transistor P2 is connected to one end of the control switch S0 and the drain of the second NMOS transistor N2. The source of the first NMOS transistor N1 is connected to the source of the second NMOS transistor N2.

[0051] Reference Figure 4 The transconductance amplifier 10 further includes a current source 20, one end of which is connected to the source of the first NMOS transistor N1 and the source of the second NMOS transistor N2, and the other end of which is grounded.

[0052] Reference Figure 4The driving unit MQ is an NMOS transistor, the sampling capacitor unit includes a sampling capacitor, the other end of the control switch S0 is connected to the gate of the driving unit MQ and one end of the sampling capacitor Cs, the other end of the sampling capacitor Cs is grounded, the drain of the driving unit MQ is connected to the power supply voltage VDD, the voltage divider unit 30 includes a first resistor R1 and a second resistor R2, one end of the first resistor R1 is connected to the source of the driving unit MQ and serves as the output terminal of the power control circuit for outputting the voltage VDD_PIX to power the pixel unit, the other end of the first resistor R1 is connected to the other end of the second resistor R2 and the gate of the second NMOS transistor N2, and the other end of the second resistor R2 is grounded.

[0053] Reference Figure 3 and Figure 4 S0 represents the control signal of the control switch S0. During the reset and exposure phases, the control signal of the control switch S0 is high, the control switch S0 is turned on, the sampling capacitor Cs is charged, and the noise of the power supply voltage VDD will reach the gate of the driving unit MQ through the drain of the second PMOS transistor P2. The source potential of the driving unit MQ will be affected by the noise of the power supply voltage VDD, following the gate potential. However, the drain impedance of the driving unit MQ is very large, and the noise of the power supply voltage VDD is greatly attenuated on the drain-source path of the driving unit MQ. Therefore, the noise at the drain of the driving unit MQ has almost no effect on the potential of the source of the driving unit MQ. Furthermore, the reset and exposure phases are not the readout phase, so the noise at the source of the driving unit MQ has no effect on the final image.

[0054] Reference Figure 3 and Figure 4 During the reading phase, the control signal of the control switch S0 goes low, turning off the control switch S0. The potential maintained by the sampling capacitor Cs continues to drive the driving unit MQ, thus cutting off the influence path of the power supply voltage VDD on the driving unit MQ via the second PMOS transistor P2. Therefore, the noise at the source of the driving unit MQ is already very low, greatly reducing its impact on the final image.

[0055] Figure 5 This is a schematic diagram of an existing technology. Figure 6 These are schematic diagrams illustrating some embodiments of the present invention. (Refer to...) Figure 5 and Figure 6 It is obvious that Figure 6 Compared to Figure 5 Image quality has been significantly improved.

[0056] While embodiments of the present invention have been described in detail above, it will be apparent to those skilled in the art that various modifications and variations can be made to these embodiments. However, it should be understood that such modifications and variations fall within the scope and spirit of the invention as set forth in the claims. Furthermore, the invention described herein may have other embodiments and can be implemented or carried out in various ways.

Claims

1. A power supply control circuit, characterized in that, include: A transconductance amplifier used to output a drive voltage based on a reference voltage and a feedback voltage; A control switch, one end of which is connected to the output terminal of the transconductance amplifier; A driving unit includes a MOSFET; the first terminal of the driving unit is connected to the power supply voltage, and the third terminal is connected to the other terminal of the control switch. A sampling capacitor unit includes a sampling capacitor; the first terminal of the sampling capacitor unit is connected to the third terminal of the driving unit, and the second terminal is grounded; as well as The voltage divider unit has a first terminal connected to the second terminal of the drive unit as the output terminal of the power control circuit, the second terminal grounded, and a third terminal connected to the transconductance amplifier for voltage division and providing the feedback voltage to the transconductance amplifier. The control switch is turned on during the reset and exposure phases; During the reading phase, the control switch is turned off.

2. The power control circuit according to claim 1, characterized in that, The transconductance amplifier includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor. The sources of the first PMOS transistor and the second PMOS transistor are connected to a power supply voltage. The gates of the first PMOS transistor and the drains of the first PMOS transistor and the second PMOS transistor are connected. The drain of the first PMOS transistor is connected to the drain of the first NMOS transistor. The gate of the first NMOS transistor is used to receive the reference voltage. The drain of the second PMOS transistor is connected to one end of the control switch and the drain of the second NMOS transistor. The gate of the second NMOS transistor is used to receive the feedback voltage. The sources of the first NMOS transistor and the second NMOS transistor are connected.

3. The power control circuit according to claim 2, characterized in that, The transconductance amplifier further includes a current source, one end of which is connected to the source of the first NMOS transistor and the source of the second NMOS transistor, and the other end of which is grounded.

4. The power control circuit according to claim 1, characterized in that, The voltage divider unit includes a first resistor and a second resistor. One end of the first resistor is connected to the second end of the driving unit, and the other end of the first resistor is connected to the other end of the second resistor, serving as the output terminal of the voltage divider unit to output the feedback voltage. The other end of the second resistor is grounded.

5. The power control circuit according to claim 1, characterized in that, The driving unit is an NMOS transistor, with its drain connected to the power supply voltage and its source connected to the other end of the control switch.

6. A pixel array, characterized in that, include: At least one pixel unit is used to output a pixel signal after light sensing; as well as The power control circuit as described in any one of claims 1 to 5 is connected to all the pixel units and is used to supply power to all the pixel units.

7. An image sensor, characterized in that, include: The pixel array as described in claim 6; A decoding driving unit, connected to the pixel array, is used to drive the pixel array; The slope generation unit is used to generate slope signals; A readout circuit, connected to the ramp generating unit and the pixel array, is used to convert the pixel signal into a digital signal; An output signal processing unit, connected to the readout circuit, is used to convert the digital signal into an image and output it. as well as The timing control unit is connected to the decoding drive unit, the ramp generation unit, the readout circuit, and the output signal processing unit, and is used to send clock signals to the decoding drive unit, the ramp generation unit, the readout circuit, and the output signal processing unit.

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