Optoelectronic device and optoelectronic integration method

Abstract

An optoelectronic device (200) and an optoelectronic integration method are capable of improving the bandwidth of signal transmission, thereby improving the performance of signal transmission. The optoelectronic device (200) comprises: a printed circuit board (PCB) (201); a first substrate (203) and a second substrate (205) are respectively arranged on the PCB (201); an application specific integrated circuit (ASIC) (202) is arranged on the first substrate (203); an optoelectronic device (204) is arranged on the second substrate (205); and a flexible circuit board (FPC) (206) is arranged, a first end of the FPC (206) is arranged on an upper surface of the first substrate (203) and is electrically connected with the ASIC (202), and a second end of the FPC (206) is arranged above the second substrate (205) and is electrically connected with the optoelectronic device (204).

Description

Technical Field

[0001] This application relates to the field of optical communication, and more specifically, to optoelectronic devices and optoelectronic integration methods in the field of optical communication. Background Technology

[0002] As optical transmission products develop towards higher transmission rates, the market places higher demands on the bandwidth of the packaging interconnects of optoelectronic devices. To ensure the reliable operation of optoelectronic devices, they are typically packaged in hermetically sealed ceramic packages. Therefore, the high-speed signals of optoelectronic devices require the use of flexible printed circuit boards (FPCs) and are connected to application-specific integrated circuits (ASICs) on the PCBs via circuit traces.

[0003] However, since existing optoelectronic devices and ASICs require electrical connections via traces on a PCB, the passive link traversed during signal transmission between the optoelectronic devices and the ASIC is relatively long. This results in significant signal loss and numerous parasitic parameters during transmission, thus limiting the signal transmission bandwidth. Furthermore, due to the significant difference in dielectric constants between the materials of the FPC and ceramic packages, incompatibility in packaging modes often occurs when connecting optoelectronic devices using FPCs, further limiting the signal transmission bandwidth. Summary of the Invention

[0004] The optoelectronic device and optoelectronic integration method provided in this application can improve the bandwidth of signal transmission, thereby improving signal transmission performance.

[0005] In a first aspect, embodiments of this application provide an optoelectronic device, comprising: a PCB, an ASIC, a first substrate, an optoelectronic device, a second substrate, and an FPC. The PCB has the first substrate and the second substrate respectively disposed thereon. The first substrate has the ASIC disposed thereon, and the second substrate has the optoelectronic device disposed thereon. A first end of the FPC is disposed on the upper surface of the first substrate and electrically connected to the ASIC, and a second end of the FPC is disposed above the second substrate and electrically connected to the optoelectronic device.

[0006] Using the optoelectronic device provided in this application embodiment, the ASIC and the optoelectronic device can be electrically connected directly via the circuit traces on the FPC. That is, the signal from the optoelectronic device can be directly transmitted to the ASIC mounted on the PCB via the circuit traces on the FPC, without needing to pass through the PCB. This reduces the length of the passive link traversed by the signal transmission and the number of solder joints, thereby reducing parasitic parameters during signal transmission and lowering signal loss. Therefore, it can increase the signal transmission bandwidth, thereby improving signal transmission performance.

[0007] Optionally, the type of optoelectronic device may include various types, and the embodiments of this application do not limit this.

[0008] In one possible implementation, the optoelectronic device can be an optoelectronic chip, which is a core device for optical communication. For example, the optoelectronic chip can be a module with optoelectronic signal conversion function. In addition, the optoelectronic chip can also have modulation and other functions. For details, please refer to prior art. This application does not make specific limitations in this regard.

[0009] In one possible implementation, the ASIC is disposed on the first substrate, which can be understood as the ASIC being packaged or mounted on the first substrate.

[0010] Optionally, the ASIC can be packaged on the first substrate in various ways, and the embodiments of this application do not limit this.

[0011] In one possible implementation, the ASIC and the first substrate can be soldered together via a first ball grid array (BGA).

[0012] For example, a first pad is provided on the lower surface of the ASIC, and a second pad is provided on the upper surface of the first substrate. The first pad and the second pad are soldered together by a first BGA.

[0013] In one possible implementation, the optoelectronic device is disposed on the second substrate, which can be understood as the optoelectronic device being packaged or mounted on the second substrate.

[0014] Optionally, the second substrate may also be a tube base or a base. In this application embodiment, only the substrate is used as an example for description, but the embodiments of this application are not limited thereto.

[0015] Optionally, the first end of the FPC and the first substrate can be electrically connected in various ways, and this application embodiment does not limit this.

[0016] In one possible implementation, the first end of the FPC is soldered to the first substrate.

[0017] For example, a third pad is provided on the first substrate, and a fourth pad is provided at the first end of the FPC. The third pad and the fourth pad are soldered together.

[0018] Optionally, the first end of the FPC and the first substrate can be bonded using existing PCB or FPC welding processes, such as hot pressing or laser welding processes, using tin-based solder. This application does not limit this aspect.

[0019] In one possible implementation, the optoelectronic device may further include a first conductive line, through which a first end of the FPC is electrically connected to the first substrate.

[0020] For example, a fifth pad is provided on the upper surface of the first substrate, and a sixth pad is provided on the upper surface of the first end of the FPC. The fifth pad and the sixth pad are electrically connected through a first conductive line.

[0021] Optionally, the second end of the FPC and the second substrate can be electrically connected in various ways, and this application embodiment does not limit this.

[0022] In one possible implementation, the optoelectronic device includes a third substrate, with a second end of the FPC disposed on the upper surface of the third substrate and a second substrate disposed on the lower surface of the third substrate. The third substrate is used to electrically connect the FPC and the optoelectronic device, wherein the difference in dielectric constant between the material of the third substrate and the material of the FPC is less than a preset dielectric constant threshold.

[0023] In other words, the material of the third substrate is similar to or the same as the material of the FPC.

[0024] For example, the upper surface of the third substrate is soldered to the second end of the FPC, and the lower surface of the third substrate is soldered to the upper surface of the second substrate via a second BGA, wherein the upper surface of the third substrate and the lower surface of the third substrate are electrically connected through at least one via.

[0025] It should be noted that vias are also called metallized holes. In double-sided and multilayer substrates, a common hole, i.e., a via, is drilled at the intersection of the printed conductors that need to be connected between the layers to connect the printed conductors.

[0026] It should be noted that, in the existing technology, the FPC and the ceramic second substrate are packaged using a PCB / FPC process. The dielectric constants of the FPC and the ceramic second substrate are quite different. When the FPC is connected to optoelectronic devices, there is usually a mismatch in the packaging mode, which limits the bandwidth of signal transmission.

[0027] In this embodiment, the FPC and the third substrate are made of similar or identical materials, which avoids the bandwidth limitation problem caused by material differences between the FPC and the third substrate. Furthermore, since the third substrate and the second substrate are in inter-substrate packaging, higher precision packaging processes, such as solder ball flip chip or copper pillar flip chip, can be used to absorb assembly tolerances between different materials, thereby avoiding the bandwidth limitation problem caused by material differences between the third substrate and the second substrate. Therefore, electrically connecting the FPC and the second substrate through the third substrate can improve the signal transmission bandwidth.

[0028] In one possible implementation, the optoelectronic device may further include a second conductive line, through which a second end of the FPC is electrically connected to the second substrate.

[0029] Using the optoelectronic device provided in this application, the FPC and the second substrate are connected by the second conductive line, which eliminates the need for a welding process and avoids the bandwidth limitation of signal transmission caused by material differences between the two in the prior art.

[0030] It should be noted that the connection methods between the first end of the FPC and the substrate, and the connection methods between the second end of the FPC and the second substrate provided above, can be combined arbitrarily, and the embodiments of this application do not limit this.

[0031] For example, the optoelectronic device may also include a third conductive line and a fourth conductive line, with the first end of the FPC connected to the substrate through the third conductive line and the second end of the FPC connected to the second substrate through the fourth conductive line.

[0032] Secondly, embodiments of this application also provide an optoelectronic integration method, comprising:

[0033] Step 1: Mount the ASIC on the first substrate.

[0034] Step 2: Mount the optoelectronic device on the second substrate.

[0035] Step 3: Mount the first substrate and the second substrate onto the PCB.

[0036] Step 4: The first end of the FPC is disposed on the first substrate and electrically connected to the ASIC on the first substrate.

[0037] Step 5: Deposit the second end of the FPC onto the second substrate and electrically connect it to the optoelectronic device on the second substrate.

[0038] Thirdly, embodiments of this application also provide another optoelectronic device, including: a PCB, an ASIC, a first substrate, an optoelectronic device, a second substrate, an FPC, and a third substrate. The PCB has the first substrate and the second substrate respectively disposed thereon; the first substrate has an application-specific integrated circuit (ASIC) disposed thereon; the second substrate has an optoelectronic device disposed thereon; a first end of the FPC is disposed on the upper surface of the PCB and electrically connected to the ASIC disposed on the first substrate; a first end of a conductive line is disposed on the second end of the FPC; the second end of the conductive line is disposed on the upper surface of the second substrate; the conductive line is used to electrically connect the FPC and the optoelectronic device.

[0039] In other words, the optoelectronic device is connected to the FPC via the third substrate, and is electrically connected to the ASIC via circuit traces on the PCB through the FPC. The material of the third substrate is similar to or the same as that of the FPC. This avoids the bandwidth limitation problem caused by material differences between the FPC and the second substrate.

[0040] In one possible implementation, the upper surface of the third substrate is electrically connected to the second end of the FPC, the lower surface of the third substrate is electrically connected to the upper surface of the second substrate, and the upper surface of the third substrate and the lower surface of the third substrate are electrically connected through at least one via.

[0041] In one possible implementation, the upper surface of the third substrate is welded to the second end of the FPC.

[0042] In one possible implementation, the lower surface of the third substrate and the upper surface of the second substrate are soldered together by a first ball grid array (BGA).

[0043] In one possible implementation, the FPC is made of an organic material, and the second substrate is made of ceramic.

[0044] It should be noted that the various parts of the optoelectronic device provided in the third aspect and the connection methods between the parts can be referred to the corresponding description in the first aspect. To avoid repetition, they will not be repeated here.

[0045] Fourthly, embodiments of this application also provide another optoelectronic integration method, including:

[0046] Step 1: Mount the ASIC on the first substrate;

[0047] Step 2: Mount the optoelectronic device on the second substrate;

[0048] Step 3: Mount the first substrate and the second substrate onto the PCB;

[0049] Step 4: The first end of the FPC is disposed on the upper surface of the PCB and electrically connected to the ASIC disposed on the first substrate;

[0050] Step 5: Electrically connect the upper surface of the third substrate to the second end of the FPC, wherein the difference in dielectric constant between the material of the third substrate and the material of the FPC is less than a preset dielectric constant threshold.

[0051] Step 6: Electrically connect the lower surface of the third substrate to the upper surface of the second substrate;

[0052] Step 7: Drill at least one via between the upper surface and the lower surface of the third substrate.

[0053] Fifthly, embodiments of this application also provide another optoelectronic device, including: a PCB, an ASIC, a first substrate, an optoelectronic device, a second substrate, an FPC, and a fifth conductive line. The first substrate and the second substrate are respectively disposed on the PCB. The ASIC is disposed on the first substrate, and the optoelectronic device is disposed in the second substrate. A first end of the FPC is disposed on the upper surface of the PCB and electrically connected to the ASIC disposed on the first substrate. A first end of the fifth conductive line is disposed on the second end of the FPC, and a second end of the fifth conductive line is disposed on the upper surface of the second substrate. The fifth conductive line is used to electrically connect the FPC and the optoelectronic device.

[0054] In other words, the optoelectronic device is connected to the FPC via the fifth conductive line, and the FPC is electrically connected to the ASIC via circuit traces on the PCB. This avoids the bandwidth limitation problem caused by material differences between the FPC and the second substrate.

[0055] In one possible implementation, the FPC is made of an organic material, and the second substrate is made of ceramic.

[0056] It should be noted that the various parts of the optoelectronic device provided in the fifth aspect and the connection methods between the parts can be referred to the corresponding description in the first aspect. To avoid repetition, they will not be repeated here.

[0057] Sixthly, embodiments of this application also provide another optoelectronic integration method, including:

[0058] Step 1: Mount the ASIC on the first substrate;

[0059] Step 2: Mount the optoelectronic device on the second substrate;

[0060] Step 3: Mount the first substrate and the second substrate onto the PCB;

[0061] Step 4: The first end of the FPC is disposed on the upper surface of the PCB and electrically connected to the ASIC disposed on the first substrate;

[0062] Step 5: Place the first end of the conductive wire at the second end of the FPC and electrically connect it to the FPC;

[0063] Step 6: The second end of the conductive wire is disposed on the upper surface of the second substrate and electrically connected to the optoelectronic device disposed on the second substrate. Attached Figure Description

[0064] Figure 1 A schematic structural diagram of the optoelectronic device 100 according to an embodiment of this application is provided;

[0065] Figure 2 A schematic structural diagram of the optoelectronic device 200 according to an embodiment of this application is provided;

[0066] Figure 3 A top view is provided showing the connection diagram (for the ASIC and the first substrate according to an embodiment of this application.)

[0067] Figure 4 A schematic diagram (side view) showing the connection between the ASIC and the first substrate according to an embodiment of this application is provided;

[0068] Figure 5 A schematic structural diagram of the optoelectronic device 300 according to an embodiment of this application is provided;

[0069] Figure 6 A top view is provided showing the connection diagram (top view) between the first substrate and the FPC according to an embodiment of this application;

[0070] Figure 7 A schematic diagram (side view) showing the connection between the first substrate and the FPC according to an embodiment of this application is provided;

[0071] Figure 8 A schematic structural diagram of the optoelectronic device 400 according to an embodiment of this application is provided;

[0072] Figure 9 Another schematic diagram (top view) showing the connection between the first substrate and the FPC according to an embodiment of this application is provided;

[0073] Figure 10 Another schematic diagram (side view) showing the connection between the first substrate and the FPC according to an embodiment of this application is provided;

[0074] Figure 11 A schematic structural diagram of the optoelectronic device 500 according to an embodiment of this application is provided;

[0075] Figure 12 Another schematic structural diagram of the optoelectronic device 500 according to an embodiment of this application is provided;

[0076] Figure 13 A schematic structural diagram of the optoelectronic device 600 according to an embodiment of this application is provided;

[0077] Figure 14 A schematic structural diagram of the optoelectronic device 700 according to an embodiment of this application is provided;

[0078] Figure 15 A schematic structural diagram of the optoelectronic device 800 according to an embodiment of this application is provided;

[0079] Figure 16 A schematic structural diagram of an optoelectronic device 900 according to an embodiment of this application is provided. Detailed Implementation

[0080] The technical solutions in this application will now be described with reference to the accompanying drawings.

[0081] Figure 1 A schematic structural diagram (side view) of a prior art optoelectronic device 100 is shown. For example... Figure 1 As shown, the optoelectronic device 100 includes a PCB 101, an ASIC 102, a first substrate 103, an optoelectronic device 104, a second substrate 105, and an FPC 106. The first substrate 103 and the second substrate 105 are respectively disposed on the PCB 101. The ASIC 102 is disposed on the first substrate 103, and the optoelectronic device 104 is disposed on the second substrate 105. A first end of the FPC 106 is disposed on the upper surface of the second substrate 105 and electrically connected to the optoelectronic device 104. A second end of the FPC 106 is disposed on the upper surface of the PCB 101 and electrically connected to the ASIC 102.

[0082] However, in the existing optoelectronic device 100, the ASIC 102 is electrically connected to the optoelectronic device 104 via the PCB 101 and the FPC 106. That is, the signal from the optoelectronic device 104 needs to utilize the FPC 106 and be transmitted to the ASIC 102 mounted on the PCB 101 via circuit traces. Because the passive link traversed during signal transmission between the optoelectronic device 104 and the ASIC 102 is relatively long and involves many solder joints, this results in significant signal loss and numerous parasitic parameters during transmission. Consequently, the bandwidth of the signal transmission may also be limited.

[0083] Furthermore, in the existing optoelectronic device 100, the pads of the FPC 106 and the pads of the second substrate 105 are soldered together. Since the FPC 106 is usually made of organic materials and the second substrate 105 is usually made of ceramic materials, the dielectric constants of these two materials are quite different. When the FPC 106 is connected to optoelectronic devices, there is usually a mismatch in the packaging mode. Therefore, the bandwidth of signal transmission may also be limited.

[0084] In summary, the existing optoelectronic device 100 has a low signal transmission bandwidth, resulting in poor signal transmission performance.

[0085] In view of the problems existing in the aforementioned optoelectronic device 100, Figure 2 A schematic structural diagram (side view) of the optoelectronic device 200 provided in an embodiment of this application is shown.

[0086] like Figure 2 As shown, the optoelectronic device 200 includes a PCB 201, an ASIC 202, a first substrate 203, an optoelectronic device 204, a second substrate 205, and an FPC 206. The first substrate 203 and the second substrate 205 are respectively disposed on the PCB 201. The ASIC 202 is disposed on the first substrate 203, and the optoelectronic device 204 is disposed on the second substrate 205. The first end of the FPC 206 is disposed on the upper surface of the first substrate 203 and electrically connected to the ASIC 202, and the second end of the FPC 206 is disposed above the second substrate 205 and electrically connected to the optoelectronic device 204.

[0087] Using the optoelectronic device 200 provided in this application embodiment, the ASIC 202 and the optoelectronic device 204 can be electrically connected directly using the circuit traces on the FPC 206. That is, the signal from the optoelectronic device 204 can be directly transmitted to the ASIC 202 on the PCB 201 via the circuit traces on the FPC 206, without needing to pass through the PCB 201. This reduces the length of the passive link and the number of solder joints traversed by the signal transmission, thereby reducing parasitic parameters during signal transmission and lowering signal loss. Therefore, it increases the bandwidth of signal transmission, thus improving signal transmission performance.

[0088] It should be noted that PCB refers to Printed Circuit Board, also known as rigid circuit board. PCB is the support for electronic components or the carrier for the electrical connections of electronic components.

[0089] It should also be noted that FPC refers to Flexible Printed Circuit Board. FPC is a highly reliable, flexible printed circuit made from flexible insulating substrates such as polyimide or polyester film. It features high wiring density, light weight, thinness, and good bendability. FPC is mainly used in electronic products. Because all circuitry is mounted on the FPC, it eliminates the need for redundant wiring connections, improves flexibility, and allows for better assembly tolerances. Furthermore, FPC can absorb assembly tolerances and enhance three-dimensional assembly within a limited space, thus reducing product size.

[0090] Optionally, the type of the optoelectronic device 204 may include various types, and this application embodiment does not limit this.

[0091] In one possible implementation, the optoelectronic device 204 can be an optoelectronic chip, which is a core device for optical communication. For example, the optoelectronic chip can be a module with optoelectronic signal conversion function. In addition, the optoelectronic chip can also have modulation and other functions. For details, please refer to the prior art. This application does not make specific limitations in this regard.

[0092] In one possible implementation, the ASIC 202 is disposed on the first substrate 203, which can be understood as the ASIC 202 being packaged or mounted on the first substrate 203.

[0093] Optionally, the ASIC 202 can be mounted on the first substrate 203 in various ways, and this application embodiment does not limit this.

[0094] In one possible implementation, such as Figure 2 As shown, the ASIC 202 and the first substrate 203 can be soldered together by the first ball grid array (BGA) 207.

[0095] For example: Figure 3 (Top view) and Figure 4 (Side view) shows a schematic diagram of the connection between the AIC202 and the first substrate 203, as follows: Figure 3 and Figure 4 As shown, a first pad 208 is provided on the lower surface of the ASIC 202, and a second pad 209 is provided on the upper surface of the first substrate 203. The first pad 208 and the second pad 209 are soldered together by a first BGA 207.

[0096] In one possible implementation, the optoelectronic device 204 is disposed on the second substrate 205, which can be understood as the optoelectronic device 204 being packaged or mounted on the second substrate 205.

[0097] It should be noted that the mounting method of the optoelectronic device 204 on the second substrate 205 can be referred to as follows: Figure 3 and Figure 4 The mounting method of the ASIC202 on the first substrate 203 described herein will not be repeated here to avoid repetition.

[0098] Optionally, the second substrate 205 may also be a tube base or a base. This application embodiment only uses a substrate as an example for description, but the embodiments of this application are not limited thereto.

[0099] Optionally, the first end of the FPC and the first substrate can be electrically connected in various ways, and this application embodiment does not limit this.

[0100] The following will combine Figures 5 to 7 This paper introduces one possible electrical connection method between the first end of the FPC and the first substrate. It should be noted that... Figure 5 For details not covered in the text, please refer to [the relevant source]. Figure 2 To avoid repetition, the relevant sections will not be repeated here.

[0101] Figure 5 A schematic structural diagram (side view) of the optoelectronic device 300 provided in an embodiment of this application is shown, such as... Figure 5 As shown, the first end of the FPC306 is soldered to the first substrate 303.

[0102] For example: Figure 6 (Top view) and Figure 7 (Side view) shows a schematic diagram of the connection between the first end of FPC306 and the first substrate 303, as follows: Figure 6 and Figure 7 As shown, a third pad 308 is provided on the upper surface of the first substrate 303, and a fourth pad 309 is provided on the lower surface of the first end of the FPC 306. The third pad 308 and the fourth pad 309 are soldered together.

[0103] Optionally, the first end of the FPC306 and the first substrate 303 can be connected using existing PCB or FPC welding processes, such as hot pressing or laser welding processes, and welding can be achieved using tin-based solder. This application embodiment does not limit this.

[0104] The following will combine Figures 8 to 10 This section introduces another possible electrical connection method between the first end of the FPC and the first substrate. It should be noted that... Figure 8 For details not covered in the text, please refer to [the relevant source]. Figure 2 To avoid repetition, the relevant sections will not be repeated here.

[0105] Figure 8A schematic structural diagram (side view) of the optoelectronic device 400 provided in an embodiment of this application is shown, such as... Figure 8 As shown, the optoelectronic device 400 also includes a first conductive line 407, and the first end of the FPC 406 is electrically connected to the first substrate 403 through the first conductive line 407.

[0106] For example: Figure 9 (Top view) and Figure 10 (Side view) shows a schematic diagram of the connection between the first end of FPC406 and the first substrate 403, as follows: Figure 9 and Figure 10 As shown, a fifth pad 408 is provided on the upper surface of the first substrate 403, and a sixth pad 409 is provided on the upper surface of the first end of the FPC 406. The fifth pad 408 and the sixth pad 409 are electrically connected through a first conductive line 407.

[0107] Optionally, the second end of the FPC and the second substrate can be electrically connected in various ways, and this application embodiment does not limit this.

[0108] The following will combine Figure 11 and Figure 12 This paper introduces one possible electrical connection method between the second end of the FPC and the second substrate. It should be noted that... Figure 11 and Figure 12 For details not covered in the text, please refer to [the relevant source]. Figure 2 , Figure 5 and / or Figure 8 To avoid repetition, the relevant sections will not be repeated here.

[0109] Figure 11 A schematic structural diagram (side view) of the optoelectronic device 500 provided in an embodiment of this application is shown, such as... Figure 11 As shown, the optoelectronic device 500 includes a third substrate 507, the second end of the FPC 506 is disposed on the upper surface of the third substrate 507, and the second substrate 505 is disposed on the lower surface of the third substrate 507. The third substrate 507 is used to electrically connect the FPC 506 and the optoelectronic device 504, wherein the difference in dielectric constant between the material of the third substrate 507 and the material of the FPC 506 is less than a preset dielectric constant threshold.

[0110] In other words, the material of the third substrate 507 is similar to or the same as the material of the FPC 506.

[0111] For example: Figure 12As shown, the upper surface of the third substrate 507 is soldered to the lower surface of the second end of the FPC 506, and the lower surface of the third substrate 507 is soldered to the upper surface of the second substrate 505 through a second BGA 508. The upper surface of the third substrate 507 and the lower surface of the third substrate 507 are electrically connected through at least one via 509.

[0112] It should be noted that vias are also called metallized holes. In double-sided and multilayer substrates, a common hole, i.e., a via, is drilled at the intersection of the printed conductors that need to be connected between the layers to connect the printed conductors.

[0113] It should also be noted that the connection method between the upper surface of the third substrate 507 and the lower surface of the second end of the FPC 506 can be referred to Figure 6 and Figure 7 The lower surface of the first end of the FPC306 described herein is connected to the upper surface of the first substrate 303. The lower surface of the third substrate 507 is connected to the upper surface of the second substrate 505 via the second BGA 508, as can be seen in the following example. Figure 3 and Figure 4 The connection method between the ASIC 202 and the first substrate 203 via the first BGA 207, as described above, will not be repeated here to avoid repetition.

[0114] It should be noted that, in the existing technology, the FPC and the ceramic second substrate are packaged using a PCB / FPC process. The dielectric constants of the FPC and the ceramic second substrate are quite different. When the FPC is connected to optoelectronic devices, there is usually a mismatch in the packaging mode, which limits the bandwidth of signal transmission.

[0115] In this embodiment, the FPC 506 and the third substrate 507 are made of similar or identical materials, which avoids the bandwidth limitation of signal transmission caused by material differences between the FPC 506 and the third substrate 507. Furthermore, since the third substrate 507 and the second substrate 505 are in inter-substrate packaging, higher precision packaging processes, such as solder ball flip chip or copper pillar flip chip, can be used to absorb assembly tolerances between different materials, thereby avoiding the bandwidth limitation of signal transmission caused by material differences between the third substrate 507 and the second substrate 505. Therefore, electrically connecting the FPC 506 and the second substrate 505 through the third substrate 507 improves the signal transmission bandwidth.

[0116] The following will combine Figure 13This section introduces another possible electrical connection method between the second end of the FPC and the second substrate. It should be noted that... Figure 13 For details not covered in the text, please refer to [the relevant source]. Figure 2 , Figure 5 and / or Figure 8 To avoid repetition, the relevant sections will not be repeated here.

[0117] Figure 13 A schematic structural diagram (side view) of the optoelectronic device 600 provided in an embodiment of this application is shown, such as... Figure 13 As shown, the optoelectronic device 600 includes a second conductive line 607, and the second end of the FPC 606 is electrically connected to the second substrate 605 through the second conductive line 607.

[0118] It should be noted that the second end of the FPC606 is connected to the second substrate 605 via the second conductive line 607, which can be referred to as... Figure 9 and Figure 10 The connection between the first end of the FPC406 and the first substrate 403 via the first conductive line 407, as described above, will not be repeated here to avoid repetition.

[0119] Using the optoelectronic device 600 provided in this application, the FPC 606 and the second substrate 605 are connected by the second conductive line 607, which means that there is no need to connect them through a welding process, thus avoiding the problem of limited signal transmission bandwidth caused by material differences between the two in the prior art.

[0120] It should be noted that the connection methods between the first end of the FPC and the substrate, and the connection methods between the second end of the FPC and the second substrate provided above, can be combined arbitrarily, and the embodiments of this application do not limit this.

[0121] For example: Figure 14 A schematic structural diagram (side view) of the optoelectronic device 700 provided in an embodiment of this application is shown, such as... Figure 14 As shown, the optoelectronic device 700 also includes a third conductive line 707 and a fourth conductive line 708. The first end of the FPC 706 is connected to the substrate 703 through the third conductive line 707, and the second end of the FPC 706 is connected to the second substrate 705 through the fourth conductive line 708.

[0122] It should be noted that the way the first end of the FPC706 is connected to the substrate 703 via the third conductive line 707, and the way the second end of the FPC706 is connected to the second substrate 705 via the fourth conductive line 708, can be referred to Figure 9 and Figure 10The connection between the first end of the FPC406 and the first substrate 403 via the first wire 407, as described above, will not be repeated here to avoid repetition.

[0123] It should also be noted that, Figure 14 For details not covered in the text, please refer to [the relevant source]. Figure 2 To avoid repetition, the relevant sections will not be repeated here.

[0124] Figure 15 A schematic structural diagram (side view) of the optoelectronic device 800 provided in an embodiment of this application is shown, such as... Figure 15 As shown, the optoelectronic device 800 includes a PCB 801, an ASIC 802, a first substrate 803, an optoelectronic device 804, a second substrate 805, an FPC 806, and a third substrate 807. The first substrate 803 and the second substrate 805 are respectively disposed on the PCB 801. The ASIC 802 is disposed on the first substrate 803. The first end of the FPC 806 is disposed on the upper surface of the PCB 801 and electrically connected to the ASIC 802 disposed on the first substrate 803. The second end of the FPC 806 is disposed on the upper surface of the third substrate 807. The second substrate 805 is disposed on the lower surface of the third substrate 807. The third substrate 807 is used to electrically connect the FPC 806 and the optoelectronic device 804. The difference in dielectric constant between the materials of the third substrate 807 and the FPC 806 is less than a preset dielectric constant threshold.

[0125] In other words, the optoelectronic device 804 is connected to the FPC 806 via the third substrate 807, and is electrically connected to the ASIC 802 via circuit traces on the PCB 801 through the FPC 806. The material of the third substrate 807 is similar to or the same as the material of the FPC 806. This avoids the bandwidth limitation problem caused by material differences between the FPC 806 and the second substrate 804.

[0126] It should be noted that the various parts of the optoelectronic device 800 and the connection methods between them can be referred to the corresponding descriptions above. To avoid repetition, they will not be repeated here.

[0127] Optionally, Figure 16 A schematic structural diagram (side view) of the optoelectronic device 900 provided in an embodiment of this application is shown, such as... Figure 16As shown, the optoelectronic device 900 includes a PCB 901, an ASIC 902, a first substrate 903, an optoelectronic device 904, a second substrate 905, an FPC 906, and a fifth conductive line 907. The first substrate 903 and the second substrate 905 are respectively disposed on the PCB 901. The ASIC 902 is disposed on the first substrate 903. The first end of the FPC 906 is disposed on the upper surface of the PCB 901 and electrically connected to the ASIC 902 disposed on the first substrate 903. The first end of the fifth conductive line 907 is disposed on the second end of the FPC 906, and the second end of the fifth conductive line 907 is disposed on the upper surface of the second substrate 905. The fifth conductive line 907 is used to electrically connect the FPC 906 and the optoelectronic device 904.

[0128] In other words, the optoelectronic device 904 is connected to the FPC 906 via the fifth conductive line 907, and is electrically connected to the ASIC 902 via the circuit traces on the PCB 901 through the FPC 906. This avoids the bandwidth limitation problem of signal transmission caused by material differences between the FPC 906 and the second substrate 904.

[0129] The above combination Figures 2 to 16 The optoelectronic device provided in the embodiments of this application has been introduced. The optoelectronic integration method provided in the embodiments of this application will be described below in conjunction with the following steps 1 to 4.

[0130] Step 1: Mount the ASIC on the first substrate.

[0131] Step 2: Mount the optoelectronic device on the second substrate.

[0132] Step 3: Mount the first substrate and the second substrate onto the PCB.

[0133] Step 4: The first end of the FPC is disposed on the first substrate and electrically connected to the ASIC on the first substrate.

[0134] Step 5: Deposit the second end of the FPC onto the second substrate and electrically connect it to the optoelectronic device on the second substrate.

[0135] It should be noted that the implementation process of steps 4 and 5 can be referred to the description of the corresponding parts in the above device embodiments.

[0136] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A photoelectric device, characterized in that, include: Printed circuit board (PCB); The PCB is provided with a first substrate and a second substrate respectively; An application-specific integrated circuit (ASIC) is disposed on the first substrate; The second substrate is encapsulated with optoelectronic devices; A flexible printed circuit board (FPC) has a first end disposed on the upper surface of the first substrate and electrically connected to the ASIC, and a second end disposed above the second substrate and electrically connected to the optoelectronic device. The third substrate has the second end of the FPC disposed on the upper surface of the third substrate and the second substrate disposed on the lower surface of the third substrate. The third substrate is used to electrically connect the FPC and the optoelectronic device. The material of the third substrate is the same as that of the FPC. The upper surface of the third substrate is electrically connected to the second end of the FPC, the lower surface of the third substrate is electrically connected to the upper surface of the second substrate, and the upper surface of the third substrate and the lower surface of the third substrate are electrically connected through at least one via. The FPC is made of organic materials, and the second substrate is made of ceramic.

2. The photoelectric device according to claim 1, characterized in that, The upper surface of the third substrate is welded to the second end of the FPC.

3. The photoelectric device according to claim 1 or 2, characterized in that, The lower surface of the third substrate and the upper surface of the second substrate are soldered together by a first ball grid array (BGA).

4. The photoelectric device according to any one of claims 1 to 3, characterized in that, The first end of the FPC is welded to the upper surface of the first substrate.

5. The photoelectric device according to any one of claims 1 to 3, characterized in that, The optoelectronic device further includes a second conductive line for electrically connecting the first end of the FPC and the first substrate.

6. A photoelectric device, characterized in that, include: Printed circuit board (PCB); The PCB is provided with a first substrate and a second substrate respectively; An application-specific integrated circuit (ASIC) is disposed on the first substrate; The second substrate is encapsulated with optoelectronic devices; Flexible printed circuit board (FPC) and third substrate; The first end of the FPC is disposed on the upper surface of the PCB and is electrically connected to the ASIC disposed on the first substrate. The second end of the FPC is disposed on the upper surface of the third substrate. The second substrate is disposed on the lower surface of the third substrate. The third substrate is used to electrically connect the FPC and the optoelectronic device. The material of the third substrate is the same as that of the FPC; The upper surface of the third substrate is electrically connected to the second end of the FPC, the lower surface of the third substrate is electrically connected to the upper surface of the second substrate, and the upper surface of the third substrate and the lower surface of the third substrate are electrically connected through at least one via. The FPC is made of organic materials; The material of the second substrate is ceramic.

7. The photoelectric device according to claim 6, characterized in that, The upper surface of the third substrate is welded to the second end of the FPC.

8. The photoelectric device according to claim 6 or 7, characterized in that, The lower surface of the third substrate and the upper surface of the second substrate are soldered together by a first ball grid array (BGA).

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