Array substrate and display device

Abstract

An array substrate and a display device. The array substrate comprises a substrate, a plurality of first pixel driving circuits, a plurality of first data lines and a plurality of first lead lines; the substrate comprises a display area and a binding area located at the periphery of the display area; the display area comprises a first area and a second area located at one side of the first area, the plurality of first pixel driving circuits are located in the second area, the plurality of first pixel driving circuits are arranged in an array along a first direction and a second direction to form a plurality of first pixel driving columns arranged along the first direction, the first area and the second area are arranged in the first direction, the plurality of first data lines are configured to provide data signals to the plurality of first pixel driving columns, and the plurality of first lead lines are respectively connected with the plurality of first data lines, and extend from the second area to the binding area through the first area. Thus, the array substrate can realize an ultra-narrow frame design.

Description

Technical Field

[0001] Embodiments of this disclosure relate to an array substrate and a display device. Background Technology

[0002] With the continuous development of display technology, people have increasingly higher requirements for the display quality of display devices. Due to its advantages such as wide color gamut, fast response speed, flexible display, bendability, and high contrast, organic light-emitting diode (OLED) display devices are being used more and more widely.

[0003] On the other hand, people have increasingly higher expectations for the overall performance and display quality of organic light-emitting diode (OLED) display devices. Narrow bezel and rounded corner designs can significantly improve the overall performance and display quality of display devices, and therefore have gradually become the development direction of the market and the research hotspot of major manufacturers. Summary of the Invention

[0004] This disclosure provides an array substrate and a display device. In the array substrate, multiple first leads pass through a second region, through a first region, and extend to a bonding region, instead of extending directly from the second region to the bonding region. This eliminates the need for a wide bezel outside the second region, thereby enabling an ultra-narrow bezel design.

[0005] At least one embodiment of this disclosure provides an array substrate, comprising: a substrate including a display area and a bonding area surrounding the display area; a plurality of first pixel driving circuits located on the substrate; a plurality of first data lines; and a plurality of first leads, wherein the display area includes a first region and a second region located on one side of the first region, the plurality of first pixel driving circuits are located in the second region, the plurality of first pixel driving circuits are arrayed along a first direction and a second direction to form a plurality of first pixel driving columns arranged along the first direction, the first region and the second region are arranged in the first direction, the plurality of first data lines are configured to provide data signals to the plurality of first pixel driving columns, and the plurality of first leads are respectively connected to the plurality of first data lines, passing through the first region from the second region and extending to the bonding area.

[0006] For example, in an embodiment of the present disclosure, the first pixel driving circuit includes a driving transistor, and the array substrate further includes a light-shielding structure located on the side of the plurality of first pixel driving circuits close to the substrate. The orthographic projection of the driving transistor of the first pixel driving circuit on the substrate and the orthographic projection of the light-shielding structure on the substrate at least partially overlap, and the plurality of first leads are disposed in the same layer as the light-shielding structure.

[0007] For example, in an embodiment of the present disclosure, the array substrate includes a channel region, the orthographic projection of the channel region on the substrate falls entirely within the range of the orthographic projection of the light-shielding structure on the substrate, and each of the first leads is spaced apart from and insulated from the light-shielding structure.

[0008] For example, an embodiment of the present disclosure provides an array substrate that further includes: a first conductive layer located on the side of the plurality of first pixel driving circuits away from the substrate; and a first via connection structure, wherein the plurality of first data lines are located on the first conductive layer, and each first lead is connected to the corresponding first data line through the first via connection structure.

[0009] For example, an embodiment of the present disclosure provides an array substrate that further includes: a first conductive layer located on the side of the plurality of first pixel driving circuits away from the substrate; a first planarization layer located on the side of the first conductive layer away from the substrate; a second conductive layer located on the side of the first planarization layer away from the substrate; a second via connection structure; and a third via connection structure located in the first planarization layer. The plurality of first data lines are located in the second conductive layer. The first conductive layer includes a connection electrode. Each first lead is connected to the connection electrode through the second via connection structure. The connection electrode is connected to the corresponding first data line through the third via connection structure.

[0010] For example, in an embodiment of the present disclosure, each of the first leads includes: a first sub-lead portion extending from the second region to the first region along the first direction; and a second sub-lead portion extending from the first region to the bonding region along the second direction.

[0011] For example, an embodiment of the present disclosure provides an array substrate that further includes: a plurality of second pixel driving circuits located in the first region; a plurality of first power lines extending along the second direction and at least partially located in the second region; and a plurality of second power lines extending along the second direction and at least partially located in the first region. The plurality of first pixel driving circuits are arranged in an array along a first direction and a second direction to form a plurality of first pixel driving rows arranged along the second direction and a plurality of first pixel driving columns arranged along the first direction. The plurality of second pixel driving circuits are arranged in an array along the first direction and a second direction to form a plurality of second pixel driving rows arranged along the second direction and a plurality of second pixel driving columns arranged along the first direction. The plurality of first power lines are configured to provide power signals to the plurality of first pixel driving columns, and the plurality of second power lines are configured to provide power signals to the plurality of second pixel driving columns. The orthographic projection of the second sub-lead portion of each first lead on the substrate at least partially overlaps with the orthographic projection of the second power line on the substrate.

[0012] For example, an embodiment of this disclosure provides an array substrate that further includes: a plurality of second pixel driving circuits located in the first region; a plurality of second data lines; a plurality of first power lines extending along the second direction and at least partially located in the second region; and a plurality of second power lines extending along the second direction and at least partially located in the first region. The plurality of first pixel driving circuits are arranged in an array along a first direction and a second direction to form a plurality of first pixel driving rows arranged along the second direction and a plurality of first pixel driving columns arranged along the first direction. The plurality of second pixel driving circuits are arranged in an array along the first direction and a second direction to form a plurality of second pixel driving rows arranged along the second direction and a plurality of second pixel driving columns arranged along the first direction. The plurality of second data lines are configured to provide data signals to the plurality of second pixel driving columns. The plurality of first power lines are configured to provide power signals to the plurality of first pixel driving columns. The plurality of second power lines are configured to provide power signals to the plurality of second pixel driving columns. The orthographic projection of the second sub-lead portion of each first lead on the substrate is located between the orthographic projection of the second data line on the substrate and the orthographic projection of the second power line on the substrate.

[0013] For example, in an array substrate provided in one embodiment of this disclosure, the lengths of the first sub-lead portions of adjacent first leads are approximately equal.

[0014] For example, in an array substrate provided in an embodiment of this disclosure, the first pixel driving circuit further includes a compensation transistor and an initialization transistor. The first electrode of the compensation transistor, the first electrode of the initialization transistor, and the gate of the driving transistor are connected to a first node. The active layer of the compensation transistor and the active layer of the initialization transistor are made of oxide semiconductor material, and the active layer of the driving transistor is made of low-temperature polycrystalline silicon material.

[0015] For example, in an embodiment of the present disclosure, the second region is closer to the edge of the array substrate than the first region in the first direction.

[0016] For example, in an embodiment of the present disclosure, the edge of the orthographic projection of the second region on the substrate includes a curve, which is connected to the edge of the orthographic projection of the first region on the substrate extending along the first direction.

[0017] For example, in an embodiment of the present disclosure, the first overlap area between the orthographic projection of the bonding region on a reference line extending along the first direction and the orthographic projection of the first region on the reference line is greater than the second overlap area between the orthographic projection of the bonding region on the reference line extending along the first direction and the orthographic projection of the second region on the reference line.

[0018] For example, in an embodiment of the present disclosure, the array substrate further includes a bending region located between the first region and the bonding region. The bending region is bent such that the bonding region and the first region are located on opposite sides of the substrate in the third direction, which is perpendicular to both the first direction and the second direction.

[0019] At least one embodiment of this disclosure also provides a display device comprising the array substrate described in any of the preceding claims. Attached Figure Description

[0020] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0021] Figure 1 This is a partial schematic diagram of an array substrate;

[0022] Figure 2 This is a planar schematic diagram of an array substrate provided according to an embodiment of the present disclosure;

[0023] Figure 3 for Figure 2An enlarged schematic diagram of the dashed box in the array substrate shown;

[0024] Figure 4 This is a partial schematic diagram of an array substrate provided in an embodiment of the present disclosure;

[0025] Figure 5 This is a partial schematic diagram of another array substrate provided in an embodiment of the present disclosure;

[0026] Figure 6 This is a partial schematic diagram of another array substrate provided in an embodiment of the present disclosure;

[0027] Figure 7 An array substrate provided in one embodiment of this disclosure is along Figure 6 A cross-sectional view along the AB direction;

[0028] Figure 8 This is a partial schematic diagram of another array substrate provided in an embodiment of the present disclosure;

[0029] Figure 9 An array substrate provided in one embodiment of this disclosure is along Figure 8 A cross-sectional view along the CD direction;

[0030] Figure 10 This is a schematic diagram of another array substrate provided in an embodiment of the present disclosure;

[0031] Figure 11 A schematic diagram of another array substrate provided in an embodiment of this disclosure; and

[0032] Figure 12 This is a schematic diagram of a display device provided according to an embodiment of the present disclosure. Detailed Implementation

[0033] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0034] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that an element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0035] To meet people's ever-increasing demands for the overall aesthetics and display quality of display devices, narrow bezel and rounded corner designs are increasingly being adopted in display devices, such as smartphones. However, display panels with rounded corners require wiring outside the rounded corner area, thus typically requiring a wider bezel outside the rounded corner area in display devices.

[0036] Figure 1 This is a partial schematic diagram of an array substrate. (For example...) Figure 1 As shown, the array substrate 10 uses leads 40 to connect the data lines in the display area 12 to the bonding area 14, thereby providing data signals to the pixel driving circuit in the display area 12 through the bonding area 14 and the leads 40. In this array substrate 10, a large number of leads 40 need to be provided outside the rounded corner area 12B of the display area 12, and these leads 40 need to be bent to connect to the bonding area 14. Therefore, a relatively wide border is required outside the rounded corner area 12B for the leads 40 to be routed. On the other hand, in this array substrate 10, because the leads 40 in the rectangular area 12A of the display area 12 need to be bent to connect to the bonding area, the rectangular area 12A of the display area 12 also needs a relatively wide border.

[0037] In response, this disclosure provides an array substrate and a display device. The array substrate includes a substrate, a plurality of first pixel driving circuits, a plurality of first data lines, and a plurality of first leads. The substrate includes a display area and a bonding area surrounding the display area. The plurality of first pixel driving circuits are located on the substrate. The display area includes a first region and a second region located on one side of the first region, and the plurality of first pixel driving circuits are located in the second region. The plurality of first pixel driving circuits are arranged in an array along a first direction and a second direction to form a plurality of first pixel driving columns arranged along the first direction. The plurality of first data lines are configured to provide data signals to the plurality of first pixel driving columns. The plurality of first leads are respectively connected to the plurality of first data lines, passing through the first region from the second region and extending to the bonding area. Thus, the plurality of first leads pass through the first region from the second region and extend to the bonding area, instead of extending directly from the second region to the bonding area. Therefore, the array substrate does not need to have a wide bezel outside the second region, thereby enabling a narrow bezel design.

[0038] The array substrate and display device provided in the embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0039] One embodiment of this disclosure provides an array substrate. Figure 2 This is a planar schematic diagram of an array substrate provided according to an embodiment of the present disclosure; Figure 3 for Figure 2 An enlarged schematic diagram of the dashed box in the array substrate shown;

[0040] Figure 4 This is a partial schematic diagram of an array substrate provided in an embodiment of the present disclosure.

[0041] like Figure 2 , Figure 3 and Figure 4 As shown, the array substrate 100 includes a substrate 110, a plurality of first pixel driving circuits 121, a plurality of first data lines 131, and a plurality of first leads 141. The substrate 110 includes a display area 112 and a bonding area 114 located around the display area 112. The display area 112 includes a first region 112A and a second region 112B located on one side of the first region 112A, and the plurality of first pixel driving circuits 121 are located in the second region 112B. The first region 11A and the second region 112B are arranged in a first direction. For example, the bonding area 114 may be located below the display area 112. The bonding area 114 can be used to connect to an external driving IC. The driving IC can provide data signals to the plurality of first data lines 131 through the plurality of first leads 141, thereby driving the array substrate to perform display.

[0042] like Figure 2 , Figure 3 and Figure 4As shown, a plurality of first pixel driving circuits 121 are arranged in an array along a first direction X and a second direction Y to form a plurality of first pixel driving columns 151 arranged along the first direction X and a plurality of first pixel driving rows 161 arranged along the second direction Y. Each first pixel driving column 151 extends along the second direction Y; that is, the plurality of first pixel driving circuits 121 in each first pixel driving column 151 are arranged along the second direction Y. A plurality of first data lines 131 are configured to provide data signals to the plurality of first pixel driving columns 151, and a plurality of first leads 141 are respectively connected to the plurality of first data lines 131, passing through the first region 112A from the second region 112B and extending to the bonding region 114. It should be noted that in the array substrate provided in the embodiments of this disclosure, one first data line 131 can drive one first pixel driving column 151, and one first data line 131 can also drive multiple first pixel driving columns 151 through a time-division driving method.

[0043] In the array substrate provided in this embodiment, multiple first data lines 131 are configured to provide data signals to multiple first pixel drive columns 151. Multiple first leads 141 are connected to the multiple first data lines 131, passing through the first region 112A from the second region 112B and extending to the bonding region 114. Therefore, the multiple first leads 141 can provide drive signals, such as data signals, to the multiple first data lines 131. Since the multiple first leads 141 extend from the second region 112B through the first region 112A to the bonding region 114 without directly extending from the second region to the bonding region, the array substrate does not need to have a wide border outside the second region, thus enabling a narrow border or even borderless design outside the second region. Furthermore, since the multiple first leads 141 can extend directly from the first region 112A to the bonding region 114 without bending outside the first region 112A, the width of the border outside the first region can also be reduced. Therefore, the array substrate has a lower bezel width on the side of the display area near the bonding area (i.e., the bottom bezel), thus enabling narrow bezel and ultra-narrow bezel designs.

[0044] On the other hand, because the array substrate has a narrow bezel outside the second region, and no first lead is placed at the bezel location, the second region of the array substrate can be bent at a large angle, thus realizing a "quad-curved screen" design. Furthermore, it avoids wrinkles in subsequent module bonding processes, thereby improving product yield. It should be noted that the "quad-curved screen" design involves bending the edges and corners of the array substrate with a certain bending radius to form an arc, achieving a full-view 3D display from the front and sides, thus creating a 3D stereoscopic effect with four curved surfaces. This creates a sense of immersive stereoscopic display, aligning with future technological development trends.

[0045] In some examples, such as Figure 2 , Figure 3 and Figure 4 As shown, in the first direction X, the second region 112B is closer to the edge of the array substrate 110 than the first region 112A.

[0046] In some examples, such as Figure 2 , Figure 3 and Figure 4 As shown, the orthographic projection of the first region 112A onto the substrate 110 is rectangular, while the orthographic projection of the second region 112B onto the substrate 110 is irregular. Therefore, the array substrate can achieve rounded corners, thereby improving the display effect. It should be noted that the aforementioned irregular shape can be non-rectangular.

[0047] In some examples, such as Figure 2 , Figure 3 and Figure 4 As shown, the edge of the orthographic projection of the second region 112B onto the substrate 110 includes a curve, which connects to the edge of the orthographic projection of the first region 112A onto the substrate 110 extending along the first direction X. Thus, the array substrate can realize irregularly shaped display areas.

[0048] For example, such as Figure 2 , Figure 3 and Figure 4 As shown, the first region 112A can be the region above the straight edge of the bottom edge of the array substrate 100, and the second region 112B can be located at the corner of the array substrate 100. The number of sub-pixels in the sub-pixel column in the second region 112B is less than the number of sub-pixels in the sub-pixel column in the first region 112A.

[0049] In some examples, such as Figure 2 , Figure 3 and Figure 4 As shown, the first overlapping area between the orthographic projection of the binding area 114 on the reference line 300 extending along the first direction X and the orthographic projection of the first region 112A on the reference line 300 is greater than the first overlapping area between the orthographic projection of the binding area 114 on the reference line 300 extending along the first direction X and the orthographic projection of the second region 112B on the reference line 300. Furthermore, the orthographic projection of the binding area 114 on the reference line 300 extending along the first direction X and the orthographic projection of the second region 112B on the reference line 300 do not overlap. Therefore, after the first lead wire emerges from the first region 112A, it can extend to the binding area 114 without bending outside the first region 112A, thus reducing the width of the border outside the first region.

[0050] In some examples, such as Figure 2 , Figure 3 and Figure 4As shown, each first lead 141 includes a first sub-lead portion 141A and a second sub-lead portion 141B; the first sub-lead portion 141A extends along a first direction X, and the second sub-lead portion 141B extends along a second direction Y. The first sub-lead portion 141A extends from the second region 112B to the first region 112A along the first direction X; the second sub-lead portion 141B extends from the first region 112A to the bonding region 114 along the second direction Y. Of course, embodiments of this disclosure include, but are not limited to, the plurality of first sub-lead portions 141A and the plurality of second sub-lead portions 141B may form a stepped first lead 141.

[0051] In some examples, such as Figure 2 , Figure 3 and Figure 4 As shown, a second region 112B can be provided on each side of the first region 112A. That is, one second region 112B is provided on the first side of the first region 112A, and the other second region 112B is provided on the second side of the first region 112A opposite to the first side.

[0052] In some examples, the lengths of the first sub-lead portions 141A of adjacent first leads 141 are approximately equal, thereby improving the uniformity of the resistance or voltage drop of different first leads. It should be noted that the above-mentioned "approximately equal" includes the case where they are completely equal, as well as the case where the difference in length between the two first sub-lead portions is less than 1 / 10 of the average length of the two first sub-lead portions.

[0053] In some examples, such as Figure 2 , Figure 3 and Figure 4 As shown, the array substrate 100 further includes a plurality of second pixel driving circuits 122, a plurality of second data lines 132, and a plurality of second leads 142. The plurality of second pixel driving circuits 122 are located in a first region 112A. The plurality of second pixel driving circuits 122 are arranged in an array along a first direction X and a second direction Y to form a plurality of second pixel driving columns 152 arranged along the first direction X and a plurality of second pixel driving rows 162 arranged along the second direction Y, with each second pixel driving column 152 extending along the second direction Y. The plurality of second data lines 132 are configured to provide data signals to the plurality of second pixel driving columns 152, and the plurality of second leads 142 are respectively connected to the plurality of second data lines 132, extending from the first region 112A to the bonding region 114.

[0054] In some examples, such as Figure 2 , Figure 3 and Figure 4As shown, the array substrate 100 also includes a plurality of first power lines 231 and a plurality of second power lines 232; the plurality of first power lines 231 extend along the second direction Y and are at least partially located in the second region 112B; the plurality of second power lines 232 extend along the second direction Y and are at least partially located in the first region 112A; the plurality of first power lines 231 are configured to provide power signals to a plurality of first pixel driving columns 151, and the plurality of second power lines 232 are configured to provide power signals to a plurality of second pixel driving columns 152; the orthographic projection of the second sub-lead portion 141B of each first lead 141 on the substrate 110 at least partially overlaps with the orthographic projection of the second power line 232 on the substrate 110.

[0055] Figure 5 This is a partial schematic diagram of another array substrate provided in one embodiment of the present disclosure. (See attached diagram.) Figure 5 As shown, the orthographic projection of the second sub-lead portion 141B of each first lead 141 on the substrate 110 is located between the orthographic projection of the second data line 132 on the substrate 110 and the orthographic projection of the second power line 232 on the substrate 110.

[0056] In some examples, such as Figure 2 , Figure 3 and Figure 4 As shown, when the number of first data lines 131 is M (M is a positive integer greater than or equal to 2) and the number of first leads 141 is M, and the number of second data lines 132 is N (N is a positive integer greater than or equal to 2, and N is greater than M) and the number of second leads 142 is N, for a second region 112B, among the multiple first leads 141 in the second region 112B, in the direction from the second region 112B to the first region 112A, the i-th first data line 131... The first lead 141 connected to the first data line 132 is the i-th first lead 141. Among the multiple second leads 142, the second lead 142 connected to the i-th second data line 132 in the direction from the second region 112B to the first region 112A is the i-th second lead 142. The second sub-lead portion 141B of the i-th first lead 141 is located between the i-th second lead 142 and the (i+1)-th second lead 143, where i is a positive integer greater than or equal to 1 and less than or equal to M. That is, the second sub-lead portion 141B of the i-th first lead 141 can be inserted between the i-th second lead 142 and the (i+1)-th second lead 143. At this time, the driving of the array substrate can be achieved by adjusting the structure of the driver IC or the driving method.

[0057] Figure 6 This is a partial schematic diagram of another array substrate provided in one embodiment of the present disclosure. (See attached diagram.) Figure 6As shown, the first pixel driving circuit 121 includes a driving transistor T1; the array substrate 100 also includes a light-shielding structure 262; the light-shielding structure 262 is located on the side of the plurality of first pixel driving circuits 121 near the substrate 110, that is, the light-shielding structure 262 is located below the plurality of first pixel driving circuits 121; the orthographic projection of the driving transistor T1 of the first pixel driving circuit 121 on the substrate 110 at least partially overlaps with the orthographic projection of the light-shielding structure 262 on the substrate 110, thereby preventing light from illuminating the driving transistor T1 and improving the electrical performance of the driving transistor T1. In this case, the array substrate can utilize the light-shielding layer 260 where the light-shielding structure 262 is located to form the aforementioned plurality of first leads 141; that is, the plurality of first leads 141 and the light-shielding structure 262 are disposed in the same layer. It should be noted that the aforementioned plurality of first leads and the light-shielding structure being disposed in the same layer means that the plurality of first leads and the light-shielding structure are formed using the same film layer and the same masking process.

[0058] In the array substrate provided in this example, the array substrate has the following beneficial technical effects by using the light-shielding layer where the light-shielding structure is located to form the above-mentioned multiple first leads: (1) Since the first leads are made of the material of the light-shielding layer (e.g., molybdenum metal), and the sheet resistance of the material of the light-shielding layer itself is low, the resistance of the first leads can be reduced by using the material of the light-shielding layer to make the first leads; (2) Since the distance between the light-shielding layer where the light-shielding structure is located and the film layer where the data line or other signal line is located is far, the crosstalk between the first leads and the light-shielding structure in the same layer can be reduced; (3) Since the first leads are located in the light-shielding layer, the size of the first leads themselves is not limited by the size of the first pixel driving circuit and the second pixel driving circuit, and thus can be applied to products with different pixel densities (PPI); (4) The first leads and the light-shielding structure can use the same masking process, so no masking process is added, thereby reducing costs.

[0059] For example, the material of the light-shielding structure described above can be selected from one or more of molybdenum and titanium. Of course, the embodiments disclosed herein are not limited to this, and the material of the light-shielding structure can also be selected from other conductive materials with light-shielding properties.

[0060] In some examples, such as Figure 6 As shown, the driving transistor T1 includes a channel region C1. The orthographic projection of the channel region C1 on the substrate 110 falls completely within the range of the orthographic projection of the light-shielding structure 262 on the substrate 110. Each first lead 141 is spaced apart from and insulated from the light-shielding structure 262.

[0061] In some examples, such as Figure 6As shown, the first pixel driving circuit 121 also includes a compensation transistor T3 and an initialization transistor T6. The first electrode of the compensation transistor T3, the first electrode of the initialization transistor T6, and the gate of the driving transistor T1 are connected to the first node N1. The active layers of the compensation transistor T3 and the initialization transistor T6 are made of oxide semiconductor material, while the active layer of the driving transistor T1 is made of low-temperature polycrystalline silicon material. Therefore, transistors with active layers made of oxide semiconductor material have good hysteresis characteristics and low leakage current (below 1e-14A), and also have low mobility, achieving low leakage current. By using oxide semiconductor material for the active layers of the compensation transistor T3 and the initialization transistor T6, the array substrate can ensure voltage stability at the gate of the driving transistor T1. On the other hand, since the driving transistor T1 requires higher mobility and a more stable source voltage, a low-temperature polycrystalline silicon (LTPS) transistor can be used.

[0062] In some examples, such as Figure 6 As shown, the first pixel driving circuit 121 also includes a data writing transistor T2, a first light-emitting control transistor T4, a second light-emitting control transistor T5, and an electrode reset transistor T7. Therefore, this driving circuit can adopt a 7T1C structure, and in this case, the pixel driving circuit 121 may also include a storage capacitor Cst. It should be noted that... Figure 6 The structure and layout of the first pixel driving circuit shown are merely examples illustrating an embodiment of the first pixel driving circuit in this disclosure; other suitable structures may also be used. Furthermore, the structure and layout of the second pixel driving circuit may be the same as or different from that of the first pixel driving circuit.

[0063] Figure 7 An array substrate provided in one embodiment of this disclosure is along Figure 6 A cross-sectional view along the AB direction. (See diagram.) Figure 6 and Figure 7 As shown, the array substrate 100 includes a first conductive layer 171 and a first via connection structure 210; the first conductive layer 171 is located on the side of the plurality of first pixel driving circuits 121 away from the substrate 110; a plurality of first data lines 131 are located on the first conductive layer 171, and each first lead 141 is connected to the corresponding first data line 131 through the first via connection structure 210.

[0064] Figure 8 This is a partial schematic diagram of another array substrate provided in an embodiment of the present disclosure; Figure 9 An array substrate provided in one embodiment of this disclosure is along Figure 8 A cross-sectional view along the CD direction. (See diagram.) Figure 8 and Figure 9 As shown, the array substrate 100 further includes a first conductive layer 171, a first planarization layer 181, and a second conductive layer 172. The first conductive layer 171 is located on the side of the plurality of first pixel driving circuits 121 away from the substrate 110. The first planarization layer 181 is located on the side of the first conductive layer 172 away from the plurality of first pixel driving circuits 121. The second conductive layer 172 is located on the side of the first planarization layer 181 away from the first conductive layer 171. The array substrate 100 also includes a second via connection structure 220 and a third via connection structure 230. The third via connection structure 230 is located within the first planarization layer 181. A plurality of first data lines 131 are located in the second conductive layer 172. The first conductive layer 171 includes a connection electrode 270. Each first lead 141 is connected to the connection electrode 270 through the second via connection structure 220, and the connection electrode 270 is connected to the corresponding first data line 131 through the third via connection structure 230. Therefore, the array substrate can form the first data line in the second conductive layer, thereby reducing the load on the first data line and reducing crosstalk between the first data line and other signal lines.

[0065] Figure 10 This is a schematic diagram of another array substrate provided in one embodiment of the present disclosure. Figure 10 As shown, the substrate 110 also includes a bending region 116 located between the first region 112A and the bonding region 114; the bending region 116 is bent so that the bonding region 114 and the first region 112A are located on opposite sides of the substrate 110 in a third direction Z, which is perpendicular to both the first direction X and the second direction Y. That is, the substrate may include a display side and a rear side opposite to the display side, the first region and the second region may be located on the display side, and the bending region is bent towards the rear side so that the bonding region is located on the rear side. Therefore, this array substrate can further reduce the width of the bezel, thereby achieving an ultra-narrow bezel design.

[0066] For example, the substrate 110 can be a flexible substrate, and the substrate 110 can be made of flexible materials such as polyimide.

[0067] Figure 11 This is a schematic diagram of another array substrate provided in one embodiment of the present disclosure. Figure 11As shown, the array substrate 100 includes a substrate 110, a plurality of first pixel driving circuits 121, a plurality of second pixel driving circuits 122, M first data lines 131, N second data lines 132, M first leads 141, and N second leads 142; the substrate 110 includes a display area 112 and a bonding area 114 located around the display area 112; the display area 112 includes a first region 112A and a second region 112B located on one side of the first region 112A, the plurality of first pixel driving circuits 121 are located in the second region 112B; the plurality of first pixel driving circuits 122 are located in the first region 112A.

[0068] In some examples, such as Figure 11 As shown, a plurality of first pixel driving circuits 121 are arranged in an array along a first direction X and a second direction Y to form a plurality of first pixel driving columns 151 arranged along the first direction X, and each first pixel driving column 151 extends along the second direction Y; that is, the plurality of first pixel driving circuits 121 in each first pixel driving column 151 are arranged along the second direction Y. M first data lines 131 are configured to provide data signals to the plurality of first pixel driving columns 151, and M first leads 141 are respectively connected to the M first data lines 131, passing through the first region 112A from the second region 112B and extending to the bonding region 114. A plurality of second pixel driving circuits 122 are arranged in an array along the first direction X and the second direction Y to form a plurality of second pixel driving columns 152 arranged along the first direction X, and each second pixel driving column 152 extends along the second direction Y. N second data lines 132 are configured to provide data signals to a plurality of second pixel drive columns 152, and N second leads 142 are respectively connected to the N second data lines 132, extending from the first region 112A to the binding region 114.

[0069] In some examples, such as Figure 11 As shown, each first lead 141 includes a first sub-lead portion 141A and a second sub-lead portion 141B; the first sub-lead portion 141A extends along a first direction X, and the second sub-lead portion 141B extends along a second direction Y. Among the N second leads 142, in the direction from the second region 112B to the first region 112A, the second lead 142 connected to the j-th second data line 132 is the j-th second lead 142, where j is a positive integer greater than or equal to 1 and less than or equal to M; the j-th second lead 142 includes a third sub-lead portion 142A and a fourth sub-lead portion 142B, the third sub-lead portion 142A is located in the first region 112A and extends along the first direction; the fourth sub-lead portion 142B is connected to the third sub-lead portion 142A and extends along the second direction from the first region 112A to the bonding area 114. Therefore, by configuring the second lead to include a third sub-lead portion and a fourth sub-lead portion, the array substrate can translate the position where the second lead extends from the first region.

[0070] In some examples, such as Figure 11 As shown, among the multiple first leads 141, the first lead 141 connected to the j-th first data line 131 is the j-th first lead 141; the orth projection of the (j+1)-th first lead 141 on the substrate 110 is located on the side of the orth projection of the j-th first lead 141 on the substrate 110 that is away from the second region 112B; the orth projection of the fourth sub-lead portion 142B of the first second lead 142 on the substrate 110 is located on the side of the orth projection of the second sub-lead portion 141B of the M-th first lead 141 on the substrate 110 that is away from the second region 112B, and the orth projection of the fourth sub-lead portion 142B of the (j+1)-th second lead 142 on the substrate 110 is located on the side of the orth projection of the j-th second lead 142 on the substrate 110 that is away from the second region 112B. Therefore, the array substrate allows the second sub-lead portion of the first lead and the fourth sub-lead portion of the second lead to be in the same order as the first data line and the second data line in the display area. Thus, it is not necessary to adjust the structure or driving method of the driver IC, thereby reducing costs.

[0071] At least one embodiment of this disclosure also provides a display device. Figure 12 This is a schematic diagram of a display device provided according to an embodiment of the present disclosure. Figure 12 As shown, the display device 500 includes the aforementioned array substrate 100. Since the array substrate can achieve narrow bezel and ultra-narrow bezel designs, the display device can also achieve narrow bezel and ultra-narrow bezel designs. Furthermore, since the array substrate can achieve a "quad-curved screen" design, and wrinkles can be avoided in subsequent module bonding processes, resulting in a high product yield, the display device can also achieve a "quad-curved screen" design and has a high product yield.

[0072] For example, in some examples, the display device can be any product or component with display capabilities, such as a smartphone, tablet, television, monitor, laptop, digital photo frame, or navigator.

[0073] The following points need to be explained:

[0074] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0075] (2) Where there is no conflict, features of the same embodiment and different embodiments of this disclosure can be combined with each other.

[0076] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. An array substrate, comprising: The substrate includes a display area and a bonding area located around the display area; Multiple first pixel driving circuits are located on the substrate. Multiple first data lines; and Multiple first leads, The display area includes a first region and a second region located on one side of the first region, wherein the plurality of first pixel driving circuits are located in the second region. The plurality of first pixel driving circuits are arranged in an array along a first direction and a second direction to form a plurality of first pixel driving columns arranged along the first direction, wherein the first region and the second region are arranged in the first direction. The plurality of first data lines are configured to provide data signals to the plurality of first pixel driving columns, and the plurality of first leads are respectively connected to the plurality of first data lines, passing through the second region, the first region, and extending to the binding region. The first pixel driving circuit includes a driving transistor, a compensation transistor, and an initialization transistor. The first electrode of the compensation transistor, the first electrode of the initialization transistor, and the gate of the driving transistor are connected to a first node. The active layers of the compensation transistor and the initialization transistor are made of oxide semiconductor material, and the active layer of the driving transistor is made of low-temperature polycrystalline silicon material. The compensation transistor and the initialization transistor are arranged along the second direction. The substrate further includes a bending region located between the first region and the bonding region, the bending region being bent such that the bonding region and the first region are located on opposite sides of the substrate in a third direction, the third direction being perpendicular to both the first direction and the second direction. The array substrate further includes a light-shielding structure located on the side of the plurality of first pixel driving circuits close to the substrate. The orthographic projection of the driving transistors of the first pixel driving circuits on the substrate overlaps at least partially with the orthographic projection of the light-shielding structure on the substrate. The plurality of first leads are disposed in the same layer as the light-shielding structure.

2. The array substrate according to claim 1, wherein, The driving transistor includes a channel region, the orthographic projection of which falls entirely within the range of the orthographic projection of the light-shielding structure on the substrate, and each of the first leads is spaced apart from and insulated from the light-shielding structure.

3. The array substrate according to claim 1, further comprising: The first conductive layer is located on the side of the plurality of first pixel driving circuits away from the substrate. as well as First via connection structure, The plurality of first data lines are located in the first conductive layer, and each first lead is connected to the corresponding first data line through the first via connection structure.

4. The array substrate according to claim 1, further comprising: The first conductive layer is located on the side of the plurality of first pixel driving circuits away from the substrate. The first planarization layer is located on the side of the first conductive layer away from the substrate. The second conductive layer is located on the side of the first planar layer away from the substrate. Second via connection structure; as well as The third via connection structure is located within the first planarization layer. The plurality of first data lines are located in the second conductive layer. The first conductive layer includes a connection electrode. Each first lead is connected to the connection electrode through the second via connection structure. The connection electrode is connected to the corresponding first data line through the third via connection structure.

5. The array substrate according to any one of claims 1-4, wherein, Each of the first leads includes: A first sub-lead portion extends from the second region to the first region along the first direction; and The second lead portion extends from the first region to the bonding area along the second direction.

6. The array substrate according to claim 5, further comprising: Multiple second pixel driving circuits are located in the first region; as well as Multiple first power lines extend along the second direction and are at least partially located in the second region; as well as Multiple second power lines extend along the second direction and are at least partially located in the first region. The plurality of first pixel driving circuits are arranged in an array along a first direction and a second direction to form a plurality of first pixel driving rows arranged along the second direction and a plurality of first pixel driving columns arranged along the first direction. Similarly, the plurality of second pixel driving circuits are arranged in an array along the first direction and a second direction to form a plurality of second pixel driving rows arranged along the second direction and a plurality of second pixel driving columns arranged along the first direction. The plurality of first power lines are configured to provide power signals to the plurality of first pixel driving columns, and the plurality of second power lines are configured to provide power signals to the plurality of second pixel driving columns. The orthographic projection of the second sub-lead portion of each of the first leads on the substrate overlaps at least partially with the orthographic projection of the second power line on the substrate.

7. The array substrate according to claim 5, further comprising: Multiple second pixel driving circuits are located in the first region; Multiple second data lines; Multiple first power lines extend along the second direction and are at least partially located in the second region; as well as Multiple second power lines extend along the second direction and are at least partially located in the first region. The plurality of first pixel driving circuits are arranged in an array along a first direction and a second direction to form a plurality of first pixel driving rows arranged along the second direction and a plurality of first pixel driving columns arranged along the first direction. Similarly, the plurality of second pixel driving circuits are arranged in an array along the first direction and a second direction to form a plurality of second pixel driving rows arranged along the second direction and a plurality of second pixel driving columns arranged along the first direction. The plurality of second data lines are configured to provide data signals to the plurality of second pixel driving columns, the plurality of first power lines are configured to provide power signals to the plurality of first pixel driving columns, and the plurality of second power lines are configured to provide power signals to the plurality of second pixel driving columns. The orthographic projection of the second sub-lead portion of each of the first leads on the substrate is located between the orthographic projection of the second data line on the substrate and the orthographic projection of the second power line on the substrate.

8. The array substrate according to claim 5, wherein, The lengths of the first sub-lead portions of adjacent first leads are approximately equal.

9. The array substrate according to claim 1, wherein, The array substrate further includes a plurality of second pixel driving circuits, a plurality of second data lines, and a plurality of second leads. The plurality of second pixel driving circuits are located in the first region and are arranged in an array along the first and second directions to form a plurality of second pixel driving rows arranged along the second direction and a plurality of second pixel driving columns arranged along the first direction. Each second pixel driving column extends along the second direction. The plurality of second data lines are configured to provide data signals to the plurality of second pixel driving columns. The plurality of second leads are respectively connected to the plurality of second data lines and extend from the first region to the bonding region. M first leads are each connected to M first data lines, and N second leads are each connected to N second data lines. In the N second leads, the second lead connected to the j-th second data line in the direction from the second region to the first region is the j-th second lead. The j-th second lead includes a third sub-lead and a fourth sub-lead. The third sub-lead is located in the first region and extends along the first direction. The fourth sub-lead is connected to the third sub-lead and extends from the first region to the bonding area along the second direction. j is a positive integer greater than or equal to 1 and less than or equal to M.

10. The array substrate according to any one of claims 1-4, wherein, In the first direction, the second region is closer to the edge of the array substrate than the first region.

11. The array substrate according to claim 10, wherein, The edge of the orthographic projection of the second region onto the substrate includes a curve, which is connected to the edge of the orthographic projection of the first region onto the substrate extending along the first direction.

12. The array substrate according to any one of claims 1-4, wherein, The first overlap area between the orthographic projection of the binding area on the reference line extending along the first direction and the orthographic projection of the first region on the reference line is greater than the second overlap area between the orthographic projection of the binding area on the reference line extending along the first direction and the orthographic projection of the second region on the reference line.

13. The array substrate according to claim 9, wherein, Among the plurality of first leads, the first lead connected to the j-th first data line is the j-th first lead; the orthographic projection of the (j+1)-th first lead on the substrate is located on the side of the orthographic projection of the j-th first lead on the substrate away from the second region; the orthographic projection of the fourth sub-lead portion of the first second lead on the substrate is located on the side of the orthographic projection of the second sub-lead portion of the M-th first lead on the substrate away from the second region, and the orthographic projection of the fourth sub-lead portion of the (j+1)-th second lead on the substrate is located on the side of the orthographic projection of the j-th second lead on the substrate away from the second region.

14. A display device comprising an array substrate according to any one of claims 1-13.

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