Single chip system for smoke alarm

Abstract

A single-chip system (SoC) (100) for smoke detection includes power regulator circuits coupled to respective pins (VLX, VBST, VINT, VCC, PLDO, VMCU) and analog sensor amplifier circuits (110, 112, 114) each coupled to a respective one of the pins (e.g., VBST, VINT) coupled to the power regulator circuits. A first one of the analog sensor amplifier circuits has a photoelectric amplifier (112) circuit, a first LED driver (114), and a second LED driver (116). The SoC also has a digital core (138) including digital logic circuits, register bits (143), and MCU communication circuits (142). The MCU communication circuits are coupled to a data pin (SDA), the register bits are coupled to control or modify operation of the power regulator circuits and the analog sensor amplifier circuits, and the register bits are operable to be written by an MCU (102).

Description

Background Technology

[0001] Smoke alarms (also known as smoke detectors or smoke detection devices) require various interconnecting circuit blocks for standard operation. Depending on the target market (which can be commercial or residential), these circuit blocks may include amplifier circuitry for the sensor, communication circuitry with a microcontroller unit (MCU), horn driver circuitry, interconnecting circuitry for communication with other smoke detection devices in the home, signaling line circuitry (SLC) for communication with commercial fire alarm systems, and power regulator circuitry for providing multiple voltages from a wired direct current (DC) power source or a battery that can have various voltages. In some cases, these circuit blocks must be implemented within constraints of size, power, and cost, requiring a 10-year sealed battery life. Cost-effective solutions that meet the latest smoke detection standards require new implementation schemes. Summary of the Invention

[0002] The disclosed embodiments provide a highly integrated single-chip system (SoC) that replaces multiple ICs and discrete components in a smoke detection device. The SoC is combined with a power supply, the desired sensor, all communication connections, and a microcontroller integrated circuit (IC) (which is a discrete IC for providing greater flexibility) to provide a smoke detection device. A digital core on the SoC allows an external microcontroller to control each integrated block on the SoC. For example, the sensor amplifier may have adjustable gain, the power regulator may have adjustable voltage, and the driver may have adjustable current. This control thereby improves system efficiency and amplifier performance. Additionally, the digital core implements power saving through sleep modes and fault monitoring (e.g., undervoltage and overtemperature fault detection).

[0003] The SoC is designed for use in multiple different configurations. Power regulator circuitry includes numerous low-dropout (LDO) regulators to allow a single SoC to couple with multiple different power supplies (e.g., batteries with voltages between 3V and 12V), AC / DC power converters, or SLC combinations. The SoC includes analog sensor amplifier circuitry, such as photoelectric amplifiers, carbon monoxide (CO) amplifiers, and ionization amplifiers, which can be electronically configured to function or not function in a given situation. Two light-emitting diodes (LEDs) are provided on the chip, allowing the use of one or both LEDs. Interconnect driver / receiver circuitry and piezoelectric horn driver circuitry for residential smoke detectors share pins on the SoC with SLC transmission and SLC receiver circuitry for commercial smoke detectors, where the interconnect driver / receiver circuitry or the SLC transmission and SLC receiver circuitry functions in a given smoke detector.

[0004] On one hand, an embodiment of a SoC for smoke detection is disclosed. The SoC includes: a power regulator circuit, an analog sensor amplifier circuit, each coupled to receive power from the power regulator circuit, a first analog sensor amplifier circuit having a photoelectric amplifier circuit, a first LED driver, and a second LED driver; an MCU communication circuit; and an external communication circuit.

[0005] On the other hand, embodiments of a smoke detection device are disclosed. The smoke detection device includes: a single-chip system (SoC) comprising a power regulator circuit, analog sensor amplifier circuits (each coupled to receive corresponding power from the power regulator circuit, a first analog sensor amplifier circuit having a photoelectric amplifier circuit, a first LED driver, and a second LED driver), an MCU communication circuit, and an external communication circuit; sensors, each of which is coupled to a corresponding one in the analog sensor amplifier circuit; a DC power supply coupled to the power regulator circuit; and a microcontroller unit (MCU) chip comprising a power input, a digital processor, an analog-to-digital converter (ADC), the SoC communication circuit, and general-purpose I / O circuitry, wherein the power input on the MCU chip is coupled to receive power from the power regulator circuit.

[0006] On the other hand, an embodiment of the process for operating a smoke detector is disclosed. The process includes: providing power to a single-chip system (SoC) including communication circuitry, analog sensor amplifier circuitry, and power regulator circuitry upon startup; determining a first voltage for a microcontroller unit (MCU) attached to the SoC; and the SoC providing power to the MCU chip at the first voltage. Attached Figure Description

[0007] Embodiments of this disclosure are illustrated by way of example and not limitation in the accompanying drawings, wherein like element symbols indicate similar elements. It should be noted that different references to a “one” or “a” embodiment in this disclosure are not necessarily the same embodiment, and such references may mean at least one. Furthermore, when a particular feature, structure, or characteristic is described in connection with embodiments, it is believed that those skilled in the art will understand to implement this feature, structure, or characteristic in conjunction with other embodiments, whether explicitly described or not. As used herein, the term “coupled” is intended to mean either an indirect or direct electrical connection unless it qualifies as “communicably coupled” (which may include a wireless connection). Thus, if a first device is coupled to a second device, the connection may be a direct electrical connection or an indirect electrical connection via other devices and connectors.

[0008] The accompanying drawings are incorporated in and form part of this specification to illustrate one or more exemplary embodiments of the present disclosure. Various advantages and features of the present disclosure will be understood from the following detailed description taken in conjunction with the appended claims and with reference to the accompanying drawings, wherein:

[0009] Figure 1 Examples of smoke detection devices according to embodiments of the present disclosure are depicted;

[0010] Figure 2 Depicting embodiments of the present disclosure that can be used... Figure 1 The photoelectric amplifier circuit in the smoke detection device;

[0011] Figure 3 Depicting embodiments of the present disclosure that can be used... Figure 1 LED driver circuit in smoke detection device;

[0012] Figure 4 Depicting embodiments of the present disclosure that can be used... Figure 1 The CO amplifier circuit in the smoke detection device;

[0013] Figure 5 Depicting embodiments of the present disclosure that can be used... Figure 1 The ionization amplifier circuit in the smoke detection device;

[0014] Figure 6 Depicting embodiments of the present disclosure that can be used... Figure 1 The analog multiplexer circuit in the smoke detection device;

[0015] Figure 7 Depicts power regulator circuits providing various voltage levels according to embodiments of the present disclosure;

[0016] Figure 8 Depicting embodiments of the present disclosure that can be used... Figure 1 Interconnected driver / receiver circuitry in smoke detection devices;

[0017] Figure 9A Depicting embodiments of the present disclosure that can be used... Figure 1 The three-terminal piezoelectric horn driver circuit in the smoke detection device;

[0018] Figure 9B Depicting embodiments of the present disclosure that can be used... Figure 1 The two-terminal piezoelectric horn driver circuit in the smoke detection device;

[0019] Figure 10 Depicting embodiments of the present disclosure that can be used... Figure 1 The signaling line circuit in the smoke detection device;

[0020] Figure 11 Depicting embodiments of the present disclosure that can be used... Figure 1 The digital core of the smoke detection device;

[0021] Figure 12 Describe the interrupt signal warning logic according to embodiments of the present disclosure;

[0022] Figure 13 The process of operating the smoke detection device according to embodiments of the present disclosure is described; and

[0023] Figures 13A to 13E Description can be Figure 13 Additional components of the process. Detailed Implementation

[0024] Specific embodiments of the invention will now be described in detail with reference to the accompanying drawings. In the following detailed description of embodiments of the invention, numerous specific details are set forth to provide a more thorough understanding of the invention. However, those skilled in the art will understand that the invention can be practiced without these specific details. In other instances, well-known features have not been described in detail to avoid unnecessarily complicating the description.

[0025] Figure 1 A smoke detection device 100 according to an embodiment of the present disclosure is depicted. The smoke detection device 100 broadly includes the following elements:

[0026] • MCU chip 102 provides overall control of smoke detection device 100;

[0027] • Sensor 104 may include (but is not limited to) an ionization sensor, a photoelectric sensor, one or more LEDs and a CO sensor;

[0028] DC power supply 106; and

[0029] • SoC 108 includes analog sensor amplifier circuitry for the sensor, power regulator circuitry for providing the appropriate voltage required by the smoke detection device 100, and communication circuitry for communication between SoC 108 and MCU chip 102, and with external circuitry or a person.

[0030] Within the SoC 108, the analog sensor amplifier circuitry includes a CO amplifier circuit 110, a photoelectric amplifier circuit 112 including a first LED driver 114 and a second LED driver 116, and an ionization amplifier circuit 118. The CO amplifier circuit 110 is coupled to a group of CO pins 120; the photoelectric amplifier circuit 112, including the first LED driver 114 and the second LED driver 116, is coupled to a group of light pins 122; and the ionization amplifier circuit 118 is coupled to a group of ion pins 124. Relative to... Figures 2 to 5 This section will discuss the details of analog sensor amplifier circuits.

[0031] The power regulator circuitry includes a DC / DC boost converter 126, a pre-LDO regulator 128, an internal LDO regulator 130, an MCU LDO regulator 132, and a voltage divider 133. The power regulator circuitry is coupled to a group of power regulator pins 134 and is relative to... Figure 7 The communication includes two types: communication with the MCU chip 102 and communication with the external world. Communication between the MCU chip 102 and the SoC 108 is performed using an analog multiplexer circuit 136 and a digital core circuit 138. The digital core circuit 138 includes a serial MCU communication circuit 142 and a register containing register bits 143. In one embodiment, the serial MCU communication circuit 142 utilizes an I2C interface using the Inter-Integrated Circuit (I2C) communication protocol. The analog multiplexer circuit 136 has a corresponding input coupled to the output of each analog sensor amplifier circuit and an output coupled to the analog MUX pin AMUX and relative to... Figure 6 The digital core circuit 138 has a first input coupled to the LED enable pin LEDEN, a second input coupled to the general purpose input / output (I / O) pin GPIO, and a third input coupled to the speaker block enable pin HBEN. The serial MCU communication circuit 142 within the digital core circuit 138 has a first input coupled to the serial clock pin SCL, a second input coupled to the serial data pin SDA, and a third input coupled to the device address select pin CSEL. The digital core circuit 138 and the serial MCU communication circuit 142 are coupled to each other to allow the MCU chip 102 to use the serial MCU communication circuit 142 to write to the registers in the digital core circuit 138.

[0032] External communication is required to signal alarms to individuals in areas where smoke has been detected, communicating with other smoke detection devices in a residence or with a fire alarm control panel (FACP) in a commercial area. The external communication circuitry may include interconnect I / O buffer 144, horn driver circuitry 146 controlling a piezoelectric horn 148, and signaling line circuitry (SLC) (not specifically shown in...). Figure 1(Middle). Interconnect I / O buffer 144 and speaker driver circuit 146 are used in residential smoke detection devices, while SLC is used in commercial smoke detection devices. Relative to Figure 8 Let's discuss the interconnect I / O buffer 144; respectively relative to Figure 9A and Figure 9B This section discusses the horn driver circuit 146 for a three-terminal piezoelectric horn and the horn driver circuit 146 for a two-terminal piezoelectric horn; and relative to Figure 10 Let's discuss SLC. The SoC 108 features three ground pins: analog ground AGND, digital ground DGND, and power ground PGND.

[0033] SoC 108 also includes a battery test circuit 150 with a programmable load and an oscillator 152. The battery test circuit 150 is used to check the integrity of the battery connected to SoC 108. When the battery test circuit 150 is enabled, a programmable load of 10mA to 20mA in one embodiment is connected to the output voltage from the DC / DC boost converter 126. This load simulates the horn driver current consumption during alarm conditions. The oscillator 152 is internal and enabled when the DC / DC boost converter 126 or the optoamplifier circuit 112 is activated.

[0034] The high-level integration demonstrated in SoC 108 comes with both advantages and inherent challenges. Smoke detectors typically require many different analog blocks, such as drivers and amplifiers. Different models of smoke detectors require many identical blocks, which can also be provided as multiple discrete IC chips, but the sensors, power supplies, and channels for communication with external circuitry or people may differ between models. The disclosed SoC 108 integrates all shared blocks onto a single chip, but does so in a way that allows for the creation of different models of smoke detection devices using various attached sensors, different power supplies, different MCUs, and different communication channels (all using the same SoC 108) to provide a circuitry for connecting the remaining components.

[0035] Of course, higher-order integration presents a new set of problems to be solved. For example, sensor signals that can provide only nanoamps of current are highly sensitive to the presence of electronic noise. When sensor amplifiers are combined with noisy components (such as DC / DC boost converter 126), careful layout must be performed to provide isolation between noisy circuitry and sensitive circuitry (such as ionization amplifier circuit 118 and, in some cases, photoelectric amplifier circuit 112).

[0036] Meanwhile, new regulations from Underwriters Laboratories (UL) require new components, such as the ability to distinguish smoke from different types of fires and to limit false alarms by incorporating newer sensor technologies. All of these must be implemented, while providing a very low-power device capable of operating for ten years on a 3.6V lithium battery. This means using bias circuitry with very low current, which is highly sensitive to clock signals, noise, and so on. A great deal of attention is needed to achieve the desired performance. Providing low-power operation means slowing down the clock and keeping the number of gates to a minimum to keep the SoC 108's power requirements as low as possible.

[0037] Because a single SoC 108 can be used with different sensors and different power supplies, many analog sensor amplifier circuits and the DC / DC boost converter 126 can be electronically configured. For example, when a given smoke detection device 100 does not include an ionization sensor, the ionization amplifier circuit 118 can be electronically disabled. Similarly, the SoC 108 can be used with interconnect I / O buffers 144 and speaker driver circuitry 146, or otherwise with signaling line circuitry (not specifically shown in this figure). As will be explained in more detail below, these circuits can share pins because interconnect buffers and SLCs are never used simultaneously.

[0038] Continuing to look at the smoke detection device 100, the DC power supply 106 is depicted using an AC / DC converter 154 with a low-voltage battery 156 for use in the event of a mains power failure. Relative to... Figure 7 Let's discuss other possible configurations. As shown in smoke detection device 100, sensor 104 includes an ionization sensor 119, a photoelectric sensor 113, one or more LEDs 115, and a CO sensor 111. Combined with... Figures 2 to 5 We will discuss these sensors by referring to their corresponding amplifier circuits.

[0039] MCU chip 102 controls the operation of each block in SoC 108 and is provided as a separate IC from SoC 108 in smoke detection device 100 to provide greater flexibility for smoke detection device 100. MCU chip 102 has an on-MCU power input, digital processor 103, ADC 158, one or more general purpose input / output (I / O) circuits 160, and serial SoC communication circuitry 162, which uses the I2C communication protocol in the illustrated embodiment. The on-MCU power input is coupled to the output of MCU LDO regulator 132 and receives all required power from SoC 108. Digital processor 103 receives programming input from the user and data collected by SoC 108 and determines the required action. ADC 158 has an input coupled to the analog multiplexer output pin AMUX. Serial MCU communication circuitry 142 in SoC 108 is coupled to serial SoC communication circuitry 162 in MCU chip 102 via three pins: serial clock pin SCL, serial data pin SDA, and device address select pin CSEL. As will be discussed throughout this application, the power regulator circuit and the analog sensor amplifier circuit can receive control bits that control or modify the operation of the corresponding circuits. These control bits can be stored in register bits 143 of the digital core circuit 138. Serial MCU communication circuit 142 and serial SoC communication circuit 162 provide a method for the MCU chip 102 to write to register bits 142 in the digital core circuit 138 and thereby provide a method for controlling the SoC 108. General purpose I / O circuit 160 has a first output coupled to control LED indicator 164, a second output coupled to the LED enable pin LEDEN, and a third output coupled to the speaker enable pin HBEN. A first bidirectional communication line is coupled to the digital core circuit 138 on the SoC 108 via a general purpose I / O pin GPIO, and a second bidirectional communication line is coupled to the interconnect MCU pin INT_MCU for communication with external circuit systems.

[0040] Figure 2 The diagram depicts an optoamp circuit 200, which may be a portion of optoamp circuit 112 in SoC 108. The optoamp circuit 200 is connected to photodiode 202 and has two stages: an optical input amplifier 204 and an optical gain amplifier 206. The outputs of the optical input amplifier 204 and the optical gain amplifier 206 are connected to an analog multiplexer circuit 136, which transmits values ​​to an ADC 158 and thus the MCU chip 102. The disclosed configuration provides high dynamic range for the photodiode signal chain because the optical gain amplifier 206 is adjustable in real time.

[0041] Optical input amplifier 204 has a power input, an inverting optical input, a non-inverting optical input, an output optical input, and an enable optical input coupled to the internal LDO regulator 130. The inverting optical input is coupled to the negative pin PDN of the photodiode, the non-inverting optical input is coupled to the positive pin PDP of the photodiode, and the output optical input is coupled to the first input of the analog multiplexer circuit 136 and the output pin PDO of the photodiode. The enable optical input is coupled to receive the optical input amplifier control bit PAMP_EN. Optical gain amplifier 206 has a power input, a non-inverting optical gain input, an inverting optical gain input, an enable optical gain input, and an output optical gain coupled to the internal LDO regulator 130. It also has a non-inverting optical gain input coupled to the output of optical input amplifier 204, an enable optical gain input coupled to receive the control bit PGAIN_EN, and an output optical gain coupled to the second input and the inverting optical gain input of the analog multiplexer circuit 136 via a first photoresistor R2a (which is an adjustable resistor).

[0042] The first optical AND gate 208 has a first input coupled to receive the optical reference selection bit PREF_SEL, a second input coupled to receive the optical gain amplifier control bit PGAIN_EN, and an output. The first optical OR gate 210 has a first input coupled to receive the optical gain amplifier control bit PGAIN_EN, a second input coupled to receive the optical input amplifier control bit PAMP_EN, and an output. The second optical AND gate 212 has a first input coupled to receive the optical reference selection bit PREF_SEL, a second input coupled to receive the output of the first optical OR gate 210, and an output.

[0043] The optical reference circuit 214 has an optical reference input and an optical reference output. A first optical voltage source VS2a is coupled between the optical reference input and the optical reference output, and a second optical voltage source VS2b is coupled between the optical reference input and the ground plane. A first optical switch S2a is coupled to the optical gain inverting input through a second photoresistor R2b. The first optical switch S2a selectively couples the optical gain inverting input to the optical reference circuit 214 or the ground plane; the output of the first optical AND gate 208 is coupled to control the first optical switch S2a. The second optical switch S2b has a first terminal coupled to the optical reference input and a second terminal coupled to the optical reference pin PREF and the CO amplifier circuit 400, such as... Figure 4 As seen in the diagram. The second optical switch S2b is controlled by the output of the second optical AND gate 212. In one embodiment, the first optical voltage source VS2a delivers a voltage of approximately 5mV and the second optical voltage source VS2b delivers a voltage of approximately 50mV.

[0044] During operation of the opto-amplifier circuit 200, the photodiode 202 has an anode coupled to the positive pin PDP and a cathode coupled to the negative pin PDN. A first photocapacitor C2a and a third photoresistor R2c are coupled in parallel between the positive pin PDP and the negative pin PDN. A second photocapacitor C2b and a fourth photoresistor R2d are coupled in parallel between the output pin PDO and the negative pin PDN. A third photocapacitor C2a and a fifth photoresistor R2e are coupled in parallel between the positive pin PDP and the ground plane. In one embodiment, the third photocapacitor C2c and the fifth photoresistor R2e are coupled in parallel between the positive pin PDP and the optical reference pin PREF. In one embodiment, the first photocapacitor C2a has a capacitance of 7pF, the second capacitor C2b has a capacitance of 10pF, the third capacitor C2c has a capacitance of 10pF, the third photoresistor R2c has a resistance of 470kΩ, the fourth photoresistor R2d has a resistance of 1.5MΩ, and the fifth photoresistor R2e has a resistance of 1.5MΩ.

[0045] The optical input amplifier 204 is a wide-bandwidth, low-offset operating amplifier designed to amplify photodiode current. Negative feedback causes the photodiode to conduct with zero voltage bias. The input stage can be selected to reference ground plane GND or the optical reference pin PREF. The optical reference pin PREF is a voltage typically pulled to the internal LDO output pin VINT and can be configured by the MCU to a reference of 50mV. The 50-mV reference keeps the input amplifier in the linear operating region when no signal is applied, improving amplifier speed and zero current sensitivity.

[0046] Photocurrent flows through a fifth photoresistor R2e, coupled between the positive pin (PDP) of the photodiode and the ground plane (GND) or the optical reference pin (PREF), and through a fourth photoresistor R2d, coupled between the negative pin (PDN) of the photodiode and the output pin (PDO) of the photodiode. These two matched resistors determine the gain of the input stage. A second photocapacitor C2b and a third photocapacitor C2c compensate the op-amp feedback loop for optimal response. In one embodiment, the second photocapacitor C2b and the third photocapacitor C2c may be 5pF when the input amplifier references the optical reference pin (PREF) and 10pF when the input amplifier references the ground plane (GND). The third photoresistor R2c and the first photocapacitor C2a (which in one embodiment are 470kΩ and 7pF, respectively) stabilize the feedback loop.

[0047] The optical gain amplifier 206 also features high bandwidth and low noise, further amplifying the photodiode signal. The optical gain amplifier 206 is real-time adjustable using I2C (back 142). In one embodiment, the optical gain amplifier 206 has four settings and can be configured to amplify by 5x, 11x, 20x, or 35x. The optical gain amplifier 206 can use the optical reference select bit PREF_SEL to reference either the ground plane or the optical reference pin PREF. When using the optical reference pin PREF, the output of the optical gain amplifier 206 remains above 50mV. Referring the optical gain amplifier 206 to the optical reference pin PREF causes a 50mV reference voltage that varies depending on the signal level at the photodiode output pin PDO. Because the reference changes with the signal level, the gain varies slightly. The output of the optical gain amplifier 206 with zero photocurrent varies as the gain setting changes to maintain the output above 50mV.

[0048] Figure 3 An LED driver circuit 300 is depicted for use in a smoke detection device 100. The LED driver circuit 300 includes an LED LDO regulator circuit 302 having an upper power input coupled to a boost pin VBST, a first LED input coupled to the LED LDO enable bit LEDLDO_EN, a second LED input coupled to the LED LDO register LEDLDO[0:2], an output coupled to the LED LDO pin LEDLDO via LED diode D3, and a third input coupled to the LED LDO pin LEDLDO. The LED driver circuit 300 also includes a first LED driver 304 and a second LED driver 306.

[0049] The first LED driver 304 includes a first LED DAC 308, a first LED amplifier 310, and a first LED NFET M3a. The first LED DAC 308 has a first input coupled to a first temperature coefficient bit TEMPCOA[1:0], a second input coupled to a first current setting register PDACA[7:0], and an output. In one embodiment, the first temperature coefficient bit TEMPCOA[1:0] provides a selection of four different temperature coefficients, and the first current setting register PDACA[7:0] influences the value of the current on the first LED. The first LED amplifier 310 has an upper supply voltage input coupled to the pre-LDO output pin PLDO, a non-inverting input coupled to the output of the first LED DAC 308, an inverting input coupled to the first LED current sensing pin CSA, an enable input, and an output. The first LED NFET M3a has a drain coupled to the first LED current sink pin DINA, a source coupled to the first LED current sensing pin CSA, and a gate coupled to the output of the first LED amplifier 310.

[0050] The second LED driver 306 includes a second LED DAC 312, a second LED amplifier 314, and a second LED NFET M3b. The second LED DAC 312 has a first input coupled to a second temperature coefficient bit TEMPCOB[1:0], a second input coupled to a second current setting register PDACB[7:0] (which again influences the value of the current on the second LED), and an output. The second LED amplifier 314 has an upper supply voltage input coupled to the pre-LDO output pin PLDO, a non-inverting input coupled to the output of the second LED DAC 312, an inverting input coupled to the second LED current sensing pin CSB, an enable input, and an output. The second LED NFET M3b has a drain coupled to the second LED current sink pin DINB, a source coupled to the LED current sensing pin CSB, and a gate coupled to the output of the second LED amplifier 314.

[0051] The operation of the first LED driver 304 and the second LED driver 306 is controlled by the operation of LED AND gate 316, the first LED OR gate 318, the second LED OR gate 320, and general-purpose I / O logic 322. General-purpose I / O logic 322 has a first input coupled to a general-purpose I / O pin GPIO, a second input coupled to a general-purpose I / O register GPIO[0:2], a first output, and a second output. LED AND gate 316 has a first input coupled to the LED enable pin LEDEN, a second input coupled to the LED pin enable bit LEDPIN_EN, and an output coupled to the LED switch S3. The first LED OR gate 318 has a first input coupled to the first output of general-purpose I / O logic 322, a second input coupled to the enable input of the first LED amplifier 310, and an output coupled to the enable input of the second LED amplifier 314. The second LED OR gate 320 has a first input, a second input coupled to the second output of general-purpose I / O logic 322, and an output coupled to the enable input of the second LED amplifier 314. The output of LED AND gate 316 can be selectively coupled to the second input of the first LED OR gate 318 or the first input of the second LED OR gate 320, depending on the value of the LED select bit LEDSEL.

[0052] When both the first LED driver 304 and the second LED driver 306 are used in a particular application, one of the attached LEDs is typically a blue LED and the other is typically an infrared LED. The first LED 324a has a cathode coupled to the first LED current sink pin DINA and an anode coupled to a first terminal of the first LED voltage source 326a and the first LED capacitor C3a. The second terminal of the first LED capacitor C3a is coupled to the power ground pin PGND. A first LED current sensing resistor Rcsa is coupled between the first LED current sensing pin CSA and the power ground pin PGND. The second LED 324b has a cathode coupled to the second LED current sink pin DINAB and an anode coupled to a first terminal of the second LED voltage source 326b and the second LED capacitor C3b. The second terminal of the second LED capacitor C3b is coupled to the power ground pin PGND. A second LED resistor Rcsb is coupled between the second LED current sensing pin CSB and the power ground pin PGND. The power supply used to provide the first LED voltage source 326a and the second LED voltage source 326b depends on the type of LED used. For infrared LEDs, LED voltage source 326x is coupled to the battery via a third LED resistor Rir, and for blue LEDs, LED voltage source 326x is coupled to the LED LDO pin LEDLDO. In one embodiment, the third LED resistor Rir has a resistance of 1kΩ, and each of the first LED capacitor C3a and the second LED capacitor C3b has a capacitance of 100μF.

[0053] The first LED driver 304 and the second LED driver 306 are regulated by an 8-bit DAC for current, temperature compensation, and adjustment. When the LED driver is enabled, the value on the corresponding current sensing pin CSx is adjusted using the values ​​provided to the corresponding LED DACs 308 and 312 and the resistance on the corresponding current sensing resistor Rcsx. The first LED driver 304 and the second LED driver 306 are enabled separately using the LED enable pin LEDEN and the LED enable bit LEDPIN_EN. Both the pin and bit must be high for the selected LED driver to operate. The LED select bit LEDSEL is used to determine the driver connected to the signal on the LED enable pin LEDEN. General purpose I / O pins GPIO can be used to enable either LED driver.

[0054] The LED driver is also temperature-compensated to account for the decrease in LED intensity as temperature increases. Four temperature compensation settings are available to support a variety of IR and blue LEDs. Temperature compensation is implemented by using the voltage on the temperature-changing LED current sensing pin CSA; therefore, the temperature compensation also depends on the corresponding LED actuator Rcsx. The LED LDO regulator circuit 302 clamps the voltage from the boost pin VBST, using an integrated LED diode D3 to block reverse current and current-limited to prevent inrush current caused by the LED capacitor C3x (which is 100μF in one embodiment).

[0055] Figure 4 A CO amplifier circuit 400, which can be used as a CO amplifier circuit 110, is depicted. The CO transimpedance amplifier 402 has an upper supply voltage input coupled to the output of an internal LDO regulator 130, a CO amplifier enable input coupled to the CO amplifier enable bit COAMP_EN, a CO inverting input coupled to the CO negative terminal pin CON via a CO input resistor R4a, a CO non-inverting input, and a CO output coupled to the CO output pin COO via a CO output resistor R4b. The CO output pin COO is coupled to a third input of an analog multiplexer circuit 136. The CO output resistor R4b is coupled in parallel with a CO output switch S4a to allow bypassing of the CO output resistor R4b. A CO gain resistor R4c (which is a variable resistor), a CO feedback switch S4b, and a first CO input switch S4c are also coupled in series between the CO output and the CO negative terminal pin CON, wherein a first CO node N4a between the CO feedback switch S4b and the first CO input switch S4c is coupled to a second CO node N4b between the CO inverting input and the CO input resistor R4a. The CO non-inverting input is coupled to the first terminal of the second CO input switch S4d. The second terminal of the second CO input switch S4d can be selectively coupled to the CO positive terminal pin COP or the first terminal of the CO voltage source VS4, wherein the second terminal of the CO voltage source VS4 is coupled to the ground plane.

[0056] In one embodiment, the CO positive terminal pin COP is coupled to a 300mV reference voltage (not specifically shown in the figure). In one embodiment, the CO amplifier circuit 400 further includes a CO connection test circuit, which includes a first CO AND gate 404 and a second CO AND gate 406. The first CO AND gate 404 has a first input coupled to receive the CO test output direction bit COTEST_DIR, a second input coupled to receive the CO test enable bit COTEST_EN, and an output coupled to control the first CO test switch S4e. The second CO AND gate 406 has a first input coupled to receive the CO test enable bit COTEST_EN, a second input coupled to receive the CO test output direction bit COTEST_DIR via the CO inverter 408, and an output coupled to control the second CO test switch S4f. The first CO test switch S4e and the second CO test switch S4f are coupled in series between the internal LDO regulator 130 and the ground plane. The node between the first CO test switch S4e and the second CO test switch S4f is coupled to the optical reference pin PREF, the opto-amplifier circuit 200, and the internal LDO regulator 130 via an internal CO resistor R4d (which has a resistance of 200kΩ in one embodiment).

[0057] like Figure 4 As shown, the photochemical CO sensor 410 is coupled between the CO negative terminal pin CON and the ground plane. A first external CO resistor R4e is coupled in parallel with the photochemical CO sensor 410 to prevent charge accumulation between the sensor terminals. The CO negative terminal pin CON is also coupled to the ground plane via a CO diode D4 and a second external CO resistor R4f. A first CO capacitor C4a is coupled between the CO output pin COO and the ground plane, and in one embodiment, the CO positive terminal pin COP is coupled to the ground plane. The optical reference pin PREF can be coupled in at least two different configurations. In one embodiment, the optical reference pin PREF is coupled to the first terminal of the second CO capacitor C4b, and the second terminal of the second CO capacitor C4b is coupled to the node between the CO diode D4 and the second external CO resistor R4f. In one embodiment, the optical reference pin PREF is coupled to the drain of the CO NFET M4, and the source of the CO NFET M4 is coupled to the ground plane. The gate of the CO NFET M4 is coupled to be controlled by the MCU chip 102 via a general purpose I / O pin GPIO on the MCU chip. The internal LDO capacitor pin is also coupled to the drain of the CO NFET M4 via a third external resistor R4g.

[0058] As seen in the CO amplifier circuit 400, the CO transimpedance amplifier 402 is a low-offset, low-power operating amplifier with configurable input, gain, and output resistors. If external resistors are desired, each of the CO input resistor R4a, CO output resistor R4b, and CO gain resistor R4c can be bypassed using the corresponding bits of the COSW register. The CO input resistor R4a limits the amplifier current during CO sensor connection testing. The CO gain resistor R4c amplifies the CO sensor signal. The CO gain resistor R4c can be adjusted by changing the CO gain register bit COGAIN, and the CO output resistor R4b can be used to filter the CO amplifier output signal. During operation of the photochemical CO sensor 410, the CO transimpedance amplifier 402 receives a microampere sensor current from the photochemical CO sensor 410 and converts the sensor current into a voltage that can be read by the ADC158 on the MCU chip 102 via the analog MUX pin AMUX to determine the concentration of CO gas in the air surrounding the sensor.

[0059] Figure 5The diagram depicts an ion amplifier circuit 500 that can be used as an ion amplifier circuit 118 in a smoke detection device 100. An ion input amplifier 502 has an ion input inverting input coupled to an ion protection pin IONG1, an ion input non-inverting input coupled to an ion input pin IONIN via a low-pass filter 504 (which in one embodiment is a 3.2kHz filter), and an ion input output coupled to a first terminal of a first ion resistor R5a. A second terminal of the first ion resistor R5a is coupled to the ion input inverting input and further coupled to a first ion switch S5a and a second ion switch S5b; both the first ion switch S5a and the second ion switch S5b are coupled to be controlled by an ion gain setting bit IGAIN_SET. The first ion switch S5a couples the ion input output to the ion gain inverting input of an ion gain amplifier 506 via the second ion resistor R5b (which in one embodiment has a resistance of 1MΩ). The second ion switch S5b couples the ion input / output to the ion gain inverting input via a third ion resistor R5c (which in one embodiment has a resistance of 200 kΩ). The ion gain non-inverting input of the ion gain amplifier 506 is coupled to the ground plane via an ion voltage source VS5 using an ion reference voltage setting IREF[0:1], and the ion gain output of the ion gain amplifier 506 is coupled to the fourth input of the analog multiplexer circuit 136 to provide the ion output signal AOUT_ION. The ion gain output is also coupled to each of a series of feedback switches 508 that allow selection of the feedback resistor using the ion gain setting register IGAIN[1:0]. In one embodiment, a first ion feedback switch is coupled to a first ion feedback resistor with a resistance of 160 kΩ, a second ion feedback switch is coupled to a second ion feedback resistor with a resistance of 190 kΩ, a third ion feedback switch is coupled to a third ion feedback resistor with a resistance of 220 kΩ, and a fourth ion feedback switch is coupled to a fourth ion feedback resistor with a resistance of 800 kΩ. The ion gain amplifier 506 has an upper power input coupled to the internal LDO regulator 130.

[0060] The ion LDO regulator circuit 510 has an upper supply voltage coupled to the boost pin VBST, and is further coupled to receive the ion LDO enable bit ILDO_EN and the ion LDO set bit ILDO[0:3]. In one embodiment, the ion LDO regulator circuit 510 and the LED LDO regulator circuit 302 are identical circuits. The ion LDO regulator circuit 510 is coupled to the ion LDO output pin IONLDO via a first ion diode D5a, wherein a first ion node N5a is located between the first ion diode D5a and the ion LDO output pin IONLDO. A first ion LDO resistor R5d and a second ion LDO resistor R5e are coupled in series with an ion NFET M5a between the first ion node N5a and the ground plane, wherein the gate of the NFET M5a is coupled to receive the ion LDO enable bit ILDO_EN. The ion LDO regulator circuit 510 is also coupled to a second ion node N5b between the first ion LDO resistor R5d and the second ion LDO resistor R5e.

[0061] As shown in the ionization amplifier circuit 500, the ionization chamber 512 has an upper supply voltage coupled to the ion LDO output pin IONLDO via a second ion diode D5b and a sixth ion resistor R5f, and an ion center electrode coupled to the ion input pin IONIN. A guard ring in the ionization chamber 512 is coupled to the ion guard pin IONG1. A first ion capacitor C5a has a first terminal coupled between the ion LDO output pin IONLDO and the second ion diode D5b, and the second ion capacitor C5b has a first terminal coupled between the second ion diode D5b and the sixth ion resistor R5f. The second ion diode D5b and the sixth ion resistor R5f are further coupled in series with a seventh ion resistor R5g and an NPN transistor M5b between the ion LDO output pin IONLDO and the ground plane; a third ion capacitor C5c has a first terminal coupled between the sixth ion resistor R5f and the seventh ion resistor R5g. Each of the first ion capacitor C5a, the second ion capacitor C5b, and the third ion capacitor C5c has a corresponding second terminal coupled to the ground plane.

[0062] Ionization amplifier circuit 500 provides an ionization chamber 512 with a bias voltage and buffers the output signal of the ionization chamber 512 via associated pins. In one embodiment, ion LDO regulator circuit 510 has six settings: 7.5V, 8.0V, 8.5V, 9.0V, 9.5V, and 10V. These settings provide the bias voltage for the ionization chamber 512 and the power supply for the ion input amplifier 502. Ion input amplifier 502 is connected to the output of ionization chamber 512 to buffer the output voltage and shield the output from leakage current. Ion input amplifier 502 is a unity-gain configured amplifier optimized for low leakage and low power. Ion input amplifier 502 is not designed to drive any load other than ion gain amplifier 506. A low-pass filter 504 is provided to filter electromagnetic interference (EMI).

[0063] Ion gain amplifier 506 inverts and shifts the output signal. Ion input amplifier 502 provides an output between 1V and 5V, which is too high for most microcontrollers. Ion gain amplifier 506 shifts this range of output voltage down to values ​​between approximately 0V and approximately 2.2V. Internally, ion gain amplifier 506 is an operational amplifier configured to invert the signal using programmable references with programmable gains. The four reference voltages are 0.71V, 1.1V, 2.08V, and 2.2V, and the seven gains are 0.16x, 0.19x, 0.22x, 0.8x, 0.95x, 1.1x, and 4x, and are programmable via the ion gain setting bit IGAIN_SET and the ion gain setting register IGAIN[1:0]. The wide bandwidth of ion gain amplifier 506 allows this amplifier to be periodically enabled for short periods to capture ion chamber signals using an external ADC. Ion input amplifier 502 must be powered and enabled in relation to ion gain amplifier 506 to function properly.

[0064] Figure 6 An analog multiplexer circuit 600 is depicted that can be used as an analog multiplexer circuit 136. The analog multiplexer circuit 600 includes an analog multiplexer (MUX) 602, a MUX amplifier 604, a MUX AND gate 606, and a MUX bypass switch S6. As shown in the analog multiplexer circuit 600, the analog multiplexer 602 is coupled to receive four signal inputs, but more or fewer signal inputs may exist. The signal inputs of the analog multiplexer 602 are coupled to:

[0065] • Ion output signal AOUT_ION;

[0066] • CO output pin COO;

[0067] • Photodiode output pin PDO; and

[0068] • Output AOUT_PH of optical gain amplifier 206.

[0069] In addition to the signal inputs, analog multiplexer 602 has inputs and outputs coupled to receive the analog MUX select bits AMUX_SEL(1:0). MUX AND gate 606 has a first input coupled to receive the reciprocal of the MUX bypass bit AMUX_BYP, a second input coupled to receive the MUX select bits (1:0), and an output. Variable MUX amplifier 604 has a first input coupled to the output of analog multiplexer 602, a second input coupled to the output of MUX AND gate 606, and an output coupled to the analog MUX pin AMUX. MUX switch S6 is coupled in parallel with variable MUX amplifier 604 between the output of analog multiplexer 602 and the analog MUX pin AMUX to provide bypass for variable MUX amplifier 604. MUX switch S6 is coupled to be controlled by the MUX bypass bit AMUX_BYP. When coupled into a smoke detection device, the MUX capacitor C6 is coupled to the analog MUX pin AMUX, and the MUX resistor R6 is coupled between the analog MUX pin AMUX and the ADC 158. In one embodiment, the resistor R6 has a resistance of 4.7kΩ and the capacitor C6 has a capacitance of 330pF.

[0070] Analog multiplexer circuit 600 is used to connect various amplifier outputs to ADC158 on MCU chip 102. MUX amplifier 604 is unity gain and improves the drive strength and fidelity of analog signals when connected to ADC (e.g., ADC 158), while MUX resistor R6 filters high-frequency noise in the analog signal. Variable MUX amplifier 604 can be bypassed to remove the added offset introduced by the unity gain amplifier.

[0071] Figure 7A power regulator circuit 700 is depicted for providing various voltage levels used by circuitry on SoC 108 via attachment to MCU chip 102 and via attachment to external sensors and alarm mechanisms. The power regulator circuit 700 includes a DC / DC boost converter 702, a pre-LDO regulator 704, an internal LDO regulator 706, and an MCU LDO regulator 708. The DC / DC boost converter 702 has an upper power input, an input coupled to the boost input pin VLX, an output coupled to the boost pin VBST, and is operable when SoC 108 is operating from a low-voltage battery (e.g., low-voltage battery 156). The pre-LDO regulator 704 has an input coupled to the pre-LDO input pin VCC and an output coupled to the pre-LDO output pin PLDO and the upper power input of the DC / DC boost converter 702. The internal LDO regulator 706 has an upper power input coupled to the output of the pre-LDO regulator 704 and an output coupled to the internal LDO output pin VINT. The MCU LDO regulator 708 has an upper power input coupled to the output of the pre-LDO regulator 704, an output coupled to the MCU LDO output pin VMCU, a first MCU-LDO input coupled to the MCU enable bit MCUENA, a second input coupled to the MCU voltage set bit VMCUSET, and a third input coupled to the MCU voltage select pin MCUSEL.

[0072] When coupled to a smoke detection device, many different power supply configurations can be used, but they all share trace T1 on a circuit board (not specifically shown in the figure); trace T1 couples the boost pin VBST to the pre-LDO input pin VCC. Figure 1 The first configuration is shown, where the AC / DC converter 154 is coupled to trace T1 to provide operating power and the low-voltage battery 156 is coupled to the boost input pin VLX to provide backup power. A first diode D1a prevents high voltage on the boost pin VBST from passing through the boost input pin VLX, but ensures power is available to the pre-LDO regulator 128 in the event of a mains power outage, regardless of whether the DC / DC boost converter 126 is active. A second diode D1b is coupled between the AC / DC converter 154 and trace T1. In the second configuration, the smoke detection device 100 operates solely from the low-voltage battery 156 coupled to the boost input pin VLX, without the AC / DC converter. During startup, diode D1a provides initial power to the pre-LDO regulator 128 until the DC / DC boost converter 126 becomes active. Figure 7The third aspect is depicted, in which a high-voltage battery 710 (e.g., 8 to 12V) is directly coupled to trace T1, decoupling the boost input pin VLX. The DC / DC boost converter 702 does not function in this configuration because it recognizes the high voltage on the boost pin VBST. A fourth configuration (not specifically shown in the figure) is used in commercial smoke detection devices utilizing SLC. In this configuration, the power line VLINE from the FACP is coupled to trace T1 and relative to... Figure 10 The communication circuit discussed.

[0073] When the power regulator circuit 700 operates from a higher voltage coupled to trace T1 (e.g., AC / DC converter 154 or high-voltage battery 710), the DC / DC boost converter 702 detects that the voltage on the boost pin VBST is greater than the programmed output voltage Vpgm and does not attempt to draw power from a backup battery (if present). The pre-LDO regulator 704 is designed to receive voltages up to 15V, outputs a regulated voltage of approximately 4 to approximately 5V, and provides the regulated voltage to the internal LDO regulator 706, the DC / DC boost converter 702, and the MCU LDO regulator 708. Circuits requiring higher voltages can be coupled to the boost pin VBST, where a higher voltage can be used.

[0074] When the power regulator circuit 700 operates from a low-voltage battery (as the sole power source or when mains power is interrupted and the backup battery becomes active), the DC / DC boost converter 702 receives an input voltage from the low-voltage battery (e.g., 156) coupled to the boost input pin VLX via inductor L and provides a boost output voltage at the boost pin VBST. The DC / DC boost converter 702 monitors the voltage at the boost pin VBST and switches to maintain the programmed output voltage Vpgm on the boost pin VBST only when needed. If the programmed output voltage Vpgm is not required, the DC / DC boost converter 702 can be disabled by the MCU chip 102 using the appropriate registers in the serial MCU communication circuit 142 and the digital core circuit 138.

[0075] The internal LDO regulator 706 receives power from the pre-LDO regulator 704 and further regulates the voltage, which is then supplied to various analog circuits and the digital core. The MCU LDO regulator 708 provides power to the attached MCU, such as MCU chip 102, at the desired voltage level. The voltage supplied to MCU chip 102 is initially determined by the voltage at the MCU voltage select pin MCUSEL. In one embodiment, the MCU voltage select pin MCUSEL can be coupled via a 620Ω resistor to any of the following: a) ground, b) left floating area, c) internal LDO output pin VINT, and d) ground, where each possible connection relates to the initial voltage supplied to the MCU LDO output pin VMCU. After MCU chip 102 is operational, MCU chip 102 can use the MCU voltage set bit VMCUSET to program different voltages to be supplied by the MCU LDO regulator 708. The output of the MCU LDO regulator 708 can also be provided to the interconnect I / O buffer 144.

[0076] Because SoC 108 provides power to MCU chip 102, the two IC chips must coordinate with each other for low-power or sleep modes. MCU chip 102 can send a command to SoC 108 to enter sleep mode, and then MCU chip 102 puts itself into sleep mode. When analog circuitry and other circuitry are in low-power mode, SoC 108 will run a timer. After a set period (e.g., 2 seconds), the MCU enable bit MCUENA is used to instruct the MCU LDO regulator 708 to provide power and wake up MCU chip 102. In this way, the smoke detection device 100 can be in sleep mode most of the time, but wakes up every few seconds to run necessary tests to provide ultra-low power operation and enable the smoke detection device 100 to operate for ten years on a 3.6V lithium battery.

[0077] Figure 8An interconnect driver / receiver circuit 800, which can be used as an interconnect I / O buffer 144, is depicted. The interconnect driver / receiver circuit 800 has an upper power supply input coupled to the output of a DC / DC boost converter 702 and provides bidirectional serial communication between an MCU chip 102 and a wired interconnect bus 802 via interconnects to the MCU pin INT_MCU and the bus pin INT_UNIT. A first interconnect AND gate 804 has a first input coupled to the interconnect enable bit INT_EN, a second input coupled to the interconnect direction bit INT_DIR, and a third input coupled to the interconnect to the MCU pin INT_MCU, as well as an output. A second interconnect AND gate 806 has a first input coupled to the reciprocal of the value on the interconnect to the MCU pin INT_MCU, a second input coupled to the interconnect enable bit INT_EN, a third input coupled to the interconnect direction bit INT_DIR, and an output. A first interconnect current source CS8a is coupled in series with an interconnect diode D8 and a second interconnect current source CS8b between the upper power supply input of the interconnect driver / receiver circuit 800 and the ground plane. The first interconnect current source CS8a has an input coupled to receive an enable signal from the output of the first interconnect AND gate 804, and the second interconnect current source CS8b has an input coupled to receive an enable signal from the output of the second interconnect AND gate 806. In one embodiment, the first interconnect current source CS8a may be replaced by a metal / oxide / silicon (MOS) transistor or a bipolar transistor acting as a switch. An interconnect node N8 between the interconnect diode D8 and the second interconnect current source CS8b is coupled to the interconnect-to-bus pin INT_UNIT. A first interconnect resistor R8a is coupled in series with the interconnect NFET M8 between the interconnect-to-bus pin INT_UNIT and the ground plane. A second interconnect resistor R8b is coupled between the interconnect-to-bus pin INT_UNIT and the ground plane. When the interconnect NFET M8 is turned on, the first interconnect resistor R8a (which has a resistance of 100kΩ in one embodiment) pulls down the bus to prevent leakage from causing false alarms. The second interconnect resistor R8b (which has a resistance of 35MΩ in one embodiment) prevents the interconnect-to-bus pin INT_UNIT from floating.

[0078] Hysteresis comparator 808 has a non-inverting input, an inverting input, an enable input, and an output coupled to interconnect node N8. Interconnect voltage source VS8 is coupled between the inverting input of hysteresis comparator 808 and the ground plane. Interconnect voltage source VS8 provides interconnect comparator hysteresis and has an input coupled to the interconnect comparator hysteresis bit INT_HYS. In one embodiment, a 0 value on the interconnect comparator hysteresis bit causes hysteresis comparator 808 to have a 1.1V hysteresis, and a 1 value on the interconnect comparator hysteresis bit causes hysteresis comparator 808 to have a 0.1V hysteresis.

[0079] The digital short-time pulse suppression circuit 810 has a first input coupled to the output of the hysteresis comparator 808, a second input coupled to the interconnect short-time pulse suppression bit INT_DEG, and a bit coupled to the STATUS1 bit on the status register. The interconnect short-time pulse suppression bit INT_DEG allows the digital short-time pulse suppression circuit 810 to be programmed from 0ms to 20ms. The interconnect OR gate 812 has a first input coupled to the output of the digital short-time pulse suppression circuit 810, a second input coupled to the output of the interconnect-to-MCU pin INT_MCU via the interconnect switch S8. The third interconnect AND gate 814 has a first input coupled to the interrupt signal INTERRUPT, a second input coupled to the status interrupt bit STATUS_INT, and an output coupled to the second input of the interrupt OR gate 812. The fourth interconnect AND gate 816 has a first input coupled to the interconnect enable bit INT_EN, a second input coupled to the interconnect direction bit INT_DIR, and an inverted output coupled to control the interconnect switch S8. The fifth interconnect AND gate 818 has a first input coupled to the interconnect enable bit INT_EN, a second input coupled to the inverse of the interconnect direction bit INT_DIR, and an output coupled to the enable input of the hysteresis comparator 808.

[0080] The interconnect driver / receiver circuit 800 functions in a residential smoke alarm system connected to mains power, where multiple smoke detectors can communicate with each other using a wired interconnect bus 802 and corresponding interconnect-to-bus pin INT_UNIT. This capability allows all smoke detectors in the residence to hear the alarm simultaneously. The interconnect driver circuit, comprising a first interconnect AND gate 804, a second interconnect AND gate 806, a first interconnect current source CS8a, and a second interconnect current source CS8b, pulls the bus high when smoke is detected and pulls the bus low when smoke is cleared. The driver is current-limited to handle short-circuit conditions and has a diode D8 on the high-side driver to prevent the bus from driving voltage to the boost pin VBST. A hysteresis comparator 808 senses when the bus is pulled high, uses a digital short-time pulse resistant circuit 810 to filter the signal, and outputs the result to the interconnect-to-MCU pin INT_MCU and the status register STATUS1. The interconnect-to-MCU pin INT_MCU has the additional function of outputting a status interrupt signal. The status interrupt bit STATUS_INT enables the interrupt signal output via the interconnect-to-MCU pin INT_MCU. However, when the interconnect driver circuit is enabled, the interrupt signal output is disconnected to allow the microcontroller to drive the interconnect to the MCU pin INT_MCU.

[0081] Looking back Figure 1The residential smoke detection device 100 provides a horn driver circuit 146, which can be used to drive a piezoelectric horn 148 having two or three terminals. The type of piezoelectric horn to be driven by the SoC 108 is selected using a horn selection bit HORN_SEL, which can be set to 0 for two terminals or 1 for three terminals. The three-terminal piezoelectric horn receives feedback from a feedback electrode on the piezoelectric horn and can use the feedback signal to optimize loudness. In contrast, the two-terminal piezoelectric horn relies on a signal from the MCU chip 102 due to the speed at which the horn is driven.

[0082] Figure 9AA piezoelectric horn driver circuit 900A and an attached piezoelectric horn 902A are described for a three-terminal piezoelectric horn configuration. The piezoelectric horn driver circuit 900A includes horn driver logic 904, which has a first horn driver input coupled to the horn feedback pin HORNFB, a second horn driver input coupled to the horn threshold bit HORN_THR, a third horn driver input coupled to the horn block enable pin HBEN, a first horn driver output coupled to the horn silver terminal pin HORNSL, and a second horn driver output coupled to the horn brass terminal pin HORNBR. A first horn amplifier 906 has a first input, a second input, and an output coupled to the horn silver terminal pin HORNSL; a second horn amplifier 908 has a first input, a second input, and an output coupled to the horn brass terminal pin HORNBR. A first horn switch S9a is set by the horn select bit HORN_SEL to couple the first input of the first horn amplifier 906 to the first output of the horn driver logic 904, and a second horn switch S9b is set by the horn select bit HORN_SEL to couple the first input of the second horn amplifier 908 to the second output of the horn driver logic 904. The first speaker resistor R9a is coupled in series with the first speaker NFET M9a between the speaker silver terminal pin HORNSL and the ground plane; the second speaker resistor R9a is coupled in series with the second speaker NFET M9b between the speaker brass terminal pin HORNBR and the ground plane. The first speaker AND gate 910 has a first input coupled to receive the speaker enable bit HORN_EN, a second output coupled to the speaker block enable pin HBEN, a third input coupled to the speaker select bit HORN_SEL, and an output providing a three-terminal enable signal. The second speaker AND gate 912 has a first input coupled to receive the reciprocal of the speaker select bit HORN_SEL, a second input coupled to the speaker enable bit HORN_EN, and an output providing a two-terminal enable signal. The speaker OR gate 914 has a first input coupled to the output of the first speaker AND gate 910, a second input coupled to the output of the second speaker AND gate 912, and an output coupled as a driver enable signal to the second input of the first speaker amplifier 906 and the second input of the second speaker amplifier 908. Inverter 916 has an input coupled to the output of horn OR gate 914 and an output coupled to the gates of the first horn NFET M9a and the second horn NFET M9b.

[0083] In the three-terminal mode, the silver and brass terminals of the piezoelectric horn 902A are directly coupled to the horn silver terminal pin HORNSL and the horn brass terminal pin HORNBR, respectively. The third horn resistor R9c is coupled in series with the fourth horn resistor R9d between the feedback terminal of the piezoelectric horn 902A and the horn feedback pin HORNFB. The fifth horn resistor R9e is coupled between the horn feedback pin HORNFB and the ground plane; the sixth horn resistor R9f is coupled between the horn brass terminal pin HORNBR and the horn node N9, which is located between the third horn resistor R9c and the fourth horn resistor R9d; and the horn capacitor C9 is coupled between the horn node N9 and the horn silver terminal pin HORNSL.

[0084] During operation, the piezoelectric horn driver circuit 900A is enabled and begins oscillation when the horn enable register bit HORN_EN and the horn block enable pin HBEN are set high. The value of the resistor connected to the piezoelectric feedback terminal can be adjusted to tune the resonant oscillation frequency. Trial and error is generally required to select this resistor. After the driver achieves resonant oscillation, the duty cycle of the outputs of the horn silver terminal pin HORNSL and the horn brass terminal pin HORNBR can be adjusted via the MCU chip 102 using the horn threshold bit HORN_THR to maximize loudness.

[0085] Figure 9B A piezoelectric horn driver circuit 900B is depicted for a two-terminal piezoelectric horn and an attached piezoelectric horn 902B. Internally, the value of the horn select bit HORN_SEL is changed such that a first horn switch S9a couples the first input of a first horn amplifier 906 to the horn feedback pin HORNFB, and a second horn switch S9b couples the first input of a second horn amplifier 908 to the horn block enable pin HBEN. In this configuration, both the horn feedback pin HORNFB and the horn block enable pin HBEN are controlled by an MCU (e.g., MCU chip 102) to ensure that the outputs of the first horn amplifier 906 and the second horn amplifier 908 are directly controlled by signals from the MCU chip 102. Externally, the piezoelectric horn 902b requires only a brass terminal to be coupled to the horn brass terminal pin HORNBR, and a silver terminal to be coupled to the horn silver terminal pin HORNSL via a horn inductor L9 (which in one embodiment has an inductance of 1mH). MCU chip 102 sends an arbitrary pulse width modulation (PWM) signal to control the drive voltage of the piezoelectric horn. The PWM signal can be a square wave at its oscillation frequency, a sine wave at its oscillation frequency, or any shape used for voice applications. Horn inductor L9 is used to improve the rise and fall times of the output and reduce power consumption.

[0086] While residential smoke detection systems use interconnect driver / receiver circuitry 800 to communicate between devices within the same residence and piezoelectric horns 902x and piezoelectric horn driver circuitry 900x to sound alarms, commercial smoke detection systems do not use either of these. Instead, the FACP in a commercial smoke detection system provides a SLC for communicating with all devices in the “zone.” Devices coupled to the SLC can include smoke detectors, thermal detectors, manual alarm points, warning systems / bells, control modules, relay modules, and so on.

[0087] The SLC provides power to all fire detection devices coupled to the SLC (e.g., smoke detection device 100). The SLC also transmits data from the FACP (e.g., address and polling information) to the fire detection devices and transmits data from the fire detection devices (e.g., address, polling approval, alarm, monitoring, and fault signals) to the FACP.

[0088] Figure 10 A signaling line circuit 1000 according to an embodiment of this disclosure is depicted. The external component selection shown is merely an example, as different components may be used with other specific SLC protocols that can be varied by the provider. Figure 1 The signaling line circuit 1000 is not specifically shown because the SLC is not a circuit completely isolated from dedicated pins (as in a sensor driver, for example). In fact, the signaling line circuit 1000 is integrated with other circuitry and reuses the horn feedback pin HORNFB, the horn brass terminal pin HORNBR, the horn silver terminal pin HORNSL, the horn block enable pin HBEN, the interconnect to MCU pin INT_MCU, and the interconnect to bus pin INT_UNIT. These reused pins are relabeled within the signaling line circuit 1000. The signaling line circuit 1000 is connected to the power line VLINE to transmit and receive data from the MCU chip 102. Although not specifically shown in the figure, the power line VLINE is also coupled to trace T1 to receive power. The SLC isolates the high-voltage power line from the MCU chip 102, reducing the risk of damage and decreasing the number of external components.

[0089] The signaling line circuit 1000 includes an SLC receiver circuit 1002 and an SLC transmitter circuit 1004. The SLC receiver circuit 1002 includes an SLC comparator 1006, an SLC AND gate 1008, an SLC OR gate 1010, a voltage source VS10, a first SLC resistor R10a, a second SLC resistor R10b, and an SLC switch S101. The SLC comparator 1006 has a non-inverting input, an inverting input, an output, a first control input coupled to the SLC receiver comparator hysteresis bit SLCRX_HYS, and a second control input coupled to the SLC receiver anti-short-time pulse bit SLCRX_DEG. The non-inverting input of the SLC comparator 1006 is coupled to the SLC receiver pin SLC_RX; the first SLC resistor R10a is coupled in series with the SLC switch S10 between the SLC receiver pin SLC_RX and the ground plane; and the second SLC resistor R10b is coupled between the SLC receiver pin SLC_RX and the ground plane. SLC switch S10 is controlled by the SLC pull-down resistor enable bit SLCRX_PD. Voltage source VS10 is coupled between the inverting input of SLC comparator 1006 and the ground plane. SLC AND gate 1008 has a first input coupled to the interrupt signal INTERRUPT, a second input coupled to the status interrupt bit STATUS_MCURX on the MCU_RX pin, and an output. SLC OR gate 1010 has a first input coupled to the output of SLC comparator 1006, a second input coupled to the output of SLC AND gate 1008, and an output coupled to the MCU receive pin MCU_RX. External to signaling line circuit 1000, power line VLINE is coupled to the SLC receive pin SLC_RX via Zener diode Z10, and SLC comparator C10 is also coupled to the SLC receive pin SLC_RX.

[0090] During operation, the SLC receiver (not specifically shown in the figure) transmits the signal on the power line VLINE to the MCU chip 102. A reverse-biased SLC Zener diode Z10 shifts and selects the power line level to reduce the voltage, such that when the power line VLINE is high, the SLC receiver pin SLC_RX is above 3V and when the power line VLINE is low, the SLC receiver pin SLC_RX is below 0.5V. An SLC capacitor (which is 100-pF in one embodiment) filters voltage surges that may occur on the power line VLINE. A hysteresis and short-time pulse comparator filters parasitic noise on the power line VLINE. The output of the SLC comparator 1006 is synchronized using a 32kHz clock before passing the short-time pulse. The hysteresis voltage and short-time pulse timing can be programmed by the SLC receiver comparator hysteresis bit SLCRX_HYS and the SLC receiver short-time pulse bit SLCRX_DEG. The second SLC resistor R10b is an internal pull-down resistor that biases the SLC Zener diode Z10 to keep the voltage on the SLC receive pin SLC_RX below 17V (which is the recommended maximum).

[0091] SLC transmission circuit 1004 includes a first SLC amplifier 1012 having an input coupled to a first MCU transmission pin MCU_TX1, an output coupled to the first SLC transmission pin SLC_TX1, and an enable input coupled to receive the SLC transmission enable bit SLCTX_EN. SLC transmission circuit 1004 also includes a second SLC amplifier 1014 having an input coupled to a second MCU transmission pin MCU_TX2, an output coupled to the second SLC transmission pin SLC_TX2, and an enable input coupled to receive the SLC transmission enable bit SLCTX_EN. Externally, a first SLC NPN M10a is coupled between the power line VLINE and the ground plane, and a second SLC NPN M10b is coupled between the power line VLINE and the ground plane. A third SLC resistor R10c is coupled between the emitter of the second SLC NPN M10b and the ground plane. The fourth SLC resistor R10d is coupled between the first SLC transmission pin SLC_TX1 and the substrate of the first SLC NPN M10a, and the second SLC transmission pin SLC_TX2 is coupled to the substrate of the second SLC NPN M10b.

[0092] MCU chip 102 transmits signals to the power line VLINE by using a controlled current sink to pull the power line VLINE low. When the SLC transmission circuitry is enabled, the microcontroller controls the outputs from the first SLC transmission pin SLC_TX1 and the second SLC transmission pin SLC_TX2 by driving the first SLC transmission pin MCU_TX1 and the second SLC transmission pin MCU_TX2 high. In the signaling line circuit 1000, the second SLC NPN M10b is coupled to a current-limiting third SLC resistor R10c and draws a limited current from the power line VLINE. The first SLC NFET M10a can fully pull the power line VLINE low. This configuration allows for multi-level communication.

[0093] One advantage of integrating multiple circuits into a SoC is the ability to integrate error messages or communications to the MCU chip 102. These interrupt signals can be individually configured to notify the MCU chip 102 when a system exception occurs. The interrupt signals are stored in the STATUS1 register, which has a higher bit that latches when various condition limits (such as temperature or voltage) are reached. Each STATUS1 register bit can be independently configured to send an interrupt signal by setting the corresponding MASK register bit. Bits GPIO[0:2] in the general-purpose I / O register can be set as output interrupt signals via the general-purpose I / O pin GPIO, and the STATUS_INT bit can be set as output interrupt signals via interconnection to the MCU pin INT_MCU or the MCU receive pin MCU_RX. By connecting the general-purpose I / O pin GPIO, the interconnection to the MCU pin INT_MCU, or the MCU receive pin MCU_RX to the microcontroller, the MCU chip 102 can be notified immediately when the STATUS1 bit changes, rather than having to repeatedly read the STATUS1 register. After the SoC 108 sends an interrupt signal, the signal remains high until the STATUS1 register is read by the MCU chip 102. If the error condition is removed at this point, the fault is cleared.

[0094] Figure 11A digital core 1100 according to an embodiment of this disclosure is depicted. The digital core 1100 includes digital logic circuitry 1102, a serial bus interface 1104, and register bits 1106. The digital logic circuitry 1102 includes interrupt signal alert logic circuitry 1108, which will be discussed in further detail below. Although register bits 1106 are shown as containing a number of individual metrics, the register bits (which may be single-bit metrics or contain more bits) can be grouped into larger registers as needed. The following description is given to provide the idea of ​​versatility that can be incorporated into the disclosed SoC when multiple capabilities are incorporated into a single chip. Other metrics not specifically shown herein may also be included. Although some metrics are interpreted in absolute terms (e.g., regardless of whether the power at a particular point is as expected), there may be other situations where the action of a particular metric is modified, such as the metric not functioning during sleep mode.

[0095] Several register bits 1106 (e.g., bits in the STATUS1 register) are used for signaling the presence of specific conditions that may affect or need to be reported to the MCU. When the smoke detection device 100 operates on a low-voltage battery (e.g., a 3-volt battery), the SoC 108 can put itself into sleep mode to save power. The sleep timer wake-up flag SLP_DONE 1111 can be used for signaling when the sleep period has expired and the SoC 108 and MCU chip 102 can be started. The VCC low warning flag VCCLOW 1112 is set when the power at the pre-LDO input pin VCC drops below a selectable drop value V_VCCLOW,FALL (not specifically shown in the figure). The MCU LDO power good error flag MCULDO_ERR 1113 is set to indicate that an error has occurred at the MCU LDO output power. The thermal shutdown error flag OTS_ERR 1114 indicates that the junction temperature has exceeded the selectable shutdown temperature T_SHUTDOWN (not shown in the figure), while the thermal warning flag OTS_WRN 1115 indicates that the junction temperature has exceeded the warning value T_WARNING (not shown in the figure). The boost activity monitoring flag BST_nACT 1116 indicates that the DC / DC boost converter 702 did not switch actively or within the selectable boost inactivity time T_BST,ACT (not shown in the figure), and the boost converter power good error flag BST_ERR 1117 indicates that an error has occurred on the DC / DC boost converter 702.

[0096] Each of the above conditions can be used by the SoC 108 and / or reported to the MCU chip 102 as needed; a corresponding mask can be used for each flag, allowing the user to indicate whether each reporting flag should be utilized. These masks include the sleep timer wake-up flag mask SLP_DONEM 1118, the VCC low warning flag mask VCCLOWM 1119, the MCU LDO power good error flag mask MCULDO_ERRM 1120, the thermal shutdown error flag mask OTS_ERRM 1121, the thermal warning flag mask OTS_WRNM 1122, the boost activity monitoring flag mask BST_nACTM 1123, and the boost converter power good error flag mask BST_ERRM 1124. (See below) Figure 12 The section discusses the use of flags and their corresponding masks. The general-purpose I / O indicator 1131 can be used to output interrupt signals via GPIO pins.

[0097] The MCU LDO power good indicator MCU_PG 1125 indicates whether the power at the MCU LDO is above or below the power good threshold, and the boost power good indicator BST_PG 1126 indicates whether the power at the DC / DC boost converter output is above or below the power good threshold. Many indicators are used to provide control or modification in analog modules (such as CO amplifier circuit 110, opto-amplifier circuit 112, and ionization amplifier circuit 118).

[0098] By returning to the reference photoamplifier circuit 200, the optical input amplifier control bit PAMP_EN 1127 can enable or disable the optical input amplifier 204; the optical gain amplifier control bit PGAIN_EN 1128 can enable or disable the optical gain amplifier 206; and the optical gain register PGAIN[1:0] 1129 can be used to set the gain by adjusting the resistance at the first photoresistor R2a. The optical reference setting PREF_SEL 1130 determines whether the optical reference pin PREF is coupled to ground or the 50mV internal reference Vs2b.

[0099] By returning to the reference LED driver circuit 300, the first temperature coefficient bit TEMPCOA[1:0]1132 and the second temperature coefficient bit TEMPCOB[1:0] (not specifically shown in the figure) are used to set the temperature coefficient of the LED driver circuit 300, and together with the first current setting register PDACA[7:0]1133 and the second current setting register PDACB[7:0]1138, they are used to control the current supplied to the first LED NFET M3a and the second LED NFET M3b. The LED selection bit LEDSEL 1134 controls the driver connected to the signal on the LED enable pin LEDEN. The LED LDO enable bit LEDLDO_EN 1135 can enable or disable the LED LDO regulator circuit 302; the LED LDO register LEDLDO[0:2]1136 can be used to adjust the regulating voltage in the LED LDO regulator circuit 302; and the LED pin enable bit LEDPIN_EN 1137 can configure whether the LED enable pin LEDEN will enable the LED block. In embodiments where the ion LDO regulator circuit 510 and the LED LDO regulator circuit 302 are the same circuit, it is possible to distinguish whether the control bit of the LED LDO regulator circuit 302 or the control bit of the ion LDO regulator circuit 510 is the same.

[0100] By returning to the reference CO amplifier circuit 400, the CO amplifier output resistor enable bit COSWRO 1139 can be used to enable or disable the CO output switch S4a; the CO gain resistor enable bit COSWRG 1140 can be used to enable or disable the CO feedback switch S4b; the CO input resistor enable bit COSWRI 1141 can be used to enable or disable the first CO input switch S4c; the CO reference switch enable bit COSWREF 1142 can be used to enable or disable the second CO input switch S4d; the CO feedback resistor setting COSGAIN[1:0] 1143 can be used to adjust the resistance on the CO gain resistor R4c; and the 300mV reference enable bit REFOP3_EN 1144 can be used to enable the 300mV reference voltage (not specifically shown in the figure). The CO amplifier reference voltage COREF[1:0]1145 can be used to set the voltage output by the CO voltage source VS4; the CO test output direction bit COTEST_DIR 1146 indicates whether the CO test output is pulled down or pulled up; the CO amplifier enable bit COAMP_EN 1147 can enable or disable the CO transimpedance amplifier 402; and the CO test output enable bit COTEST_EN 1148 can enable or disable the CO test output on the optical reference pin PREF.

[0101] By returning to the reference ionization amplifier circuit 500, the ion LDO enable bit ILDO_EN 1149 can be used to enable or disable the ion LDO regulator circuit 510, and the ion LDO setting ILDO[0:3] 1150 can be used to set the voltage of the ion LDO regulator circuit 510. The ion gain setting register IGAIN[1:0] 1151 can be used to set the gain of the ion gain amplifier 506; the ion reference voltage setting IREF[0:1] 1152 can be used to set the reference voltage on the ion voltage source VS5.

[0102] By referring to the interconnect driver / receiver circuit 800, the interconnect short-time pulse immunity bit INT_DEG 1153 can be used to program the digital short-time pulse immunity circuit 810 between 0ms and 20ms. The interconnect cell pull-down resistor enable bit INT_PD 1154 can be used to enable the interconnect NFET M8; the interconnect enable bit INT_EN 1156 can be used to enable or disable the interconnect driver / receiver circuit 800; the interconnect direction bit INT_DIR 1157 can be used to indicate the direction of communication on the interconnect driver / receiver circuit 800. The status interrupt bit STATUS_INT 1158 can be used to provide an interrupt to the MCU via the interconnect to the MCU pin INT_MCU; and the interconnect comparator hysteresis bit INT_HYS 1159 can be used to indicate the voltage hysteresis on the third interconnect voltage source VS8.

[0103] By referring to the horn driver circuit 146, the horn threshold bit HORN_THR 1160 can be used to provide duty cycle tuning for the piezoelectric horn 148 in three-terminal operation. The horn selection bit HORN_SEL 1161 can be used to specify whether the horn is a two-terminal or three-terminal piezoelectric horn; while the horn enable bit HORN_EN 1162 can be used to enable the horn driver circuit 146.

[0104] Referring to signaling line circuit 1000, the SLC receiver enable bit SLCRX_EN 1163 can be used to enable or disable the SLC receiver circuit 1002; the SLC pull-down resistor enable bit SLCRX_PD 1164 can be used to enable the pull-down resistor by turning off the SLC switch S10; and the SLC receiver comparator hysteresis bit SLCRX_HYS 1165 can be used to specify the hysteresis voltage on the SLC comparator 1006. The status interrupt on the MCU receive pin STATUS_MCURX 1167 can be set to specify the interrupt signal output through the MCU receive pin MCU_RX, and the SLC transmission enable bit SLCTX_EN 1168 can be set to enable the SLC transmission circuit 1004. In any particular example of a smoke detection device, such as the discussion of signaling line circuit 1000, because signaling line circuit 1000 is integrated with other circuits (such as piezoelectric horn driver circuit 900 and interconnect driver / receiver circuit 800), only one of signaling line circuit 1000 and interconnect driver / receiver circuit 800 will function and provide communication with the MCU.

[0105] Finally, the battery test enable bit BATTEST_EN 1155 uses the battery test circuit 150 in the smoke detection device 100 to enable or disable the battery test, and the analog MUX select bit AMUX_SEL[1:0] can be used to specify the input of the analog multiplexer circuit 600 to be sent to the MCU.

[0106] By providing all these control inputs and error flags and their control circuitry on a single chip, the MCU can easily change the parameters of analog circuits in real time and monitor and respond to situations in ways that were previously impossible or even more difficult to implement with existing circuitry.

[0107] Figure 12An interrupt signal alert logic circuit 1200 according to an embodiment of the present disclosure is depicted, utilizing some flags and masks stored in register bit 1106. The interrupt signal alert logic circuit 1200 includes several interrupt AND gates (each input to both a given flag bit and a corresponding mask bit) and several interrupt OR gates (their combination into individual AND gate outputs). A first interrupt AND gate 1202 has a first interrupt input coupled to the sleep timer wake-up flag SLP_DONE, a second interrupt input coupled to the reciprocal of the sleep timer wake-up interrupt mask SLP_DONEM, and an interrupt output; a second interrupt AND gate 1204 has a first interrupt input coupled to the VCC low warning flag VCCLOW, a second interrupt input coupled to the reciprocal of the VCC low warning interrupt mask VCCLOWM, and an interrupt output; a third interrupt AND gate 1206 has a first interrupt input coupled to the MCU LDO power good error flag MCULDO_ERR, a second interrupt input coupled to the MCU... The fourth interrupt AND gate 1208 has a first interrupt input coupled to the thermal shutdown error flag OTS_ERR, a second interrupt input coupled to the second interrupt of the thermal shutdown error interrupt mask OTS_ERRM, and an interrupt output; the fifth interrupt AND gate 1210 has a first interrupt input coupled to the thermal warning flag OTS_WRN, a second interrupt input coupled to the second interrupt of the thermal warning interrupt mask OTS_WRNM, and an interrupt output; the sixth interrupt AND gate 1212 has a first interrupt input coupled to the boost activity monitoring flag BST_nACT, a second interrupt input coupled to the second interrupt of the boost activity monitoring interrupt mask BST_nACTM, and an interrupt output; and the seventh interrupt AND gate 1214 has a first interrupt input coupled to the boost converter power good error flag BST_ERR, a second interrupt input coupled to the second interrupt of the boost converter power good interrupt mask BST_ERRM, and an interrupt output.

[0108] The first interrupt OR gate 1216 has a first interrupt input coupled to the interrupt output of the first interrupt AND gate 1202, a second interrupt input coupled to the interrupt output of the second interrupt AND gate 1204, a third interrupt input coupled to the interrupt output of the third interrupt AND gate 1206, and an interrupt output. Similarly, the second interrupt OR gate 1218 has a first interrupt input coupled to the output of the fifth interrupt AND gate 1210, a second interrupt input coupled to the output of the sixth interrupt AND gate 1212, a third interrupt input coupled to the interrupt output of the seventh interrupt AND gate 1214, and an interrupt output. The third interrupt OR gate 1220 has a first interrupt input coupled to the interrupt output of the first interrupt OR gate 1216, a second interrupt input coupled to the interrupt output of the fourth interrupt AND gate 1208, a third interrupt input coupled to the interrupt output of the second interrupt OR gate 1218, and an interrupt output selectively coupled to a general purpose I / O pin GPIO, an interconnect pin INT_MCU, or an MCU receive pin MCU_RX. It should be understood that although the interrupt procedure has been shown to be implemented by a specific logic gate, the same result can be achieved using other arrangements of logic gates.

[0109] Figure 13 A method 1300 for operating a smoke detection device according to an embodiment of the present disclosure is described. Figures 13A to 13E Possible additions to method 1300 are described. Method 1300 includes providing 1305 power to the SoC, which includes communication circuitry, analog sensor amplifier circuitry, and power regulator circuitry, upon startup. The SoC determines 1310 a first voltage to the MCU chip attached to the SoC. This determination may be made, for example, based on what is attached to a given pin on the SoC. The SoC then provides 1315 power to the MCU chip at the first voltage.

[0110] exist Figure 13A In the process, method 1300 can continue, in response to the initial activation of the MCU chip, the MCU chip writes the second voltage to a register in the SoC at 1320. Subsequently, the SoC supplies power to the MCU chip at 1325 using the second voltage. Figure 13B In this configuration, the MCU chip controls the actions on the SoC 1330 during its active period. At a certain moment, the MCU chip sends a sleep signal to the SoC 1335 and enters sleep mode. In response to receiving the sleep signal, the SoC enters sleep mode 1340. After a configurable time, the SoC sends a wake-up signal to the MCU chip 1345 and waits for commands from the MCU chip. In one embodiment, the configurable time is between 1 millisecond and 65 seconds (inclusive).

[0111] exist Figure 13CIn the SoC, the DC / DC boost converter with a 1350 power regulator circuit is either disabled or remains unchanged in sleep mode. The MCU LDO regulator, which also has a 1360 power regulator circuit, is either disabled or remains unchanged in sleep mode. The ability to disable circuitry within the SoC during sleep mode can be crucial when the smoke detection device operates on a low-voltage battery, but it is less critical when the smoke detection device receives power from a high-voltage source (e.g., AC mains) via an AC / DC converter or from a central alarm system via the VLINE power line.

[0112] exist Figure 13D In this configuration, each of the signaling line circuitry, interconnect circuitry, horn driver circuitry, carbon monoxide amplifier circuitry, and ionization amplifier circuitry is individually electronically configured (1365) to be enabled or disabled. This configurable SoC is used in specific types of smoke detection devices. Figure 13E In this process, the SoC detects warning conditions on the 1370 SoC and sends an interrupt related to the warning condition to the MCU chip via the 1375. As previously mentioned, the interrupt can be caused by conditions including (but not limited to) the following: boost regulator undervoltage, MCU-LDO output undervoltage, SoC substrate overtemperature, interconnect warnings, and SLC power warnings. Interconnect warnings can be any warning provided by the interconnect driver / receiver.

[0113] The applicant has disclosed a smoke detection device utilizing only two ICs: an MCU and a SoC. The SoC incorporates a power regulator circuit, sensor amplifier, horn driver circuit, and communication circuitry that operate under the control of the MCU. This high level of integration provides greater control over individual blocks on the SoC, improved error detection, and enhanced power control. The disclosed smoke detection device and SoC provide all the capabilities required by the 2020 UL regulations.

[0114] Although various embodiments have been shown and described in detail, the claims are not limited to any particular embodiment or instance. None of the foregoing detailed descriptions should be construed as implying that any particular component, element, step, action, or function is essential and therefore must be included within the scope of the claims. Unless expressly stated otherwise, reference to a singular element is not intended to mean "one and only one," but rather "one or more." All structural and functional equivalents of the elements of the foregoing embodiments known to those skilled in the art are expressly incorporated herein by reference and are intended to be covered by these claims. Therefore, those skilled in the art will recognize that the exemplary embodiments described herein can be practiced with various modifications and alterations within the spirit and scope of the appended claims.

Claims

1. A single-chip system-on-a-chip (SoC) for smoke detection, the SoC comprising: A power regulator circuit coupled to the power regulator pin of the SoC; Analog sensor amplifier circuits, each coupled to a group of corresponding pins of the SoC, wherein the first analog sensor amplifier circuit in the analog sensor amplifier circuit has a photoelectric amplifier circuit, a first LED driver and a second LED driver; as well as The digital core includes digital logic circuits, register bits, and a microcontroller unit (MCU) communication circuit. The MCU communication circuit is coupled to data pins, and the register bits are coupled to control or modify the operation of the power regulator circuit and the analog sensor amplifier circuit. Furthermore, the register bits are operable and can be written to by the MCU chip. The SoC is configured to enter a sleep mode together with the MCU chip in response to receiving a sleep signal from the MCU chip, and after a configurable time, send a wake-up signal to the MCU chip to wake up the MCU chip and wait for commands from the MCU chip.

2. The SoC of claim 1, wherein the SoC includes an interrupt signal warning logic circuit, the interrupt signal warning logic circuit having: The first interrupt AND gate has a corresponding first interrupt input coupled to a corresponding flag of a flag group, a corresponding second interrupt input coupled to a corresponding flag mask, and a corresponding interrupt output; The second interrupt AND gate has a corresponding first interrupt input coupled to a corresponding flag of the flag group, a corresponding second interrupt input coupled to a corresponding flag mask, and a corresponding interrupt output; as well as An interrupt signal is output, which is coupled to the interrupt output of the first interrupt AND gate and the interrupt output of the second interrupt AND gate.

3. The SoC according to claim 1, wherein: The MCU communication circuit is an I2C interface between integrated circuits coupled to the serial data pin and the serial clock pin; and The SoC includes a signaling line circuit SLC, which is coupled to an SLC receive pin, a first SLC transmit pin, a second SLC transmit pin, an MCU receive pin, a first MCU transmit pin, and a second MCU transmit pin.

4. The SoC of claim 2, wherein the flag group comprises at least one of a sleep timer wake-up flag, a VCC low warning flag, an MCU LDO power good error flag, a thermal shutdown error flag, a thermal warning flag, a boost activity monitoring flag, and a boost converter power good error flag.

5. The SoC of claim 1, wherein the analog sensor amplifier circuit further comprises an ionization amplifier circuit having: An ion low-dropout LDO regulator having an upper power input coupled to the output pin of a DC / DC boost converter and an output coupled to the output pin of an ion LDO; An ion input amplifier has an upper power input, an ion input non-inverting input, an ion input inverting input, and an ion input output. The upper power input is coupled to the ion LDO output pin, the ion input non-inverting input is coupled to the ion input pin through a filter, and the ion input inverting input is coupled to an ion protection pin. and An ion gain amplifier having an upper power input, an ion gain non-inverting input, an ion gain inverting input, and an ion gain output, wherein the ion gain inverting input is coupled to the output of the ion input amplifier via a resistor and the ion gain inverting input is coupled to the ion protection pin.

6. The SoC of claim 2, wherein the photoelectric amplifier circuit comprises: An optical input amplifier has an upper power input, an optical input non-inverting input, an optical input inverting input, an optical input enable input, and an optical input output. The optical input non-inverting input is coupled to the positive pin of a photodiode, the optical input inverting input is coupled to the negative pin of a photodiode, the optical input enable input is coupled to an optical input amplifier control bit, and the optical input output is coupled to the output pin of a photodiode. An optical gain amplifier has an upper power input, an optical gain non-inverting input, an optical gain inverting input, an optical gain enable input, and an optical gain output. The optical gain non-inverting input is coupled to the optical input and output, the optical gain inverting input is selectively coupled to an optical reference circuit, and the optical gain enable input is coupled to an optical gain amplifier control bit. and A first photoresistor, coupled between the optical gain output and the optical gain inverting input, is an adjustable resistor having a resistance controlled by an optical gain register.

7. The SoC of claim 1, wherein the analog sensor amplifier circuit further comprises a carbon monoxide (CO) amplifier circuit, the CO amplifier circuit having a CO transimpedance amplifier, the CO transimpedance amplifier including a CO non-inverting input, a CO amplifier enable input, a CO inverting input, and a CO output, the CO non-inverting input being coupled to a CO positive terminal pin, the CO inverting input being coupled to a CO negative terminal pin, the CO amplifier enable input being coupled to a CO amplifier enable bit, and the CO output being coupled to a CO output pin.

8. The SoC of claim 1, comprising: Interconnect driver / receiver circuitry, coupled between interconnects to MCU pins and interconnects to bus pins; and A horn driver circuit having a first horn driver input coupled to a horn feedback pin, a second horn driver input coupled to a horn threshold bit, a third horn driver input coupled to a horn block enable pin, a first horn driver output coupled to a horn silver terminal pin, and a second horn driver output coupled to a horn brass terminal pin.

9. The SoC of claim 1, comprising a signaling line circuit SLC, the SLC having: The SLC receiver circuit includes: An SLC comparator has a non-inverting input coupled to the SLC receive pin, an inverting input coupled to the ground plane via a voltage source, and an output; and An SLC OR gate has a first input coupled to the output of the SLC comparator, a second input coupled to the SLC AND gate, and an output coupled to the MCU receive pin. and SLC transmission circuit, which includes: The first SLC amplifier is coupled between the first MCU transmission pin and the first SLC transmission pin; A second SLC amplifier is coupled between a second MCU transmission pin and a second SLC transmission pin; and The SLC transmission enable bit is coupled to enable the first SLC amplifier and the second SLC amplifier.

10. A smoke detection device, comprising: A single-chip system-on-a-chip (SoC) includes: A power regulator circuit coupled to the power regulator pin of the SoC; Analog sensor amplifier circuits, each coupled to a group of corresponding pins of the SoC, wherein the first analog sensor amplifier circuit in the analog sensor amplifier circuit has a photoelectric amplifier circuit, a first LED driver and a second LED driver; as well as The digital core includes digital logic circuits, register bits, and a microcontroller unit (MCU) communication circuit. The MCU communication circuit is coupled to a data pin, and the register bits are coupled to control or modify the operation of the power regulator circuit and the analog sensor amplifier circuit. The register bits are operable to be written to by the MCU chip. Each of the sensors is coupled to a corresponding one in the analog sensor amplifier circuit; DC power supply, which is coupled to the power regulator circuit; as well as The MCU chip includes an upper power input, a digital processor, an analog-to-digital converter (ADC), a SoC communication circuit, and general-purpose I / O circuitry. The upper power input on the MCU chip is coupled to receive power from the power regulator circuit. The SoC is configured to enter a sleep mode together with the MCU chip in response to receiving a sleep signal from the MCU chip, and after a configurable time, send a wake-up signal to the MCU chip to wake up the MCU chip and wait for commands from the MCU chip.

11. The smoke detection device according to claim 10, wherein: The analog sensor amplifier circuit includes a carbon monoxide (CO) amplifier circuit and an ionization amplifier circuit; and The sensor includes any combination of ionization sensors, CO sensors, and photoelectric sensors.

12. The smoke detection device according to claim 11, wherein the MCU communication circuit and the SoC communication circuit utilize the I2C communication protocol between integrated circuits.

13. The smoke detection device of claim 11, comprising an interconnect I / O buffer operable to couple to the MCU chip and a signaling line circuit operable to couple to the MCU chip, wherein only one of the interconnect I / O buffer and the signaling line circuit functions in the smoke detection device.

14. The smoke detection device according to claim 13, wherein the power regulator circuit comprises a DC / DC boost converter, a pre-LDO regulator, an internal LDO regulator, a voltage divider, and an MCU LDO regulator, wherein the MCU LDO regulator is coupled to the upper power input of the MCU chip.

15. A method for performing smoke detection, comprising: During startup, power is supplied to the single-chip system SoC used for smoke detection, the SoC including communication circuitry, analog sensor amplifier circuitry, and power regulator circuitry; Determine the first voltage of the microcontroller unit (MCU) chip attached to the SoC; The SoC provides power to the MCU chip at the first voltage; The MCU chip sends a sleep signal to the SoC and enters sleep mode; In response to receiving the sleep signal, the SoC enters sleep mode; and After a configurable period of time, the SoC sends a wake-up signal to the MCU chip to wake up the MCU chip and wait for commands from the MCU chip.

16. The method of claim 15, further comprising: In response to the initial operation of the MCU chip, the MCU chip writes a second voltage into a register in the SoC; and The SoC provides power to the MCU chip using the second voltage.

17. The method of claim 15, comprising: The MCU chip controls the actions on the SoC during the operating period.

18. The method of claim 17, wherein the configurable time is between 1 millisecond and 65 seconds, including 1 millisecond and 65 seconds.

19. The method of claim 17, wherein the SoC entering sleep mode comprises: The DC / DC boost converter configured with the power regulator circuit is either disabled or remains unchanged in sleep mode; Configure the analog sensor amplifier circuit to be disabled or unchanged in sleep mode; and The MCU low-dropout LDO regulator configured in the power regulator circuit is either disabled or remains unchanged in sleep mode.

20. The method of claim 15, further comprising electronically configuring each of the signaling line circuit, interconnect circuit, horn driver circuit, carbon monoxide amplifier circuit, photoelectric amplifier circuit, and ionization amplifier circuit to be active or deactivated.

21. The method of claim 15, further comprising the SoC detecting an alarm condition and sending an interrupt regarding the alarm condition to the MCU chip, the alarm condition being selected from the group consisting of: the output of the boost regulator being undervoltage, the output of the MCU LDO being undervoltage, the substrate of the SoC being over-temperature, interconnect alarms, and SLC power alarms.

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