Selective mold placement and method of manufacture on integrated circuit (IC) packages

Abstract

An integrated circuit (IC) package to be included in a computing device can include a metallization structure with circuitry and / or other elements, such as capacitors or inductors, thereon. Pads for input / output (I / O) (or other) purposes can also be present at different locations on the metallization structure. Exemplary aspects of the present disclosure allow a mold material to be placed over the circuitry and / or other elements in a readily customizable configuration so as to allow I / O pads to be placed at any desired location on the metallization structure. Specifically, a masking material, such as tape, can be applied to portions of the metallization structure that contain I / O pads or otherwise have reason for no mold material thereon, prior to applying the mold material to the metallization structure. The mold material is applied, and the masking material is removed, taking unwanted mold material with it.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to U.S. Provisional Patent Application Serial No. 63 / 021908, filed May 8, 2020, entitled “SELECTIVE MOLD PLACEMENT ON PACKAGES AND METHODS OF FABRICATING,” the contents of which are incorporated herein by reference in their entirety.

[0003] This application also claims priority to U.S. Patent Application Serial No. 17 / 110837, filed December 3, 2020, entitled “SELECTIVE MOLD PLACEMENT ON INTEGRATED CIRCUIT (IC) PACKAGES AND METHODS OF FABRICATING,” the contents of which are incorporated herein by reference in their entirety. Technical Field

[0004] The techniques disclosed herein generally relate to placing mold material on top of components on a metallized structure (such as a printed circuit board (PCB)), wherein the components may be integrated circuit (IC) chips, active components, passive components, wafers, etc. Background Technology

[0005] Computing devices can utilize a variety of integrated circuits (ICs), inductors, capacitors, dies, and other components to achieve desired functionality. In many cases, these components are formed into a package, which is then sealed within a mold material to protect the component when mounted in the computing device. The mold material also aids in pick-and-place operations, provides thermal paths to assist in heat dissipation, or performs other functions. As package sizes continue to shrink, there are increasing challenges in providing the necessary geometry for signal input / output (I / O), test purposes, thermal purposes, power I / O purposes, or similar purposes, while simultaneously providing mold material over the component to be protected. Summary of the Invention

[0006] The aspects disclosed in the detailed description include selective die placement on integrated circuit (IC) packages and methods for manufacturing such packages. An IC package to be included in a computing device may include a metallized structure having circuitry and / or other components, such as capacitors or inductors. Pads for input / output (I / O) (or other) purposes may also be present at different locations on the metallized structure. Exemplary aspects of this disclosure allow die material to be placed over the circuitry and / or other components in an easily customizable configuration, allowing I / O pads to be placed at any desired location on the metallized structure. Specifically, a mask material, such as tape, may be applied to multiple portions of the metallized structure, which contain I / O pads or otherwise have no reason to have die material on them, prior to the application of die material to the metallized structure. The die material is applied, and the mask material is removed, removing the unwanted die material along with the mask material. This improved die placement flexibility allows for greater I / O pad placement flexibility, which in turn provides additional design options.

[0007] In this regard, on one hand, an IC package is disclosed. The IC package includes a mold material attached to a metallized structure, the mold material having at least three sides perpendicular to the metallized structure. Each of the at least three sides has a corresponding pad positioned adjacent to it.

[0008] In another aspect, an IC package is disclosed. The IC package includes components positioned on a metallized structure. The IC package also includes mask residue positioned on the metallized structure. The IC package further includes mold material positioned above the mask residue.

[0009] In another aspect, a method for manufacturing an IC package is disclosed. The method includes attaching a component to a metallized structure. The method also includes forming at least one pad on the metallized structure. The method further includes attaching a mask material over the at least one pad. The method also includes allowing mold material to flow over the component and the mask material. The method further includes cutting off the mold material adjacent to the edge of the mask material. The method also includes removing a portion of the mask material and any mold material above the mask material along the cut to expose at least one pad.

[0010] In another aspect, a process for manufacturing an IC package is disclosed. The process includes attaching a mask material to at least one pad on a metallized structure. The process also includes allowing a mold material to flow over the mask material. The process further includes cutting off the mold material adjacent to the edges of the mask material. The process also includes removing the mask material along with any mold material above the mask material to expose at least one pad.

[0011] In another aspect, an IC package is disclosed. The IC package includes a metallized structure. The IC package also includes components positioned on the metallized structure. The IC package further includes a mold material covering the components, the mold material being attached to the metallized structure and having at least three sides perpendicular to the metallized structure. The IC package also includes at least three pads on the metallized structure, the at least three pads not covered by the mold material, and a respective pad of the at least three pads being positioned adjacent to a respective side of the at least three sides. Attached Figure Description

[0012] Figure 1A This is a top plan view of a conventional integrated circuit (IC) package having a mold material above a portion of a metallized structure (such as a printed circuit board (PCB)) and having pads exposed on either side of the mold material for input / output (I / O) purposes;

[0013] Figure 1B yes Figure 1A Side view of the IC package;

[0014] Figure 2A This is a top plan view of an IC package having a mold material above a portion of a metallized structure such as a PCB, and pads for I / O purposes on at least three sides of the mold material.

[0015] Figure 2B yes Figure 2A A side view of an IC package, showing tape residue after the IC package has been manufactured according to an exemplary aspect of this disclosure;

[0016] Figure 3 The illustration is for manufacturing. Figure 2A and Figure 2B A flowchart illustrating an exemplary process for IC packaging, utilizing a mask to remove portions of the mold material;

[0017] Figures 4A to 4F The diagram shows Figure 3 The various steps of the process;

[0018] Figures 5A to 5C The illustration shows various IC package configurations on a metallized structure, including single-sided and double-sided packages with a custom mold material, as well as double-sided packages where both sides are customized.

[0019] Figures 6A to 6F The illustration shows various possible configurations of the mold material on one side of the metallized structure;

[0020] Figures 7A to 7E The diagram illustrates various connection types that can benefit from different configurations of mold materials;

[0021] Figures 8A to 8C The illustration shows the flexibility to provide different mold configurations by using straight or non-linear edges and discontinuous mold materials;

[0022] Figure 9 It can include Figure 2A , Figure 2B , Figures 4A to 4F , Figures 5A to 5C , Figures 6A to 6F , Figures 7A to 7E and Figures 8A to 8C An exemplary block diagram of a processor-based system in IC packaging; and

[0023] Figure 10 This is a block diagram of an exemplary wireless communication device including radio frequency (RF) components, wherein any component may include an IC package manufactured according to exemplary aspects of this disclosure. Detailed Implementation

[0024] Several exemplary aspects of this disclosure are now described with reference to the accompanying drawings. The word “exemplary” is used herein to mean “as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.

[0025] The aspects disclosed in the detailed description include selective die placement on integrated circuit (IC) packages and methods for manufacturing such packages. An IC package to be included in a computing device may include a metallized structure having circuitry and / or other components, such as capacitors or inductors. Pads for input / output (I / O) (or other) purposes may also be present at different locations on the metallized structure. Exemplary aspects of this disclosure allow die material to be placed over the circuitry and / or other components in an easily customizable configuration, allowing I / O pads to be placed at any desired location on the metallized structure. Specifically, a mask material, such as tape, may be applied to multiple portions of the metallized structure, which contain I / O pads or otherwise have no reason to have die material on them, prior to the application of die material to the metallized structure. The die material is applied, and the mask material is removed, removing the unwanted die material along with the mask material. This improved die placement flexibility allows for greater I / O pad placement flexibility, which in turn provides additional design options.

[0026] Before addressing selective die placement on IC packages according to exemplary aspects of this disclosure, refer to Figure 1A and Figure 1B This provides a brief overview of standard packaging and standard die placement. See below for reference. Figure 2A We begin to discuss selective die placement on IC packages according to this disclosure.

[0027] in this regard, Figure 1A This is a top plan view of IC package 100, which has a metallized or support structure such as PCB 102, on which mold material 104 is positioned. Mold material 104 covers and protects any of a variety of possible components, such as ICs, inductors, capacitors, active components, passive components, etc. Mold material 104 may be plastic and may be used for heat dissipation and to provide electrical insulation for components beneath it. IC package 100 also includes multiple pads for I / O or other purposes, referred to herein as I / O pads 106; it should be understood that these pads are not strictly limited to I / O purposes. Multiple I / O pads 106 may be arranged on either side 108 or 110 of mold material 104.

[0028] In use, such as Figure 1B As can be seen more clearly, the IC package 100 can be positioned such that the I / O pad 106 is on the bottom side 112 of the PCB 102 and ready to couple to a complementary connector on a system board within a computing device (not shown). In another aspect, the die material 104 can be fitted into a recess in such a system board.

[0029] In practice, most conventional flow molding techniques only allow pads (e.g., I / O pad 106) to be positioned on either side (or both sides) of the mold material 104. As package sizes continue to shrink and the number of pads continues to increase (especially with the advent of 5G telecommunications), limiting the area where pads can be placed may become unacceptable.

[0030] There exists a molding technique known as top-gated molding, which allows for the formation of a molding structure that enables the placement of a pad on two or more sides of the mold material (see, for example, U.S. Patent Application Publication No. 2015 / 0118802 assigned to NXP Semiconductors). However, top-gated molding produces a non-right-angle (i.e., 90-degree) draft angle (i.e., the angle between the horizontal substrate and the vertical molding material). Typically, this draft angle exceeds the true vertical direction by 10 degrees (e.g., less than 80 degrees or greater than 100 degrees, depending on which side is being measured from). This angle facilitates the ejection of molding material from the mold. However, even with this angle, top-gated molding typically requires ejector pins and may leave a gate or mold overflow in the mold.

[0031] Therefore, an exemplary aspect of this disclosure provides a manufacturing process that allows pads to be placed on at least three sides of mold material within an IC package, making different pad configurations possible without an ejector gate molding process. Consequently, the draft angle is closer to a true 90 degrees, and there is no mold gate or mold overflow. Furthermore, ejector pins are not required. For example, exemplary aspects of this disclosure allow the manufacture of products such as… Figure 2A and Figure 2B The IC package 200 shown in the diagram allows for the provision of I / O pads 202 adjacent to two or more sides (i.e., at least three) of the die material 204. Therefore, in addition to the first side 206 and the second side 208 of a metallized structure such as PCB 210, the I / O pads 202 can also be positioned on the third side 212 and the fourth side 214. Figure 2B As shown, this flexibility is made possible by mask material 216, the residue of which is retained along the outer edge of mold material 204. A draft angle 218 is formed between the metallized structure and the side surface of mold material 204. Draft angle 218 is a right angle and can therefore be considered to be formed by mutually perpendicular elements (i.e., the side surface of the mold material is perpendicular to the metallized structure). “Perpendicular” is defined herein as within 5 degrees of a true 90-degree angle (e.g., 85-95 degrees). Note that “adjacent” is defined herein as adjacent, but not necessarily contiguous. Thus, I / O pad 202A within the dashed box of the third side surface 212 is adjacent to the third side surface 217 of mold material 204, while pad 202B is not adjacent to the third side surface 217 but will be considered adjacent to the side surface 219 of mold material 204.

[0032] refer to Figure 3 A review of process 300 used to manufacture IC package 200 can help in understanding the flexibility of the process. Also refer to... Figures 4A to 4F To help understand process 300. In this respect, process 300 begins with the formation of metallized structure 400 (box 302, see...). Figure 4A Manufacturing stage 401A). The metallization structure 400 can be a PCB, an organic PCB, or other well-known materials. The metallization structure 400 can be large enough to manufacture multiple IC packages according to this disclosure. Components 402 are attached to the metallization structure 400 (box 304, see manufacturing stage 401A). Figure 4A In one exemplary aspect, component 402 may include one or more of a die, chip, wafer, inductor, capacitor, passive component, active component, etc. Additionally, I / O pads 404 (box 306, see box 306) may be created or exposed in portions of the metallized structure 400. Figure 4A ).

[0033] Continue to refer to Figure 3 Process 300 continues by attaching mask material 406 above any space on any I / O pad 404 and metallized structure 400 that does not require mold material (box 308, see box 308). Figure 4B Manufacturing stage 401B). In one exemplary aspect, mask material 406 may be a tape material, such as epoxy resin-based tape material or silicone resin-based tape material.

[0034] After the mask material 406 is fixed, the mold material 408 can be applied, such as by causing the mold material 408 to flow (box 310, see box 310). Figure 4C (Manufacturing stage 401C). As described above, the mold material 408 can be a free-flowing plastic material and can surround and seal the assembly 402. The mold material 408 can also conduct heat to aid heat dissipation, while also being an electrical insulator to prevent accidental short circuits.

[0035] The mold material 408 (see frame 312) can be cut along the dotted line 410. Figure 4D Manufacturing stage 401D). This cutting can be performed after initial partial curing, such as after curing in a molding machine or after curing in an oven. Dashed line 412 indicates the boundary of the different mold seals formed on the metallized structure 400. After the cutting along dashed line 410, the mold material 408A (box 314, see box 314) positioned on the mask material 406 can be removed. Figure 4E In manufacturing stage 401E, mold material 408B is left as a covering mold for the component 402 embedded therein. Furthermore, the I / O pad 404 is now exposed through the removal of mold material 408A. Finally, the IC package can be monolithically assembled (box 316, see...). Figure 4F During manufacturing stage 401F, an individual IC package 414 is left with exposed I / O pads 404 and components 402 embedded in residual mold material 408B. It should be understood that some small amounts of residual mask material 416 (also referred to herein as mask residue) may remain at the edges of the residual mold material 408B. Depending on the size of the IC package, this residual material can range from a few nanometers to a few micrometers.

[0036] Although the IC package 200 in Figure 2 and Figure 4F The IC package 414 is single-sided (because the components and die material are only present on one side of the PCB), but it should be understood that this disclosure is not limited thereto. Instead, as Figures 5A to 5C As shown, various configurations are possible. Therefore, Figure 5A The illustration shows an IC package 500 with mold material 502 and I / O pads 504 on the lower surface of a metallized structure such as PCB 506, leaving the upper surface "clean" with no additional components, mold material, or I / O pads. In contrast, Figure 5B The illustration shows an IC package 508 with a mold material 510 and I / O pads 512 on the lower surface of a metallized structure such as a PCB 514, but the upper surface 516 is completely covered by mold material 518 without I / O pads. Various components (not shown) may be inside the mold material 518. Figure 5CThe diagram shows a third variation in which the IC package 520 has mold materials 522A, 522B and I / O pads 524A, 524B on both sides of a metallized structure such as a PCB 526. Another variation (not shown) is similar to the IC package 508, but instead of the upper surface 516 being completely covered by mold material 518, there is no mold material at all; instead, multiple I / O pads are positioned on the upper surface 516.

[0037] Although Figure 2A The IC package 200 shows I / O pads 202 on four sides surrounding the periphery of the mold material 204, but this disclosure is not limited thereto. Instead, as Figures 6A-6F As shown, various configurations are possible by using a mask as described in process 300. For example, as... Figure 6A As shown, IC package 600A includes a metallized structure 602 partially covered by a mold material 604. The mold material 604 extends to edges 606A-606C of the metallized structure 602. However, the mold material 604 has a first mold edge 608 that does not extend to edge 606D of the metallized structure 602. In the exposed portion 610 of the metallized structure 602, an I / O pad 612 is provided for IC package 600A. Therefore, in IC package 600A, the I / O pad 612 is provided adjacent to only one edge of the mold material 604.

[0038] Figure 6B The illustration shows an IC package 600B, in which a metallized structure 614 is partially covered by a mold material 616. The mold material 616 extends to edges 618A and 618B of the metallized structure 614. However, the mold material 616 has two mold edges 620A and 620B that do not extend to edges 618C or 618D of the metallized structure 614. I / O pads 624 are provided for the IC package 600B in the exposed portion 622 of the metallized structure 614. Therefore, in the IC package 600B, the I / O pads 624 are provided adjacent to the two edges of the mold material 616.

[0039] Figure 6C The illustration shows an IC package 600C, in which a metallized structure 626 is partially covered by a mold material 628. The mold material 628 extends to only one edge 630A of the metallized structure 626. However, the mold material 628 has three mold edges 632A-632C that do not extend to edges 630B-630D of the metallized structure 626. I / O pads 636 are provided for the IC package 600C in the exposed portion 634 of the metallized structure 626. Therefore, in the IC package 600C, the I / O pads 636 are provided adjacent to only three edges of the mold material 628.

[0040] Figure 6DThe illustration shows an IC package 600D, in which a metallized structure 638 is partially covered by a mold material 640. The mold material 640 does not contact any edges 642A-642D of the metallized structure 638. That is, all edges 644A-644D of the mold material 640 are spaced apart from edges 642A-642D, such that I / O pads 646 are provided around the mold material 640.

[0041] Figure 6E The illustration shows an IC package 600E including a metallized structure 648, which has two regions 650A and 650B covered by a mold material 652. The mold material 652 may be adjacent to the edge of the metallized structure 648, but is not required to be. I / O pads 654 may be positioned on any exposed portion of the metallized structure 648.

[0042] Figure 6F The illustration shows an IC package 600F including a metallized structure 656, in which an area 658 is covered by a mold material 660. In addition to I / O pads 662 on the exposed portion of the metallized structure 656, an add-on component 664 can be mounted on the exposed portion of the metallized structure 656.

[0043] It should be understood that using mask material to remove mold material offers great flexibility in terms of mold material placement and the shape of the space available for I / O pads. As seen in the case of IC package 600F, this space can also be used for other components not intended to be located under the mold material.

[0044] Although the preceding diagrams assume the base pad to be an I / O pad, this disclosure is not limited thereto. Figures 7A to 7D As observed, various connectors can be found within IC packages 700A-700D, and the placement of these connectors is only constrained by the ability to cut and remove mold material. It should also be noted that although pads are generally referred to as I / O pads herein, these pads can be used for purposes other than signal paths. As noted, pads can be used for testing purposes, heat dissipation purposes, power I / O purposes, etc. Now turning to... Figure 7A , Figure 7A The connector 702 in the diagram can be a planar grid array (LGA) connector. Figure 7B Connector 704 in the diagram can be a ball grid array (BGA) connector. Note that balls can be applied to IC package 700B after the masking material is removed. Figure 7C Connector 706 in the diagram can be a pad-on solder (SOP) connector. Note that solder can be applied to IC package 700C before molding or after removing the mask material. Figure 7DConnectors 708 and 710 can be either female or male connectors, respectively. Note again that the connectors can be applied to the IC package 700D after the masking material is removed. Although in Figures 7A to 7D The diagrams show some specific connectors, but other connectors may be used without departing from this disclosure.

[0045] Figure 7E The illustration depicts a specific case where the IC package 700E has no pad. However, the mold material 712 covers the components (not shown) on the metallized structure 714 and can be shaped to fit within a specific recess on a system board or for other reasons. Alternatively and non-exclusively, the shape of the mold can be made to facilitate the pick-and-place process, including for orienting the package for placement, etc.

[0046] Figures 8A to 8C The illustrations illustrate additional flexibility in the mask materials of this disclosure. For example, in Figure 8A In this context, the mask material can be used to fabricate the straight edge 802 of the mold material 804 in the IC package 800A. Conversely, the mask material can be used to fabricate general straight shapes, curves, arc edges, bevels, ellipses, or other shapes, such as... Figure 8B The edges 806 and 808 of the mold material 810 in the IC package 800B are shown in the figure. Figure 8C The illustration shows an IC package 800C with a mold material 812 having a ring or nanoring shape, wherein a pad 814 is positioned inside the centrally exposed area, and a pad 816 is positioned outside the mold material 812. Similarly, the flexibility of this disclosure allows for different shapes and placements as needed or desired.

[0047] IC packages with selective die placement manufactured according to the aspects disclosed herein can be provided in or integrated into any processor-based device. Examples include, but are not limited to: set-top boxes, entertainment units, navigation devices, communication devices, fixed location data units, mobile location data units, Global Positioning System (GPS) devices, mobile phones, cellular phones, smartphones, Session Initiation Protocol (SIP) phones, tablet computers, tablet phones, servers, computers, portable computers, mobile computing devices, wearable computing devices (e.g., smartwatches, health or fitness trackers, glasses, etc.), desktop computers, personal digital assistants (PDAs), monitors, computer monitors, televisions, tuners, radios, satellite broadcasting, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, motor vehicles, vehicle components, avionics systems, drones, and multirotor aircraft.

[0048] in this regard, Figure 9The illustration shows an example of a processor-based system 900, which may include, for example... Figure 2A , Figure 2B , Figures 4A to 4F , Figures 5A to 5C , Figures 6A to 6F , Figures 7A to 7E and Figures 8A to 8C The IC packages shown are IC packages. In this example, the processor-based system 900 includes a processor 902 having one or more central processing units (CPUs) 904. The processor 902 may have a cache memory 906 coupled to the CPU 904 for fast access to temporarily stored data. The processor 902 is coupled to a system bus 910 and can couple master and slave devices included in the processor-based system 900 to each other. It is known that the processor 902 communicates with these other devices by exchanging address information, control information, and data information on the system bus 910. Although... Figure 9 Not shown in the diagram, but multiple system buses 910 may be provided, each forming a different architecture. For example, processor 902 may transmit bus transaction requests to memory system 912, which is an example of a slave device. Memory system 912 may include components included in an IC package (such as...) Figure 2A , Figure 2B , Figures 4A to 4F , Figures 5A to 5C , Figures 6A to 6F , Figures 7A to 7E and Figures 8A to 8C The memory structures or arrays shown in those examples.

[0049] Other master and slave devices can be connected to system bus 910. For example... Figure 9 As shown, these devices may include a memory system 912 and one or more input devices 916. Input devices 916 may include any type of input device, including but not limited to input keys, switches, voice processors, etc. These devices may also include one or more output devices 920 and one or more network interface devices 922. Output devices 920 may include any type of output device, including but not limited to audio, video, other visual indicators, etc. These devices may also include one or more display controllers 926. Network interface devices 922 may be any device configured to allow data to and from network 930. Network 930 may be any type of network, including but not limited to wired or wireless networks, private or public networks, local area networks (LANs), wireless local area networks (WLANs), wide area networks (WANs), and bluetext. TM Networks and the Internet. The network interface device 922 can be configured to support any type of communication protocol required.

[0050] The processor 902 can also be configured to access the display controller 926 via the system bus 910 to control information sent to one or more displays 932. The display controller 926 sends information to the displays 932 for display via one or more video processors 934, which process the information to be displayed into a format suitable for the displays 932. The displays 932 can include any type of display, including but not limited to cathode ray tube (CRT), liquid crystal display (LCD), plasma display, light-emitting diode (LED) display, etc.

[0051] Figure 10 The illustration shows an example of a wireless communication device 1000, which may be included in an IC package (such as...). Figure 2A , Figure 2B , Figures 4A to 4F , Figures 5A to 5C , Figures 6A to 6F , Figures 7A to 7E and Figures 8A to 8C The radio frequency (RF) components provided in those shown. As an example, wireless communication device 1000 may include any of the aforementioned devices or be provided in any of the aforementioned devices. Figure 10 As shown, the wireless communication device 1000 includes a transceiver 1004 and a data processor 1008. The data processor 1008 may include a memory (not shown) for storing data and program code. The transceiver 1004 includes a transmitter 1010 and a receiver 1012 supporting bidirectional communication. Typically, the wireless communication device 1000 may include any number of transmitters and / or receivers for any number of communication systems and frequency bands. All or part of the transceiver 1004 may be implemented on one or more analog ICs, RF ICs (RFICs), mixed-signal ICs, etc.

[0052] Transmitter 1010 or receiver 1012 can be implemented using either a superheterodyne architecture or a direct conversion architecture. In a superheterodyne architecture, the signal undergoes frequency conversion between RF and baseband in multiple stages; for example, for receiver 1012, it is converted from RF to intermediate frequency (IF) in one stage and then from IF to baseband in another stage. In a direct conversion architecture, the signal undergoes frequency conversion between RF and baseband in a single stage. Superheterodyne and direct conversion architectures can use different circuit blocks and / or have different requirements. Figure 10 In the wireless communication device 1000, the transmitter 1010 and the receiver 1012 are implemented using a direct conversion architecture.

[0053] In the transmission path, the data processor 1008 processes the data to be transmitted and provides I and Q analog output signals to the transmitter 1010. In the exemplary wireless communication device 1000, the data processor 1008 includes digital-to-analog converters (DACs) 1014(1) and 1014(2) for converting digital signals generated by the data processor 1008 into I and Q analog output signals, such as I and Q output currents, for further processing.

[0054] Within transmitter 1010, low-pass filters 1016(1) and 1016(2) filter the I and Q analog output signals, respectively, to remove unwanted signals caused by the previous digital-to-analog conversion. Amplifiers (AMPs) 1018(1) and 1018(2) amplify the signals from low-pass filters 1016(1) and 1016(2), respectively, and provide I and Q baseband signals. Upconverter 1020 upconverts the I and Q baseband signals using mixers 1024(1) and 1024(2) with the I and Q transmit (TX) local oscillator (LO) signals from TX LO signal generator 1022 to provide upconverted signal 1026. Filter 1028 filters upconverted signal 1026 to remove unwanted signals caused by frequency upconversion and noise in the receive band. Power amplifier (PA) 1030 amplifies the up-converted signal 1026 from filter 1028 to obtain the desired output power level and provide a transmit RF signal. The transmit RF signal is routed via duplexer or switch 1032 and transmitted via antenna 1034.

[0055] In the receiving path, antenna 1034 receives the signal transmitted by the base station and provides the received RF signal, which is routed through duplexer or switch 1032 and provided to low-noise amplifier (LNA) 1036. Duplexer or switch 1032 is designed to operate at a specific RX to TX duplexer frequency separation to isolate the RX signal from the TX signal. The received RF signal is amplified by LNA 1036 and filtered by filter 1038 to obtain the desired RF input signal. Down-conversion mixers 1040(1) and 1040(2) mix the output of filter 1038 with the I and Q received (RX) LO signals (i.e., LO_I and LO_Q) from RX LO signal generator 1042 to generate I and Q baseband signals. The I and Q baseband signals are amplified by AMPs 1044(1) and 1044(2) and further filtered by low-pass filters 1046(1) and 1046(2) to obtain I and Q analog input signals, which are then provided to data processor 1008. In this example, data processor 1008 includes analog-to-digital converters (ADCs) 1048(1) and 1048(2) for converting the analog input signals into digital signals for further processing by data processor 1008.

[0056] exist Figure 10 In the wireless communication device 1000, a TX LO signal generator 1022 generates I and Q TX LO signals for frequency up-conversion, while an RX LO signal generator 1042 generates I and Q RX LO signals for frequency down-conversion. Each LO signal is a periodic signal with a specific base frequency. A transmit (TX) phase-locked loop (PLL) circuit 1050 receives timing information from a data processor 1008 and generates control signals for adjusting the frequency and / or phase of the TX LO signals from the TX LO signal generator 1022. Similarly, a receive (RX) PLL circuit 1052 receives timing information from a data processor 1008 and generates control signals for adjusting the frequency and / or phase of the RX LO signals from the RX LO signal generator 1042.

[0057] Those skilled in the art will further understand that the various illustrative logic blocks, modules, circuits, and algorithms described in conjunction with the aspects disclosed herein can be implemented as electronic hardware, stored in memory or another computer-readable medium, and executed by a processor or other processing device, or a combination of both. As an example, the devices described herein can be employed in any circuit, hardware component, IC, or IC chip. The memory disclosed herein can be of any type and size and can be configured to store any type of information desired. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above generally according to their functionality. How such functionality is implemented depends on the specific application, design choices, and / or design constraints imposed on the system as a whole. Those skilled in the art can implement the described functionality in varying ways for each specific application, but such implementation decisions should not be construed as departing from the scope of this disclosure.

[0058] The various illustrative logic blocks, modules, and circuits described in conjunction with the aspects disclosed herein can be implemented or executed using a general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. The processor may be a microprocessor, but alternatively, it may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration).

[0059] The aspects disclosed herein can be embodied in hardware and instructions stored in that hardware, and can reside in, for example, random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of computer-readable medium known in the art. An exemplary storage medium is coupled to a processor such that the processor can read information from and write information to the storage medium. Alternatively, the storage medium can be integrated into the processor. The processor and storage medium can reside in an ASIC. The ASIC can reside in a remote station. Alternatively, the processor and storage medium can reside as discrete components in a remote station, base station, or server.

[0060] It should also be noted that the operational steps described in any exemplary aspect of this document are described to provide examples and discussion. The described operations can be performed in many different orders besides the order illustrated. Furthermore, the operations described in a single operational step can actually be performed in many different steps. Additionally, one or more operational steps discussed in the exemplary aspects can be combined. It should be understood that the operational steps illustrated in the flowcharts can be modified in many different ways, as will be apparent to those skilled in the art. Those skilled in the art will also understand that information and signals can be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the foregoing specification can be represented by voltage, current, electromagnetic waves, magnetic fields or particles, light fields or particles, or any combination thereof.

[0061] The prior description of this disclosure is provided to enable those skilled in the art to make or use it. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein can be applied to other variations. Therefore, this disclosure is not intended to be limited to the examples and designs described herein, but is consistent with the widest scope of the principles and novel features disclosed herein.

Claims

1. An integrated circuit (IC) package, comprising: Components; A mold material attached to a metallized structure and covering the component, the mold material having at least three sides including a first side, a second side, and a third side, wherein each of the at least three sides is perpendicular to the metallized structure; A first pad positioned adjacent to the first side; The second pad is positioned adjacent to the second side. A third pad is positioned adjacent to the third side so that each of the first pad, the second pad, and the third pad is not covered by the mold material; as well as Mask residue positioned on the top surface of the metallized structure, below the mold material, wherein there is no mask residue on the component or on the first pad, the second pad, or the third pad.

2. The integrated circuit (IC) package according to claim 1, wherein the metallization structure includes a printed circuit board (PCB).

3. The integrated circuit (IC) package of claim 1, wherein the component is selected from the group consisting of: chip, die, wafer, inductor, or capacitor.

4. The integrated circuit (IC) package according to claim 1, wherein the mold material comprises a linear shape.

5. The integrated circuit (IC) package according to claim 1, further comprising: The fourth side of the mold material, wherein each of the four sides of the mold material is perpendicular to the metallized structure.

6. The integrated circuit (IC) package of claim 1, wherein the first pad comprises a planar grid array (LGA) connector.

7. The integrated circuit (IC) package of claim 1, wherein the first pad comprises a ball grid array (BGA) connector.

8. The integrated circuit (IC) package of claim 1, wherein the first pad includes a male connector.

9. The integrated circuit (IC) package of claim 1, wherein the first pad includes a female connector.

10. The integrated circuit (IC) package of claim 1, wherein the first pad includes a solder on pad (SOP) connector.

11. The integrated circuit (IC) package of claim 1, wherein the integrated circuit (IC) package is integrated into a device selected from the group consisting of: set-top boxes, navigation devices, communication devices, fixed location data units, mobile location data units, computers, monitors, televisions, tuners, music players, video players, and vehicle components.

12. The integrated circuit (IC) package of claim 1, wherein the integrated circuit (IC) package is integrated into a device selected from the group consisting of: Global Positioning System (GPS) devices, cellular phones, Session Initiation Protocol (SIP) phones, servers, portable computers, desktop computers, digital music players, digital video players, motor vehicles, avionics systems, and unmanned aerial vehicles.

13. The integrated circuit (IC) package of claim 1, wherein the integrated circuit (IC) package is integrated into a device selected from the group consisting of: smartphones, mobile computing devices, radio devices, portable music players, portable digital video players, and multi-rotor aircraft.

14. The integrated circuit (IC) package of claim 1, wherein the integrated circuit (IC) package is integrated into a device selected from the group consisting of: entertainment units, mobile phones, wearable computing devices, computer displays, and satellite broadcasting.

15. The integrated circuit (IC) package of claim 1, wherein the integrated circuit (IC) package is integrated into a device selected from the group consisting of: tablet computers, tablet phones, personal digital assistants (PDAs), and digital video disc (DVD) players.

16. An integrated circuit (IC) package, comprising: Components and pads positioned on a metallized structure having a flat top surface; Mask residue positioned on the flat top surface of the metallized structure, wherein there is no mask residue on the component or the pad; as well as A mold material positioned above the mask residue, the mold material being parallel to the flat top surface such that the mask residue is sandwiched between the metallized structure and the mold material.

17. The integrated circuit (IC) package of claim 16, wherein the mask residue surrounds the component.

18. The integrated circuit (IC) package of claim 16, wherein the mask residue includes tape residue.

19. A method for manufacturing an integrated circuit (IC) package, the method comprising: Attach the components to the metallized structure; At least one pad is created on the metallized structure; A mask material, including adhesive tape, is attached above the at least one pad. The mold material flows over the component and the mask material; Cut the mold material adjacent to the edge of the mask material; as well as A portion of the mask material and any mold material above the mask material are removed along the cut to expose the at least one pad, wherein the remaining portion of the mask material remains on the top surface of the metallized structure, below the mold material.

20. The method of claim 19, further comprising providing the metallized structure.

21. The method of claim 20, wherein providing the metallization structure includes providing a printed circuit board (PCB) as the metallization structure.

22. The method of claim 19, wherein attaching the component comprises attaching a chip, a die, a wafer, an inductor, or a capacitor.

23. The method of claim 19, wherein attaching the tape material comprises attaching one of silicone-based or epoxy-based tape materials.

24. The method of claim 19 further comprises monolithizing the metallized structure to form a plurality of integrated circuit (IC) packages.

25. The method of claim 19, wherein cutting the mold material comprises cutting along a plurality of edges.

26. The method of claim 19, wherein cutting the mold material includes cutting straight edges.

27. The method of claim 19, wherein cutting the mold material includes cutting the arcuate edge.

28. The method of claim 19, wherein removing the portion of the mask material and any mold material above the mask material along the cut to expose the at least one pad comprises: A pad is exposed adjacent to at least three edges of the mold material.

29. A method for manufacturing an integrated circuit (IC) package, the method comprising: Components and pads are provided on the metallized structure; A masking material, comprising adhesive tape, is attached above at least one pad on the metallized structure, wherein the masking material is not placed on the assembly; The mold material flows over the mask material; Cut the mold material adjacent to the edge of the mask material; as well as The mask material, along with any mold material above it, is removed to expose the at least one pad, wherein a portion of the mask material remains on the flat top surface of the metallized structure, beneath the mold material.

30. An integrated circuit (IC) package, comprising: Metallized structure; Components positioned on the metallized structure; A mold material covering the component, the mold material being attached to the metallized structure and having at least three sides perpendicular to the metallized structure; At least three pads on the metallized structure, the at least three pads not covered by the mold material, and a corresponding pad of the at least three pads being positioned adjacent to a corresponding side of the at least three sides; as well as Tape residue positioned on top of the metallized structure and below the mold material, wherein no tape residue is present on the component or on any of the at least three pads.

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