Semiconductor device

Abstract

A semiconductor device includes a plurality of semiconductor elements electrically connected in parallel with each other, a pad portion in conduction with the plurality of semiconductor elements, and a terminal portion in conduction with the pad portion. The plurality of semiconductor elements are arranged along a first direction orthogonal to a thickness direction, as viewed in the thickness direction. The pad portion includes a closed region surrounded by three line segments connecting each two of a first vertex, a second vertex, and a third vertex not on the same straight line. The first vertex overlaps, as viewed in the thickness direction, with a semiconductor element of the plurality of semiconductor elements that is outermost at one side in the first direction. The second vertex overlaps, as viewed in the thickness direction, with a semiconductor element of the plurality of semiconductor elements that is outermost at the other side in the first direction. The third vertex is located, as viewed in the thickness direction, on a perpendicular bisector of a line segment connecting the first vertex and the second vertex.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices. Background Technology

[0002] A known semiconductor device includes power semiconductor elements such as MOSFETs (Metal Oxide Semiconductor Field-Effect Transistors) and IGBTs (Insulated Gate Bipolar Transistors). To achieve high capacity and high output, multiple semiconductor elements are sometimes connected in parallel (e.g., Patent Document 1). The semiconductor device described in Patent Document 1 includes: two semiconductor elements, a first terminal and a second terminal, a first connecting conductor and a second connecting conductor, and leads. In Patent Document 1, the two semiconductor elements are IGBTs. Each semiconductor element is mounted on the first connecting conductor, and the collector electrode of each semiconductor element is connected to the first connecting conductor. The first connecting conductor is connected to the first terminal. The first terminal is, for example, a collector terminal. Leads are attached to the emitter electrodes of each semiconductor element, and these leads are connected to the second connecting conductor. The second connecting conductor is connected to the second terminal. The second terminal is, for example, an emitter terminal.

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Application Publication No. 2009-148077 Summary of the Invention

[0006] The problem that the invention aims to solve

[0007] In the semiconductor device described in Patent Document 1, for example, there is a distance difference in the current path from the first terminal to each semiconductor element. This distance difference may cause unevenness in the magnitude of the current flowing in each semiconductor element. This unevenness is an important factor that leads to increased load on one semiconductor element and a shorter lifespan compared to the other semiconductor element.

[0008] In view of the above, one object of this disclosure is to provide a semiconductor device that can suppress uneven current flow in a plurality of semiconductor elements connected in parallel.

[0009] Solution for solving the problem

[0010] The semiconductor device disclosed herein includes: a plurality of first semiconductor elements electrically connected in parallel, each having a first element main surface and a first element back surface separated in the thickness direction; a bonding pad portion conductive to the plurality of first semiconductor elements; and a first terminal portion conductive to the bonding pad portion. Viewed in the thickness direction, the plurality of first semiconductor elements are arranged along a first direction orthogonal to the thickness direction. The bonding pad portion is formed to include a closed region enclosed by three line segments, which are formed by connecting every two of a first vertex, a second vertex, and a third vertex that are not on the same straight line. Viewed in the thickness direction, the first vertex overlaps with the first semiconductor element that is the outermost one on one side of the plurality of first semiconductor elements in the first direction. Viewed in the thickness direction, the second vertex overlaps with the first semiconductor element that is the outermost one on the other side of the plurality of first semiconductor elements in the first direction. Viewed in the thickness direction, the third vertex lies on the perpendicular bisector of the line segment connecting the first vertex and the second vertex.

[0011] The effects of the invention

[0012] According to the semiconductor device disclosed herein, deviations in the current flowing in a plurality of semiconductor elements connected in parallel can be suppressed. Attached Figure Description

[0013] Figure 1 This is a perspective view of the semiconductor device according to the first embodiment.

[0014] Figure 2 Is Figure 1 The resin components are omitted from the 3D diagram.

[0015] Figure 3 This is a top view showing the semiconductor device according to the first embodiment.

[0016] Figure 4 Is Figure 3 The top view shows the resin components represented by virtual lines.

[0017] Figure 5 Is Figure 4 The top view of the diagram uses virtual lines to represent the two input terminals and the output terminal.

[0018] Figure 6 It is Figure 5 A magnified partial view.

[0019] Figure 7 This is a front view showing the semiconductor device according to the first embodiment.

[0020] Figure 8 This is a bottom view showing the semiconductor device of the first embodiment.

[0021] Figure 9 This is a left-side view of the semiconductor device according to the first embodiment.

[0022] Figure 10 It is along Figure 5 A cross-sectional view of the X-ray.

[0023] Figure 11 This is a top view of the semiconductor device according to the second embodiment, and a diagram in which resin components are represented by virtual lines.

[0024] Figure 12 This is a top view of the semiconductor device according to the third embodiment, and the diagram shows two input terminals, an output terminal, and a resin component represented by virtual lines.

[0025] Figure 13 Is Figure 12 The main parts are extracted from the top view.

[0026] Figure 14 It is along Figure 12 A cross-sectional view of line XIV-XIV.

[0027] Figure 15 This is a top view of the semiconductor device according to the fourth embodiment, and the resin component is represented by a virtual line.

[0028] Figure 16 It is along Figure 15 A cross-sectional view of the XVI-XVI line. Detailed Implementation

[0029] Preferred embodiments of the semiconductor device of this disclosure will now be described with reference to the accompanying drawings. In the following description, the same or similar components will be denoted by the same symbols, and repeated descriptions will be omitted.

[0030] Figures 1-10 A semiconductor device A1 according to a first embodiment is shown. The semiconductor device A1 includes: a plurality of semiconductor elements 10, 20; a support substrate 30; a plurality of terminals; a plurality of connecting components; and a resin component 60. The plurality of terminals include: two input terminals 41, 42; an output terminal 43; a pair of control terminals 44A, 44B; and a pair of detection terminals 45A, 45B. The plurality of connecting components include: a plurality of gate leads 51; a plurality of detection leads 52; a pair of first connecting leads 53; a pair of second connecting leads 54; and a plurality of conductor plates 55.

[0031] Figure 1 This is a three-dimensional diagram representing semiconductor device A1. Figure 2 Is Figure 1 The resin component 60 is omitted from the 3D view. Figure 3This is a top view of semiconductor device A1. Figure 4 Is Figure 3 The resin component 60 is represented by a dashed line (double-dotted line) in the top view. Figure 5 Is Figure 4 The top view shows the two input terminals 41 and 42 and the output terminal 43 represented by virtual lines. Figure 6 It is Figure 5 A magnified partial view. Figure 7 This is the front view of semiconductor device A1. Figure 8 This is a bottom view showing semiconductor device A1. Figure 9 This is a side view (left side view) of semiconductor device A1. Figure 10 It is along Figure 5 A cross-sectional view of the X-ray.

[0032] For clarity, reference is made to three mutually orthogonal directions (x, y, and z). The z-direction is the thickness direction of semiconductor device A1. The x-direction is a top view of semiconductor device A1 (refer to...). Figure 3 The left and right directions in the diagram. The y-direction is the top view of semiconductor device A1 (see reference). Figure 3 The vertical direction is defined as follows: One side of the x-direction is designated x1, and the other side is designated x2. Similarly, one side of the y-direction is designated y1, and the other side is designated y2; one side of the z-direction is designated z1, and the other side is designated z2. In the following description, "top view" refers to viewing in the z-direction. The z-direction is an example of the "thickness direction," the x-direction is an example of the "second direction," and the y-direction is an example of the "first direction."

[0033] Multiple semiconductor elements 10, 20 are configured, for example, using a semiconductor material primarily composed of SiC (silicon carbide). This semiconductor material is not limited to SiC, but can also be Si (silicon), GaAs (gallium arsenide), or GaN (gallium nitride), and a wide-bandgap semiconductor material is preferred. Each semiconductor element 10, 20 is, for example, a MOSFET. Each semiconductor element 10, 20 is not limited to MOSFETs, but can also be other transistors, including field-effect transistors such as MISFETs (Metal-Insulator-Semiconductor FETs), bipolar transistors such as IGBTs. Each semiconductor element 10, 20 is an identical element and is, for example, an n-channel MOSFET. Each semiconductor element 10, 20 has a rectangular shape in top view, but is not limited to this.

[0034] Semiconductor device A1, for example, includes four semiconductor elements 10 and four semiconductor elements 20. Furthermore, the number of semiconductor elements 10 and 20 is not limited to this structure and can be varied according to the performance requirements of semiconductor device A1. Semiconductor device A1 is, for example, a half-bridge switching circuit. In this case, the semiconductor elements 10 constitute the upper arm circuit of semiconductor device A1, and the semiconductor elements 20 constitute the lower arm circuit of semiconductor device A1. The semiconductor elements 10 are electrically connected in parallel using the structure described later, and the semiconductor elements 20 are electrically connected in parallel using the structure described later. Additionally, the semiconductor elements 10 and 20 are connected in series to form a bridge circuit.

[0035] like Figure 10 As shown, each of the plurality of semiconductor elements 10 has a main surface 10a and a back surface 10b. In each semiconductor element 10, the main surface 10a and the back surface 10b are separated in the z-direction. The main surface 10a faces the z2 direction, and the back surface 10b faces the z1 direction. The main surface 10a is an example of a "first main surface", and the back surface 10b is an example of a "first back surface".

[0036] Each of the multiple semiconductor elements 10 includes: a main electrode 11, a control electrode 12, a back electrode 13, and an insulating film 14. For example... Figure 6 and Figure 10 As shown, a main surface electrode 11 and a control electrode 12 are disposed on the main surface 10a of the device. The main surface electrode 11 is, for example, a source electrode, through which source current flows. The control electrode 12 is, for example, a gate electrode, to which a gate voltage is applied to drive each semiconductor element 10. Viewed from above, the main surface electrode 11 is larger than the control electrode 12. Figure 6 In the example shown, the main electrode 11 is composed of a single region, but it can also be divided into multiple regions. For example... Figure 10 As shown, a back electrode 13 is disposed on the back side 10b of the device. The back electrode 13 is, for example, a drain electrode, through which drain current flows. The back electrode 13 is formed over approximately the entire surface of the back side 10b of the device. Figure 6 and Figure 10 As shown, an insulating film 14 is disposed on the main surface 10a of the device. The insulating film 14 has electrical insulation properties. Viewed from above, the insulating film 14 surrounds the main surface electrode 11 and the control electrode 12, thus insulating the main surface electrode 11 and the control electrode 12. The insulating film 14 is, for example, formed by sequentially stacking a SiO2 (silicon dioxide) layer, a SiN4 (silicon nitride) layer, and a polybenzoxazole layer, wherein the polybenzoxazole layer is the surface layer of each semiconductor device 10. The structure of the insulating film 14 is not limited to the above; for example, a polyimide layer may be stacked instead of a polybenzoxazole layer.

[0037] If a first drive signal (e.g., gate voltage) is input to the control electrode 12 (gate electrode), each semiconductor element 10 switches between an on state and an off state according to the first drive signal. This switching action between the on and off states is called a switching action. In the on state, current flows from the back electrode 13 (drain electrode) to the main electrode 11 (source electrode), and in the off state, no current flows.

[0038] like Figure 5 , Figure 6 and Figure 10 As shown, multiple semiconductor elements 10 are respectively mounted on the support substrate 30. Figure 5 In the example, multiple semiconductor elements 10 are arranged along the y-direction and separated from each other. Each semiconductor element 10 is electrically bonded to a support substrate 30 (conductive substrate 32A described later) via a conductive bonding material (not shown) (e.g., sintered metals such as sintered silver or sintered copper, metal paste materials such as silver or copper, or solder). When each semiconductor element 10 is bonded to the conductive substrate 32A, the back surface 10b of the element faces the conductive substrate 32A. Each semiconductor element 10 is an example of a "first semiconductor element". Furthermore, in each semiconductor element 10, the main surface electrode 11 is an example of a "first main surface electrode", the control electrode 12 is an example of a "first control electrode", and the back surface electrode 13 is an example of a "first back surface electrode".

[0039] like Figure 5 As shown, the plurality of semiconductor elements 10 includes two outer elements 10A and a plurality of inner elements 10B. The two outer elements 10A are the outermost ones in the y-direction of the plurality of semiconductor elements 10. The plurality of inner elements 10B are those sandwiched between the two outer elements 10A in the y-direction of the plurality of semiconductor elements 10. In this embodiment, since the semiconductor device A1 has four semiconductor elements 10, the number of inner elements 10B is two. In a structure different from that of semiconductor device A1, there are no inner elements 10B when the number of semiconductor elements 10 is two, and there is one inner element 10B when the number of semiconductor elements is three.

[0040] like Figure 10 As shown, each of the plurality of semiconductor elements 20 has a main surface 20a and a back surface 20b. In each semiconductor element 20, the main surface 20a and the back surface 20b are separated in the z-direction. The main surface 20a faces the z2 direction, and the back surface 20b faces the z1 direction. The main surface 20a is an example of a "second main surface", and the back surface 20b is an example of a "second back surface".

[0041] Each of the multiple semiconductor elements 20 includes: a main electrode 21, a control electrode 22, a back electrode 23, and an insulating film 24. For example... Figure 6 and Figure 10 As shown, a main electrode 21 and a control electrode 22 are disposed on the main surface 20a of the device. The main electrode 21 is, for example, a source electrode, through which source current flows. The control electrode 22 is, for example, a gate electrode, to which a gate voltage is applied to drive each semiconductor element 20. Viewed from above, the main electrode 21 is larger than the control electrode 22. Figure 6 In the example shown, the main electrode 21 is composed of a single region, but it can also be divided into multiple regions. For example... Figure 10 As shown, a back electrode 23 is disposed on the back side 20b of the device. The back electrode 23 is, for example, a drain electrode, through which drain current flows. The back electrode 23 is formed over approximately the entire surface of the back side 20b of the device. Figure 6 and Figure 10 As shown, an insulating film 24 is disposed on the main surface 20a of the component. The insulating film 24 has electrical insulation properties. Viewed from above, the insulating film 24 surrounds the main surface electrode 21 and the control electrode 22. The insulating film 24 insulates the main surface electrode 21 and the control electrode 22 on the main surface 20a of the component. The constituent material of the insulating film 24 is, for example, the same as that of the insulating film 14.

[0042] If a second drive signal (e.g., gate voltage) is input to the control electrode 22 (gate electrode), each semiconductor element 20 switches between an on state and an off state (i.e., performs a switching operation) according to the second drive signal. In the on state, current flows from the back electrode 23 (drain electrode) to the main electrode 21 (source electrode), and no current flows in the off state.

[0043] like Figure 5 , Figure 6 and Figure 10 As shown, multiple semiconductor elements 20 are respectively mounted on the support substrate 30. Figure 5 In the example, multiple semiconductor elements 20 are arranged along the y-direction and separated from each other. Viewed in the x-direction, each semiconductor element 20 overlaps with each semiconductor element 10. Each semiconductor element 20 is electrically bonded to a support substrate 30 (conductive substrate 32B described later) via a conductive bonding material (not shown) (e.g., sintered metals such as sintered silver or sintered copper, metal paste materials such as silver or copper, or solder). When each semiconductor element 20 is bonded to the conductive substrate 32B, the back surface 20b of the element faces the conductive substrate 32B. Each semiconductor element 20 is an example of a "second semiconductor element". Furthermore, in each semiconductor element 20, the main surface electrode 21 is an example of a "second main surface electrode", the control electrode 22 is an example of a "second control electrode", and the back surface electrode 23 is an example of a "second back surface electrode".

[0044] like Figure 5As shown, the plurality of semiconductor elements 20 includes two outer elements 20A and a plurality of inner elements 20B. The two outer elements 20A are the outermost ones in the y-direction of the plurality of semiconductor elements 20. The plurality of inner elements 20B are those sandwiched between the two outer elements 20A in the y-direction of the plurality of semiconductor elements 20. In this embodiment, since the semiconductor device A1 has four semiconductor elements 20, the number of inner elements 20B is two. In a structure different from that of semiconductor device A1, there are no inner elements 20B when there are two semiconductor elements 20, and there is one inner element 20B when there are three semiconductor elements.

[0045] The support substrate 30 supports a plurality of semiconductor devices 10 and 20. The support substrate 30 includes: a pair of insulating substrates 31A and 31B, a pair of conductive substrates 32A and 32B, a pair of insulating layers 33A and 33B, a pair of gate layers 34A and 34B, and a pair of detection layers 35A and 35B.

[0046] A pair of insulating substrates 31A and 31B are electrically insulating. The constituent material of each insulating substrate 31A and 31B is, for example, a ceramic with excellent thermal conductivity. AlN (aluminum nitride) is an example of such a ceramic. The insulating substrates 31A and 31B are not limited to ceramic; they can also be insulating resin sheets, etc. Each insulating substrate 31A and 31B is, for example, rectangular in plan view. Figure 5 and Figure 10 As shown, a pair of insulating substrates 31A and 31B are arranged in the x direction and separated from each other. Insulating substrate 31A is located on the x2 direction side of insulating substrate 31B.

[0047] like Figure 10 As shown, insulating substrates 31A and 31B each have a main surface 311 and a back surface 312. For each of the insulating substrates 31A and 31B, the main surface 311 and the back surface 312 are separated in the z-direction. The main surface 311 faces the z2 direction, and the back surface 312 faces the z1 direction. Regarding the main surface 311, a pair of conductive substrates 32A and 32B and a plurality of semiconductor elements 10 and 20 are covered by a resin component 60. The back surface 312 is as follows... Figure 8 It protrudes from the resin component 60 (the resin back surface 62 described later) as shown. The back surface 312 can be connected, for example, to a heat sink or the like not shown.

[0048] A pair of conductive substrates 32A and 32B are plate-shaped components made of metal. The metal is, for example, Cu (copper) or a Cu alloy. The pair of conductive substrates 32A and 32B are not limited to being made of metal; for example, they can also be structures in which metal layers (e.g., Cu, Al, etc.) are formed on both sides of the graphite in the thickness direction (z-direction). The pair of conductive substrates 32A and 32B, together with two input terminals 41 and 42 and an output terminal 43, constitute a conductive path to a plurality of semiconductor elements 10 and 20. Plating can be applied to the surface of each conductive substrate 32A and 32B in the z2 direction. Figure 5 and Figure 10 As shown, a pair of conductive substrates 32A and 32B are separated in the x-direction. Figure 5 and Figure 10 In the example, the conductive substrate 32A is located closer to the x2 direction than the conductive substrate 32B.

[0049] like Figure 10 As shown, conductive substrates 32A and 32B each have a main surface 321 and a back surface 322. For each of conductive substrates 32A and 32B, the main surface 321 and the back surface 322 are separated in the z-direction. The main surface 321 faces the z2 direction, and the back surface 322 faces the z1 direction.

[0050] like Figure 10 As shown, the conductive substrate 32A is bonded to the insulating substrate 31A via a bonding material (not shown). This bonding material can be conductive or insulating. With the conductive substrate 32A and the insulating substrate 31A bonded, the back surface 322 of the conductive substrate 32A faces the main surface 311 of the insulating substrate 31A. A plurality of semiconductor elements 10 are mounted on the main surface 321 of the conductive substrate 32A. Each semiconductor element 10 is bonded to the conductive substrate 32A via a conductive bonding material, and the back electrode 13 (drain electrode) of each semiconductor element 10 is conductive to the conductive substrate 32A. In this embodiment, the conductive substrate 32A is an example of a "first conductive component".

[0051] like Figure 10 As shown, the conductive substrate 32B is bonded to the insulating substrate 31B via a bonding material (not shown). This bonding material can be conductive or insulating. With the conductive substrate 32B and the insulating substrate 31B bonded, the back surface 322 of the conductive substrate 32B faces the main surface 311 of the insulating substrate 31B. A plurality of semiconductor elements 20 are mounted on the main surface 321 of the conductive substrate 32B. Each semiconductor element 20 is bonded to the conductive substrate 32B via a conductive bonding material, and the back electrode 13 (drain electrode) of each semiconductor element 20 is conductive to the conductive substrate 32B. In this embodiment, the conductive substrate 32B is an example of a "second conductive component".

[0052] A pair of insulating layers 33A and 33B are electrically insulating, and their constituent materials are, for example, glass epoxy resin. Figure 5 As shown, a pair of insulating layers 33A and 33B are strips extending in the y-direction. Figure 5 and Figure 10 As shown, the insulating layer 33A is bonded to the main surface 321 of the conductive substrate 32A. The insulating layer 33A is located in the x2 direction relative to the plurality of semiconductor elements 10. Figure 5 and Figure 10 As shown, insulating layer 33B is bonded to the main surface 321 of conductive substrate 32B. Insulating layer 33B is located in the x1 direction relative to the plurality of semiconductor elements 20. Insulating layer 33A insulates conductive substrate 32A, gate layer 34A and detection layer 35A, and insulating layer 33B insulates conductive substrate 32B, gate layer 34B and detection layer 35B.

[0053] A pair of gate layers 34A and 34B are conductive, and their constituent materials are, for example, copper or a copper alloy. Figure 5 As shown, each of the pair of gate layers 34A and 34B includes a strip-shaped portion 341 and a plurality of hook-shaped portions 342. The strip-shaped portion 341 is a strip-shaped portion in top view and extends in the y-direction. The plurality of hook-shaped portions 342 are portions protruding from the strip-shaped portion 341. Each gate layer 34A and 34B may also be composed only of the strip-shaped portion 341 without the plurality of hook-shaped portions 342. Figure 5 and Figure 10 As shown, gate layer 34A is disposed on insulating layer 33A. Gate layer 34A is bonded to a plurality of gate leads 51, and is connected to the control electrode 12 (gate electrode) of each semiconductor element 10 via each gate lead 51. Figure 5 and Figure 10 As shown, the gate layer 34B is disposed on the insulating layer 33B. The gate layer 34B is bonded to a plurality of gate leads 51 and is connected to the control electrode 22 (gate electrode) of each semiconductor element 20 via each gate lead 51.

[0054] A pair of detection layers 35A and 35B are conductive, and their constituent materials are, for example, copper or a copper alloy. Figure 5 As shown, a pair of detection layers 35A and 35B each include a strip-shaped portion 351 and a plurality of hook-shaped portions 352. The strip-shaped portion 351 is a strip-shaped portion in top view and extends in the y-direction. The plurality of hook-shaped portions 352 are portions protruding from the strip-shaped portion 351. Each detection layer 35A and 35B may also be composed only of the strip-shaped portion 351 without the plurality of hook-shaped portions 352. Figure 5 and Figure 10 As shown, both the detection layer 35A and the gate layer 34A are disposed on the insulating layer 33A. The detection layer 35A is bonded to a plurality of detection leads 52, and is connected to the main electrode 11 (source electrode) of each semiconductor element 10 via each detection lead 52. Figure 5 and Figure 10 As shown, the detection layer 35B and the gate layer 34B are both disposed on the insulating layer 33B. The detection layer 35B is bonded to a plurality of detection leads 52 and is connected to the main electrode 21 (source electrode) of each semiconductor element 20 via each detection lead 52.

[0055] like Figure 5 and Figure 10 As shown, the gate layer 34A and the detection layer 35A are arranged in the x-direction on the insulating layer 33A and are separated from each other. Figure 5 and Figure 10 In the example, the gate layer 34A is disposed in the x-direction closer to the plurality of semiconductor elements 10 than the detection layer 35A. That is, the gate layer 34A is located on the x1-direction side of the detection layer 35A. Furthermore, the arrangement of the gate layer 34A and the detection layer 35A in the x-direction can also be reversed. Additionally, as... Figure 5 and Figure 10 As shown, the gate layer 34B and the detection layer 35B are arranged in the x-direction on the insulating layer 33B and are separated from each other. Figure 5 and Figure 10 In the example, the gate layer 34B is disposed in the x-direction closer to the plurality of semiconductor elements 20 than the detection layer 35B. That is, the gate layer 34B is located on the x2 direction side of the detection layer 35B. Furthermore, the configuration of the gate layer 34B and the detection layer 35B in the x-direction can also be reversed.

[0056] The structure of the support substrate 30 is not limited to the examples described above. For example, two conductive substrates 32A and 32B can be bonded to an insulating substrate. That is, a pair of insulating substrates 31A and 31B can be formed integrally without separation. In addition, in order to improve the bonding strength with the heat sink, a metal layer can be formed on the back surface 312 of each insulating substrate 31A and 31B. Furthermore, the shape, size, and arrangement of each pair of insulating substrates 31A and 31B and the pair of conductive substrates 32A and 32B can be appropriately changed according to the number and arrangement of the plurality of semiconductor elements 10 and 20.

[0057] Multiple terminals are external terminals used when mounting the semiconductor device A1 onto a circuit board of electrical equipment, etc. As described above, the multiple terminals include: two input terminals 41 and 42, an output terminal 43, a pair of control terminals 44A and 44B, and a pair of detection terminals 45A and 45B. Each terminal is constructed of a metal plate. The metal plate is made of, for example, Cu or a Cu alloy. Each terminal is made of a material with a lower conductivity than the conductive substrates 32A and 32B. That is, the resistivity of each terminal is greater than the resistivity of the conductive substrates 32A and 32B. The multiple terminals are formed, for example, from identical lead frames.

[0058] Two input terminals 41 and 42 are supplied with a power supply voltage. For example, input terminal 41 is the positive terminal (P terminal), and input terminal 42 is the negative terminal (N terminal). Figures 1-4 As shown, the two input terminals 41 and 42 are located on the semiconductor device A1 in the x1 direction. The two input terminals 41 and 42 are separated from each other.

[0059] like Figure 4 As shown, the input terminal 41 includes a pad portion 411 and a terminal portion 412.

[0060] The solder pad portion 411 is covered by the resin component 60. For example... Figure 2 , Figure 4 , Figure 5 and Figure 10 As shown, the solder pad 411 is electrically bonded to the conductive substrate 32B via a conductive block 419. The material of the block 419 is not particularly limited; for example, it can be a composite material of Cu, Cu alloy, CuMo (copper-molybdenum), or CIC (Copper-Inver-Copper). The solder pad 411 is bonded to the block 419, and the block 419 is bonded to the conductive substrate 32B. The bonding between the solder pad 411 and the block 419, and the bonding between the block 419 and the conductive substrate 32B, can each be achieved using any method such as bonding with a conductive bonding material, laser bonding, or ultrasonic bonding. The bonding between the solder pad 411 and the conductive substrate 32B is not limited to the structure of the block 419; the solder pad 411 can also be bonded directly to the conductive substrate 32B by partially bending the solder pad 411.

[0061] Terminal portion 412 is exposed from resin component 60. For example... Figure 4 As shown, the terminal portion 412, viewed from above, extends from the resin component 60 in the x1 direction. The terminal portion 412, for example, is rectangular in plan view. Figure 4 and Figure 5 As shown, terminal portion 412 is located closer to the center of resin component 60 in the y-direction towards the y1-direction. Terminal portion 412 is an example of a "second terminal portion".

[0062] like Figure 4 As shown, the input terminal 42 includes a solder pad portion 421, a terminal portion 422, and a connecting portion 423. The solder pad portion 421, the terminal portion 422, and the connecting portion 423 are each plate-shaped and integrally formed.

[0063] The solder pad portion 421 is covered by the resin component 60. Because the solder pad portion 421 is covered by the resin component 60, the input terminal 42 is supported by the resin component 60. Figure 5 , Figure 6 and Figure 10As shown, the pad portion 421 is electrically bonded to the main surface electrode 11 of each semiconductor element 10 via a conductive bulk material 429. The material of the bulk material 429 is the same as that of the bulk material 419, such as a composite material of Cu, Cu alloy, CuMo, or CIC, but is not limited to these materials. The pad portion 421 is bonded to the bulk material 429, and the bulk material 429 is bonded to the main surface electrode 11 of each semiconductor element 10. The bonding between the pad portion 421 and the bulk material 429 can be achieved by any method, such as bonding with a conductive bonding material, laser bonding, or ultrasonic bonding. The bonding between the bulk material 429 and the main surface electrode 11 of each semiconductor element 10 is, for example, bonding with a conductive bonding material (solder, metal paste, or sintered metal, etc.). The pad portion 421 is, for example, rectangular in plan view. In plan view, the edges of the pad portion 421 along the x-direction overlap with the outer elements 10A and 20A. Viewed from above, the solder pad 421 spans the conductive substrate 32A and the conductive substrate 32B. For example... Figure 4 As shown, viewed from above, a portion of each of the multiple semiconductor elements 10 is exposed from the solder pad portion 421. That is, viewed from above, a portion of each semiconductor element 10 does not overlap with the solder pad portion 421.

[0064] like Figure 4 As shown, viewed from above, the solder pad portion 421 is formed to include the closed region R1. For ease of understanding, in Figure 4 The closed region R1 in the diagram depicts the point. The closed region R1 is enclosed by three line segments L12, L23, and L31. Line segment L12 connects the first vertex P1 and the second vertex P2. Line segment L23 connects the second vertex P2 and the third vertex P3. Line segment L31 connects the third vertex P3 and the first vertex P1. Viewed from above, the first vertex P1, the second vertex P2, and the third vertex P3 are not on the same straight line.

[0065] like Figure 4 As shown, viewed from above, the first vertex P1 overlaps with the outermost semiconductor element 10 (outer element 10A on the y1 direction side) among the plurality of semiconductor elements 10. For example, the first vertex P1 overlaps with the top-view center of the outer element 10A on the y1 direction side. Furthermore, the main electrode 11 of each semiconductor element 10 is connected to the pad portion 421 via each block 429, therefore the first vertex P1 can overlap with the top-view center of the block 429 to which the outer element 10A on the y1 direction side is bonded. Figure 4 As shown, viewed from above, the first vertex P1 overlaps with the conductive substrate 32A.

[0066] like Figure 4As shown, viewed from above, the second vertex P2 overlaps with the outermost semiconductor element 10 (outer element 10A on the y2 direction side) among the plurality of semiconductor elements 10. For example, the second vertex P2 overlaps with the top-view center of the outer element 10A on the y2 direction side. Furthermore, the main electrode 11 of each semiconductor element 10 is connected to the pad 421 via each block 429, therefore the second vertex P2 can overlap with the top-view center of the block 429 to which the outer element 10A on the y2 direction side is bonded. Figure 4 As shown, viewed from above, the second vertex P2 overlaps with the conductive substrate 32A.

[0067] like Figure 4 As shown, viewed from above, the third vertex P3 lies on the perpendicular bisector L0 of line segment L12. Additionally, as... Figure 4 As shown, viewed from above, the third vertex P3 is located on the abutting edge 421a of the solder pad portion 421. The abutting edge 421a is the portion (edge) of the solder pad portion 421 that, viewed from above, connects to the connecting portion 423 (the first portion 424 described later). Figure 4 As shown, when viewed from above, the third vertex P3 overlaps with the conductive substrate 32B.

[0068] Terminal portion 422 is exposed from resin component 60. For example... Figure 4 As shown, viewed from above, terminal portion 422 extends from resin component 60 in the x1 direction. Terminal portion 422 is, for example, rectangular in plan view. Terminal portion 422 is parallel to terminal portion 412 in the y-direction and overlaps with terminal portion 412 when viewed in the y-direction. In this embodiment, as... Figures 1-5 As shown, terminal portion 422 is located further towards the y2 direction than terminal portion 412. Figure 4 and Figure 5 As shown, terminal portion 422 is located closer to the center of resin component 60 in the y-direction towards the y2-direction. Terminal portion 422 is an example of a "first terminal portion".

[0069] The connecting portion 423 connects the solder pad portion 421 and the terminal portion 422. The connecting portion 423 is partially bent. The connecting portion 423 includes a first portion 424, a second portion 425 and a third portion 426.

[0070] The first part 424 is connected to the solder pad part 421 (abutment edge 421a). The first part 424 is rectangular when viewed from above, and... Figure 4 In the example, it is a strip extending in the x-direction. The first part 424 extends in the x-direction from the central portion in the y-direction of the end edge on the x1-direction side of the solder pad part 421. The first part 424 has a smaller dimension in the y-direction compared to the solder pad part 421. Figure 4As shown, viewed from above, the first part 424 overlaps with the vertical bisector L0. The first part 424 has a pair of end edges 424a. The pair of end edges 424a are respectively connected to the pad portion 421 and extend from the pad portion 421 in the x1 direction. Viewed in the x direction, the pair of end edges 424a are respectively located on two inner components 10B. When the number of inner components 10B is one, viewed in the x direction, the pair of end edges 424a are respectively located on that one inner component 10B.

[0071] The second part 425 is connected to the first part 424 and the third part 426. The second part 425 extends in the y direction from the end of the end edge 424a on the y2 direction side of the first part 424 on the x1 direction side. The second part 425 is strip-shaped when viewed from above. In addition, in order to suppress the positional displacement of the input terminal 42, an insulating block material sandwiched between the second part 425 and the conductive substrate 32B can be disposed.

[0072] The third part 426 is connected to the second part 425 and the terminal part 422. The third part 426 extends in the x direction from the y2 direction side portion of the end edge of the second part 425 in the x1 direction direction. The y-direction dimension of the third part 426 is approximately the same as the y-direction dimension of the terminal part 422.

[0073] Output terminal 43 is a terminal for outputting AC power (voltage) or DC power (voltage) that has undergone power conversion through multiple semiconductor elements 10 and 20. For example... Figures 1-4 As shown, the output terminal 43 is located in the semiconductor device A1 in the x2 direction. The output terminal 43 includes a pad portion 431 and a terminal portion 432.

[0074] The solder pad portion 431 is covered by the resin component 60. For example... Figure 2 , Figure 4 , Figure 5 and Figure 10 As shown, the solder pad 431 is electrically bonded to the conductive substrate 32A via a conductive block 439. The material of the block 439 is the same as that of the blocks 419 and 429, such as Cu, Cu alloys, CuMo composites, CIC composites, etc., but is not limited to these materials. The solder pad 431 is bonded to the block 439, and the block 439 is bonded to the conductive substrate 32A. The bonding of the solder pad 431 to the block 439 and the bonding of the block 439 to the conductive substrate 32A can each be achieved by any method, such as bonding using a conductive bonding material, laser bonding, or ultrasonic bonding. The bonding of the solder pad 431 to the conductive substrate 32A is not limited to the structure of the block 439; it can also be achieved by partially bending the solder pad 431 to directly bond it to the conductive substrate 32A.

[0075] Terminal portion 432 is exposed from resin component 60. For example... Figure 4 As shown, terminal portion 432 extends from resin component 60 in the x2 direction. Terminal portion 432 is rectangular in plan view, for example. Terminal portion 432 is an example of a "third terminal portion".

[0076] A pair of control terminals 44A and 44B and a pair of detection terminals 45A and 45B are arranged, for example, along the x-direction. The control terminals 44A and 44B and the detection terminals 45A and 45B are approximately identical in shape. Viewed in the x-direction, the control terminals 44A and 44B and the detection terminals 45A and 45B each appear L-shaped. Figure 9 As shown, when viewed in the x-direction, a pair of control terminals 44A and 44B and a pair of detection terminals 45A and 45B overlap. Figure 5 and Figure 6 As shown in the figure, viewed from above, the control terminal 44A and the detection terminal 45A are adjacent in the y-direction of the conductive substrate 32A; Figure 5 and Figure 6 As shown, viewed from above, the control terminal 44B and the detection terminal 45B are adjacent in the y-direction of the conductive substrate 32B. A pair of control terminals 44A, 44B and a pair of detection terminals 45A, 45B protrude from, for example, the surface of the resin component 60 facing the y1 direction (the resin side surface 633 described later).

[0077] like Figure 5 and Figure 6 As shown, a pair of control terminals 44A and 44B are respectively connected to a pair of gate layers 34A and 34B via a first connecting lead 53. A first drive signal (gate voltage) for driving the plurality of semiconductor elements 10 is input at control terminal 44A. Therefore, regarding control terminal 44A, a second drive signal (gate voltage) for driving the plurality of semiconductor elements 20 is input at control terminal 44B, the terminal for inputting the first drive signal. Therefore, control terminal 44B is the terminal for inputting the second drive signal.

[0078] like Figure 6 As shown, each of the pair of control terminals 44A and 44B includes a pad portion 441 and a terminal portion 442. For each control terminal 44A and 44B, the pad portion 441 is covered by a resin component 60. This structure allows each control terminal 44A and 44B to be supported by the resin component 60. The terminal portion 442 is connected to the pad portion 441 and protrudes from the resin component 60. Each control terminal 44A and 44B is bent at the terminal portion 442.

[0079] like Figure 5 and Figure 6As shown, a pair of detection terminals 45A and 45B are respectively connected to a pair of detection layers 35A and 35B via a second connecting lead 54. The voltage (corresponding to the source current) applied to each main electrode 11 of the plurality of semiconductor elements 10 is detected from the detection terminal 45A. Therefore, the detection terminal 45A is the source signal detection terminal for the plurality of semiconductor elements 10. The voltage (corresponding to the source current) applied to each main electrode 21 of the plurality of semiconductor elements 20 is detected from the detection terminal 45B. Therefore, the detection terminal 45B is the source signal detection terminal for the plurality of semiconductor elements 20.

[0080] like Figure 6 As shown, a pair of detection terminals 45A and 45B each include a pad portion 451 and a terminal portion 452. For each detection terminal 45A and 45B, the pad portion 451 is covered by a resin component 60. This structure allows each detection terminal 45A and 45B to be supported by the resin component 60. The terminal portion 452 is connected to the pad portion 451 and protrudes from the resin component 60. Each detection terminal 45A and 45B is bent at the terminal portion 452.

[0081] Multiple connecting components enable conduction between two separate components. As described above, the multiple connecting components include: multiple gate leads 51, multiple detection leads 52, a pair of first connecting leads 53, a pair of second connecting leads 54, and multiple conductor plates 55.

[0082] The plurality of gate leads 51, the plurality of detection leads 52, the pair of first connection leads 53, and the pair of second connection leads 54 are respectively called bonding leads. The constituent materials of each of the plurality of gate leads 51, the plurality of detection leads 52, the pair of first connection leads 53, and the pair of second connection leads 54 can be, for example, any of Al, Au, Cu, and their alloys. The plurality of conductor plates 55 are respectively conductive plate-shaped components. The constituent materials of each of the plurality of conductor plates 55 can be, for example, Cu, Cu alloys, CuMo composites, or CIC composites, but are not limited to these materials.

[0083] like Figure 5 and Figure 6 As shown, one end of each of the plurality of gate leads 51 is connected to either the control electrode 12 of each semiconductor element 10 or the control electrode 22 of each semiconductor element 20, and the other end is connected to either one of a pair of gate layers 34A, 34B. Figure 5 As shown, the other end of each gate lead 51 is suitably engaged with the hook portion 342. Among the plurality of gate leads 51 are: leads for connecting the control electrode 12 of each semiconductor element 10 to the gate layer 34A; and leads for connecting the control electrode 22 of each semiconductor element 20 to the gate layer 34B.

[0084] like Figure 5 and Figure 6 As shown, one end of each of the plurality of detection leads 52 is bonded to either the main surface electrode 11 of each semiconductor element 10 or the main surface electrode 21 of each semiconductor element 20, and the other end is bonded to either one of a pair of detection layers 35A, 35B. Figure 5 As shown, the other end of each detection lead 52 is suitably engaged with the hook portion 352. Among the plurality of detection leads 52 are: leads for connecting the main surface electrode 11 of each semiconductor element 10 to the detection layer 35A; and leads for connecting the main surface electrode 21 of each semiconductor element 20 to the detection layer 35B.

[0085] like Figure 5 and Figure 6 As shown, regarding one of the pair of first connection leads 53, one end is connected to the gate layer 34A, and the other end is connected to the control terminal 44A. Thus, the gate layer 34A and the control terminal 44A are connected via this first connection lead 53. Figure 5 and Figure 6 As shown, regarding the other end of the pair of first connection leads 53, one end is connected to the gate layer 34B, and the other end is connected to the control terminal 44B. Thus, the gate layer 34B and the control terminal 44B are connected via the first connection leads 53. Each second connection lead 54 is connected to the side of the strip portion 351 of each detection layer 35A, 35B that is close to each detection terminal 45A, 45B in the y-direction.

[0086] like Figure 5 and Figure 6 As shown, regarding one of the pair of second connecting leads 54, one end is connected to the detection layer 35A, and the other end is connected to the detection terminal 45A. Thus, the detection layer 35A and the detection terminal 45A are made conductive via the second connecting lead 54. Figure 5 and Figure 6 As shown, regarding the other side of the pair of detection leads 52, one end is engaged with the detection layer 35B, and the other end is engaged with the detection terminal 45B. Thus, the detection layer 35B and the detection terminal 45B are connected via the second connecting lead 54. Each second connecting lead 54 is engaged with the side of the strip portion 351 of each detection layer 35A, 35B that is close to the detection terminal 45A, 45B in the y-direction.

[0087] like Figure 5 , Figure 6 and Figure 10 As shown, multiple conductor plates 55 respectively connect the main electrode 21 of each semiconductor element 20 to the conductive substrate 32A. Each conductor plate 55 includes a pair of junctions 551 and 552.

[0088] In each conductor plate 55, the bonding portion 551 is bonded to the main electrode 21 of each semiconductor element 20 via a conductive bonding material (not shown) (e.g., solder, metal paste, or sintered metal). The bonding portion 552 is bonded to the conductive substrate 32A via a conductive bulk material 559. The constituent material of each bulk material 559 may be, for example, Cu, Cu alloy, CuMo composite material, CIC composite material, etc., but is not limited to these materials. The bonding portion 552 is bonded to the bulk material 559, and the bulk material 559 is bonded to the conductive substrate 32A. The bonding of the bonding portion 552 to the bulk material 559, and the bonding of the bulk material 559 to the conductive substrate 32A, can each be achieved by any method such as bonding using a conductive bonding material, laser bonding, or ultrasonic bonding. The bonding of the bonding portion 552 to the conductive substrate 32A is not limited to the structure of the block material 559. The bonding portion 552 can also be directly bonded to the conductive substrate 32A by partially bending the bonding portion 552 or by forming the bonding portion 552 to be thicker than the bonding portion 551.

[0089] like Figure 1 and Figures 3 to 10 As shown, the resin component 60 covers: a plurality of semiconductor elements 10, 20; a support substrate 30 (except for the back surfaces 312 of each of the pair of insulating substrates 31A, 31B); portions of a plurality of terminals (two input terminals 41, 42, an output terminal 43, a pair of control terminals 44A, 44B, and a pair of detection terminals 45A, 45B); and a plurality of connecting components (a plurality of gate leads 51, a plurality of detection leads 52, a pair of first connection leads 53, a pair of second connection leads 54, and a plurality of conductor plates 55). The resin component 60 is made of, for example, epoxy resin. Figure 4 , Figure 5 and Figure 10 As shown, the resin component 60 has a resin main surface 61, a resin back surface 62, and a plurality of resin side surfaces 631 to 634.

[0090] like Figure 10 As shown, the resin main surface 61 and the resin back surface 62 are separated in the z-direction. The resin main surface 61 faces the z2 direction, and the resin back surface 62 faces the z1 direction. Figure 8 As shown, viewed from above, the resin back surface 62 is frame-shaped, surrounding the back surfaces 312 of a pair of insulating substrates 31A and 31B. The back surfaces 312 of the pair of insulating substrates 31A and 31B protrude from the resin back surface 62. Multiple resin side surfaces 631-634 are each connected to both the resin main surface 61 and the resin back surface 62, and are held by them in the z-direction. Figures 3-5 , Figure 7 and Figure 8As shown, resin side 631 and resin side 632 are separated in the x-direction. Resin side 631 faces the x1 direction, and resin side 632 faces the x2 direction. Two input terminals 41 and 42 protrude from resin side 631, and output terminal 43 protrudes from resin side 632. Figures 3-5 , Figure 8 and Figure 9 As shown, resin side 633 and resin side 634 are separated in the y-direction. Resin side 633 faces the y1 direction, and resin side 634 faces the y2 direction. Protruding from resin side 633 are a pair of control terminals 44A and 44B and a pair of detection terminals 45A and 45B.

[0091] like Figure 8 and Figure 10 As shown, the resin component 60 includes a recess 65 that is recessed in the z-direction from the resin back surface 62. As... Figure 8 As shown, viewed from above, the recess 65 is formed in a ring shape surrounding the support substrate 30. Furthermore, the shape, arrangement, and number of the recesses 65 are not limited to... Figure 8 and Figure 10 Example. Alternatively, the recess 65 may not be formed in the resin part 60.

[0092] The function and effect of semiconductor device A1 are as follows.

[0093] Semiconductor device A1 includes a pad portion 421 (input terminal 42) that is conductive to a plurality of semiconductor elements 10. The pad portion 421 is formed to include a closed region R1 enclosed by three line segments L12, L23, and L31. Line segment L12 is the line segment connecting the first vertex P1 and the second vertex P2, line segment L23 is the line segment connecting the second vertex P2 and the third vertex P3, and line segment L31 is the line segment connecting the third vertex P3 and the first vertex P1. Viewed from above, the first vertex P1 overlaps with the outermost semiconductor element 10 in the y1 direction (outer element 10A in the y1 direction) among the plurality of semiconductor elements 10. Viewed from above, the second vertex P2 overlaps with the outermost semiconductor element 10 in the y2 direction (outer element 10A in the y2 direction) among the plurality of semiconductor elements 10. Viewed from above, the third vertex P3 is located on the vertical bisector L0 of line segment L12. By employing this structure, a current path from each semiconductor element 10 to the third vertex P3 can be ensured on the pad portion 421. For points on the vertical bisector L0, the distance to the first vertex P1 and the distance to the second vertex P2 are essentially the same; therefore, the distance from the third vertex P3 to the first vertex P1 and the distance from the third vertex P3 to the second vertex P2 are also essentially the same. That is, path differences in the current path from each semiconductor element 10 to the third vertex P3 on the pad portion 421 can be suppressed. Therefore, in the semiconductor device A1, for the current from each semiconductor element 10 through the pad portion 421 to the terminal portion 422, uneven current flow among the multiple semiconductor elements 10 connected in parallel can be suppressed by ensuring a current path through the third vertex P3.

[0094] In semiconductor device A1, input terminal 42 includes a connecting portion 423 that connects pad portion 421 and terminal portion 422. Connecting portion 423 includes a first portion 424 that connects to pad portion 421, and the first portion 424 overlaps with the vertical bisector L0 when viewed from above. With this structure, when current flows from pad portion 421 to connecting portion 423, it first passes through the first portion 424. Assuming that the first portion 424 does not overlap with the vertical bisector L0 when viewed from above, there is a possibility that the current path from each semiconductor element 10 to terminal portion 422 may not pass through the third vertex P3. On the other hand, in semiconductor device A1, by making the first portion 424 overlap with the vertical bisector L0 when viewed from above, the current path from each semiconductor element 10 to terminal portion 422 can pass through the third vertex P3. Therefore, semiconductor device A1 can ensure the current path through the third vertex P3, thereby suppressing the unevenness of current flowing in the multiple semiconductor elements 10 connected in parallel.

[0095] In particular, in semiconductor device A1, the y-direction dimension of the first portion 424 is smaller than the y-direction dimension of the pad portion 421. With this structure, when current flowing through the pad portion 421 is input to the first portion 424, it is concentrated in the first portion 424. Therefore, for the current path from each semiconductor element 10 to the terminal portion 422, the path that does not pass through the third vertex P3 can be further reduced. Furthermore, the pair of end edges 424a of the first portion 424, viewed in the x-direction, are located on the two inner elements 10B respectively. With this structure, the contact portion between the first portion 424 (connecting portion 423) and the pad portion 421 is confined to a relatively narrow area, thus for the current path from each semiconductor element 10 to the terminal portion 422, the path that does not pass through the third vertex P3 can be further reduced.

[0096] In semiconductor device A1, gate layer 34A includes strip-shaped portions 341 and multiple hook-shaped portions 342. Furthermore, for each gate lead 51, one end of which is connected to each semiconductor element 10, the other end is appropriately connected to each hook-shaped portion 342. With this structure, the length of each signal path of the first drive signal used to drive the multiple semiconductor elements 10 connected in parallel is uniformized. Suppose that when the signal path of the first drive signal is uneven, driving is performed from the semiconductor element with the shorter signal path. In this case, the uneven driving state of the multiple semiconductor elements 10 connected in parallel can lead to overvoltage or overcurrent in a certain semiconductor element 10. Therefore, in semiconductor device A1, by uniformizing the length of the signal path of the first drive signal input to each semiconductor element 10, the driving state of each semiconductor element 10 can be uniformized compared to when multiple hook-shaped portions 342 are not provided in each gate layer 34A. The same applies to the relationship between the gate layer 34B and each semiconductor element 20.

[0097] Figure 11 Semiconductor device A2 according to the second embodiment is shown. Figure 11 This is a top view of semiconductor device A2, with resin component 60 indicated by a virtual line.

[0098] The difference between semiconductor device A2 and semiconductor device A1 lies in the top view shape of the solder pad portion 421 of the input terminal 42. Apart from this, semiconductor device A2 is constructed in the same manner as semiconductor device A1.

[0099] Viewed from above, the solder pad 421 in semiconductor device A2 is roughly triangular in shape. For example... Figure 11 As shown, a closed region R1 is also formed within the triangular solder pad portion 421. For ease of understanding, in Figure 11 The closed region R1 is depicted using points. Figure 11In the example, the solder pad 421 is formed along the closed region R1 when viewed from above.

[0100] In semiconductor device A2, similarly to semiconductor device A1, the pad portion 421 is formed to include a closed region R1. Therefore, like semiconductor device A1, semiconductor device A2 can ensure a current path through the third vertex P3 for the current from each semiconductor element 10 through the pad portion 421 to the terminal portion 422, thereby suppressing the unevenness of current flowing in the multiple semiconductor elements 10 connected in parallel.

[0101] Viewed from above, the entire area of ​​the pad portion 421 of the semiconductor device A2 is a closed region R1. With this structure, current flowing outside the closed region R1 can be suppressed within the pad portion 421. Therefore, the semiconductor device A2 can suppress unwanted current flow within the pad portion 421.

[0102] Figures 12-14 Semiconductor device A3 according to the third embodiment is shown. Figure 12 This is a top view of semiconductor device A3, with the resin component 60, two input terminals 41 and 42, and output terminal 43 indicated by virtual lines. Figure 13 Is Figure 12 The diagram shown is a top view with the main parts extracted. Figure 13 In, relative to Figure 12 As shown in the top view, the main components extracted are: multiple semiconductor elements 10, 20, a portion of the support substrate 30 (a pair of insulating substrates 31A, 31B, a pair of conductive substrates 32A, 32B), and multiple conductor plates 55, etc., while the following are omitted: a pair of insulating layers 33A, 33B, a pair of gate layers 34A, 34B, a pair of detection layers 35A, 35B, multiple gate leads 51, multiple detection leads 52, a pair of first connection leads 53, and a pair of second connection leads 54, etc. Figure 14 It is along Figure 12 A cross-sectional view of line XIV-XIV.

[0103] like Figures 12-14 As shown, the difference between semiconductor device A3 and semiconductor device A1 lies in the structure of the conductive substrate 32B. Apart from this, semiconductor device A3 is constructed in the same manner as semiconductor device A1.

[0104] Viewed from above, the conductive substrate 32B of the semiconductor device A3 has portions that are recessed inward in the y direction from a pair of end edges extending along the x direction. The conductive substrate 32B includes a pad portion 320a and a connecting portion 320b.

[0105] The solder pad portion 320a is the part that mounts multiple semiconductor components 20. Viewed from above, the solder pad portion 320a is rectangular. (The rest of the text appears to be unrelated and likely refers to a different topic.) Figure 13 As shown, viewed from above, the solder pad portion 320a is formed to include the closed region R2. For ease of understanding, in Figure 13 In the diagram, a closed region R2 is depicted using points. Region R2 is enclosed by three line segments L45, L56, and L64. Line segment L45 connects the first vertex P4 and the second vertex P5. Line segment L56 connects the second vertex P5 and the third vertex P6. Line segment L64 connects the third vertex P6 and the first vertex P4. Viewed from above, the first vertex P4, the second vertex P5, and the third vertex P6 are not collinear.

[0106] Viewed from above, the first vertex P4 overlaps with the outermost semiconductor element 20 (outer element 20A on the y1 direction side) among the plurality of semiconductor elements 20. For example, the first vertex P4 overlaps with the center of the outer element 20A on the y1 direction side when viewed from above. In this embodiment, since the back electrode 23 of the semiconductor element 20 is formed over approximately the entire area of ​​the back surface 20b of the semiconductor element 20, the first vertex P4 overlaps with the center of the back electrode 23 of the outer element 20A on the y1 direction side when viewed from above.

[0107] Viewed from above, the second vertex P5 overlaps with the outermost semiconductor element 20 (outer element 20A on the y2 direction side) among the plurality of semiconductor elements 20. For example, the second vertex P5 overlaps with the center of the outer element 20A on the y2 direction side when viewed from above. In this embodiment, since the back electrode 23 of the semiconductor element 20 is formed over approximately the entire area of ​​the back surface 20b of the semiconductor element 20, the second vertex P5 overlaps with the center of the back electrode 23 of the outer element 20A on the y2 direction side when viewed from above.

[0108] like Figure 13 As shown, viewed from above, the third vertex P6 lies on the perpendicular bisector L9 of line segment L45. Additionally, as... Figure 13 As shown, viewed from above, the third vertex P6 is located on the abutting edge 320z of the pad portion 320a. The abutting edge 320z is the portion (edge) of the pad portion 320a that connects to the connecting portion 320b (the first portion 320c described later) when viewed from above.

[0109] The connecting part 320b connects the solder pad part 320a and the input terminal 41. For example... Figure 12 and Figure 13 As shown, since the input terminal 41 is joined to the connecting portion 320b via the block 419, the connecting portion 320b connects the pad portion 320a and the terminal portion 412 (input terminal 41). Figure 13 As shown, the connecting part 320b includes a first part 320c and a second part 320d.

[0110] The first part 320c is connected to the solder pad part 320a. Viewed from above, the first part 320c is rectangular. The first part 320c extends in the x-direction from the central portion of the end edge of the solder pad part 320a on the x1 direction side. The first part 320c is smaller in the y-direction compared to the solder pad part 320a. For example... Figure 13 As shown, viewed from above, the first part 320c overlaps with the vertical bisector L9. The conductive substrate 32B is recessed in the manner described above through the first part 320c.

[0111] A block 419 is joined to the second part 320d. The second part 320d is connected to the first part 320c and is connected to the input terminal 41 via the block 419. The second part 320d is rectangular in plan view. The y-direction dimension of the second part 320d is larger than that of the first part 320c, for example, it is approximately the same as the y-direction dimension of the pad part 320a.

[0112] For the conductive substrate 32B, since the y-direction dimension of the first part 320c is smaller than the y-direction dimension of the pad part 320a and the second part 320d respectively, a portion that is recessed inward in the y-direction is formed as described above.

[0113] In semiconductor device A3, similarly to semiconductor devices A1 and A2, the pad portion 421 is formed to include a closed region R1. Therefore, like semiconductor devices A1 and A2, semiconductor device A3 can suppress the unevenness of current flowing through the multiple semiconductor devices 10 connected in parallel by ensuring the current path through the third vertex P3 for the current from each semiconductor element 10 through the pad portion 421 to the terminal portion 422.

[0114] In semiconductor device A3, conductive substrate 32B includes a pad portion 320a. The pad portion 320a is formed to include a closed region R2 enclosed by three line segments L45, L56, and L64. Line segment L45 connects the first vertex P4 and the second vertex P5, line segment L56 connects the second vertex P5 and the third vertex P6, and line segment L64 connects the third vertex P6 and the first vertex P4. Viewed from above, the first vertex P4 overlaps with the semiconductor element 20 located in the direction closest to y1 among the plurality of semiconductor elements 20. Viewed from above, the second vertex P5 overlaps with the semiconductor element 20 located in the direction closest to y2 among the semiconductor elements 20. The third vertex P6 is located on the vertical bisector L9 of line segment L45. With this structure, a current path, for example, from each semiconductor element 20 to the third vertex P6, can be ensured in the pad portion 320a. Therefore, in the semiconductor device A3, for the current from each semiconductor element 20 through the pad portion 320a to the terminal portion 412, the current path through the third vertex P6 can be ensured, thereby suppressing the unevenness of the current flowing in the multiple semiconductor elements 20 connected in parallel.

[0115] In semiconductor device A3, conductive substrate 32B includes a connecting portion 320b connected to pad portion 320a and terminal portion 412 (input terminal 41). Connecting portion 320b includes a first portion 320c connected to pad portion 320a, which overlaps with vertical bisector L9 when viewed from above. With this structure, when current flows from pad portion 320a to connecting portion 320b, it first passes through the first portion 320c. If the first portion 320c does not overlap with vertical bisector L9 when viewed from above, there is a possibility that the current path from each semiconductor element 20 to terminal portion 412 may not pass through the third vertex P6. On the other hand, in semiconductor device A3, by making the first portion 320c overlap with vertical bisector L9 when viewed from above, the current path from each semiconductor element 20 to terminal portion 412 can pass through the third vertex P6. Therefore, semiconductor device A3 can ensure a current path through the third vertex P6, thereby suppressing uneven current flow among the multiple semiconductor elements 20 connected in parallel. This structure is effective when the resistivity of the conductive substrate 32B is greater than that of the input terminal 42.

[0116] In particular, in semiconductor device A3, the y-direction dimension of the first portion 320c is smaller than that of the pad portion 320a. With this structure, when current flowing through the pad portion 320a is input to the first portion 320c, it is concentrated in the first portion 320c. Therefore, the current path from each semiconductor element 20 to the terminal portion 412 can be further reduced by avoiding the third vertex P6. Furthermore, the pair of edges of the first portion 320c, viewed in the x-direction, are located on the two inner elements 20B respectively. With this structure, the contact portion between the first portion 320c (connecting portion 320b) and the pad portion 320a is confined to a relatively narrow area, thus further reducing the current path from each semiconductor element 20 to the terminal portion 412 by avoiding the third vertex P6.

[0117] Figure 15 and Figure 16 Semiconductor device A4 according to the fourth embodiment is shown. Figure 15 This is a top view showing semiconductor device A4, with resin component 60 indicated by dashed lines. For ease of understanding, in Figure 15 The closed region R1 is depicted using points. Figure 16 It is along Figure 15 A cross-sectional view of the XVI-XVI line.

[0118] like Figure 15 As shown, the difference between semiconductor device A4 and semiconductor device A1 lies in the structure of the supporting substrate 30. Apart from this, semiconductor device A4 is constructed in the same manner as semiconductor device A1.

[0119] The support substrate 30 of semiconductor device A4 is a so-called DBC (Direct Bonded Copper) substrate. However, the support substrate 30 may also not be a DBC substrate, but rather a DBA (Direct Bonded Aluminum) substrate. Figure 15 As shown, the support substrate 30 of the semiconductor device A4 includes: an insulating substrate 36, a pair of main surface metal layers 37A and 37B and a back surface metal layer 38.

[0120] Like insulating substrates 31A and 31B, insulating substrate 36 is, for example, made of ceramic with excellent thermal conductivity. Insulating substrate 36 is, for example, rectangular in plan view. Figure 15 As shown, the insulating substrate 36 has a main surface 361 and a back surface 362. The main surface 361 and the back surface 362 are separated in the z-direction. The main surface 361 faces the z2 direction, and the back surface 362 faces the z1 direction.

[0121] like Figure 15As shown, a pair of main surface metal layers 37A and 37B are formed on the main surface 361 of the insulating substrate 36. In a structure where the support substrate 30 is a DBC substrate, the constituent material of each of the pair of main surface metal layers 37A and 37B is, for example, Cu. In a structure where the support substrate 30 is a DBA substrate, the constituent material is Al, not Cu. The pair of main surface metal layers 37A and 37B are separated in the x-direction. The main surface metal layer 37A is located on the x2 direction side of the main surface metal layer 37B. The main surface metal layer 37A, like the conductive substrate 32A, hosts a plurality of semiconductor elements 10. The main surface metal layer 37B, like the conductive substrate 32B, hosts a plurality of semiconductor elements 20. Each main surface metal layer 37A and 37B is thinner than each conductive substrate 32A and 32B. In this embodiment, the main surface metal layer 37A is an example of a "first conductive component," and the main surface metal layer 37B is an example of a "second conductive component."

[0122] A back metal layer 38 is formed on the back surface 362 of the insulating substrate 36. The material of the back metal layer 38 is the same as that of the main surface metal layers 37A and 37B. The back metal layer 38 may be covered by the resin component 60, or it may be exposed from the resin component 60 (resin back surface 62) with its z1-oriented surface.

[0123] The structure of the support substrate 30 of the semiconductor device A4 can be modified as follows. For example, instead of an insulating substrate 36, it can be divided into a pair of main surface metal layers 37A and 37B. That is, it can be divided into two insulating substrates in the same way as the semiconductor device A1, and a pair of main surface metal layers 37A and 37B can be formed on each insulating substrate. In addition, instead of a back surface metal layer 38, it can be divided into two back surface metal layers. In this case, viewed from top, the two back surface metal layers are separated in the x-direction and overlap with the pair of main surface metal layers 37A and 37B respectively. In addition, for example, the aforementioned pair of conductive substrates 32A and 32B can be mounted on the pair of main surface metal layers 37A and 37B respectively.

[0124] In semiconductor device A4, similarly to semiconductor devices A1 to A3, the pad portion 421 is formed to include a closed region R1. Therefore, like semiconductor devices A1 to A3, semiconductor device A4 can suppress the unevenness of current flowing through the multiple semiconductor devices 10 connected in parallel by ensuring the current path through the third vertex P3 for the current from each semiconductor element 10 through the pad portion 421 to the terminal portion 422.

[0125] The semiconductor device disclosed herein is not limited to the embodiments described above. The specific structure of each part of the semiconductor device disclosed herein can be freely modified in various ways. For example, the semiconductor device disclosed herein includes the following appended embodiments.

[0126] Postscript 1.

[0127] A semiconductor device comprising:

[0128] A plurality of first semiconductor elements electrically connected in parallel to each other, each having a first element main surface and a first element back surface separated in the thickness direction;

[0129] The bonding pad is conductive to the plurality of first semiconductor elements; and

[0130] The first terminal portion is in communication with the solder pad portion.

[0131] Viewed along the thickness direction, the plurality of first semiconductor elements are arranged along a first direction orthogonal to the thickness direction.

[0132] The solder pad portion is formed as a closed region consisting of three line segments, which are formed by connecting every two of the first, second, and third vertices that are not on the same straight line.

[0133] Viewed in the thickness direction, the first vertex overlaps with the outermost first semiconductor element on one side of the plurality of first semiconductor elements in the first direction.

[0134] Viewed in the thickness direction, the second vertex overlaps with the outermost first semiconductor element on the other side of the plurality of first semiconductor elements in the first direction.

[0135] Viewed in the thickness direction, the third vertex is located on the perpendicular bisector of the line segment connecting the first vertex and the second vertex.

[0136] Postscript 2.

[0137] Regarding the semiconductor device described in Appendix 1

[0138] It also includes a connecting portion that connects the solder pad portion to the first terminal portion.

[0139] The connecting portion includes a first portion that connects to the solder pad portion.

[0140] Viewed in the thickness direction, the first part overlaps with the vertical bisector.

[0141] Postscript 3.

[0142] Regarding the semiconductor device described in Appendix 2

[0143] The first portion has a pair of end edges that are separated from each other in the first direction and each extends along a second direction orthogonal to the thickness direction and the first direction.

[0144] Viewed in the thickness direction, each of the pair of end edges is connected to the pad portion.

[0145] Appendix 4.

[0146] Regarding the semiconductor device described in Appendix 3

[0147] Viewed in the thickness direction, both the solder pad portion and the first portion are rectangular.

[0148] The dimension of the first part in the first direction is smaller than that of the pad part.

[0149] Postscript 5.

[0150] Regarding the semiconductor device described in Appendix 3 or Appendix 4

[0151] The plurality of first semiconductor elements includes two inner elements located between a first semiconductor element that overlaps with the first vertex when viewed in the thickness direction and a first semiconductor element that overlaps with the second vertex when viewed in the thickness direction, and adjacent to each other sandwiching the vertical bisector.

[0152] Viewed in the second direction, the pair of end edges are located on the two inner elements respectively.

[0153] Postscript 6.

[0154] Regarding the semiconductor device mentioned in any one of Annexes 3 to 5

[0155] Viewed in the thickness direction, a portion of each of the plurality of first semiconductor elements does not overlap with the pad portion.

[0156] Postscript 7.

[0157] With respect to any one of Annexes 3 to 6, the semiconductor device

[0158] Each of the plurality of first semiconductor elements includes: a first main surface electrode formed on the main surface of the first element; and a first back surface electrode formed on the back surface of the first element.

[0159] The pad portion is located on the main surface of the first element in the thickness direction and is connected to the first main surface electrode of each of the plurality of first semiconductor elements.

[0160] Postscript 8.

[0161] Regarding the semiconductor device described in Appendix 7

[0162] It also includes a first conductive component, which carries the plurality of first semiconductor elements.

[0163] The first back electrode of each of the plurality of first semiconductor elements is coupled to the first conductive component.

[0164] Postscript 9.

[0165] Regarding the semiconductor device described in Appendix 8

[0166] The solder pad portion, the first terminal portion, and the connecting portion are each plate-shaped and integrally formed.

[0167] Postscript 10.

[0168] Regarding the semiconductor device described in Appendix 9

[0169] It also includes a plurality of second semiconductor elements electrically connected in parallel with each other, each of the plurality of second semiconductor elements having a second element main surface and a second element back surface separated in the thickness direction.

[0170] The plurality of first semiconductor elements are electrically connected in series with the plurality of second semiconductor elements.

[0171] Postscript 11.

[0172] Regarding the semiconductor device described in Appendix 10

[0173] It also includes a second conductive component, which carries the plurality of second semiconductor elements.

[0174] The first conductive component and the second conductive component are separated and side by side in the second direction.

[0175] Postscript 12.

[0176] Regarding the semiconductor device described in Appendix 11

[0177] Each of the plurality of second semiconductor elements includes: a second main surface electrode formed on the main surface of the second element; and a second back surface electrode formed on the back surface of the second element.

[0178] Postscript 13.

[0179] Regarding the semiconductor device described in Appendix 12

[0180] The second back electrode of each of the plurality of second semiconductor elements is coupled to the second conductive component.

[0181] Postscript 14.

[0182] Regarding the semiconductor device described in Appendix 13

[0183] It also includes multiple connecting components that enable the first conductive component to conduct to the second main surface electrode of each of the multiple second semiconductor elements.

[0184] Postscript 15.

[0185] The semiconductor device described in Appendix 14 further comprises:

[0186] The second terminal portion is connected to the second conductive component; and

[0187] The third terminal portion is connected to the first conductive component.

[0188] Postscript 16.

[0189] Regarding the semiconductor device described in Appendix 15

[0190] Viewed in the thickness direction, the pad portion spans the first conductive component and the second conductive component.

[0191] Postscript 17.

[0192] Regarding the semiconductor device described in Appendix 16

[0193] Viewed in the thickness direction, the first vertex and the second vertex overlap with the first conductive component.

[0194] Viewed in the thickness direction, the third vertex overlaps with the second conductive component.

[0195] Postscript 18.

[0196] Regarding the semiconductor device described in any of Appendix 16 or Appendix 17,

[0197] The second terminal portion is parallel to the first terminal portion in the first direction and overlaps with the first terminal portion when viewed in the first direction.

[0198] Postscript 19.

[0199] Regarding the semiconductor device mentioned in any one of Annexes 15 to 18,

[0200] It also includes a resin component that covers the plurality of first semiconductor elements and the plurality of second semiconductor elements.

[0201] The first terminal portion, the second terminal portion, and the third terminal portion are exposed from the resin component.

[0202] Postscript 20.

[0203] Regarding the semiconductor device described in any one of Annexes 12 to 19,

[0204] Each of the plurality of first semiconductor elements further includes a first control electrode that is insulated from the first main surface electrode and formed on the main surface of the first element, and the first main surface electrode is connected to the first back surface electrode according to a first drive signal input to the first control electrode.

[0205] Each of the plurality of second semiconductor elements further includes a second control electrode that is insulated from the second main surface electrode and formed on the main surface of the second element, and the second main surface electrode is connected to the second back surface electrode according to a second drive signal input to the second control electrode.

[0206] Postscript 21.

[0207] Regarding the semiconductor device mentioned in any one of Annexes 11 to 20,

[0208] It also includes an insulating substrate on which the first conductive component and the second conductive component are mounted.

[0209] Postscript 22.

[0210] Regarding the semiconductor device described in any one of Annexes 11 to 21,

[0211] The resistivity of the second conductive component is lower than that of the solder pad.

[0212] Symbol Explanation

[0213] A1~A4—Semiconductor devices; 10, 20—Semiconductor elements; 10A, 20A—Outer elements; 10B, 20B—Inner elements; 10a, 20a—Element main surface; 10b, 20b—Element back surface; 11, 21—Main surface electrodes; 12, 22—Control electrodes; 13, 23—Back surface electrodes; 14, 24—Insulating film; 30—Support substrate; 31A, 31B—Insulating substrate; 311—Main surface; 312—Back surface; 32A, 32B—Conductive substrate; 321—Main surface; 322—Back surface; 320a—Board 320b—Connector; 320c—First part; 320d—Second part; 320z—Abutment edge; 33A, 33B—Insulating layer; 34A, 34B—Gate layer; 341—Strip; 342—Hook; 35A, 35B—Detection layer; 351—Strip; 352—Hook; 36—Insulating substrate; 361—Main surface; 362—Back surface; 37A, 37B—Main surface metal layer; 38—Back surface metal layer; 41—Input terminal; 411—Pad; 412—Terminal; 419—Block; 42—Input Input terminal; 421—Pad portion; 421a—Abutting edge; 422—Terminal portion; 423—Connecting portion; 424—First part; 424a—Edge; 425—Second part; 426—Third part; 429—Bulk material; 43—Output terminal; 431—Pad portion; 432—Terminal portion; 439—Bulk material; 44A, 44B—Control terminals; 441—Pad portion; 442—Terminal portion; 45A, 45B—Detection terminals; 451—Pad portion; 452—Terminal portion; 51—Gate lead; 52—Detection lead; 53—First connecting portion 54—Second connecting lead; 55—Conductor plate; 551, 552—Joint; 559—Block; 60—Resin component; 61—Resin main surface; 62—Resin back side; 631—Resin side; 632—Resin side; 633—Resin side; 634—Resin side; 65—Recess; R1, R2—Closed area; L12, L23, L31, L45, L56, L64—Line segment; L0, L9—Perpendicular bisector; P1, P4—First vertex; P2, P5—Second vertex; P3, P6—Third vertex.

Claims

1. A semiconductor device, characterized in that, have: A plurality of first semiconductor elements electrically connected in parallel to each other, each having a first element main surface and a first element back surface separated in the thickness direction; A plurality of second semiconductor elements electrically connected in parallel to each other, each having a second element main surface and a second element back surface separated in the thickness direction; The bonding pad is connected to the plurality of first semiconductor elements; as well as The first terminal portion is in communication with the solder pad portion. The plurality of first semiconductor elements and the plurality of second semiconductor elements are electrically connected in series. Viewed along the thickness direction, the plurality of first semiconductor elements are arranged along a first direction orthogonal to the thickness direction. The solder pad portion is formed as a closed region consisting of three line segments, which are formed by connecting every two of the first, second, and third vertices that are not on the same straight line. Viewed in the thickness direction, the first vertex overlaps with the outermost first semiconductor element on one side of the plurality of first semiconductor elements in the first direction. Viewed in the thickness direction, the second vertex overlaps with the outermost first semiconductor element on the other side of the plurality of first semiconductor elements in the first direction. Viewed in the thickness direction, the third vertex lies on the perpendicular bisector of the line segment connecting the first vertex and the second vertex. Viewed in the thickness direction, the pad portion spans the plurality of first semiconductor elements and the plurality of second semiconductor elements. Viewed in the thickness direction, a portion of each of the plurality of first semiconductor elements and a portion of each of the plurality of second semiconductor elements do not overlap with the pad portion.

2. The semiconductor device according to claim 1, characterized in that, It also includes a connecting portion that connects the solder pad portion to the first terminal portion. The connecting portion includes a first portion that connects to the solder pad portion. Viewed in the thickness direction, the first part overlaps with the vertical bisector.

3. The semiconductor device according to claim 2, characterized in that, The first portion has a pair of end edges that are separated from each other in the first direction and each extends along a second direction orthogonal to the thickness direction and the first direction. Viewed in the thickness direction, each of the pair of end edges is connected to the pad portion.

4. The semiconductor device according to claim 3, characterized in that, Viewed in the thickness direction, both the solder pad portion and the first portion are rectangular. The dimension of the first part in the first direction is smaller than that of the pad part.

5. The semiconductor device according to claim 3, characterized in that, The plurality of first semiconductor elements includes two inner elements located between a first semiconductor element that overlaps with the first vertex when viewed in the thickness direction and a first semiconductor element that overlaps with the second vertex when viewed in the thickness direction, and adjacent to each other sandwiching the vertical bisector. Viewed in the second direction, the pair of end edges are located on the two inner elements respectively.

6. The semiconductor device according to claim 3, characterized in that, Viewed in the thickness direction, a portion of each of the plurality of first semiconductor elements does not overlap with the pad portion.

7. The semiconductor device according to any one of claims 3 to 6, characterized in that, Each of the plurality of first semiconductor elements includes: a first main surface electrode formed on the main surface of the first element; and a first back surface electrode formed on the back surface of the first element. The pad portion is located on the main surface of the first element in the thickness direction and is connected to the first main surface electrode of each of the plurality of first semiconductor elements.

8. The semiconductor device according to claim 7, characterized in that, It also includes a first conductive component, which carries the plurality of first semiconductor elements. The first back electrode of each of the plurality of first semiconductor elements is coupled to the first conductive component.

9. The semiconductor device according to claim 8, characterized in that, The solder pad portion, the first terminal portion, and the connecting portion are each plate-shaped and integrally formed.

10. The semiconductor device according to claim 8 or 9, characterized in that, It also includes a second conductive component, which carries the plurality of second semiconductor elements. The first conductive component and the second conductive component are separated and side by side in the second direction.

11. The semiconductor device according to claim 10, characterized in that, Each of the plurality of second semiconductor elements includes: a second main surface electrode formed on the main surface of the second element; and a second back surface electrode formed on the back surface of the second element.

12. The semiconductor device according to claim 11, characterized in that, The second back electrode of each of the plurality of second semiconductor elements is coupled to the second conductive component.

13. The semiconductor device according to claim 12, characterized in that, It also includes multiple connecting components that enable the first conductive component to conduct to the second main surface electrode of each of the plurality of second semiconductor elements.

14. The semiconductor device according to claim 13, characterized in that, It also has: The second terminal portion is connected to the second conductive component; and The third terminal portion is connected to the first conductive component.

15. The semiconductor device according to claim 14, characterized in that, Viewed in the thickness direction, the pad portion spans the first conductive component and the second conductive component.

16. The semiconductor device according to claim 15, characterized in that, Viewed in the thickness direction, the first vertex and the second vertex overlap with the first conductive component. Viewed in the thickness direction, the third vertex overlaps with the second conductive component.

17. The semiconductor device according to claim 15, characterized in that, The second terminal portion is parallel to the first terminal portion in the first direction and overlaps with the first terminal portion when viewed in the first direction.

18. The semiconductor device according to any one of claims 14 to 17, characterized in that, It also includes a resin component that covers the plurality of first semiconductor elements and the plurality of second semiconductor elements. The first terminal portion, the second terminal portion, and the third terminal portion are exposed from the resin component.

19. The semiconductor device according to any one of claims 11 to 17, characterized in that, Each of the plurality of first semiconductor elements further includes a first control electrode that is insulated from the first main surface electrode and formed on the main surface of the first element, and the first main surface electrode is connected to the first back surface electrode according to a first drive signal input to the first control electrode. Each of the plurality of second semiconductor elements further includes a second control electrode that is insulated from the second main surface electrode and formed on the main surface of the second element, and the second main surface electrode is connected to the second back surface electrode according to a second drive signal input to the second control electrode.

20. The semiconductor device according to any one of claims 11 to 17, characterized in that, It also includes an insulating substrate on which the first conductive component and the second conductive component are mounted.

21. The semiconductor device according to any one of claims 11 to 17, characterized in that, The resistivity of the second conductive component is lower than that of the solder pad.

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