Display panel, manufacturing method thereof, and display device

Abstract

A display panel includes a main display area and a functional device area, wherein the main display area at least partially surrounds the functional device area. The display panel includes a plurality of first pixel circuits and a plurality of redundant pixel circuits, wherein the plurality of first pixel circuits are located in the main display area; the plurality of redundant pixel circuits are adjacent to a plurality of first pixel circuits arranged at the edge of the main display area near the functional device area. The display panel includes an active layer and an anode layer sequentially arranged in a direction perpendicular to a substrate and away from the substrate; the anode layer includes a plurality of first anodes located in the main display area, each first anode being electrically connected to a first pixel circuit; the redundant pixel circuit includes at least a redundant active layer pattern located in the active layer, and the redundant pixel circuit is electrically insulated from the anode layer.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a manufacturing method thereof, and a display device. Background Art

[0002] The organic light-emitting diode (OLED) display panel includes a plurality of sub-pixels, each of which includes a pixel circuit and a light-emitting device stacked on a substrate, and the pixel circuit includes an active layer pattern. Due to the influence of the manufacturing process, during the manufacturing process of the pixel circuit, the uniformity of the pixel circuit located in the edge area of ​​the display panel close to the under-screen camera is poor, resulting in the problem of threshold voltage (Vth) shift of the pixel circuit in this area, which in turn causes abnormal light emission of the sub-pixel (such as dark spots, bright spots or different colors).

[0003] Public Content

[0004] On the one hand, a display panel is provided. It includes a main display area and a functional device area, and the main display area at least partially surrounds the functional device area. The display panel includes a plurality of first pixel circuits and a plurality of redundant pixel circuits, and the plurality of first pixel circuits are located in the main display area; the plurality of redundant pixel circuits are adjacent to a plurality of first pixel circuits arranged at the edge of the main display area near the functional device area. The display panel includes an active layer and an anode layer arranged in sequence along a direction perpendicular to a substrate and away from the substrate; the anode layer includes a plurality of first anodes located in the main display area, and each first anode is electrically connected to a first pixel circuit; the redundant pixel circuit includes at least a redundant active layer pattern located in the active layer, and the redundant pixel circuit is electrically insulated from the anode layer.

[0005] In some embodiments, the first pixel circuits in any row are arranged along a first direction, and the first pixel circuits in any column are arranged along a second direction, and the first direction intersects the second direction. At least two redundant pixel circuits arranged along the first direction are provided at an edge of the first pixel circuits in any row that intersects with the boundary of the functional device area and close to the functional device area; at least two redundant pixel circuits arranged along the second direction are provided at an edge of the first pixel circuits in any column that intersects with the boundary of the functional device area and close to the functional device area.

[0006] In some embodiments, 2 to 4 redundant pixel circuits arranged along a first direction are provided near an edge of the functional device area of ​​any row of first pixel circuits intersecting with the functional device area; 2 to 4 redundant pixel circuits arranged along a second direction are provided near an edge of the functional device area of ​​any column of first pixel circuits intersecting with the functional device area.

[0007] In some embodiments, the edge of the main display area close to the functional device area, and / or the edge of the functional device area close to the main display area is a transition area, and the plurality of redundant pixel circuits are located in the transition area. The transition area at least includes a first straight line extension segment and two second straight line extension segments; the first straight line extension segment is located at an edge of the transition area in the second direction, and the first straight line extension segment is provided with at least two rows of redundant pixel circuits; the two second straight line extension segments are respectively located at two edges of the transition area in the first direction, and each second straight line extension segment is provided with at least two columns of redundant pixel circuits.

[0008] In some embodiments, the transition zone also includes four fold line extension segments; each line segment is provided with multiple rows of redundant pixel circuits, the multiple rows of redundant pixel circuits located in different line segments are staggered in a first direction, and the first straight line extension segment and the second straight line extension segment are connected through the fold line extension segment.

[0009] In some embodiments, the transition region is a ring with one side open, and the opening is located at an edge of the transition region opposite to the first straight line segment. Alternatively, the transition region further includes a third straight line extension segment, which is located at an edge of the transition region opposite to the first straight line segment, and the third straight line extension segment includes at least two rows of redundant pixel circuits; the transition region is a closed ring.

[0010] In some embodiments, the pattern formed by the arrangement of the multiple redundant pixel circuits is symmetrical with respect to a straight line along the first direction of the transition zone; and / or the pattern formed by the arrangement of the multiple redundant pixel circuits is symmetrical with respect to a straight line along the second direction of the transition zone.

[0011] In some embodiments, the first pixel circuit includes a plurality of first thin film transistors and a first storage capacitor; the active layer also includes a first active layer pattern of the plurality of first thin film transistors. The display panel also includes a first gate conductive layer, a second gate conductive layer, and a source-drain conductive layer. The first gate conductive layer is disposed between the active layer and the anode layer, and includes a first gate pattern of the plurality of first pixel circuits, the first gate pattern includes the gates of the plurality of first thin film transistors, the first electrode plate of the first storage capacitor, a scan line, and a light emitting signal line. The second gate conductive layer is disposed between the first gate conductive layer and the anode layer, and includes a second gate pattern of the plurality of first pixel circuits, the second gate pattern includes the second electrode plate of the first storage capacitor, a first initialization power line, and a second initialization power line. The source-drain conductive layer is disposed between the second gate conductive layer and the anode layer, and includes a source-drain conductive pattern of the plurality of first pixel circuits, the source-drain conductive pattern includes the source and drain electrodes of the plurality of first thin film transistors, a data line, and a voltage signal line.

[0012] In some embodiments, orthographic projections of all patterns of the first gate conductive layer, all patterns of the second gate conductive layer, and all patterns of the source-drain conductive layer on the substrate are separated from orthographic projections of the redundant active layer patterns on the substrate.

[0013] In some embodiments, the display panel further includes a first gate insulating layer, a second gate insulating layer, and an interlayer insulating layer. The first gate insulating layer is disposed between the active layer and the first gate conductive layer; the second gate insulating layer is disposed between the first gate conductive layer and the second gate conductive layer; and the interlayer insulating layer is disposed between the second gate conductive layer and the source-drain conductive layer. The first gate insulating layer, the second gate insulating layer, and the interlayer insulating layer all cover the redundant active layer pattern; and a plurality of vias are disposed in the first gate insulating layer, the second gate insulating layer, and the interlayer insulating layer, the vias pass through the interlayer insulating layer, the second gate insulating layer, and the first gate insulating layer, and the orthographic projection of the vias on the substrate is located within the orthographic projection range of the redundant active layer pattern on the substrate.

[0014] In some embodiments, the display panel further comprises a passivation layer, the passivation layer is disposed between the source-drain conductive layer and the anode layer, and covers the redundant active layer pattern. The plurality of via holes are filled with a material of the passivation layer.

[0015] In some embodiments, the redundant pixel circuit includes a plurality of redundant thin film transistors and a redundant storage capacitor. The first gate conductive layer also includes a first redundant gate pattern for the plurality of redundant pixel circuits, the first redundant gate pattern including the gates of the plurality of redundant thin film transistors and the first plate of the redundant storage capacitor. The second gate conductive layer also includes a second redundant gate pattern for the plurality of redundant pixel circuits, the second redundant gate pattern including the second plate of the redundant storage capacitor. The source-drain conductive layer also includes a redundant source-drain conductive pattern for the plurality of redundant pixel circuits, the redundant source-drain conductive pattern including the source and drain of the plurality of redundant thin film transistors, a data line, and a voltage signal line; the redundant source-drain conductive pattern is electrically insulated from the anode layer.

[0016] In some embodiments, in two redundant pixel circuits adjacent to each other along a first direction, the redundant active layer patterns are separated from each other, the first redundant gate patterns are connected, and the second redundant gate patterns are connected; the first direction is the row direction in which the plurality of first pixel circuits are arranged. In two redundant pixel circuits adjacent to each other along a second direction, the redundant active layer patterns are separated from each other, and the redundant source-drain conductive patterns are connected; the second direction is the column direction in which the plurality of first pixel circuits are arranged.

[0017] In some embodiments, the display panel further comprises a plurality of second pixel circuits, which are arranged in an area of ​​the display panel other than the functional device area. The anode layer further comprises a plurality of second anodes, which are located in the functional device area, and each second anode is electrically connected to a second pixel circuit.

[0018] In some embodiments, the display panel further includes a transfer conductive layer, which is located between the film layer where the plurality of first pixel circuits and the plurality of second pixel circuits are located and the anode layer, and includes a plurality of transfer blocks separated from each other; the plurality of transfer blocks include a first transfer block electrically connected to the first pixel circuit, and a second transfer block electrically connected to the second pixel circuit. The orthographic projection of the first transfer block on the substrate covers the first connection node of the first pixel circuit electrically connected thereto, and is electrically connected to the first connection node; the first connection node is a node in the first pixel circuit configured to be electrically connected to the first anode; the orthographic projection of the second transfer block on the substrate covers the second connection node of the second pixel circuit electrically connected thereto, and is electrically connected to the second connection node; the second connection node is a node in the second pixel circuit configured to be electrically connected to the second anode.

[0019] In some embodiments, the plurality of first pixel circuits and the plurality of second pixel circuits are both located in the main display area. The plurality of second pixel circuits are arranged in a plurality of rows and a plurality of columns, and a plurality of first pixel circuits are arranged between two adjacent second pixel circuits in the same row.

[0020] In some embodiments, the display panel further includes a frame area surrounding the main display area, and the plurality of second pixel circuits are located in the frame area.

[0021] In some embodiments, the display panel also includes at least one connecting layer; the at least one connecting layer is located between the switching conductive layer and the anode layer; the connecting layer includes a plurality of connecting wires, one end of the connecting wire is electrically connected to the second pixel circuit through a second switching block, and the other end of the connecting wire is electrically connected to the second anode.

[0022] On the other hand, a display device is further provided, comprising the display panel described in any one of the above embodiments.

[0023] On the other hand, a method for manufacturing a display panel is also provided, wherein the display panel includes a main display area and a functional device area, wherein the main display area at least partially surrounds the functional device area; the display panel includes a plurality of first pixel circuits, and a plurality of redundant pixel circuits, wherein the plurality of first pixel circuits are located in the main display area, and the plurality of redundant pixel circuits are adjacent to the first pixel circuits in the main display area close to the functional device area. The manufacturing method includes: manufacturing an active layer on a substrate; and manufacturing an anode layer on a side of the active layer away from the substrate. The active layer includes a first active layer pattern of the plurality of first pixel circuits, and a redundant active layer pattern of the plurality of redundant pixel circuits; the anode layer includes a plurality of first anodes located in the main display area, each first anode being electrically connected to a first pixel circuit; and the plurality of redundant pixel circuits are electrically insulated from the anode layer.

[0024] In some embodiments, the first pixel circuit includes a plurality of first thin film transistors and a first storage capacitor. Between the step of forming an active layer on the substrate and the step of forming an anode layer on the side of the active layer away from the substrate, the method further includes: forming a first gate conductive layer on the side of the active layer away from the substrate; forming a second gate conductive layer on the side of the first gate conductive layer away from the substrate; and forming a source-drain conductive layer on the side of the second gate conductive layer away from the substrate. The first gate conductive layer includes a first gate pattern of the plurality of first pixel circuits, the first gate pattern includes the gates of the plurality of first thin film transistors, the first plates of the first storage capacitor, the scanning line, and the light emitting signal line; the second gate conductive layer includes a second gate pattern of the plurality of first pixel circuits, the second gate pattern includes the second plates of the first storage capacitor, the first initialization power line, and the second initialization power line; the source-drain conductive layer includes a source-drain conductive pattern of the plurality of first pixel circuits, the source-drain conductive pattern includes the source and drain electrodes of the plurality of first thin film transistors, the data line, and the voltage signal line.

[0025] The orthographic projections of all patterns of the first gate conductive layer, all patterns of the second gate conductive layer, and all patterns of the source-drain conductive layer on the substrate are separated from the orthographic projections of the redundant active layer on the substrate. Alternatively, the redundant pixel circuit includes a plurality of redundant thin film transistors and a redundant storage capacitor; the first gate conductive layer also includes a first redundant gate pattern of the plurality of redundant pixel circuits, the first redundant gate pattern includes the gates of the plurality of redundant thin film transistors and the first plate of the redundant storage capacitor; the second gate conductive layer also includes a second redundant gate pattern of the plurality of redundant pixel circuits, the second redundant gate pattern includes the second plate of the redundant storage capacitor; the source-drain conductive layer also includes a redundant source-drain conductive pattern of the plurality of redundant pixel circuits, the redundant source-drain conductive pattern includes the source and drain of the plurality of redundant thin film transistors; the redundant source-drain conductive pattern is electrically insulated from the anode layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required to be used in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the product involved in the embodiments of the present disclosure, the actual process of the method, the actual timing of the signal, etc.

[0027] Figure 1 is a structural diagram of a display panel according to some embodiments;

[0028] Figure 2 A pixel arrangement structure diagram of a boundary area between a main display area and a functional device setting area in a display panel;

[0029] Figure 3A is a structural diagram of a transition zone according to some embodiments;

[0030] Figure 3B is another structural diagram of a transition zone according to some embodiments;

[0031] Figure 3C is another structural diagram of a transition zone according to some embodiments;

[0032] Figure 3D is another structural diagram of a transition zone according to some embodiments;

[0033] Figure 3E is another structural diagram of a transition zone according to some embodiments;

[0034] Figure 4is a structural diagram of a redundant pixel circuit according to some embodiments;

[0035] Figure 5A for Figure 4 A cross-sectional view taken along lines A′-A′ and A″-A″;

[0036] Figure 5B for Figure 4 Another cross-sectional view of A′-A′ and A″-A″;

[0037] Figure 6 is another structural diagram of a redundant pixel circuit according to some embodiments;

[0038] Figure 7 for Figure 6 The cross-sectional views taken along lines B′-B′ and B″-B″;

[0039] Figure 8 is a structural diagram of a first pixel circuit according to some embodiments;

[0040] Fig. 9 A structural diagram showing that a second pixel circuit is arranged in a main display area according to some embodiments;

[0041] Fig.10 FIG. 4 is a structural diagram showing a second pixel circuit disposed in a border area according to some embodiments. DETAILED DESCRIPTION

[0042] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0043] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and other forms thereof, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open, inclusive, that is, "including, but not limited to". In the description of the specification, the terms "some embodiments", "exemplary embodiments", "example" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics described may be included in any one or more embodiments or examples in any appropriate manner.

[0044] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0045] When describing some embodiments, the expressions "connected", "electrically connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0046] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0047] The use of "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0048] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0049] In this article, the expression "same-layer arrangement" is used, which means that a film layer with a specific pattern is formed by a single patterning process using the same mask. Depending on the specific pattern, a single patterning process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights or have different thicknesses.

[0050] Some embodiments of the present disclosure provide a display device 1000, referring to Figure 1 The display device 1000 can be a television, a computer, a laptop computer, a mobile phone, a tablet computer, a personal digital assistant (PDA), a car computer, etc.

[0051] The display device 1000 adopts a technology of setting functional components on the back side of the screen (the side away from the light-emitting surface of the screen), and the functional components are, for example, a front camera component, an under-screen fingerprint component, a 3D face recognition component, an iris recognition component, a proximity sensor, and other components that can realize specific functions. For example, when a front camera component is set on the back side of the screen, the display device 1000 adopts the under-screen camera technology.

[0052] See also Figure 1 The display device 1000 includes a display panel 100. In some embodiments, the display panel 100 may be an organic light-emitting diode (OLED) display panel.

[0053] The display panel 100 includes a main display area 101, a functional device area 102, and a frame area 104 surrounding the main display 101. The functional device is arranged on the back side of the functional device area 102, and the functional device needs to receive light from the outside when working. In order to improve the sensitivity of the functional device, it is necessary to ensure that the functional device can receive a sufficient amount of light, and the light transmittance of the functional device area 102 needs to be improved.

[0054] See also Figure 2 The display panel 100 includes a plurality of sub-pixels 110, and the sub-pixel 110 includes a pixel circuit 20 disposed on a substrate 120, and an anode 32 disposed on a side of a film layer where the pixel circuit 20 is located away from the substrate 120. The anode 32 includes a first anode 321 located in the main display area 101, and a second anode 322 disposed in the functional device area 102.

[0055] See also Figure 2 In order to improve the light transmittance of the functional device area 102, the pixel circuit 20 connected to the second anode 322 is arranged in the area of ​​the display panel 100 other than the functional device area 102; that is, the pixel circuit 20 is not arranged in the functional device area 102, and only the second anode 322 is retained. Due to the poor uniformity of the pixel circuit 20 in the edge area of ​​the display panel close to the under-screen camera during the pixel circuit manufacturing process, the pixel circuit in this area is prone to Vth shift, which in turn causes the sub-pixel 110 where the pixel circuit 20 is located to emit abnormal light (such as dark spots, bright spots, etc.); that is, the pixel circuit 20 contained in the sub-pixel 110 located in the main display area 101 close to the edge of the functional device area 102 has poor uniformity, which may cause the sub-pixel 110 located in the main display area 101 close to the edge of the functional device area 102 to emit abnormal light.

[0056] Some embodiments of the present disclosure provide a display panel 100. Figure 1 , including a main display area 101 and a functional device area 102, wherein the main display area 101 at least partially surrounds the functional device area 102. Figure 3A and Figure 3B , a portion of the boundary of the functional device area 102 overlaps with a portion of the frame area 104, and a portion of the main display area 101 surrounds the functional device area 102; see Figure 3C , the boundary of the functional device area 102 is separated from the frame area 104 , and the main display area 101 surrounds the functional device area 102 .

[0057] See also Figure 3A , Figure 3B , Figure 3C and Figure 3D The display panel 100 includes a plurality of first pixel circuits 210 and a plurality of redundant pixel circuits 220. The plurality of first pixel circuits 210 are located in the main display area 101; the plurality of redundant pixel circuits 220 are adjacent to the plurality of first pixel circuits 210 disposed at the edge of the main display area 101 close to the functional device area 102. That is, the redundant pixel circuit 220 adjacent to the first pixel circuit 210 is disposed on one side of the first pixel circuit 210 located at the edge of the main display area 101 close to the functional device area 102 and close to the functional device area 102.

[0058] See also Figure 4 and Figure 5A The display panel 100 includes an active layer 310 and an anode layer 320 which are sequentially arranged in a direction perpendicular to the substrate 120 and away from the substrate 120. The anode layer 320 includes a plurality of first anodes 321 located in the main display area 101, and each first anode 321 is electrically connected to a first pixel circuit 210. The first pixel circuit 210 is electrically connected to the first anode 321 and is configured to transmit a driving current to the first anode 321 to control the light emitting device 30 where the first anode 321 is located to emit light.

[0059] The redundant pixel circuit 220 at least includes a redundant active layer pattern 311 located in the active layer 310, and the redundant pixel circuit 220 is electrically insulated from the anode layer 320. Due to the influence of the manufacturing process, during the manufacturing process of the pixel circuit, the uniformity of the pixel circuit located in the edge area of ​​the display panel close to the under-screen camera is poor, and the problem of poor uniformity mainly occurs in the active layer 310. Therefore, the redundant pixel circuit 220 at least includes a redundant active layer pattern 311 located in the active layer 310.

[0060] The display panel 100 provided in the embodiment of the present disclosure is shown in FIG. Figure 3A to Figure 3E , a redundant pixel circuit 220 adjacent to the first pixel circuit 210 is provided on one side of the first pixel circuit 210 located at the edge of the main display area 101 close to the functional device area 102; and, referring to Figure 4 and Figure 6 , the redundant pixel circuit 220 includes a redundant active layer pattern 311 located on the active layer 310. The edge of the active layer 310 close to the functional device area 102 is transferred from the first active layer pattern 312 of the first pixel circuit 210 to the redundant active layer pattern 311 of the redundant pixel circuit 220; thereby avoiding the problem of poor uniformity of the first pixel circuit 210, so that the sub-pixel 20 located at the edge of the main display area 101 close to the functional device area 102 can emit light normally. Moreover, the redundant pixel circuit 220 is electrically insulated from the anode layer 320, that is, the redundant pixel circuit 220 does not control any sub-pixel 20 to emit light, and even if the redundant active layer pattern 311 of the redundant pixel circuit 220 has a problem of poor uniformity, it will not affect the light emission of any sub-pixel 20.

[0061] In some embodiments, see Figure 3A , the plurality of first pixel circuits 210 are arranged in a plurality of rows and a plurality of columns, and the first pixel circuits 210 in any row are arranged in a first direction M1 ( Figure 3A The first pixel circuits 210 of any column are arranged along the second direction M2 ( Figure 3A The first direction M1 intersects with the second direction M2.

[0062] At least two redundant pixel circuits 220 arranged along the first direction are provided at the edge of any row of first pixel circuits 210 intersecting with the boundary of the functional device area 102 close to the functional device area 102. At least two redundant pixel circuits arranged along the second direction are provided at the edge of any column of first pixel circuits 210 intersecting with the boundary of the functional device area 102 close to the functional device area 102. That is, each first pixel circuit 210 located at the edge of the main display area 101 close to the functional device area 102 is provided with at least two redundant pixel circuits 220 adjacent to the first pixel circuit 210 on the side close to the functional device area 102 along the first direction M1 or along the second direction M2; to ensure that the area with poor uniformity that may appear on the active layer 310 completely falls on the redundant active layer pattern 311 of the redundant pixel circuit 220, which is conducive to improving the yield rate of the display panel 100.

[0063] The more the number of redundant pixel circuits 220 disposed near the edge of the functional device area 102 of the first pixel circuit 210 of the main display area 101, the larger the area occupied by the redundant pixel circuits 220, and the more redundant pixel circuits 220 are located at the edge of the functional device area 102, resulting in a decrease in the light transmittance at the edge of the functional device area 102, affecting the operation of the functional device. Alternatively, the opening of the functional device area 102 needs to be made larger to prevent the redundant pixel circuits 220 from affecting the lighting of the functional device, which is not conducive to the arrangement of the pixel circuits 20 contained in the sub-pixels 120 located in the functional device area 102.

[0064] Therefore, at the edge of any row of first pixel circuits 210 intersecting the functional device area 102 close to the functional device area 102, 2 to 4 redundant pixel circuits 220 arranged along the first direction are provided; similarly, at the edge of any column of first pixel circuits 210 intersecting the functional device area 102 close to the functional device area 102, 2 to 4 redundant pixel circuits arranged along the second direction are provided. Under the premise of ensuring that the first pixel circuits 210 located at the edge of the main display area 01 close to the functional device area 102 do not have the problem of poor uniformity, the influence of the redundant pixel circuits on the light transmittance of the functional device area 102 can be minimized.

[0065] For example, see Figure 3A, the functional device area 102 is located in the middle of the display panel 100 along the first direction, and any row of first pixel circuits 210 intersecting the boundary of the functional device area 102 is divided into two parts by the functional device area 102. Among them, at least two redundant pixel circuits 220 adjacent to the first pixel circuit 210 are arranged on the right side of the rightmost first pixel circuit 210 in the Nth row of first pixel circuits 210 located on the left side of the functional device area 102. For example, two, three or four redundant pixel circuits 220 may be arranged.

[0066] At least two redundant pixel circuits 220 adjacent to the first pixel circuit 210 are arranged on the left side of the leftmost first pixel circuit 210 in the Mth row of first pixel circuits 210 located on the right side of the functional device area 102; at least two redundant pixel circuits 220 adjacent to the first pixel circuit 210 are arranged on the upper side of the first pixel circuit 210 at the upper end of the first pixel circuit 210 in the Oth column of the first pixel circuits 210 located on the lower side of the functional device area 102; at least two redundant pixel circuits 220 adjacent to the first pixel circuit 210 are arranged on the lower side of the first pixel circuit 210 at the lower end of the first pixel circuit 210 in the Pth column of the first pixel circuits 210 located on the upper side of the functional device area 102. The first pixel circuits 210 in the Nth and Mth rows intersect with the boundary of the functional device area 102, and the first pixel circuits 210 in the Oth and Pth columns intersect with the boundary of the functional device area 102.

[0067] For example, see Figure 3A At the edge of any row of first pixel circuits 210 intersecting with the functional device area 102 close to the functional device area 102, four redundant pixel circuits 220 arranged along the first direction M1 are provided; at the edge of any column of first pixel circuits 210 intersecting with the functional device area 102 close to the functional device area 102, two redundant pixel circuits 220 arranged along the second direction M2 are provided.

[0068] For example, see Figure 3C , at the edge of any row of the first pixel circuit 210 intersecting with the functional device area 102 close to the functional device area 102, two redundant pixel circuits 220 arranged along the first direction M1 are provided; at the edge of any column of the first pixel circuit 210 intersecting with the functional device area 102 close to the functional device area 102, two redundant pixel circuits 220 arranged along the second direction M2 are provided.

[0069] In some embodiments, the area where the redundant pixel circuit 220 is located is defined as a transition area 103. The transition area 103 includes the edge of the main display area 101 close to the functional device area 102, and / or the edge of the functional device area 102 close to the main display area 101 is the transition area 103; that is, the transition area 103 may include part of the main display area 101 and / or part of the functional device area 102. Exemplarily, the transition area 103 may be entirely located in the functional device area 102; or, a portion of the transition area 102 is located in the functional device area 102 and a portion is located in the main display area 101; or, the transition area 102 is entirely located in the main display area 101. It should be understood that the area where the first anode 321 is located is the main display area; the area where the second anode 321 is located is the functional device area 102; and the area where the redundant pixel circuit 220 is located is the transition area 103.

[0070] Depending on the shape of the functional device, the shape of the boundary of the functional device area 102 may be different, and thus the shape of the transition area 103 may also be different. For example, the boundary of the functional device area 102 may be rectangular or approximately rectangular, circular or approximately circular, etc., which is not specifically limited here.

[0071] The plurality of first pixel circuits 210 are arranged in a plurality of rows and columns, and the boundary of the functional device area 102 is formed by alternately connecting a plurality of boundaries of the first pixel circuits 210 arranged along a first direction M1 (the row direction of the plurality of first pixel circuits 210) and a plurality of boundaries of the first pixel circuits 210 arranged along a second direction M2 (the row direction of the plurality of first pixel circuits 210). Figure 3B When a portion of the boundary of the functional device area 102 overlaps a portion of the frame area 104 , the boundary of the functional device area 102 includes at least one straight line segment extending along the first direction M1 and two straight line segments extending along the second direction M2 .

[0072] Corresponding to the boundary of the functional device area 102, the transition area 103 includes at least a first straight extension segment 1031 and two second straight extension segments 1032; the first straight extension segment 1031 is located at an edge of the transition area 103 in the second direction M2, and the two second straight extension segments 1032 are respectively located at two edges of the transition area 103 in the first direction M1.

[0073] For example, see Figure 3B , the boundary of the functional device area 102 is a rectangle, and a boundary ( Figure 3B The upper boundary of the middle functional device area 102) coincides with the boundary portion of the frame area 104; at this time, the transition area 103 may include a first straight extension segment 1031 and two second straight extension segments 1032. The first straight extension segment 1031 constitutes a boundary ( Figure 3B The two second straight extension segments 1032 respectively constitute the two boundaries of the transition zone 103 in the first direction ( Figure 3B The left and right boundaries of the transition zone 103).

[0074] The first straight extension section 1031 is provided with at least two rows of redundant pixel circuits 220 (the edge of any column of first pixel circuits 210 intersecting with the boundary of the functional device area 102 close to the functional device area 102 is provided with at least two redundant pixel circuits 220 arranged along the second direction M2); that is, in at least one row of first pixel circuits 210 overlapping with part of the boundary of the functional device area 102, at least two rows of redundant pixel circuits 220 are provided on the side close to the functional device area 102 of the part overlapping with the boundary of the functional device area 102.

[0075] Each second straight line extension segment 1302 is provided with at least two columns of redundant pixel circuits 220 (the edge of any row of first pixel circuits 210 intersecting with the boundary of the functional device area 102 close to the functional device area 102 is provided with at least two redundant pixel circuits 220 arranged along the first direction M1); that is, in at least one column of first pixel circuits 210 overlapping with part of the boundary of the functional device area 102, at least two columns of redundant pixel circuits 220 are provided on the side close to the functional device area 102 of the part overlapping with the part of the boundary of the functional device area 102.

[0076] In some embodiments, see Figure 3A and Figure 3C The transition zone 103 also includes four fold line extension segments 1033; each fold line extension segment 1033 includes a plurality of line segments 10331 connected in sequence, each line segment 10331 is provided with a plurality of rows of redundant pixel circuits 220, and the plurality of rows of redundant pixel circuits 220 located in different line segments 10331 are staggered in the first direction M1; the first straight line extension segment 1031 and the second straight line extension segment 1032 are connected via the fold line extension segment 1033.

[0077] Exemplarily, the boundary shape of the functional device area 102 is approximately circular, and at the corner of the boundary of the functional device area 102, a folded line segment is formed by alternately connecting a plurality of straight line segments extending along the first direction M1 and a plurality of straight line segments extending along the second direction M2. Corresponding to the folded line segment of the boundary of the functional device area 102, the transition area 103 includes a folded line extension segment 1033, and the folded line extension segment 1033 of the transition area 103 is arranged at a position corresponding to the folded line segment of the boundary of the functional device area 102.

[0078] The position of the functional device area 102 on the display panel 100 is not unique. Depending on the different positions of the functional device area 102 on the display panel 100, the shape of the transition area 103 may also be different. For example, the functional device area 102 can be set at the upper middle position of the display panel 100 (such as Figure 3A ), or arranged on the left or right side of the upper part of the display panel 100, or arranged in the middle position of the lower part of the display panel 100; the functional device area 102 can be completely surrounded by the main display area 101 (as shown in Figure 3C ), a portion of the boundary of the functional device area 102 may also overlap with a portion of the boundary of the frame area 104, that is, the main display area 101 partially surrounds the functional device area 102 (as shown in FIG. Figure 3A shown).

[0079] See also Figure 3A When the upper boundary of the functional device area 102 coincides with a portion of the boundary of the border area 104 , the transition area 103 is a ring having an opening 1035 on one side (the upper side), and the opening 1035 is located at the edge of the transition area 103 opposite to the first straight line segment 1031 .

[0080] The transition zone 103 may only include a first straight extension segment 1031 and two second straight extension segments 1032 (eg Figure 3B Alternatively, the transition zone 103 further includes two fold line extension segments 1033 or four fold line extension segments 1033 (as shown in Figure 3A The transition zone 103 may also include other extension sections, which are not listed here one by one.

[0081] See also Figure 3C , when the boundaries of the functional device area 102 are all located in the main display area 101, the transition area 103 further includes a third straight extension segment 1034, the third straight extension segment 1034 is located at the edge of the transition area 103 opposite to the first straight segment 1031, and the third straight extension segment 1034 includes at least two rows of redundant pixel circuits 220; the transition area 103 is a closed ring. The first straight extension segment 1301 and the third straight extension segment 1034 respectively constitute two boundaries of the transition area 103 in the first direction M1 ( Figure 3C , the upper and lower boundaries of the transition zone 103).

[0082] For example, the transition zone 103 may include a first straight extension segment 1031, two second straight extension segments 1032 and a third straight extension segment 1034; or, the transition zone 103 may also include two fold line extension segments 1303 or four fold line extension segments 1033. The transition zone 103 may also include other extension segments, which are not listed here one by one.

[0083] In some embodiments, see Figure 3DAlternatively, at least two redundant pixel circuits 220 arranged along the first direction M1 may be provided only at the edge of any row of first pixel circuits 210 that intersects the boundary of the functional device area 102 and is close to the functional device area 102. Alternatively, see Figure 3E At least two redundant pixel circuits 220 arranged along the second direction M2 are provided only on the edge of any column of first pixel circuits 210 close to the functional device area 102 that intersects with the boundary of the functional device area 102 .

[0084] In some embodiments, see Figure 3C The pattern formed by arranging the plurality of redundant pixel circuits 220 is symmetrical with respect to a straight line L2 along the first direction M1 of the transition region 103. And / or, refer to Figure 3A , Figure 3B and Figure 3C , see Figure 3C The pattern formed by arranging the plurality of redundant pixel circuits 220 is symmetrical with respect to a straight line L1 along the second direction M2 of the transition region 103. The plurality of redundant pixel circuits 220 are symmetrical with respect to a straight line L2 along the first direction M1 of the transition region 103, and / or are symmetrical with respect to a straight line L1 along the second direction M2 of the transition region 103, which is beneficial to improving the uniformity of the redundant active layer pattern 311 of the redundant pixel circuits 220 and improving the uniformity of the entire active layer 310.

[0085] In some embodiments, see Figure 4 and Figure 5A The first pixel circuit 210 includes a plurality of first thin film transistors (TFT) 211 and a first storage capacitor 212; Figure 5A The section A′-A′ is a cross-sectional view of a first thin film transistor 211 and a first storage capacitor 212 in the first pixel circuit 210. The first thin film transistor 211 may be a P-type transistor or an N-type transistor, which is not specifically limited herein.

[0086] The active layer 310 includes a plurality of first active layer patterns 312 of the first thin film transistors 211 , and each of the first pixel circuits 210 includes a first active layer pattern 312 located in the active layer 310 .

[0087] See also Figure 4 , Figure 5A and Figure 8 The display panel 100 further includes a first gate conductive layer 330 , a second gate conductive layer 340 , and a source-drain conductive layer 350 .

[0088] The first gate conductive layer 330 is disposed between the active layer 310 and the anode layer 320, and includes a first gate pattern 331 of a plurality of first pixel circuits 210. The first gate pattern 331 includes gates G1 of a plurality of first thin film transistors 211, a first electrode C11 of a first storage capacitor 212, a scan line GL, and a light emitting signal line EM.

[0089] The second gate conductive layer 340 is disposed between the first gate conductive layer 330 and the anode layer 320 and includes a second gate pattern 341 of a plurality of first pixel circuits 210 . The second gate pattern 341 includes a second electrode C12 of the first storage capacitor 212 , a first initialization power line Vint1 , and a second initialization power line Vint2 .

[0090] The source-drain conductive layer 350 is disposed between the second gate conductive layer 340 and the anode layer 320, and includes a plurality of source-drain conductive patterns 351 of the first pixel circuits 210. The source-drain conductive patterns 351 include the source electrodes S1 and the drain electrodes D1, the data lines DATA, and the voltage signal lines VDD of the first thin film transistors 30. The first active layer pattern 312, the first gate pattern 331, the second gate pattern 341, and the source-drain conductive patterns 351 together constitute the first pixel circuits 210.

[0091] The display panel 100 further includes a first gate insulating layer 360 disposed between the active layer 310 and the first gate conductive layer 330; a second gate insulating layer 370 disposed between the first gate conductive layer 330 and the second gate conductive layer 340; an interlayer insulating layer 380 disposed between the second gate conductive layer 340 and the source-drain conductive layer 350; and a passivation layer 390 and a planarization layer 420 disposed between the source-drain conductive layer 350 and the anode layer 320. The first gate insulating layer 360, the second gate insulating layer 370, the interlayer insulating layer 380, the passivation layer 390, and the planarization layer 420 are all whole-layer structures, and all cover the redundant active layer pattern 311. At least one insulating layer is disposed between two adjacent conductive layers to prevent the patterns on the two adjacent conductive layers from overlapping.

[0092] The redundant pixel circuit 220 may include only a redundant active layer pattern 311 ; or, the redundant pixel circuit 220 may include a redundant active layer pattern 311 , a redundant first gate pattern 332 , a redundant second gate pattern 342 , and a redundant source-drain conductive layer pattern 352 sequentially stacked on the substrate 120 .

[0093] See also Figure 6 , Figure 7 and Figure 8In the case where the redundant pixel circuit 220 only includes the redundant active layer pattern 311, the orthographic projections of all patterns of the first gate conductive layer 330, all patterns of the second gate conductive layer 340, and all patterns of the source-drain conductive layer 350 on the substrate 120 are separated from the orthographic projections of the redundant active layer pattern 311 on the substrate 120; that is, there is no conductive pattern in the first gate conductive layer 330, the second gate conductive layer 340, and the source-drain conductive layer 350 above the redundant active layer pattern 311. In this way, the redundant pixel circuit 210 has a simple structure, and the patterns of the first gate conductive layer 330, the second gate conductive layer 340, and the source-drain conductive layer 350 are simple, which is conducive to improving the manufacturing efficiency of the display panel 100.

[0094] See also Figure 7 A plurality of via holes 361 are provided in the first gate insulating layer 360, the second gate insulating layer 370 and the interlayer insulating layer 380, and the plurality of via holes 361 pass through the first gate insulating layer 360, the second gate insulating layer 370 and the interlayer insulating layer 380, and the orthographic projections of the via holes 361 on the substrate 120 are located within the orthographic projection range of the redundant active layer pattern 311 on the substrate 120; so that the redundant active layer pattern 311 of the redundant pixel circuit 210 has the same structure as the first active layer pattern 312 of the first pixel circuit 210, which is beneficial to improving the uniformity of the edge of the active layer 310 close to the functional device area 102 and reducing the possibility of poor uniformity of the first active layer pattern 312.

[0095] Since the redundant pixel circuit 220 only includes a redundant active layer pattern 311, and a passivation layer 390 is provided on the side of the interlayer insulating layer 380 away from the redundant active layer pattern 311, according to the manufacturing process of the display panel 100, after the via 361 is formed, a source-drain conductive layer 350 and a passivation layer 390 need to be manufactured; the via of the first pixel circuit 210 is filled with the source-drain conductive layer 350; and the via 361 of the redundant pixel circuit 220 is filled with the material of the passivation layer 390.

[0096] See also Figure 4 , Figure 5A and Figure 8 In the case where the redundant pixel circuit 220 includes a plurality of redundant thin film transistors 221 and redundant storage capacitors 222, that is, the redundant pixel circuit 220 includes a redundant active layer pattern 311, a redundant first gate pattern 332, a redundant second gate pattern 342, and a redundant source-drain conductive layer pattern 352 sequentially stacked on the substrate 120. Figure 82 is a structural diagram of the first pixel circuit 210. In the case where the redundant pixel circuit 220 includes a plurality of redundant thin film transistors 221 and a redundant storage capacitor 222, the structure of the redundant pixel circuit 220 is the same as that of the first pixel circuit 210. Therefore, the conductive layer patterns of the redundant pixel circuit 220 may refer to the conductive layer patterns corresponding to the first pixel circuit 210.

[0097] The first gate conductive layer 330 further includes a first redundant gate pattern 332 of multiple redundant pixel circuits 220 , the first redundant gate pattern 332 includes gates G2 of multiple redundant thin film transistors 221 and a first electrode plate C21 of a redundant storage capacitor 222 ; and the first redundant gate pattern 332 is disposed in the same layer as the first gate pattern 331 .

[0098] The second gate conductive layer 340 further includes a second redundant gate pattern 342 of a plurality of redundant pixel circuits 220 . The second redundant gate pattern 342 includes a second electrode plate C22 of a redundant storage capacitor 222 . The second redundant gate pattern 342 is disposed in the same layer as the second gate pattern 341 .

[0099] The source-drain conductive layer 350 also includes a redundant source-drain conductive pattern 352 of multiple redundant pixel circuits 220, and the redundant source-drain conductive pattern 352 includes a source S2 and a drain D2 of multiple redundant thin film transistors 221; the redundant source-drain conductive pattern 352 is electrically insulated from the anode layer 320, and the redundant source-drain conductive pattern 352 is arranged on the same layer as the source-drain conductive pattern 351.

[0100] The redundant pixel circuit 220 includes a plurality of redundant thin film transistors 221 and a redundant storage capacitor 222. The redundant pixel circuit 220 is structurally identical to the first pixel circuit 210 (but the redundant pixel circuit 220 is not electrically connected to the anode layer 320, and the first pixel circuit 210 is electrically connected to the first anode 321 of the anode layer 320); the uniformity of the first gate pattern 331, the second gate pattern 341 and the source-drain conductive pattern 351 of the plurality of first pixel circuits 210 at the edge of the main display area 101 close to the functional device area 102 can be improved, so that the uniformity of the plurality of first pixel circuits 210 at the edge of the main display area 101 close to the functional device area 102 is better, and the probability of Vth shift occurring in the first pixel circuit 210 at the edge of the main display area 101 close to the functional device area 102 is further reduced, so that the light-emitting device 30 at the edge of the main display area 101 close to the functional device area 102 can emit light normally.

[0101] In some embodiments, in two redundant pixel circuits 220 adjacent to each other along the first direction M1, the redundant active layer patterns 311 are separated from each other (see Figure 6), the first redundant gate pattern 332 is connected (the scanning line GL is connected to the light emitting signal line EM), and the second redundant gate pattern 342 is connected (the first initialization power line Vint1 is connected to the second initialization power line Vint2). In two redundant pixel circuits 220 adjacent to each other along the second direction M2, the redundant active layer patterns 311 are separated from each other (see Figure 6 ), the redundant source-drain conductive pattern 352 is connected (the data line DATA and the voltage signal line VDD are connected). That is, in the case where the redundant pixel circuit 220 includes a plurality of redundant thin film transistors 221 and a redundant storage capacitor 222, the redundant active layer patterns 351 of two redundant pixel circuits 220 adjacent to each other along the first direction are separated from each other, and the first redundant gate pattern 332 and the second redundant gate pattern 342 are connected; the redundant active layer patterns 311 of two redundant pixel circuits 220 adjacent to each other along the second direction M2 are separated from each other, and the redundant source-drain conductive patterns are connected.

[0102] It should be understood that, when the redundant pixel circuit 220 only includes a redundant active layer pattern 311 disposed on the active layer 310, the redundant active layer patterns 311 of two redundant pixel circuits 220 adjacent along the first direction M1 are separated from each other; and the redundant active layer patterns 311 of two redundant pixel circuits 220 adjacent along the second direction M2 are separated from each other.

[0103] In some embodiments, see Fig. 9 or Fig.10 , the anode layer 320 further includes a plurality of second anodes 322, and the plurality of second anodes 322 are located in the functional device area 102. The display panel 100 further includes a plurality of second pixel circuits 230, each second anode 322 is connected to a second pixel circuit 230; the plurality of second pixel circuits 230 are arranged in an area other than the functional device area 102 in the display panel 100. The structure of the second pixel circuit 203 may be the same as that of the first pixel circuit 210; the second pixel circuit 230 is arranged in an area other than the functional device area 102 in the display panel 100, which is conducive to improving the light transmittance of the functional device area 102, so that the functional device can collect enough light when the functional device is working.

[0104] In some embodiments, see Figure 5A , Fig. 9 and Fig.10The display panel 100 further includes a switching conductive layer 410, through which the first pixel circuit 210 and the second pixel circuit 230 are electrically connected to the first anode 321 or the second anode 322. The switching conductive layer 410 is located between the film layer where the plurality of first pixel circuits 210 and the plurality of second pixel circuits 230 are located and the anode layer 320, and is located between the passivation layer 390 and the anode layer 320. The switching conductive layer 410 can reduce the depth of a single via when the source-drain conductive layer 350 is connected to the anode layer 320, improve the connection stability between the pixel circuit 20 and the light-emitting device 30 indirectly, and reduce the process difficulty of making the via.

[0105] The transfer conductive layer 410 includes a plurality of transfer blocks 411 separated from each other. The plurality of transfer blocks 411 include a first transfer block 4111 electrically connected to the first pixel circuit 210 and a second transfer block 4112 electrically connected to the second pixel circuit 230 .

[0106] The orthographic projection of the first adapter block 4111 on the substrate 120 covers the first connection node N1 of the first pixel circuit 210 electrically connected thereto, thereby shielding the connection layer 430 on the side of the first adapter block 4111 away from the substrate 120, reducing or eliminating the influence of the connection layer 430 on the first connection node N1. The first adapter block 4111 is electrically connected to the first connection node N1, and the first anode 321 is electrically connected to the first adapter block 4111; so that the first anode 321 is electrically connected to the first pixel circuit 210 through the first adapter block 4111. The first connection node N1 is a node in the first pixel circuit 210 configured to be connected to the first anode 321.

[0107] The orthographic projection of the second adapter block 4112 on the substrate 120 covers the second connection node N2 of the second pixel circuit 230 electrically connected thereto, thereby shielding the connection layer 430 on the side of the second adapter block 4112 away from the substrate 120, reducing or eliminating the influence of the connection layer 430 on the second connection node N2. The second adapter block 4112 is electrically connected to the second connection node N2, and the second anode 322 is electrically connected to the second adapter block 4112, so that the second anode 322 is electrically connected to the second pixel circuit 230 through the second adapter block 4112. The second connection node N2 is a node in the second pixel circuit 230 configured to be electrically connected to the second anode 322.

[0108] In some embodiments, the display panel 100 further includes a frame area 104, and the frame area 104 surrounds the main display area 101. The second pixel circuit 230 can be arranged in the main display area 101 (eg Fig. 9 ) or in the border area 104 (as shown Fig.10 shown).

[0109] See also Fig. 9, when the second pixel circuit 230 is arranged in the main display area 101, the plurality of first pixel circuits 210 and the plurality of second pixel circuits 230 are both located in the main display area 101. The plurality of second pixel circuits 230 are arranged in a plurality of rows and columns, and a plurality of first pixel circuits 210 are arranged between two adjacent second pixel circuits 230 in the same row, that is, a plurality of columns of second pixel circuits 230 are alternately inserted into the gaps between the plurality of columns of first pixel circuits 210, and the second pixel circuits 230 are arranged in the main display area 101, which is conducive to reducing the width of the border area 104 and improving the screen-to-body ratio of the display panel 100.

[0110] See also Fig.10 , setting the second pixel circuit 230 in the frame area 104 is conducive to improving the pixel density of the main display area 101 of the display panel 100. For example, in some high pixel density (English: Pixels Per Inch; abbreviated: PPI) display panels 100, the pixel density is relatively large, and accordingly, the density of the first pixel circuits 210 is relatively large, and the available gaps between the first pixel circuits 210 are very small, and the second pixel circuit 230 is not easy to insert into the gaps between the first pixel circuits 210. Therefore, setting the second pixel circuit 230 in the frame area 104 is conducive to improving the pixel density of the main display area 101 of the display panel 100, and is conducive to manufacturing a high PPI display panel 100.

[0111] The second anode 322 is located in the functional device area 102, and the second pixel circuit 230 is arranged in an area of ​​the display panel 100 other than the functional device area 102; that is, the orthographic projection of the second pixel circuit 230 on the substrate 120 does not overlap with the orthographic projection of the second anode 322 on the substrate, and the second anode 322 and the second pixel circuit 230 cannot be directly electrically connected through a via.

[0112] Therefore, see Fig. 9 and Fig.10 The display panel 100 also includes at least one connecting layer 430, and the at least one connecting layer 430 is located between the switching conductive layer 410 and the anode layer 320; the connecting layer 430 includes a plurality of connecting wires 431, one end of the connecting wire 431 is electrically connected to the second pixel circuit 230 through the second switching block 4112, and the other end of the connecting wire 431 is electrically connected to the second anode 322.

[0113] In order to improve the light transmittance of the functional device area 102 , the connection line 431 of the connection layer 430 may be made of a transparent conductive material, such as indium tin oxide (ITO).

[0114] Since there are multiple second anodes 322 in the functional device area 102, multiple connection lines 431 are required to connect the multiple second anodes 322 and the multiple second pixel circuits 230. The multiple connection lines 431 can be arranged in the same connection layer 430 or in different connection layers 430 to provide sufficient wiring space for the multiple connection lines 431; wherein, when the number of connection layers 430 is greater than two, at least one insulating layer 440 is arranged between any two adjacent connection layers 430.

[0115] For example, see Figure 5B and Figure 7 , the number of connection layers 430 is three; along the direction perpendicular to the substrate 120 and from the substrate 120 to the anode layer 320, the three connection layers 430 are respectively a first connection layer 4301, a second connection layer 4302 and a third connection layer 4303, an insulating layer 441 is provided between the first connection layer 4301 and the second connection layer 4302, and an insulating layer 442 is provided between the second connection layer 4302 and the third connection layer 4303; and an insulating layer 443 is provided between the transfer conductive layer 410 and the first connection layer 4301, and an insulating layer 444 is provided between the third connection layer 4303 and the anode layer 320.

[0116] See also Figure 5A and Figure 5B In the case where the display panel 100 includes a plurality of connection layers 430, for the second pixel circuit 230 and the second anode 322 that need to be electrically connected through the connection line 431, it is necessary to set the connection line 431 on one of the connection layers 430, and it is also necessary to set a third adapter block 432 on other connection layers 430 except the connection layer 430 where the connection line 431 is located, the second anode 322 is electrically connected to the connection line 431 through the third adapter block 422, and / or the connection line 431 is electrically connected to the second adapter block 412 through the third adapter block 422.

[0117] In some embodiments, since the number of second anodes 322 is large, the second anodes 322 at different positions can be electrically connected to the second pixel circuit 230 through the connection lines 431 of different connection layers 430. Exemplarily, the second anodes of different sub-pixels 120 of the same pixel unit (including at least red sub-pixels, green sub-pixels, and blue sub-pixels) are electrically connected to the second pixel circuit 230 through the connection lines 431 of different layers; or, two adjacent second anodes 322 are electrically connected to the second pixel circuit 230 through the connection lines 431 of different layers, and so on, which are not listed one by one here.

[0118] For example, referring to FIG5A , the second anode 322 is electrically connected to the second pixel circuit 230 via a connection line 431 in the third connection layer 4303; Figure 5B, the second anode 322 is electrically connected to the second pixel circuit 230 through the connection line 431 in the first connection layer 4301. Figure 5B In Figure 4 The second anode 322 cut by A″-A″ is the second anode 322 located in the central area of ​​the functional device area 102 , so that there is no redundant pixel circuit on the side of the second anode 322 close to the substrate 110 .

[0119] In some quantities, see Figures 5 and Figure 7 The display panel 100 further includes a pixel defining layer 450 disposed on a side of the anode layer 320 away from the substrate 120 . The pixel defining layer 450 includes a plurality of opening areas 451 . One first anode 321 or one second anode 321 corresponds to one opening area 451 .

[0120] A light-emitting functional layer 460 is provided in the opening area 451. Exemplarily, the light-emitting functional layer 460 includes one or more layers of an electron transport layer (election transporting layer, ETL), an electron injection layer (election injection layer, EIL), a hole transporting layer (hole transporting layer, HTL) and a hole injection layer (hole injection layer, HIL).

[0121] The display panel 100 further includes a cathode conductive layer 470 disposed on a side of the pixel defining layer 450 and the light emitting functional layer away from the substrate 120 , and an encapsulation layer 480 located on a side of the cathode conductive layer 470 away from the substrate 120 .

[0122] Some embodiments of the present disclosure also provide a method for manufacturing a display panel 100, wherein the display panel 100 includes a main display area 101 and a functional device area 102, wherein the main display area 101 at least partially surrounds the functional device area 102; the display panel 100 includes a plurality of first pixel circuits 210, and a plurality of redundant pixel circuits 220, wherein the plurality of first pixel circuits 210 are located in the main display area 101, and the plurality of redundant pixel circuits 220 are adjacent to the first pixel circuits 210 in the main display area 101 close to the functional device area 102.

[0123] The above-mentioned production method comprises:

[0124] S10 , forming an active layer 310 on the substrate 120 .

[0125] The active layer 310 includes a first active layer pattern 312 of a plurality of first pixel circuits 210 , and a redundant active layer pattern 311 of a plurality of redundant pixel circuits 220 .

[0126] S20 , forming an anode layer 320 on a side of the active layer 310 away from the substrate 120 .

[0127] The anode layer 320 includes a plurality of first anodes 321 located in the main display area 101 , each of the first anodes 321 is electrically connected to a first pixel circuit 210 ; and the plurality of redundant pixel circuits 220 are electrically insulated from the anode layer 320 .

[0128] The display panel 100 obtained by the above-mentioned manufacturing method includes a redundant pixel circuit 220 adjacent to the first pixel circuit 210 on the side close to the functional device area 102 of the first pixel circuit 210 located at the edge of the main display area 101 close to the functional device area 102, and the redundant pixel circuit 220 includes a redundant active layer pattern 311 located in the active layer 310, thereby avoiding the problem of poor uniformity of the first active layer pattern 312 of the first pixel circuit 210, so that the sub-pixel 120 where the first anode 321 located at the edge of the main display area 101 close to the functional device area 102 can emit light normally.

[0129] In some embodiments, the first pixel circuit 210 includes a plurality of first thin film transistors 211 and a first storage capacitor 212. Between S10 of forming an active layer 310 on the substrate 120 and S20 of forming an anode layer 320 on a side of the active layer 310 away from the substrate 120, the manufacturing method further includes:

[0130] S11 , forming a first gate conductive layer 330 on a side of the active layer 310 away from the substrate 120 .

[0131] The first gate conductive layer 330 includes a first gate pattern 331 of a plurality of first pixel circuits 210 . The first gate pattern 331 includes gates G1 of a plurality of first thin film transistors 211 , a first electrode C11 of a first storage capacitor 212 , a scan line GL, and a light emitting signal line EM.

[0132] S12 , forming a second gate conductive layer 340 on a side of the first gate conductive layer 330 away from the substrate 120 .

[0133] The second gate conductive layer 340 includes a second gate pattern 341 of a plurality of first pixel circuits 210 , and the second gate pattern 341 includes a second plate C12 of the first storage capacitor 212 , a first initialization power line Vint1 , and a second initialization power line Vint2 .

[0134] S13 , forming a source-drain conductive layer 350 on a side of the second gate conductive layer 340 away from the substrate 120 .

[0135] The source-drain conductive layer 350 includes a plurality of source-drain conductive patterns 351 of the first pixel circuits 210 . The source-drain conductive patterns 351 include the source electrodes S1 and the drain electrodes D1 of the first thin film transistors 30 , the data line DATA, and the voltage signal line VDD.

[0136] The first active layer pattern 312 , the first gate pattern 331 , the second gate pattern 341 and the source-drain conductive pattern 351 together constitute the first pixel circuit 210 .

[0137] In some embodiments, the redundant pixel circuit 220 may include only a redundant active layer pattern 311, or may include a redundant active layer pattern 311, a redundant first gate pattern 332, a redundant second gate pattern 342, and a redundant source and drain conductive layer pattern 352 sequentially stacked on the substrate 120.

[0138] When the redundant pixel circuit 220 only includes the redundant active layer pattern 311, the orthographic projections of all patterns of the first gate conductive layer 330, all patterns of the second gate conductive layer 340, and all patterns of the source-drain conductive layer 350 on the substrate 120 are separated from the orthographic projections of the redundant active layer pattern 311 on the substrate 120.

[0139] In the case where the redundant pixel circuit 220 includes multiple redundant thin film transistors 221 and redundant storage capacitors 222; that is, the redundant pixel circuit 220 also includes a redundant active layer pattern 311, a redundant first gate pattern 332, a redundant second gate pattern 342, and a redundant source and drain conductive layer pattern 352 sequentially stacked on the substrate 120.

[0140] The first gate conductive layer 330 further includes a first redundant gate pattern 332 of multiple redundant pixel circuits 220 . The redundant gate pattern 332 includes gates G2 of multiple redundant thin film transistors 221 and a first electrode plate C21 of a redundant storage capacitor 222 . The first redundant gate pattern 332 is disposed in the same layer as the first gate pattern 331 .

[0141] The second gate conductive layer 340 further includes a second redundant gate pattern 342 of a plurality of redundant pixel circuits 220 . The second redundant gate pattern 342 includes a second electrode plate C22 of a redundant storage capacitor 222 . The second redundant gate pattern 342 is disposed in the same layer as the second gate pattern 341 .

[0142] The source-drain conductive layer 350 also includes a redundant source-drain conductive pattern 352 of multiple redundant pixel circuits 220, and the redundant source-drain conductive pattern 352 includes a source S2 and a drain D2 of multiple redundant thin film transistors 221; the redundant source-drain conductive pattern 352 is electrically insulated from the anode layer 320, and the redundant source-drain conductive pattern 352 is arranged on the same layer as the source-drain conductive pattern 351.

[0143] The structure of the redundant pixel circuit 220 is the same as that of the first pixel circuit 210. However, the redundant pixel circuit 220 is electrically insulated from the anode layer 320, and the redundant pixel circuit 220 does not control any light-emitting device 30 to emit light; the first pixel circuit 210 is electrically connected to the first anode 321, and is used to control the light-emitting device 30 where the first anode 321 is located. The redundant pixel circuit 220 can improve the uniformity of the first pixel circuit 210, avoid the problem of Vth shift in the first pixel circuit 210, and thus solve the problem of abnormal display of the light-emitting device 30 connected to the first pixel circuit 210 located at the edge of the main display area 101 close to the functional device area 102.

[0144] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or substitutions that can be thought of by any person skilled in the art within the technical scope disclosed in the present disclosure should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A display panel, characterized in that: It comprises a main display area and a functional device area, wherein the main display area at least partially surrounds the functional device area; The display panel comprises a plurality of first pixel circuits, a plurality of second pixel circuits and a plurality of redundant pixel circuits, wherein the plurality of first pixel circuits are located in the main display area, and the plurality of second pixel circuits are arranged in an area of ​​the display panel other than the functional device area; The display panel comprises an active layer and an anode layer which are sequentially arranged in a direction perpendicular to the substrate and away from the substrate; The anode layer includes a plurality of first anodes located in the main display area and a plurality of second anodes located in the functional device area, each first anode is electrically connected to a first pixel circuit, an orthographic projection of at least one second anode on the substrate at least partially overlaps with an orthographic projection of the redundant pixel circuit on the substrate, and each second anode is electrically connected to a second pixel circuit; The plurality of redundant pixel circuits are adjacent to a plurality of first pixel circuits disposed at an edge of the main display area close to the functional device area; The redundant pixel circuit at least comprises a redundant active layer pattern located in the active layer, and the redundant pixel circuit is electrically insulated from the anode layer; In two redundant pixel circuits adjacent to each other along a first direction, the redundant active layer patterns are separated from each other, and the first direction is a row direction in which the plurality of first pixel circuits are arranged; In two redundant pixel circuits adjacent to each other along a second direction, the redundant active layer patterns are separated from each other, and the second direction is a column direction in which the plurality of first pixel circuits are arranged.

2. The display panel according to claim 1, characterized in that: The first pixel circuits in any row are arranged along a first direction, and the first pixel circuits in any column are arranged along a second direction, and the first direction intersects the second direction; At least two redundant pixel circuits arranged along the first direction are provided at an edge of any row of first pixel circuits intersecting with the boundary of the functional device area close to the functional device area; At least two redundant pixel circuits arranged along the second direction are arranged at an edge close to the functional device area of ​​any column of first pixel circuits intersecting with the boundary of the functional device area.

3. The display panel according to claim 2, characterized in that: At an edge of any row of first pixel circuits intersecting the functional device area and close to the functional device area, 2 to 4 redundant pixel circuits arranged along the first direction are provided; Two to four redundant pixel circuits arranged along the second direction are arranged near the edge of the functional device area in any column of the first pixel circuits intersecting with the functional device area.

4. The display panel according to any one of claims 1 to 3, characterized in that: The plurality of redundant pixel circuits are located in a transition region; the transition region comprises: A first straight line extension section is located at an edge of the transition area in the second direction, and the first straight line extension section is provided with at least two rows of redundant pixel circuits; The two second straight line extension segments are respectively located at two edges of the transition area in the first direction, and each second straight line extension segment is provided with at least two columns of redundant pixel circuits.

5. The display panel according to claim 4, characterized in that: The transition zone also includes: Four fold line extension segments, each fold line extension segment includes a plurality of line segments connected in sequence, each line segment is provided with a plurality of rows of redundant pixel circuits, the plurality of rows of redundant pixel circuits located in different line segments are staggered in a first direction, and the first straight line extension segment and the second straight line extension segment are connected via the fold line extension segment.

6. The display panel according to claim 5, characterized in that: The transition zone is a ring with an opening on one side, and the opening is located at an edge of the transition zone opposite to the first straight line segment; or, The transition zone further includes a third straight line extension segment, which is located at an edge of the transition zone opposite to the first straight line segment, and includes at least two rows of redundant pixel circuits; the transition zone is a closed ring.

7. The display panel according to claim 5, characterized in that: The pattern formed by the arrangement of the plurality of redundant pixel circuits is symmetrical with respect to a straight line along the first direction of the transition region; and / or, The pattern formed by the arrangement of the plurality of redundant pixel circuits is symmetrical with respect to a straight line along the second direction of the transition region.

8. The display panel according to any one of claims 1 to 3, characterized in that: The first pixel circuit includes a plurality of first thin film transistors and a first storage capacitor; the active layer further includes a first active layer pattern of the plurality of first thin film transistors; The display panel further includes: A first gate conductive layer, disposed between the active layer and the anode layer, including first gate patterns of the plurality of first pixel circuits, wherein the first gate patterns include gates of the plurality of first thin film transistors, a first electrode plate of the first storage capacitor, a scan line, and a light emitting signal line; A second gate conductive layer, disposed between the first gate conductive layer and the anode layer, including a second gate pattern of the plurality of first pixel circuits, wherein the second gate pattern includes a second plate of the first storage capacitor, a first initialization power line, and a second initialization power line; The source-drain conductive layer is disposed between the second gate conductive layer and the anode layer, and includes source-drain conductive patterns of the plurality of first pixel circuits, and the source-drain conductive patterns include source and drain electrodes, data lines, and voltage signal lines of the plurality of first thin film transistors.

9. The display panel according to claim 8, characterized in that: The orthographic projections of all patterns of the first gate conductive layer, all patterns of the second gate conductive layer, and all patterns of the source-drain conductive layer on the substrate are separated from the orthographic projections of the redundant active layer patterns on the substrate.

10. The display panel according to claim 9, characterized in that: Also includes: a first gate insulating layer, disposed between the active layer and the first gate conductive layer; A second gate insulating layer, disposed between the first gate conductive layer and the second gate conductive layer; an interlayer insulating layer, disposed between the second gate conductive layer and the source-drain conductive layer; Wherein, the first gate insulating layer, the second gate insulating layer and the interlayer insulating layer all cover the redundant active layer pattern; A plurality of vias are provided in the first gate insulating layer, the second gate insulating layer and the interlayer insulating layer, the vias pass through the interlayer insulating layer, the second gate insulating layer and the first gate insulating layer, and the orthographic projection of the vias on the substrate is located within the orthographic projection range of the redundant active layer pattern on the substrate.

11. The display panel according to claim 10, characterized in that: Also includes: A passivation layer, disposed between the source-drain conductive layer and the anode layer, and covering the redundant active layer pattern; The via hole is filled with the material of the passivation layer.

12. The display panel according to claim 8, characterized in that: The redundant pixel circuit includes a plurality of redundant thin film transistors and a redundant storage capacitor; The first gate conductive layer further includes a first redundant gate pattern of the plurality of redundant pixel circuits, the first redundant gate pattern including gates of the plurality of redundant thin film transistors and a first plate of the redundant storage capacitor; The second gate conductive layer further includes a second redundant gate pattern of the plurality of redundant pixel circuits, the second redundant gate pattern including a second plate of the redundant storage capacitor; The source-drain conductive layer further includes redundant source-drain conductive patterns of the plurality of redundant pixel circuits, the redundant source-drain conductive patterns including sources and drains of the plurality of redundant thin film transistors; the redundant source-drain conductive patterns are electrically insulated from the anode layer.

13. The display panel according to claim 12, characterized in that: In two redundant pixel circuits adjacent to each other along the first direction, the first redundant gate patterns are connected, and the second redundant gate patterns are connected; In two redundant pixel circuits adjacent to each other along the second direction, the redundant source-drain conductive patterns are connected.

14. The display panel according to claim 1, characterized in that: Also includes: A transfer conductive layer, located between the film layer where the plurality of first pixel circuits and the plurality of second pixel circuits are located and the anode layer, comprising a plurality of transfer blocks separated from each other; The plurality of adapter blocks include a first adapter block electrically connected to the first pixel circuit, and a second adapter block electrically connected to the second pixel circuit; The orthographic projection of the first adapter block on the substrate covers the first connection node of the first pixel circuit electrically connected thereto, and is electrically connected to the first connection node; the first connection node is a node in the first pixel circuit configured to be electrically connected to the first anode; The orthographic projection of the second adapter block on the substrate covers the second connection node of the second pixel circuit electrically connected thereto and is electrically connected to the second connection node; the second connection node is a node in the second pixel circuit configured to be electrically connected to the second anode.

15. The display panel according to claim 14, characterized in that: The plurality of first pixel circuits and the plurality of second pixel circuits are both located in the main display area; The plurality of second pixel circuits are arranged in a plurality of rows and a plurality of columns, and a plurality of first pixel circuits are arranged between two adjacent second pixel circuits in the same row.

16. The display panel according to claim 14, characterized in that: Also includes a frame area surrounding the main display area; The plurality of second pixel circuits are located in the frame area.

17. The display panel according to any one of claims 14 to 16, characterized in that: Also includes: At least one connection layer is located between the switching conductive layer and the anode layer; the connection layer includes a plurality of connection lines, one end of the connection line is electrically connected to the second pixel circuit through a second switching block, and the other end of the connection line is electrically connected to the second anode.

18. A display device, characterized in that: The invention comprises the display panel according to any one of claims 1 to 17.

19. A method for manufacturing a display panel, characterized in that: The display panel comprises a main display area and a functional device area, wherein the main display area at least partially surrounds the functional device area; the display panel comprises a plurality of first pixel circuits, a plurality of second pixel circuits and a plurality of redundant pixel circuits, wherein the plurality of first pixel circuits are located in the main display area, the plurality of second pixel circuits are arranged in an area of ​​the display panel other than the functional device area, and the plurality of redundant pixel circuits are adjacent to the first pixel circuits in the main display area close to the functional device area; The production method comprises: An active layer is fabricated on a substrate; the active layer comprises a first active layer pattern of the plurality of first pixel circuits and a redundant active layer pattern of the plurality of redundant pixel circuits; in two redundant pixel circuits adjacent to each other along a first direction, the redundant active layer patterns are separated from each other, the first direction being the row direction in which the plurality of first pixel circuits are arranged; in two redundant pixel circuits adjacent to each other along a second direction, the redundant active layer patterns are separated from each other, the second direction being the column direction in which the plurality of first pixel circuits are arranged; An anode layer is fabricated on a side of the active layer away from the substrate; the anode layer comprises a plurality of first anodes located in the main display area and a plurality of second anodes located in the functional device area, each first anode being electrically connected to a first pixel circuit; an orthographic projection of at least one second anode on the substrate at least partially overlaps with an orthographic projection of the redundant pixel circuit on the substrate, each second anode is electrically connected to a second pixel circuit, and the plurality of redundant pixel circuits are electrically insulated from the anode layer.

20. The method according to claim 19, characterized in that The first pixel circuit includes a plurality of first thin film transistors and a first storage capacitor; Between the step of fabricating an active layer on the substrate and the step of fabricating an anode layer on a side of the active layer away from the substrate, the method further includes: A first gate conductive layer is formed on a side of the active layer away from the substrate; the first gate conductive layer includes a first gate pattern of the plurality of first pixel circuits, and the first gate pattern includes gates of the plurality of first thin film transistors, a first electrode plate of the first storage capacitor, a scan line, and a light emitting signal line; A second gate conductive layer is formed on a side of the first gate conductive layer away from the substrate; the second gate conductive layer includes a second gate pattern of the plurality of first pixel circuits, and the second gate pattern includes a second plate of the first storage capacitor, a first initialization power line, and a second initialization power line; A source-drain conductive layer is formed on a side of the second gate conductive layer away from the substrate; the source-drain conductive layer includes source-drain conductive patterns of the plurality of first pixel circuits, and the source-drain conductive patterns include source electrodes and drain electrodes, data lines, and voltage signal lines of the plurality of first thin film transistors; The orthographic projections of all patterns of the first gate conductive layer, all patterns of the second gate conductive layer and all patterns of the source-drain conductive layer on the substrate are separated from the orthographic projections of the redundant active layer on the substrate; or, The redundant pixel circuit includes a plurality of redundant thin film transistors and a redundant storage capacitor; the first gate conductive layer also includes a first redundant gate pattern of the plurality of redundant pixel circuits, the redundant gate pattern includes the gates of the plurality of redundant thin film transistors and the first plate of the redundant storage capacitor; the second gate conductive layer also includes a second redundant gate pattern of the plurality of redundant pixel circuits, the second redundant gate pattern includes the second plate of the redundant storage capacitor; the source-drain conductive layer also includes a redundant source-drain conductive pattern of the plurality of redundant pixel circuits, the redundant source-drain conductive pattern includes the source and drain of the plurality of redundant thin film transistors; the redundant source-drain conductive pattern is electrically insulated from the anode layer.

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