Display substrate and manufacturing method thereof, and display device

Abstract

A display substrate and a preparation method thereof, and a display device, wherein the display substrate comprises a display area and a binding area located on one side of the display area, wherein the binding area comprises at least a lead area; the display area comprises a plurality of data lines and a plurality of data fan-out lines, and the lead area comprises a plurality of lead-out lines; at least one lead-out line is connected to the data line through the data fan-out line; in a plane perpendicular to the display substrate, the display substrate comprises a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer, wherein insulating layers are arranged between the first conductive layer and the second conductive layer, between the second conductive layer and the third conductive layer, and between the third conductive layer and the fourth conductive layer; the data lines and the data fan-out lines are arranged in different conductive layers.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to but are not limited to the field of display technology, and in particular to a display substrate and a method for preparing the same, and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) is an active light-emitting display device with the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, and extremely high response speed. With the continuous development of display technology, display devices using OLED as a light-emitting device and thin film transistors (TFT) for signal control have become the mainstream products in the current display field. Summary of the invention

[0003] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0004] The embodiment of the present disclosure provides a display substrate, comprising a display area and a binding area located at one side of the display area, wherein the binding area at least comprises a lead area; the display area comprises a plurality of data lines and a plurality of data fan-out lines, and the lead area comprises a plurality of lead-out lines; at least one lead-out line is connected to the data line through the data fan-out line;

[0005] In a plane perpendicular to the display substrate, the display substrate includes a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer, and an insulating layer is arranged between the first conductive layer and the second conductive layer, between the second conductive layer and the third conductive layer, and between the third conductive layer and the fourth conductive layer; the data line and the data fan-out line are arranged in different conductive layers.

[0006] In an exemplary embodiment, the at least one data fan-out line includes a first line segment and a second line segment; the first end of the first line segment is connected to the lead line, the second end of the first line segment extends in a direction away from the lead area and is connected to the first end of the second line segment; the second end of the second line segment extends in a direction close to the lead area and is connected to the data line through a via.

[0007] In an exemplary embodiment, the first line segment is parallel to a first direction, and a first angle is formed between the second line segment and the first direction, and the first angle is in a range of 20° to 70°.

[0008] In an exemplary embodiment, the second line segment includes an extension segment and a connection segment; the first end of the extension segment is located in the display area and connected to the second end of the first line segment, the second end of the extension segment extends toward the direction close to the lead area to the edge of the display area, and is connected to the first end of the connection segment, the second end of the connection segment extends toward the direction away from the display area, and is connected to the data line extending to the lead area through a via hole; the edge of the display area is the edge of the display area close to the lead area.

[0009] In an exemplary embodiment, the display area further includes a first power line and a plate connection line, the first power line extends along a first direction, and the plate connection line extends along a second direction; the second direction intersects the first direction;

[0010] The extended segment includes M1 first sub-line segments and M1 second sub-line segments, M1 is a natural number greater than or equal to 1, the first sub-line segments and the second sub-line segments are alternately connected, the first sub-line segment located on one side of the extended segment is connected to the first line segment, and the second sub-line segment located on the other side of the extended segment is connected to the connecting segment, the orthographic projections of the first line segment and the second sub-line segment on the display substrate plane both overlap with the orthographic projection of the first power line on the display substrate plane, and the orthographic projection of the first sub-line segment on the display substrate plane overlaps with the orthographic projection of the electrode connecting line on the display substrate plane.

[0011] In an exemplary embodiment, the display area further includes a first power line and a plate connection line, the first power line extends along a first direction, and a second angle is formed between the plate connection line and the first direction, and the second angle is 20° to 70°;

[0012] The extended segment includes M1 first sub-line segments and M1 second sub-line segments, M1 is a natural number greater than or equal to 1, the first sub-line segments and the second sub-line segments are alternately connected, the first sub-line segment located on one side of the extended segment is connected to the first line segment, and the second sub-line segment located on the other side of the extended segment is connected to the connecting segment, the orthographic projections of the first line segment and the second sub-line segment on the display substrate plane both overlap with the orthographic projection of the first power line on the display substrate plane, and the orthographic projection of the first sub-line segment on the display substrate plane overlaps with the orthographic projection of the electrode connecting line on the display substrate plane.

[0013] In an exemplary embodiment, the plate connection line is located in the second conductive layer, the first power line is located in the third conductive layer, and the data fan-out line is located in the fourth conductive layer.

[0014] In an exemplary embodiment, the display area further includes a first power line, an initial signal line and a plate connection line, the first power line extends along a first direction, the initial signal line and the plate connection line both extend along a second direction; the second direction intersects the first direction;

[0015] The extended segment includes M1 first sub-line segments and M1 second sub-line segments, M1 is a natural number greater than or equal to 1, the first sub-line segments and the second sub-line segments are alternately connected, the first sub-line segment located on one side of the extended segment is connected to the first line segment, and the second sub-line segment located on the other side of the extended segment is connected to the connecting segment, the orthographic projections of the first line segment and the second sub-line segment on the display substrate plane both overlap with the orthographic projection of the first power line on the display substrate plane, and the orthographic projection of the first sub-line segment on the display substrate plane overlaps with any one of the following: the initial signal line and the electrode connecting line, the orthographic projection on the display substrate plane overlaps.

[0016] In an exemplary embodiment, the display area further includes a first power line, an initial signal line and a plate connection line, the first power line extends along a first direction, the initial signal line and the plate connection line both have a second angle with the first direction, and the second angle is 20° to 70°;

[0017] The extended segment includes M1 first sub-line segments and M1 second sub-line segments, M1 is a natural number greater than or equal to 1, the first sub-line segments and the second sub-line segments are alternately connected, the first sub-line segment located on one side of the extended segment is connected to the first line segment, and the second sub-line segment located on the other side of the extended segment is connected to the connecting segment, the orthographic projections of the first line segment and the second sub-line segment on the display substrate plane both overlap with the orthographic projection of the first power line on the display substrate plane, and the orthographic projection of the first sub-line segment on the display substrate plane overlaps with any one of the following: the initial signal line and the electrode connecting line, the orthographic projection on the display substrate plane overlaps.

[0018] In an exemplary embodiment, the initial signal line and the plate connection line are both located in the second conductive layer, the first power line is located in the third conductive layer, and the data fan-out line is located in the fourth conductive layer.

[0019] In an exemplary embodiment, the widths of the plurality of lead wires in the lead wire region along the second direction are the same, and the intervals between adjacent lead wires along the second direction are the same.

[0020] In an exemplary embodiment, the plurality of lead wires of the lead wire area include a first lead wire group and a second lead wire group, and the lead wires of the first lead wire group and the lead wires of the second lead wire group are alternately arranged along the second direction;

[0021] The plurality of lead wires in the first lead wire group are connected to the data lines via the plurality of data fan-out lines, and the plurality of lead wires in the second lead wire group are directly connected to the data lines.

[0022] An embodiment of the present disclosure further provides a display device, comprising a display substrate as described in any of the preceding items.

[0023] The embodiment of the present disclosure further provides a method for preparing a display substrate, wherein the display substrate comprises a display area and a binding area located on one side of the display area, wherein the binding area at least comprises a lead area; the preparation method comprises:

[0024] A plurality of data lines and a plurality of data fan-out lines are formed in the display area, and a plurality of lead-out lines are formed in the lead area; at least one lead-out line is connected to the data line through the data fan-out line; in a plane perpendicular to the display substrate, the display substrate comprises a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer, and insulating layers are arranged between the first conductive layer and the second conductive layer, between the second conductive layer and the third conductive layer, and between the third conductive layer and the fourth conductive layer; the data lines and the data fan-out lines are arranged in different conductive layers.

[0025] Other aspects will become apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The accompanying drawings are used to provide a further understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation on the technical solution of the present disclosure. The shapes and sizes of the components in the accompanying drawings do not reflect the actual proportions and are only intended to illustrate the contents of the present disclosure.

[0027] Figure 1 is a structural schematic diagram of a display device;

[0028] Figure 2 It is a schematic diagram of a planar structure of a display substrate;

[0029] Figure 3 It is a schematic diagram of the planar structure of a display area in a display substrate;

[0030] Figure 4 A schematic diagram of the cross-sectional structure of a display area in a display substrate;

[0031] Figure 5 is a schematic diagram of an equivalent circuit of a pixel driving circuit;

[0032] Figure 6 is a working timing diagram of a pixel driving circuit;

[0033] Figure 7 A schematic diagram of a planar structure showing a binding region in a substrate;

[0034] Figure 8 A schematic diagram of a data fan-out line in a binding area;

[0035] Fig. 9 A schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure;

[0036] Fig.10 for Fig. 9 A side view of the substrate is shown in FIG.

[0037] Fig.11 A schematic diagram of the structure of a lead-out line and a data fan-out line according to an exemplary embodiment of the present disclosure;

[0038] Fig.12 for Fig.11 Enlarged view of the middle C1 region;

[0039] Fig.13 for Fig.12 Enlarged view of the middle C2 region;

[0040] Fig.14 for Fig.13 Sectional view along AA direction;

[0041] Fig.15 It is a schematic diagram of the structure of another lead-out line and a data fan-out line of an exemplary embodiment of the present disclosure;

[0042] Fig.16 for Fig.15 Enlarged view of the middle C3 region;

[0043] Fig.17 It is a structural schematic diagram of another lead-out line and a data fan-out line of an exemplary embodiment of the present disclosure;

[0044] Fig.18 for Fig.17 Enlarged view of the middle C4 region;

[0045] Fig.19 It is a structural schematic diagram of another lead-out line and a data fan-out line of an exemplary embodiment of the present disclosure;

[0046] Fig. 20 for Fig.19 Enlarged view of the middle C5 region;

[0047] Fig.21a This is a schematic diagram of a display substrate after a semiconductor layer pattern is formed on the display substrate of the present disclosure;

[0048] Figure 21b for Fig.21a Sectional view along AA direction;

[0049] Fig.22a This is a schematic diagram of a display substrate after a first conductive layer pattern is formed on the display substrate of the present disclosure;

[0050] Figure 22b for Fig.22a Sectional view along AA direction;

[0051] Fig.23a This is a schematic diagram of a display substrate after a second conductive layer pattern is formed on the display substrate of the present disclosure;

[0052] Figure 23b for Fig.23a Sectional view along AA direction;

[0053] Fig.24a This is a schematic diagram of a display substrate after a fourth insulating layer pattern is formed on the display substrate of the present disclosure;

[0054] Figure 24b for Fig.24a Sectional view along AA direction;

[0055] Fig.25a This is a schematic diagram of a display substrate after a third conductive layer pattern is formed on the display substrate of the present disclosure;

[0056] Fig.25b for Fig.25a Sectional view along AA direction;

[0057] Fig.26a This is a schematic diagram of a display substrate after a fourth conductive layer pattern is formed on the display substrate of the present disclosure;

[0058] Figure 26b for Fig.26a Sectional view along AA direction;

[0059] Fig.27a This is a schematic diagram of a display substrate after a flat layer pattern is formed in the present disclosure;

[0060] Figure 27b for Fig.27a Sectional view along AA direction;

[0061] Fig.28a This is a schematic diagram of a display substrate after an anode pattern is formed in the present disclosure;

[0062] Fig.28b for Fig.28a Sectional view along AA direction;

[0063] Fig.29 The figure is a schematic diagram of the planar structure of a display area in a display substrate. DETAILED DESCRIPTION

[0064] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail in conjunction with the accompanying drawings hereinafter. Note that the embodiments can be implemented in a number of different forms. A person of ordinary skill in the relevant technical field can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits the detailed description of some known functions and known components. The drawings of the embodiments of the present disclosure only involve the structures involved in the embodiments of the present disclosure, and other structures can refer to the general design.

[0065] In the drawings, the size of each component, the thickness of a layer, or the area is sometimes exaggerated for the sake of clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to this size, and the shape and size of each component in the drawings do not reflect the true proportion. In addition, the drawings schematically show ideal examples, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0066] In the present specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0067] In this specification, for the sake of convenience, the words and phrases indicating the orientation or positional relationship, such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words and phrases described in the specification, and can be appropriately replaced according to the situation.

[0068] In this specification, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this disclosure can be understood according to specific circumstances.

[0069] In this specification, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to a region where current mainly flows.

[0070] In this specification, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors with opposite polarities or when the direction of current changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and the "drain electrode" may be interchanged.

[0071] In this specification, "electrical connection" includes the case where components are connected together through an element having some electrical function. There is no particular limitation on the "element having some electrical function" as long as it can transmit and receive electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0072] In this specification, "parallel" means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes a state where the angle is greater than -5° and less than 5°. In addition, "perpendicular" means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes a state where the angle is greater than 85° and less than 95°.

[0073] In this specification, "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced by "conductive film". Similarly, "insulating film" may be replaced by "insulating layer".

[0074] The term "about" in the present disclosure refers to a numerical value that is not strictly limited to allow for process and measurement errors.

[0075] Figure 1 FIG. 1 is a schematic diagram of the structure of a display device. Figure 1As shown, the OLED display device may include a timing controller, a data signal driver, a scan signal driver, a light emitting signal driver, and a pixel array, and the pixel array may include a plurality of scan signal lines (S1 to Sm), a plurality of data lines (D1 to Dn), a plurality of light emitting signal lines (E1 to Eo), and a plurality of sub-pixels Pxij. In an exemplary embodiment, the timing controller may provide a grayscale value and a control signal suitable for the specification of the data signal driver to the data signal driver, a clock signal suitable for the specification of the scan signal driver, a scan start signal, etc. to the scan signal driver, and a clock signal suitable for the specification of the light emitting signal driver, an emission stop signal, etc. to the light emitting signal driver. The data signal driver may generate a data voltage to be provided to the data lines D1, D2, D3, ... and Dn using the grayscale value and the control signal received from the timing controller. For example, the data signal driver may sample the grayscale value using the clock signal, and apply the data voltage corresponding to the grayscale value to the data lines D1 to Dn in units of pixel rows, where n may be a natural number. The scan signal driver may generate a scan signal to be provided to the scan signal lines S1, S2, S3, ... and Sm by receiving a clock signal, a scan start signal, etc. from a timing controller. For example, the scan signal driver may sequentially provide a scan signal having an on-level pulse to the scan signal lines S1 to Sm. For example, the scan signal driver may be constructed in the form of a shift register, and may generate a scan signal in a manner that sequentially transmits a scan start signal provided in the form of an on-level pulse to a next-level circuit under the control of a clock signal, and m may be a natural number. The luminous signal driver may generate an emission signal to be provided to the luminous signal lines E1, E2, E3, ... and Eo by receiving a clock signal, an emission stop signal, etc. from a timing controller. For example, the luminous signal driver may sequentially provide an emission signal having an off-level pulse to the luminous signal lines E1 to Eo. For example, the luminous signal driver may be constructed in the form of a shift register, and may sequentially transmit a luminous stop signal provided in the form of an off-level pulse to a next-level circuit under the control of a clock signal, and o may be a natural number. The pixel array may include a plurality of sub-pixels Pxij, each of which may be connected to a corresponding data line, a corresponding scan signal line, and a corresponding light emitting signal line, and i and j may be natural numbers. The sub-pixel Pxij may refer to a sub-pixel in which a transistor is connected to the i-th scan signal line and to the j-th data line.

[0076] Figure 2 FIG. 1 is a schematic diagram of a planar structure of a display substrate. Figure 2As shown, the display substrate may include a display area 100, a binding area 200 located on one side of the display area 100, and a frame area 300 located on the other side of the display area 100. The display area 100 may include a plurality of sub-pixels configured to display dynamic pictures or still images, the binding area 200 may include connection lines and circuits for connecting a plurality of data lines to an integrated circuit, the frame area 300 may include a power line for transmitting a voltage signal, the binding area 200 and the frame area 300 may include an isolation dam of a ring structure, at least one side of the frame area 300 may be a curled area formed by bending, or the display area 100 and the frame area 300 may both be bent or curved areas, which is not limited in the present disclosure.

[0077] In an exemplary embodiment, the display area may include a plurality of pixel units arranged in a matrix manner. Figure 3 FIG. 1 is a schematic diagram of a planar structure of a display area in a display substrate. Figure 3 As shown, the display substrate may include a plurality of pixel units P arranged in a matrix, at least one of the plurality of pixel units P includes a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light, and the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 each include a pixel driving circuit and a light-emitting device. The pixel driving circuits in the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 are respectively connected to the scanning signal line, the data line, and the light-emitting signal line, and the pixel driving circuit is configured to receive the data voltage transmitted by the data line under the control of the scanning signal line and the light-emitting signal line, and output a corresponding current to the light-emitting device. The light-emitting devices in the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 are respectively connected to the pixel driving circuits of the sub-pixels in which they are located, and the light-emitting devices are configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel in which they are located.

[0078] In an exemplary embodiment, the pixel unit P may include a red (R) sub-pixel, a green (G) sub-pixel, and a blue (B) sub-pixel, or may include a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, which is not limited in the present disclosure. In an exemplary embodiment, the shape of the sub-pixel in the pixel unit may be a rectangle, a rhombus, a pentagon, or a hexagon. When the pixel unit includes three sub-pixels, the three sub-pixels may be arranged in a horizontal parallel, vertical parallel, or in a triangular manner. When the pixel unit includes four sub-pixels, the four sub-pixels may be arranged in a horizontal parallel, vertical parallel, or square manner, which is not limited in the present disclosure.

[0079] Figure 4 FIG. 1 is a schematic diagram of a cross-sectional structure of a display area in a display substrate, illustrating the structure of three sub-pixels of an OLED display substrate. Figure 4 As shown, on a plane perpendicular to the display substrate, the display substrate may include a driving circuit layer 102 disposed on a substrate 101, a light emitting structure layer 103 disposed on a side of the driving circuit layer 102 away from the substrate 101, and an encapsulation layer 104 disposed on a side of the light emitting structure layer 103 away from the substrate 101. In some possible implementations, the display substrate may include other film layers, such as spacers, etc., which are not limited in the present disclosure.

[0080] In an exemplary embodiment, the substrate 101 may be a flexible substrate, or may be a rigid substrate. The driving circuit layer 102 of each sub-pixel may include a plurality of transistors and storage capacitors constituting a pixel driving circuit. Figure 4 Only one transistor 102A and one storage capacitor 102B are taken as examples. The light-emitting structure layer 103 may include an anode 301, a pixel definition layer 302, an organic light-emitting layer 303 and a cathode 304. The anode 301 is connected to the drain electrode of the driving transistor 210 through a via, the organic light-emitting layer 303 is connected to the anode 301, and the cathode 304 is connected to the organic light-emitting layer 303. The organic light-emitting layer 303 emits light of corresponding colors under the drive of the anode 301 and the cathode 304. The encapsulation layer 104 may include a first encapsulation layer 401, a second encapsulation layer 402 and a third encapsulation layer 403 stacked together. The first encapsulation layer 401 and the third encapsulation layer 403 may be made of inorganic materials, and the second encapsulation layer 402 may be made of organic materials. The second encapsulation layer 402 is arranged between the first encapsulation layer 401 and the third encapsulation layer 403, which can ensure that external water vapor cannot enter the light-emitting structure layer 103.

[0081] In an exemplary embodiment, the organic light emitting layer 303 may include a stacked hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), an emitting layer (EML), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, the hole injection layers of all sub-pixels may be a common layer connected together, the electron injection layers of all sub-pixels may be a common layer connected together, the hole transport layers of all sub-pixels may be a common layer connected together, the electron transport layers of all sub-pixels may be a common layer connected together, the hole blocking layers of all sub-pixels may be a common layer connected together, the emitting layers of adjacent sub-pixels may have a small overlap, or may be isolated, and the electron blocking layers of adjacent sub-pixels may have a small overlap, or may be isolated.

[0082] In exemplary embodiments, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, or 7T1C structure. Figure 5 FIG. 1 is a schematic diagram of an equivalent circuit of a pixel driving circuit. Figure 5 As shown, the pixel driving circuit may include 7 switching transistors (first transistor T1 to seventh transistor T7), 1 storage capacitor C1 and 7 signal lines (data line DATA, first scanning signal line S1, second scanning signal line S2, initial signal line INIT, first power line VDD, second power line VSS and light emitting signal line EM).

[0083] In an exemplary embodiment, a gate electrode of the first transistor T1 is connected to the second scan signal line S2, a first electrode of the first transistor T1 is connected to the initial signal line INIT, and a second electrode of the first transistor is connected to the second node N2. A gate electrode of the second transistor T2 is connected to the first scan signal line S1, a first electrode of the second transistor T2 is connected to the second node N2, and a second electrode of the second transistor T2 is connected to the third node N3. A gate electrode of the third transistor T3 is connected to the second node N2, a first electrode of the third transistor T3 is connected to the first node N1, and a second electrode of the third transistor T3 is connected to the third node N3. A gate electrode of the fourth transistor T4 is connected to the first scan signal line S1, a first electrode of the fourth transistor T4 is connected to the data line DATA, and a second electrode of the fourth transistor T4 is connected to the first node N1. A gate electrode of the fifth transistor T5 is connected to the light emitting signal line EM, a first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and a second electrode of the fifth transistor T5 is connected to the first node N1. The gate electrode of the sixth transistor T6 is connected to the light emitting signal line EM, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light emitting device. The gate electrode of the seventh transistor T7 is connected to the second scanning signal line S2, the first electrode of the seventh transistor T7 is connected to the initial signal line INIT, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light emitting device. The first end of the storage capacitor C1 is connected to the first power supply line VDD, and the second end of the storage capacitor C1 is connected to the second node N2.

[0084] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 may be a P-type transistor, or may be an N-type transistor. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. In some possible implementations, the first transistor T1 to the seventh transistor T7 may include a P-type transistor and an N-type transistor.

[0085] In an exemplary embodiment, the second electrode of the light emitting device is connected to the second power line VSS, the signal of the second power line VSS is a low level signal, and the signal of the first power line VDD is a continuously provided high level signal. The first scanning signal line S1 is a scanning signal line in the pixel driving circuit of the current display row, and the second scanning signal line S2 is a scanning signal line in the pixel driving circuit of the previous display row, that is, for the nth display row, the first scanning signal line S1 is S(n), and the second scanning signal line S2 is S(n-1), and the second scanning signal line S2 of the current display row and the first scanning signal line S1 in the pixel driving circuit of the previous display row can be the same signal line, so as to reduce the signal lines of the display panel and realize the narrow frame of the display panel.

[0086] In an exemplary embodiment, the first scan signal line S1, the second scan signal line S2, the emission signal line EM, and the initial signal line INIT extend in a horizontal direction, and the second power line VSS, the first power line VDD, and the data line DATA extend in a vertical direction.

[0087] In an exemplary embodiment, the light emitting device may be an organic light emitting diode (OLED) including a first electrode (anode), an organic light emitting layer, and a second electrode (cathode) stacked.

[0088] Figure 6 This is a working timing diagram of a pixel driving circuit. Figure 5 The operation process of the pixel driving circuit of the example is described in detail. Figure 5 The pixel driving circuit includes 7 transistors (first transistor T1 to sixth transistor T7), 1 storage capacitor C1 and 7 signal lines (data line DATA, first scanning signal line S1, second scanning signal line S2, initial signal line INIT, first power line VDD, second power line VSS and light-emitting signal line EM), and all 7 transistors are P-type transistors.

[0089] In an exemplary embodiment, the operation process of the pixel driving circuit may include:

[0090] The first stage A1 is called the reset stage. The signal of the second scanning signal line S2 is a low-level signal, and the signals of the first scanning signal line S1 and the light-emitting signal line EM are high-level signals. The signal of the second scanning signal line S2 is a low-level signal, which turns on the first transistor T1. The signal of the initial signal line INIT is provided to the second node N2 to initialize the storage capacitor C1 and clear the original data voltage in the storage capacitor. The signals of the first scanning signal line S1 and the light-emitting signal line EM are high-level signals, which turns off the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7. In this stage, the OLED does not emit light.

[0091] The second stage A2 is called the data writing stage or the threshold compensation stage. The signal of the first scanning signal line S1 is a low level signal, the signals of the second scanning signal line S2 and the light emitting signal line EM are high level signals, and the data line DATA outputs the data voltage. In this stage, since the second end of the storage capacitor C1 is at a low level, the third transistor T3 is turned on. The signal of the first scanning signal line S1 is a low level signal, which turns on the second transistor T2, the fourth transistor T4 and the seventh transistor T7. The second transistor T2 and the fourth transistor T4 are turned on so that the data voltage output by the data line DATA is provided to the second node N2 through the first node N1, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2, and the difference between the data voltage output by the data line DATA and the threshold voltage of the third transistor T3 is charged into the storage capacitor C1. The voltage of the second end (second node N2) of the storage capacitor C1 is Vdata-|Vth|, Vdata is the data voltage output by the data line DATA, and Vth is the threshold voltage of the third transistor T3. The seventh transistor T7 is turned on so that the initial voltage of the initial signal line INIT is provided to the first electrode of the OLED, the first electrode of the OLED is initialized (reset), the pre-stored voltage inside it is cleared, the initialization is completed, and the OLED is ensured not to emit light. The signal of the second scanning signal line S2 is a high-level signal, which turns off the first transistor T1. The signal of the luminous signal line EM is a high-level signal, which turns off the fifth transistor T5 and the sixth transistor T6.

[0092] The third stage A3 is called the light-emitting stage, the signal of the light-emitting signal line EM is a low-level signal, and the signals of the first scanning signal line S1 and the second scanning signal line S2 are high-level signals. The signal of the light-emitting signal line EM is a low-level signal, so that the fifth transistor T5 and the sixth transistor T6 are turned on, and the power supply voltage output by the first power supply line VDD provides a driving voltage to the first electrode of the OLED through the turned-on fifth transistor T5, the third transistor T3 and the sixth transistor T6, driving the OLED to emit light.

[0093] During the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and the first electrode. Since the voltage of the second node N2 is Vdata-|Vth|, the driving current of the third transistor T3 is:

[0094] I=K*(Vgs-Vth) 2 =K*[(Vdd-Vdata+|Vth|)-Vth] 2 =K*[(Vdd-Vdata] 2

[0095] Among them, I is the driving current flowing through the third transistor T3, that is, the driving current driving the OLED, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vdata is the data voltage output by the data line DATA, and Vdd is the power supply voltage output by the first power supply line VDD.

[0096] Figure 7 A schematic diagram showing a planar structure of a binding area in a substrate. Figure 8 Figure 1 is a schematic diagram of a data fan-out line in a binding area. Figure 7 As shown, in a plane parallel to the display substrate, the binding area 200 is located on one side of the display area 100, and the binding area 200 may include a first fan-out area 201, a bending area 202, a second fan-out area 203, an anti-static area 204, a driver chip area 205 and a binding pin area 206 which are sequentially arranged in a direction away from the display area 100. The first fan-out area 201 includes at least a data fan-out line, and a plurality of data fan-out lines are configured to connect the data lines (Data Line) of the display area in a fan-out routing manner, as shown in FIG. Figure 8 As shown. The bending area 202 includes a composite insulating layer provided with grooves, which is configured to bend the binding area 200 to the back of the display area 100. The second fan-out area 203 includes a plurality of data fan-out lines led out in a fan-out routing manner. The anti-static area 204 includes an anti-static circuit, which is configured to prevent electrostatic damage to the display substrate by eliminating static electricity. The driving chip area 205 includes an integrated circuit (IC), which is configured to be connected to a plurality of data fan-out lines. The binding pin area 206 includes a binding pad (Bonding Pad), which is configured to be bound and connected to an external flexible printed circuit (FPC).

[0097] With the development of OLED display technology, consumers have higher and higher requirements for the display effect of display products, and extremely narrow borders have become a new trend in the development of display products. Therefore, the narrowing of the border or even the borderless design has received more and more attention in the design of OLED display products. At present, the left border, right border and upper border of the display device can be controlled within 1.0mm, but the narrowing design of the lower border (the border on the side of the binding area) is more difficult and has been maintained at about 2.0mm. This is because the data fan-out line is usually set in the fan-out area of ​​the binding area, and the fan-shaped area occupies a large space. Usually, the width of the binding area is smaller than the width of the display area. The signal lines of the integrated circuit and the binding pad in the binding area need to be introduced into the wider display area in a fan-out manner through the fan-out area. The greater the width difference between the display area and the binding area, the more oblique fan-out lines in the fan-shaped area, and the greater the distance between the driver chip area and the display area, the wider the lower border, resulting in the lower border being much larger than the left and right borders.

[0098] The exemplary embodiments of the present disclosure provide a display substrate. The display substrate may include a display area and a binding area located on one side of the display area, the binding area at least including a lead area; the display area includes a plurality of data lines and a plurality of data fan-out lines, the lead area includes a plurality of lead-out lines; at least one lead-out line is connected to the data line through the data fan-out line; in a plane perpendicular to the display substrate, the display substrate includes a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer, an insulating layer is provided between the first conductive layer and the second conductive layer, between the second conductive layer and the third conductive layer, and between the third conductive layer and the fourth conductive layer; the data line and the data fan-out line are provided in different conductive layers.

[0099] Fig. 9 is a schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure. Fig.10 for Fig. 9 A side view of the substrate is shown in FIG. Fig. 9 and Fig.10 As shown, the display substrate 10 may include a display area 100, a binding area 500 located at one side of the display area 100, and a frame area 300 located at the other side of the display area 100. In an exemplary embodiment, the display area 100 may be a planarized area, including a plurality of sub-pixels Pxij constituting a pixel array, a plurality of data lines, and a plurality of data fan-out lines, the plurality of sub-pixels Pxij are configured to display dynamic pictures or still images, the plurality of data lines are configured to provide data signals to the plurality of sub-pixels Pxij, the plurality of data fan-out lines are correspondingly connected to the plurality of data lines, and are configured to make the plurality of data lines correspondingly connected to the plurality of lead-out lines in the binding area 500. In an exemplary embodiment, the display substrate may be a flexible substrate, so the display substrate may be deformable, such as curling, bending, folding, or rolling.

[0100] In an exemplary embodiment, the binding area 500 may include a lead area 501, a bending area 502 and a composite circuit area 503 arranged in sequence along the opposite direction of the first direction D1 (the direction away from the display area), the lead area 501 is connected to the display area 100, the bending area 502 is connected to the lead area 501, and the composite circuit area 503 is connected to the bending area 502.

[0101] In an exemplary embodiment, the lead area 501 may be provided with a plurality of lead lines, one end of a portion of the plurality of lead lines being connected to a plurality of data fan-out lines in the display area 100, one end of another portion of the plurality of lead lines being connected to a plurality of data lines in the display area 100, and the other ends of the plurality of lead lines crossing the bending area 502 to connect to the integrated circuit of the composite circuit area 503, so that the integrated circuit applies data signals to the data lines through the lead lines and the data fan-out lines.

[0102] In an exemplary embodiment, the bending region 502 may be bent with a curvature in the third direction D3, and the surface of the composite circuit region 503 may be reversed, that is, the surface of the composite circuit region 503 facing upward may be converted to face downward by the bending of the bending region 502, and the third direction D3 intersects with the first direction D1. In an exemplary embodiment, when the bending region 502 is bent, the composite circuit region 503 may overlap with the display region 100 in the third direction D3 (thickness direction).

[0103] In an exemplary embodiment, the composite circuit area 503 may include an antistatic area, a driving chip area, and a binding pin area, the integrated circuit (IC) 20 may be bound and connected to the driving chip area, and the flexible printed circuit (FPC) 30 may be bound and connected to the binding pin area. In an exemplary embodiment, the integrated circuit 20 may generate a driving signal required for driving a sub-pixel, and may provide the driving signal to the sub-pixel in the display area 100. For example, the driving signal may be a data signal for driving the luminous brightness of the sub-pixel. In an exemplary embodiment, the integrated circuit 20 may be bound and connected to the driving chip area through an anisotropic conductive film or other means, and the width of the integrated circuit 20 in the second direction D2 may be less than the width of the composite circuit area 503 in the second direction D2, and the second direction D2 intersects with the first direction D1. In an exemplary embodiment, the binding pin area may be provided with a pad including a plurality of pins (PINs), and the flexible printed circuit 30 may be bound and connected to the pad.

[0104] In an exemplary embodiment, the first direction D1 may be an extension direction (column direction) of a data line in the display area, the second direction D2 may be an extension direction (row direction) of a scanning signal line in the display area, and the third direction D3 may be a direction perpendicular to the plane of the display substrate. The first direction D1 and the second direction D2 may be perpendicular to each other, and the first direction D1 and the third direction D3 may be perpendicular to each other.

[0105] Fig.11 FIG. 1 is a schematic diagram of a structure of a lead-out line and a data fan-out line according to an exemplary embodiment of the present disclosure. Fig.11 As shown, the display area 100 may include a plurality of sub-pixels, a plurality of data lines DA, and a plurality of data fan-out lines 700 arranged in a matrix manner, and the lead area 501 of the binding area may include a plurality of lead lines 600. In an exemplary embodiment, the plurality of sub-pixels in the display area 100 form a plurality of pixel rows and a plurality of pixel columns, the plurality of data lines DA extend in the opposite direction of the first direction D1, and are sequentially arranged at set intervals along the second direction D2, each data line DA is connected to all sub-pixels of a pixel column in the display area 100, and the end of each data line DA extends to the lead area 501 of the binding area. The first end of each data fan-out line 700 is connected to a portion of the lead lines 600 in the lead area 501, and the second end of each data fan-out line 700 is connected to a portion of the data lines DA extending to the lead area 501. A portion of the lead lines 600 in the lead area 501 is connected to the data fan-out line 700, and another portion of the lead lines 600 is connected to another portion of the data lines DA extending to the lead area 501.

[0106] In an exemplary embodiment, the display substrate has a center line O, which extends along the first direction D1 and divides the plurality of pixel columns of the display area 100 in half. The plurality of data lines DA in the display area 100, the plurality of data fan-out lines 700, and the plurality of lead lines 600 in the lead area 501 of the binding area may be symmetrically arranged relative to the center line O. In other exemplary embodiments, the plurality of data lines DA in the display area 100, the plurality of data fan-out lines 700, and the plurality of lead lines 600 in the lead area 501 of the binding area may also be asymmetrically arranged on both sides of the center line O. Exemplarily, the plurality of data lines DA in the display area 100, the plurality of data fan-out lines 700, and the plurality of lead lines 600 in the lead area 501 of the binding area may have similar designs on both sides of the center line O. The following is an example in which the left side of the display substrate includes N data lines, M data fan-out lines, and N lead lines, where N is a positive integer greater than 2, and M is a positive integer greater than 2 and less than N.

[0107] In an exemplary embodiment, the N data lines on the left side of the display area may include a first data line group and a second data line group divided according to the number size. The first data line group may include a first data line DA1, a second data line DA2, ..., an Mth data line, and the second data line group may include an (M+1)th data line, an (M+2)th data line, ..., an Nth data line.

[0108] In an exemplary embodiment, M may be the number of data lines that need to be led out in a fan-out manner. For example, when N is an even number, M may be N / 2, and when N is an odd number, M may be (N+1) / 2, or M may be (N-1) / 2. M may be set according to actual conditions, and the present disclosure does not limit this.

[0109] In an exemplary embodiment, a plurality of data lines of the first data line group are sequentially arranged along the second direction D2 in an ascending manner, a plurality of data lines of the second data line group are sequentially arranged along the second direction D2 in an ascending manner, and the second data line group is arranged on one side of the first data line group in the second direction D2. That is, the N data lines include a first data line DA1, a second data line DA2, ..., an Nth data line DAN sequentially arranged along the second direction D2, that is, the numbers of the N data lines are sequentially increased along the second direction D2. In an exemplary embodiment, the i-th data line may be a data line located in the i-th pixel column, and the i-th data line is connected to a sub-pixel in the i-th pixel column.

[0110] In an exemplary embodiment, the N lead wires on the left side of the lead wire area 501 may include a first lead wire group and a second lead wire group divided according to the number size. The first lead wire group may include a first lead wire 601, a second lead wire 602, ..., an Mth lead wire, and the second lead wire group may include an (M+1)th lead wire, an (M+2)th lead wire, ..., an Nth lead wire.

[0111] In an exemplary embodiment, the plurality of lead wires of the first lead wire group are sequentially arranged along the reverse direction of the second direction D2 in an ascending manner, the plurality of lead wires of the second lead wire group are sequentially arranged along the second direction D2 in an ascending manner, and the lead wires of the first lead wire group are alternately arranged with the lead wires of the second lead wire group. For example, the first lead wire is adjacent to the Nth lead wire, the second lead wire is adjacent to the N-1th lead wire, ..., the Mth lead wire is adjacent to the (M+1)th lead wire.

[0112] In an exemplary embodiment, multiple lead lines in the first lead group can be correspondingly connected to multiple data lines in the first data line group through multiple data fan-out lines, and multiple lead lines in the second lead group can be directly connected to multiple data lines in the second data line group, and the lead lines can provide data signals to the data lines directly or through the data fan-out lines.

[0113] In an exemplary embodiment, the first end of the i-th data fan-out line is connected to the i-th lead line in the first lead line group near the display area edge B, and the second end of the i-th data fan-out line first extends in a direction away from the lead area 501, then returns to the lead area 501, and is connected to the i-th data line in the first data line group extending to the lead area 501, i=1, 2, ..., M. In an exemplary embodiment, the display area edge B is the edge of the display area 100 on the side close to the lead area 501.

[0114] In an exemplary embodiment, the i-th data fan-out line may include a first line segment and a second line segment connected in sequence, wherein a first end of the first line segment is located near an edge B of the display area and is connected to the i-th lead line, and a second end of the first line segment is connected to a first end of the second line segment after extending in a direction away from the lead area. The second end of the second line segment is connected to the i-th data line extending to the lead area 501 after extending from the display area 100 to the lead area 501 in the direction of the lead area.

[0115] In an exemplary embodiment, the second line segment may include an extension segment and a connection segment, the first end of the extension segment is located in the display area 100 and is connected to the second end of the second line segment, the second end of the extension segment extends toward the direction close to the lead area to the edge B of the display area, and is connected to the first end of the connection segment, and the second end of the connection segment extends toward the direction away from the display area and is connected to the i-th data line extending to the lead area through a via.

[0116] In an exemplary embodiment, the connection segment may be a broken line segment including a vertical line segment parallel to the first direction D1 and a horizontal line segment parallel to the second direction D2.

[0117] In an exemplary embodiment, the plurality of data lines in the first and second data line groups may be arranged to be parallel to the first direction D1, and the plurality of lead lines in the first and second lead groups may be arranged to be parallel to the first direction D1, that is, the lead lines are parallel to the data lines.

[0118] In an exemplary embodiment, extension lines of the plurality of data lines in the second data line group in the first direction D1 may overlap with the plurality of lead lines in the second lead line group.

[0119] In an exemplary embodiment, the first line segments of the plurality of data fan-out lines may be arranged to be parallel to the first direction D1, and the second line segments of the plurality of data fan-out lines may be arranged to have a first angle θ1 with the first direction D1, and the first angle θ1 may be approximately greater than 0° and less than 90°.

[0120] In an exemplary embodiment, the first angle θ1 may be approximately 20° to 70°, and the first angle θ1 and the second angle θ2 may be the same, or may be different.

[0121] In an exemplary embodiment, at least one first line segment is disposed between adjacent data lines.

[0122] In an exemplary embodiment, multiple line segments of the kth data fan-out line can form a triangular routing, and the triangular routing formed by the kth data fan-out line is nested in the triangular routing formed by the k-1th data fan-out line to form a triangular nested structure, and the distance between the first end of the second line segment of the k-1th data fan-out line and the edge B of the display area is greater than the distance between the first end of the second line segment of the kth data fan-out line and the edge B of the display area, and the distance between the second ends of the first line segment and the second line segment in the k-1th data fan-out line is greater than the distance between the second ends of the first line segment and the second line segment in the k-1th data fan-out line, k=2,...,M.

[0123] Fig.12 for Fig.11 The enlarged view of the C1 area in the figure shows the structure of the lead-out line and the data fan-out line when N=8. Fig.12 As shown, the multiple data lines may include a first data line DA1, a second data line DA2, a third data line DA3, a fourth data line DA4, a fifth data line DA5, a sixth data line DA6, a seventh data line DA7 and an eighth data line DA8 arranged in sequence along the second direction D2, and the multiple lead lines of the lead area 501 of the binding area may include a first lead line 601, an eighth lead line 608, a second lead line 602, a seventh lead line 607, a third lead line 603, a sixth lead line 606, a fourth lead line 604 and a fifth lead line 605 arranged in sequence along the opposite direction of the second direction D2.

[0124] In an exemplary embodiment, a first end of the first data fan-out line 701 is connected to the first lead line 601 near the edge B of the display area, and a second end extends to the vicinity of the first data line DA1 of the display area 100, and then extends from the display area 100 to the lead area 501 to be connected to the first data line DA1. A first end of the second data fan-out line 702 is connected to the second lead line 602 near the edge B of the display area, and a second end extends to the vicinity of the second data line DA2 of the display area 100, and then extends from the display area 100 to the lead area 501 to be connected to the second data line DA2. A first end of the third data fan-out line 703 is connected to the third lead line 603 near the edge B of the display area, and a second end extends to the vicinity of the third data line DA3 of the display area 100, and then extends from the display area 100 to the lead area 501 to be connected to the third data line DA3. The first end of the fourth data fan-out line 704 is connected to the fourth lead line 604 near the edge B of the display area, and the second end extends to the vicinity of the fourth data line DA4 of the display area 100, and then extends from the display area 100 to the lead area 501 to connect to the fourth data line DA4.

[0125] In an exemplary embodiment, the fifth data line DA5 extending to the lead area 501 is directly connected to the fifth lead line 605, the sixth data line DA6 extending to the lead area 501 is directly connected to the sixth lead line 606, the seventh data line DA7 extending to the lead area 501 is directly connected to the seventh lead line 607, and the eighth data line DA8 extending to the lead area 501 is directly connected to the eighth lead line 608.

[0126] Although Fig.12 The exemplary embodiment shown is described by taking the case where the second line segment of the data fan-out line is located on the right side of the corresponding data line as an example, but in the present disclosure, the second line segment of the data fan-out line may be located on the left side of the corresponding data line, or a portion of the second line segment may be located on the right side of the data line and another portion of the second line segment may be located on the left side of the data line, and the present disclosure does not make any limitation thereto.

[0127] Fig.13 for Fig.12 Magnified view of the C2 region. Fig.13 As shown, the third data line DA3, the fourth data line DA4, the fifth data line DA5 and the sixth data line DA6 are respectively extended to the lead area 501 of the binding area along the first direction D1. In the lead area 501, the third data fan-out line 703 first extends to the vicinity of the third data line DA3 of the display area 100, and then extends from the display area 100 to the lead area 501, and is connected to the end of the third data line DA3 through the first via K1. The fourth data fan-out line 704 first extends to the vicinity of the fourth data line DA4 of the display area 100, and then extends from the display area 100 to the lead area 501, and is connected to the end of the fourth data line DA4 through the second via K2. The fifth lead line 605 is connected to the end of the fifth data line DA5 through the third via K3, and the sixth connection signal line 606 is connected to the end of the sixth data line DA6 through the fourth via K4.

[0128] In an exemplary embodiment, the data line and the data fan-out line may be disposed in different film layers with an insulating layer disposed therebetween.

[0129] In an exemplary embodiment, the lead-out line and the data fan-out line may be disposed in the same film layer and formed simultaneously through the same patterning process, and the lead-out line and the data fan-out line may be an integrated structure connected to each other.

[0130] In an exemplary embodiment, the lead-out line and the data fan-out line may be disposed in different film layers, with an insulating layer disposed therebetween, and the two are connected through vias.

[0131] Fig.14 for Fig.13 Sectional view along AA direction. Fig.14 As shown, in a plane perpendicular to the display substrate, the display substrate may include a plurality of conductive layers arranged on a base, the plurality of conductive layers may include a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer arranged in sequence along a direction away from the base, the first conductive layer (not shown in the figure) may include a scanning signal line, gate electrodes of a plurality of transistors, a light-emitting control line and a first plate of a storage capacitor, the second conductive layer (not shown in the figure) may include an initial signal line, a plate connecting line and a second plate of a storage capacitor, the third conductive layer may include: a first power line (not shown in the figure), a data line, source electrodes and drain electrodes of a plurality of transistors (not shown in the figure), and the fourth conductive layer may include: a data fan-out line.

[0132] In an exemplary embodiment, in a plane perpendicular to the display substrate, the display substrate may include a semiconductor layer and a plurality of insulating layers, the semiconductor layer may include an active layer of a plurality of transistors, and the plurality of insulating layers may include a first insulating layer 91, a second insulating layer 92, a third insulating layer 93, a fourth insulating layer 94, and a fifth insulating layer 95 sequentially disposed in a direction away from the substrate. In an exemplary embodiment, the first insulating layer 91 is disposed on the substrate 10, the semiconductor layer is disposed on a side of the first insulating layer 91 away from the substrate, the second insulating layer 92 covers the semiconductor layer, the first conductive layer is disposed on a side of the second insulating layer 92 away from the substrate, the third insulating layer 93 covers the first conductive layer, the second conductive layer is disposed on a side of the third insulating layer 93 away from the substrate, the fourth insulating layer 94 covers the second conductive layer, the third conductive layer is disposed on a side of the fourth insulating layer 94 away from the substrate, the fifth insulating layer 95 covers the third conductive layer, and the fourth conductive layer is disposed on a side of the fifth insulating layer 95 away from the substrate.

[0133] In an exemplary embodiment, the orthographic projection of any lead line on the substrate has no overlapping area with the orthographic projection of other lead lines on the substrate, and the orthographic projection of any data fan-out line on the substrate has no overlapping area with the orthographic projection of other data fan-out lines on the substrate.

[0134] In an exemplary embodiment, the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer and the fifth insulating layer may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be a single layer, a multilayer or a composite layer. The first insulating layer may be referred to as a buffer layer, configured to prevent ionic impurity diffusion, prevent moisture penetration, and perform a surface flattening function, the second insulating layer disposed between the semiconductor layer and the first conductive layer, the third insulating layer disposed between the first conductive layer and the second conductive layer may be referred to as a gate insulating (GI) layer, and the fourth insulating layer disposed between the second conductive layer and the third conductive layer may be referred to as an interlayer insulating (ILD) layer. The first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer may be metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and may be a single layer structure, or a multilayer composite structure, such as Ti / Al / Ti, etc. The semiconductor layer can be made of amorphous indium gallium zinc oxide material (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), sexithiophene or polythiophene and the like, that is, the present disclosure is applicable to transistors manufactured based on oxide technology, silicon technology or organic technology. The active layer based on oxide technology can be made of oxides containing indium and tin, oxides containing tungsten and indium, oxides containing tungsten, indium and zinc, oxides containing titanium and indium, oxides containing titanium, indium and tin, oxides containing indium and zinc, oxides containing silicon, indium and tin, oxides containing indium, gallium and zinc, and the like.

[0135] In an exemplary embodiment, a plurality of openings (K1 to K4 in the figure) may be formed on the fifth insulating layer 95, and the plurality of openings are located at the ends of the data lines, and the fifth insulating layer 95 in the openings is etched away to expose the surfaces of the data lines. The openings are configured so that the subsequently formed data fan-out lines or lead-out lines are connected to the data lines through the openings.

[0136] In an exemplary embodiment, if Fig.13 and Fig.14 As shown, the width M of each lead-out line is the same, the spacing L between adjacent lead-out lines is the same, and the width M and the spacing L are both dimensions in the second direction D2. In an exemplary embodiment, the width of each data fan-out line may be the same.

[0137] In an exemplary embodiment, Fig.15 Schematic diagram of another structure of lead-out lines and data fan-out lines according to an embodiment of the present disclosure. Fig.16 for Fig.15 The enlarged view of the C3 area is shown in Figure 2. Fig.15 and Fig.16 As shown, the display area further includes a first power line VDD and a plate connection line 35, the first power line VDD extends along a first direction D1, and the plate connection line 35 extends along a second direction D2;

[0138] The extended segment 700b includes M1 first sub-segments 700b1 and M1 second sub-segments 700b2, M1 is a natural number greater than or equal to 1, the first sub-segments 700b1 and the second sub-segments 700b2 are alternately connected, the first sub-segment 700b1 located on one side of the extended segment 700b is connected to the first segment 700a, and the second sub-segment 700b2 located on the other side of the extended segment 700b is connected to the connecting segment 700c, the orthographic projections of the first segment 700a and the second sub-segment 700b2 on the display substrate plane both overlap with the orthographic projection of the first power line VDD on the display substrate plane, and the orthographic projection of the first sub-segment 700b1 on the display substrate plane overlaps with the orthographic projection of the electrode connecting line 35 on the display substrate plane.

[0139] In an exemplary embodiment, Fig.17 Schematic diagram of another structure of a lead-out line and a data fan-out line according to an embodiment of the present disclosure. Fig.18 for Fig.17 The enlarged view of the C4 region is shown in Figure 2. Fig.17 and Fig.18 As shown, the display area further includes a first power line VDD and a plate connection line 35, the first power line VDD extends along a first direction D1, and a second angle θ2 is formed between the plate connection line 35 and the first direction D1, and the second angle θ2 is 20° to 70°;

[0140] The extended segment 700b includes M1 first sub-segments 700b1 and M1 second sub-segments 700b2, M1 is a natural number greater than or equal to 1, the first sub-segments 700b1 and the second sub-segments 700b2 are alternately connected, the first sub-segment 700b1 located on one side of the extended segment 700b is connected to the first segment 700a, and the second sub-segment 700b2 located on the other side of the extended segment 700b is connected to the connecting segment 700c, the orthographic projections of the first segment 700a and the second sub-segment 700b2 on the display substrate plane both overlap with the orthographic projection of the first power line VDD on the display substrate plane, and the orthographic projection of the first sub-segment 700b1 on the display substrate plane overlaps with the orthographic projection of the electrode connecting line 35 on the display substrate plane.

[0141] In an exemplary embodiment, the plate connection line 35 is located in the second conductive layer, the first power line VDD is located in the third conductive layer, and the data fan-out line 700 is located in the fourth conductive layer.

[0142] In an exemplary embodiment, Fig.19Schematic diagram of another structure of a lead-out line and a data fan-out line according to an embodiment of the present disclosure. Fig. 20 for Fig.19 The enlarged view of the C5 area is shown in Figure 2. Fig.19 and Fig. 20 As shown, the display area further includes a first power line VDD, an initial signal line 31 and a plate connection line 35, the first power line VDD extends along a first direction D1, and the initial signal line 31 and the plate connection line 35 both extend along a second direction D2;

[0143] The extended segment 700b includes M1 first sub-segments 700b1 and M1 second sub-segments 700b2, M1 is a natural number greater than or equal to 1, the first sub-segments 700b1 and the second sub-segments 700b2 are alternately connected, the first sub-segment 700b1 located on one side of the extended segment 700b is connected to the first segment 700a, and the second sub-segment 700b2 located on the other side of the extended segment 700b is connected to the connecting segment 700c, the orthographic projections of the first segment 700a and the second sub-segment 700b2 on the display substrate plane both overlap with the orthographic projection of the first power line VDD on the display substrate plane, and the orthographic projection of the first sub-segment 700b1 on the display substrate plane overlaps with the orthographic projection of any one of the following: the initial signal line 31 and the electrode connecting line 35 on the display substrate plane.

[0144] In an exemplary embodiment, the display area further includes a first power line VDD, an initial signal line, and a plate connection line 35, the first power line VDD extends along a first direction D1, the initial signal line 31 and the plate connection line 35 both have a second angle with the first direction D1, and the second angle is 20° to 70°;

[0145] The extended segment 700b includes M1 first sub-segments 700b1 and M1 second sub-segments 700b2, M1 is a natural number greater than or equal to 1, the first sub-segments 700b1 and the second sub-segments 700b2 are alternately connected, the first sub-segment 700b1 located on one side of the extended segment 700b is connected to the first segment 700a, and the second sub-segment 700b2 located on the other side of the extended segment 700b is connected to the connecting segment 700c, the orthographic projections of the first segment 700a and the second sub-segment 700b2 on the display substrate plane both overlap with the orthographic projection of the first power line VDD on the display substrate plane, and the orthographic projection of the first sub-segment 700b1 on the display substrate plane overlaps with the orthographic projection of any one of the following: the initial signal line 31 and the electrode connecting line 35 on the display substrate plane.

[0146] In an exemplary embodiment, the initial signal line 31 and the plate connection line 35 are both located in the second conductive layer, the first power line VDD is located in the third conductive layer, and the data fan-out line 700 is located in the fourth conductive layer.

[0147] The following is an exemplary explanation through the preparation process of the display substrate. The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials or transparent conductive materials, and includes processes such as coating organic materials, mask exposure and development for organic materials. Deposition can be any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be any one or more of spraying, spin coating and inkjet printing, and etching can be any one or more of dry etching and wet etching, which are not limited in the present disclosure. "Thin film" refers to a layer of thin film made by deposition, coating or other processes of a certain material on a substrate. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The "A and B are arranged in the same layer" mentioned in the present disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the size of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of the present disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B. "The orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0148] In an exemplary embodiment, a process of preparing a display substrate may include the following operations.

[0149] (11) Forming a semiconductor layer pattern. In an exemplary embodiment, forming a semiconductor layer pattern may include: sequentially depositing a first insulating film and a semiconductor film on a substrate, patterning the semiconductor film through a patterning process to form a first insulating layer covering the substrate, and a semiconductor layer disposed on the first insulating layer, such as Fig.21a and Figure 21b As shown, Figure 21b for Fig.21a Sectional view along AA direction.

[0150] In an exemplary embodiment, the semiconductor layer of each sub-pixel may include a first active layer 11 of the first transistor T1 to a seventh active layer 17 of the seventh transistor T7 , and the first active layer 11 to the seventh active layer 17 are an integral structure connected to each other.

[0151] In an exemplary embodiment, the first region R1 may include at least part of the first active layer 11 of the first transistor T1, the second active layer 12 of the second transistor T2, the fourth active layer 14 of the fourth transistor T4, and the seventh active layer 17 of the seventh transistor T7, the second region R2 may include at least part of the third active layer 13 of the third transistor T3, and the third region R3 may include at least part of the fifth active layer 15 of the fifth transistor T5 and the sixth active layer 16 of the sixth transistor T6. The first active layer 11 and the seventh active layer 17 are disposed on a side of the first region R1 away from the second region R2, and the second active layer 12 and the fourth active layer 14 are disposed on a side of the first region R1 adjacent to the second region R2.

[0152] In an exemplary embodiment, the first active layer 11 may be shaped like an "n", the second active layer 12 may be shaped like a "7", the third active layer 13 may be shaped like a "J", the fourth active layer 14 may be shaped like a "1", and the fifth active layer 15, the sixth active layer 16 and the seventh active layer 17 may be shaped like an "L".

[0153] In an exemplary embodiment, the active layer of each transistor may include a first region, a second region, and a channel region between the first region and the second region. In an exemplary embodiment, the first region 11-1 of the first active layer 11 is simultaneously used as the first region 17-1 of the seventh active layer 17, the second region 11-2 of the first active layer 11 is simultaneously used as the first region 12-1 of the second active layer 12, the first region 13-1 of the third active layer 13 is simultaneously used as the second region 14-2 of the fourth active layer 14 and the second region 15-2 of the fifth active layer 15, the second region 13-2 of the third active layer 13 is simultaneously used as the second region 12-2 of the second active layer 12 and the first region 16-1 of the sixth active layer 16, and the second region 16-2 of the sixth active layer 16 is simultaneously used as the second region 17-2 of the seventh active layer 17. In an exemplary embodiment, the first region 14-1 of the fourth active layer 14 and the first region 15-1 of the fifth active layer 15 are separately provided.

[0154] In an exemplary embodiment, the third active layer 13 of the third transistor includes a first region 13-1, a second region 13-2, and a channel region, the channel region of the third active layer 13 is disposed between the first region 13-1 and the second region 13-2, and both ends of the channel region are connected to the first region 13-1 and the second region 13-2, respectively. The first region 13-1 of the third active layer 13 simultaneously serves as the second region 14-2 of the fourth active layer 14 and the second region 15-2 of the fifth active layer 15, that is, the first region 13-1 of the third active layer 13, the second region 14-2 of the fourth active layer 14, and the second region 15-2 of the fifth active layer 15 are connected to each other. The second region 13-2 of the third active layer 13 simultaneously serves as the second region 12-2 of the second active layer 12 and the first region 16-1 of the sixth active layer 16, that is, the second region 13-2 of the third active layer 13, the second region 12-2 of the second active layer 12, and the first region 16-1 of the sixth active layer 16 are connected to each other.

[0155] like Figure 21b As shown, after this process, the display substrate includes a first insulating layer 91 disposed on the base 10 and a semiconductor layer disposed on the first insulating layer 91 , and the semiconductor layer may include a first active layer 11 and a third active layer 13 .

[0156] (12) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: depositing a second insulating film and a first metal film in sequence on a substrate having the aforementioned pattern, patterning the first metal film through a patterning process to form a second insulating layer covering the semiconductor layer pattern, and a first conductive layer pattern disposed on the second insulating layer, wherein the first conductive layer pattern includes at least: a first scanning signal line 21, a second scanning signal line 22, a light emitting control line 23, and a first electrode plate 24 of a storage capacitor, such as Fig.22a and Figure 22b As shown, Figure 22b for Fig.22a In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE 1) layer.

[0157] In an exemplary embodiment, the first scan signal line 21, the second scan signal line 22 and the light emitting control line 23 extend along the second direction D2. The first scan signal line 21 and the second scan signal line 22 are arranged in the first region R1, the second scan signal line 22 is located on a side of the first scan signal line 21 away from the second region R2, the light emitting control line 23 is arranged in the third region R3, and the first electrode plate 24 of the storage capacitor is arranged in the second region R2, and is located between the first scan signal line 21 and the light emitting control line 23.

[0158] In an exemplary embodiment, the first electrode plate 24 may be rectangular, and the corners of the rectangle may be chamfered, and the orthographic projection of the first electrode plate 24 on the substrate overlaps with the orthographic projection of the third active layer of the third transistor T3 on the substrate. In an exemplary embodiment, the first electrode plate 24 also serves as the gate electrode of the third transistor T3.

[0159] In an exemplary embodiment, the area where the first scan signal line 21 overlaps with the fourth active layer of the fourth transistor T4 serves as the gate electrode of the fourth transistor T4. The first scan signal line 21 is provided with a gate block 21-1 protruding toward the side of the second scan signal line 22, and the positive projection of the gate block 21-1 on the substrate overlaps with the positive projection of the second active layer of the second transistor T2 on the substrate, and the area where the first scan signal line 21 and the gate block 21-1 overlap with the second active layer of the second transistor T2 serves as the gate electrode of the double-gate structure of the second transistor T2. The area where the second scan signal line 22 overlaps with the first active layer of the first transistor T1 serves as the gate electrode of the double-gate structure of the first transistor T1, the area where the second scan signal line 22 overlaps with the seventh active layer of the seventh transistor T7 serves as the gate electrode of the seventh transistor T7, the area where the light emitting control line 23 overlaps with the fifth active layer of the fifth transistor T5 serves as the gate electrode of the fifth transistor T5, and the area where the light emitting control line 23 overlaps with the sixth active layer of the sixth transistor T6 serves as the gate electrode of the sixth transistor T6.

[0160] In an exemplary embodiment, after forming the first conductive layer pattern, the first conductive layer can be used as a shield to perform conductorization on the semiconductor layer. The semiconductor layer in the area shielded by the first conductive layer forms the channel region of the first transistor T1 to the seventh transistor T7, and the semiconductor layer in the area not shielded by the first conductive layer is conductorized, that is, the first area and the second area of ​​the first active layer to the seventh active layer are both conductorized.

[0161] like Figure 22b As shown, after this process, the display substrate includes a first insulating layer 91 arranged on the base 10, a semiconductor layer arranged on the first insulating layer 91, a second insulating layer 92 covering the semiconductor layer, and a first conductive layer arranged on the second insulating layer 92, the semiconductor layer may include a first active layer 11 and a third active layer 13, the first conductive layer may include a first scanning signal line 21, a second scanning signal line 22, a light emitting control line 23 and a first electrode 24 of the storage capacitor.

[0162] (13) Forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: depositing a third insulating film and a second metal film in sequence on the substrate on which the aforementioned pattern is formed, patterning the second metal film using a patterning process to form a third insulating layer 93 covering the first conductive layer, and a second conductive layer pattern disposed on the third insulating layer 93, wherein the second conductive layer pattern includes at least: an initial signal line 31, a second plate 32 of a storage capacitor, a shielding electrode 33, and a plate connecting line 35, such as Fig.23a and Figure 23b As stated, Figure 23b for Fig.23a In an exemplary embodiment, the second conductive layer may be referred to as a second gate metal (GATE 2) layer.

[0163] like Fig.23a As shown, in an exemplary embodiment, the initial signal line 31 extends along the second direction D2, is arranged in the first region R1, and is located on the side of the second scanning signal line 22 away from the second region R2. The second electrode 32 of the storage capacitor is arranged in the second region R2, and is located between the first scanning signal line 21 and the light emitting control line 23. The shielding electrode 33 is arranged in the first region R1, and the shielding electrode 33 is configured to shield the influence of the data voltage jump on the key node, so as to prevent the data voltage jump from affecting the potential of the key node of the pixel driving circuit, and improve the display effect.

[0164] In an exemplary embodiment, the initial signal line 31 may be set to have unequal widths, and the width of the initial signal line 31 is the size of the initial signal line 31 in the first direction D1. The initial signal line 31 includes an area overlapping with the semiconductor layer and an area not overlapping with the semiconductor layer, and the width of the initial signal line 31 in the area not overlapping with the semiconductor layer may be smaller than the width of the initial signal line 31 in the area overlapping with the semiconductor layer.

[0165] In an exemplary embodiment, the outline of the second electrode plate 32 may be rectangular, and the corners of the rectangle may be chamfered, and the orthographic projection of the second electrode plate 32 on the substrate and the orthographic projection of the first electrode plate 24 on the substrate have an overlapping area. An opening 34 is provided on the second electrode plate 32, and the opening 34 may be located in the middle of the second region R2. The opening 34 may be rectangular, so that the second electrode plate 32 forms an annular structure. The opening 34 exposes the third insulating layer 93 covering the first electrode plate 24, and the orthographic projection of the first electrode plate 24 on the substrate includes the orthographic projection of the opening 34 on the substrate. In an exemplary embodiment, the opening 34 is configured to accommodate a first via hole formed subsequently, and the first via hole is located in the opening 34 and exposes the first electrode plate 24, so that the second pole of the first transistor T1 formed subsequently is connected to the first electrode plate 24.

[0166] In an exemplary embodiment, the plate connection line 35 is disposed between the second plates 32 of adjacent sub-pixels in the second direction D2, the first end of the plate connection line 35 is connected to the second plate 32 of the sub-pixel, the second end of the plate connection line 35 extends along the second direction D2 or the opposite direction of the second direction D2, and is connected to the second plate 32 of the adjacent sub-pixel, that is, the plate connection line 35 is configured to interconnect the second plates of adjacent sub-pixels in the second direction D2. In an exemplary embodiment, the second plates in a sub-pixel row are formed into an integrated structure that is interconnected through the plate connection line 35, and the second plates of the integrated structure can be reused as a power signal line to ensure that multiple second plates in a sub-pixel row have the same potential, which is conducive to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.

[0167] In an exemplary embodiment, the orthographic projection of the edge of the second electrode plate 32 adjacent to the first region R1 on the substrate overlaps with the orthographic projection of the boundary line between the first region R1 and the second region R2 on the substrate, and the orthographic projection of the edge of the second electrode plate 32 adjacent to the third region R3 on the substrate overlaps with the orthographic projection of the boundary line between the second region R2 and the third region R3 on the substrate, that is, the length of the second electrode plate 32 is equal to the length of the second region R2, and the length of the second electrode plate 32 refers to the dimension of the second electrode plate 32 in the second direction D2.

[0168] like Figure 23b As shown, in a plane perpendicular to the substrate, a first insulating layer 91 is arranged on the substrate 10, a semiconductor layer is arranged on the first insulating layer 91, a second insulating layer 92 covers the semiconductor layer, a first conductive layer is arranged on the second insulating layer 92, a third insulating layer 93 covers the first conductive layer, and the second conductive layer is arranged on the third insulating layer 93, the second conductive layer includes at least an initial signal line 31 and a second electrode plate 32 of a storage capacitor, an opening 34 is arranged on the second electrode plate 32 of the storage capacitor, the opening 34 exposes the third insulating layer 93 covering the first electrode plate 24, and an orthographic projection of the second electrode plate 32 on the substrate and an orthographic projection of the first electrode plate 24 on the substrate have an overlapping area.

[0169] (14) Forming a fourth insulating layer pattern. In an exemplary embodiment, forming the fourth insulating layer pattern may include: depositing a fourth insulating film on the substrate on which the aforementioned pattern is formed, patterning the fourth insulating film using a patterning process to form a fourth insulating layer covering the second conductive layer, wherein a plurality of via holes are disposed on the fourth insulating layer, and the plurality of via holes include at least a first via hole V1, a second via hole V2, a third via hole V3, a fourth via hole V4, a fifth via hole V5, a sixth via hole V6, a seventh via hole V7, an eighth via hole V8, and a ninth via hole V9, such as Fig.24a and Figure 24b As shown, Figure 24b for Fig.24a Sectional view along AA direction.

[0170] like Fig.24a As shown, in an exemplary embodiment, the first via hole V1 is located in the opening 34 of the second electrode plate 32, the orthographic projection of the first via hole V1 on the substrate is located within the range of the orthographic projection of the opening 34 on the substrate, and the fourth insulating layer and the third insulating layer in the first via hole V1 are etched away to expose the surface of the first electrode plate 24. The first via hole V1 is configured to connect the second electrode of the first transistor T1 formed subsequently to the first electrode plate 24 through the via hole.

[0171] In an exemplary embodiment, the second via hole V2 is located in the area where the second electrode plate 32 is located, and the orthographic projection of the second via hole V2 on the substrate is located within the range of the orthographic projection of the second electrode plate 32 on the substrate, and the fourth insulating layer in the second via hole V2 is etched away to expose the surface of the second electrode plate 32. The second via hole V2 is configured to connect the first power line formed subsequently to the second electrode plate 32 through the via hole. In an exemplary embodiment, the second via hole V2 as a power via hole may include a plurality of second via holes V2, and the plurality of second via holes V2 may be arranged in sequence along the first direction D1 to increase the connection reliability between the first power line and the second electrode plate 32.

[0172] In an exemplary embodiment, the third via hole V3 is located in the third region R3, and the fourth insulating layer, the third insulating layer, and the second insulating layer in the third via hole V3 are etched away to expose the surface of the first region of the fifth active layer. The third via hole V3 is configured to connect a subsequently formed first power line to the fifth active layer through the via hole.

[0173] In an exemplary embodiment, the fourth via hole V4 is located in the third region R3, and the fourth insulating layer, the third insulating layer, and the second insulating layer in the fourth via hole V4 are etched away to expose the surface of the second region of the sixth active layer (also the second region of the seventh active layer). The fourth via hole V4 is configured to connect the second electrode of the subsequently formed sixth transistor T6 to the sixth active layer through the via hole, and to connect the second electrode of the subsequently formed seventh transistor T7 to the seventh active layer through the via hole.

[0174] In an exemplary embodiment, the fifth via hole V5 is located in the first region R1, and the fourth insulating layer, the third insulating layer, and the second insulating layer in the fifth via hole V5 are etched away to expose the surface of the first region of the fourth active layer. The fifth via hole V5 is configured to connect a subsequently formed data line to the fourth active layer through the via hole, and the fifth via hole V5 is called a data writing hole.

[0175] In an exemplary embodiment, the sixth via hole V6 is located in the first region R1, and the fourth insulating layer, the third insulating layer, and the second insulating layer in the sixth via hole V6 are etched away to expose the surface of the second region of the first active layer (also the first region of the second active layer). The sixth via hole V6 is configured to connect the second electrode of the first transistor T1 formed subsequently to the first active layer through the via hole, and to connect the first electrode of the second transistor T2 formed subsequently to the second active layer through the via hole.

[0176] In an exemplary embodiment, the seventh via hole V7 is located in the first region R1, and the fourth insulating layer, the third insulating layer, and the second insulating layer in the seventh via hole V7 are etched away to expose the surface of the first region of the seventh active layer (also the first region of the first active layer). The seventh via hole V7 is configured to connect the first electrode of the subsequently formed seventh transistor T7 to the seventh active layer through the via hole, and to connect the first electrode of the subsequently formed first transistor T1 to the first active layer through the via hole.

[0177] In an exemplary embodiment, the eighth via hole V8 is located in the first region R1, and the fourth insulating layer in the eighth via hole V8 is etched away to expose the surface of the shielding electrode 33. The eighth via hole V8 is configured to connect a subsequently formed first power line to the shielding electrode 33 through the via hole.

[0178] In an exemplary embodiment, the ninth via hole V9 is located in the first region R1, and the fourth insulating layer in the ninth via hole V9 is etched away to expose the surface of the initial signal line 31. The ninth via hole V9 is configured to connect the first electrode of the subsequently formed seventh transistor T7 (also the first electrode of the first transistor T1) to the initial signal line 31 through the via hole.

[0179] like Figure 24b As shown, in a plane perpendicular to the substrate, the first insulating layer 91 is disposed on the substrate 10, the semiconductor layer is disposed on the first insulating layer 91, the second insulating layer 92 covers the semiconductor layer, the first conductive layer is disposed on the second insulating layer 92, the third insulating layer 93 covers the first conductive layer, the second conductive layer is disposed on the third insulating layer 93, the fourth insulating layer 94 covers the second conductive layer, and a plurality of vias are disposed on the fourth insulating layer 94, the plurality of vias at least include a first via V1 and a sixth via V6. The fourth insulating layer 94 and the third insulating layer 93 in the first via V1 are etched away to expose the surface of the second electrode plate 32. The fourth insulating layer 94, the third insulating layer 93, and the second insulating layer 92 in the sixth via V6 are etched away to expose the surface of the first active layer 11.

[0180] (15) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer may include: depositing a third metal film on the substrate on which the aforementioned pattern is formed, patterning the third metal film using a patterning process, and forming a third conductive layer disposed on the fourth insulating layer, wherein the third conductive layer at least includes: a first power line 41, a data line 42, a first connection electrode 43, a second connection electrode 44, and a third connection electrode 45, such as Fig.25a and Fig.25b As shown, Fig.25b for Fig.25a In an exemplary embodiment, the third conductive layer may be referred to as a first source-drain metal (SD1) layer.

[0181] like Fig.25a As shown, in the exemplary embodiment, the first power line 41 extends along the first direction D1, and the first power line 41 is connected to the second electrode plate 32 through the second via hole V2 on the one hand, and is connected to the shielding electrode 33 through the eighth via hole V8 on the other hand, and is connected to the fifth active layer through the third via hole V3 on the other hand, so that the shielding electrode 33 and the second electrode plate 32 have the same potential as the first power line 41. Since the orthographic projection of the shielding electrode 33 on the substrate and the orthographic projection of the subsequently formed data line on the substrate have an overlapping area, and the shielding electrode 33 is connected to the first power line 41, the influence of the data voltage jump on the key nodes is effectively shielded, and the data voltage jump is prevented from affecting the potential of the key nodes of the pixel driving circuit, thereby improving the display effect.

[0182] In an exemplary embodiment, the data line 42 extends along the first direction D1 and is connected to the first region of the fourth active layer through the fifth via hole V5 so that the data signal transmitted by the data line 42 is written into the fourth transistor T4 .

[0183] In an exemplary embodiment, the first connection electrode 43 extends along the first direction D1, and its first end is connected to the second region of the first active layer (also the first region of the second active layer) through the sixth via hole V6, and its second end is connected to the first electrode plate 24 through the first via hole V1, so that the first electrode plate 24, the second electrode of the first transistor T1, and the first electrode of the second transistor T2 have the same potential. In an exemplary embodiment, the first connection electrode 43 can serve as the second electrode of the first transistor T1 and the first electrode of the second transistor T2.

[0184] In an exemplary embodiment, the second connection electrode 44 extends along the first direction D1, a first end thereof is connected to the initial signal line 31 through a ninth via hole V9, and a second end thereof is connected to the first region of the seventh active layer (also the first region of the first active layer) through a seventh via hole V7, so that the first electrode of the seventh transistor T7 and the first electrode of the first transistor T1 have the same potential as the initial signal line 31. In an exemplary embodiment, the second connection electrode 44 can serve as the first electrode of the seventh transistor T7 and the first electrode of the first transistor T1.

[0185] In an exemplary embodiment, the third connection electrode 45 is connected to the second region of the sixth active layer (also the second region of the seventh active layer) through the fourth via hole V4, so that the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7 have the same potential. In an exemplary embodiment, the third connection electrode 45 can serve as the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7. In an exemplary embodiment, the third connection electrode 45 is configured to be connected to an anode formed subsequently.

[0186] In an exemplary embodiment, the first power line 41 and the data line 42 may be straight lines of equal width, or straight lines of unequal width.

[0187] like Fig.25b As shown, in a plane perpendicular to the substrate, a first insulating layer 91 is arranged on the substrate 10, a semiconductor layer is arranged on the first insulating layer 91, a second insulating layer 92 covers the semiconductor layer, a first conductive layer is arranged on the second insulating layer 92, a third insulating layer 93 covers the first conductive layer, the second conductive layer is arranged on the third insulating layer 93, a fourth insulating layer 94 covers the second conductive layer, and the third conductive layer is arranged on the fourth insulating layer 94, the third conductive layer includes at least a first connecting electrode 43 and a third connecting electrode 45, and the first connecting electrode 43 is connected to the first electrode plate 24 and the first active layer 11 of the first transistor T1 through a first via hole V1 and a sixth via hole V6, respectively.

[0188] (16) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer pattern may include: depositing a fifth insulating film and a fourth metal film in sequence on the substrate on which the aforementioned pattern is formed, patterning the fourth metal film using a patterning process to form a fifth insulating layer 95 covering the third conductive layer, and a fourth conductive layer pattern disposed on the fifth insulating layer 95, wherein the fourth conductive layer pattern includes at least: a data fan-out line 700 and a fourth connection electrode 52, such as Fig.26a and Fig.16 b, Figure 26b for Fig.26a In an exemplary embodiment, the fourth conductive layer may be referred to as a second source-drain metal (SD2) layer.

[0189] In an exemplary embodiment, a tenth via hole (not shown) is disposed on the fifth insulating layer 95 , the tenth via hole exposes the surface of the third connection electrode 45 , and the fourth connection electrode 52 is connected to the third connection electrode 45 through the tenth via hole.

[0190] In an exemplary embodiment, the orthographic projection of the data fan-out line 700 on the substrate is located at any one or more of the following: the first power line 41 , the plate connection line 35 , and the initial signal line 31 , within the range of the orthographic projection on the substrate.

[0191] In the disclosed embodiment, by making the data fan-out line 700 overlap with some fixed potential signal lines (the first power line 41, the plate connection line 35 and the initial signal line 31, etc.), it is possible to avoid the potential change on the data fan-out line 700 causing the potential jump of other signal lines in the pixel circuit when the data signal is written, thereby improving the display quality.

[0192] In an exemplary embodiment, if Fig.26a As shown, the orthographic projection of the data fan-out line 700 on the substrate is located within the range of the orthographic projection of the first power line 41 and / or the plate connection line 35 on the substrate.

[0193] Since the plate connection line 35 is connected to the first power line 41, the voltage in the first power line 41 is a constant positive voltage, and the range of the data voltage is usually also a positive voltage. Therefore, the potential difference between the data fan-out line 700 and the first power line 41 (or the plate connection line 35) is small, and when the data signal is written, the load is relatively small, thereby further reducing the signal crosstalk of the data fan-out line to other signal lines.

[0194] (17) Forming a planar layer pattern. In an exemplary embodiment, forming the planar layer pattern may include: coating a planar film on the substrate formed with the aforementioned pattern, patterning the planar film using a patterning process to form a planar layer covering the third conductive layer, wherein the planar layer is provided with an eleventh via hole V11, such as Fig.27a and Figure 27b As shown, Figure 27b for Fig.27a Sectional view along AA direction.

[0195] like Fig.27a As shown, the tenth via hole V10 is located in the area where the fourth connection electrode 52 is located, the flat layer in the eleventh via hole V11 is removed to expose the surface of the fourth connection electrode 52, and the eleventh via hole V11 is configured to connect the subsequently formed anode to the fourth connection electrode 52 through the via hole.

[0196] like Figure 27bAs shown, in a plane perpendicular to the substrate, a first insulating layer 91 is arranged on the substrate 10, a semiconductor layer is arranged on the first insulating layer 91, a second insulating layer 92 covers the semiconductor layer, a first conductive layer is arranged on the second insulating layer 92, a third insulating layer 93 covers the first conductive layer, the second conductive layer is arranged on the third insulating layer 93, a fourth insulating layer 94 covers the second conductive layer, the third conductive layer is arranged on the fourth insulating layer 94, a fifth insulating layer 95 covers the third conductive layer, the fourth conductive layer is arranged on the fifth insulating layer 95, a flat layer 96 covers the fourth conductive layer, an eleventh via hole V11 is arranged on the flat layer, and the flat layer 95 in the eleventh via hole V11 is removed to expose the surface of the fourth connecting electrode 52.

[0197] (18) Forming an anode pattern. In an exemplary embodiment, forming the anode pattern may include: depositing a transparent conductive film on the substrate on which the aforementioned pattern is formed, patterning the transparent conductive film using a patterning process, and forming an anode 71 disposed on the flat layer, such as Fig.28a and Fig.28b As shown, Fig.28b for Fig.28a The cross-sectional view along the AA direction is shown.

[0198] like Fig.28a As shown, the anode 71 may be hexagonal, and the anode 71 is connected to the fourth connection electrode 52 through the eleventh via hole V11. Since the fourth connection electrode 52 is connected to the third connection electrode 45 through the tenth via hole, the third connection electrode 45 serves as the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, and thus the anode 71 is connected to the sixth transistor T6 and the seventh transistor T7, so that the pixel driving circuit can drive the light-emitting device to emit light.

[0199] like Fig.28b As shown, in a plane perpendicular to the substrate, a first insulating layer 91 is arranged on the substrate 10, a semiconductor layer is arranged on the first insulating layer 91, a second insulating layer 92 covers the semiconductor layer, a first conductive layer is arranged on the second insulating layer 92, a third insulating layer 93 covers the first conductive layer, the second conductive layer is arranged on the third insulating layer 93, a fourth insulating layer 94 covers the second conductive layer, the third conductive layer is arranged on the fourth insulating layer 94, a fifth insulating layer 95 covers the third conductive layer, the fourth conductive layer is arranged on the fifth insulating layer 95, a flat layer 96 covers the fourth conductive layer, an anode 71 is arranged on the flat layer 96, and the anode 71 is connected to the fourth connecting electrode 52 through an eleventh via hole.

[0200] In an exemplary embodiment, the subsequent preparation process may include: coating a pixel definition film, patterning the pixel definition film through a patterning process to form a pixel definition layer, wherein the pixel definition layer of each sub-pixel is provided with a pixel opening, and the pixel opening exposes the anode. An organic light-emitting layer is formed by an evaporation or inkjet printing process, and a cathode is formed on the organic light-emitting layer. An encapsulation layer is formed, and the encapsulation layer may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The first encapsulation layer and the third encapsulation layer may be made of inorganic materials, and the second encapsulation layer may be made of organic materials. The second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to ensure that external water vapor cannot enter the light-emitting structure layer.

[0201] In an exemplary embodiment, the substrate may be a flexible substrate or a rigid substrate. The rigid substrate may be, but is not limited to, one or more of glass and quartz, and the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber. In an exemplary embodiment, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked, and the materials of the first flexible material layer and the second flexible material layer may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, and the materials of the first inorganic material layer and the second inorganic material layer may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the water and oxygen resistance of the substrate, and the material of the semiconductor layer may be amorphous silicon (a-si).

[0202] In an exemplary embodiment, the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and can be a single layer structure, or a multi-layer composite structure, such as Mo / Cu / Mo, etc. The first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer and the fifth insulating layer can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and can be a single layer, a multi-layer or a composite layer. The first insulating layer is called a buffer layer, which is used to improve the water and oxygen resistance of the substrate. The second insulating layer and the third insulating layer are called gate insulating (GI) layers, and the fourth insulating layer is called an interlayer insulating (ILD) layer. The flat layer can be made of organic materials, and the transparent conductive film can be made of indium tin oxide ITO or indium zinc oxide IZO. The active layer may be made of polycrystalline silicon (p-Si), that is, the present disclosure is applicable to LTPS thin film transistors.

[0203] Although Fig.28b The exemplary embodiment shown is described by taking the example that the data line is set in the third conductive layer and the data fan-out line is set in the fourth conductive layer, but in the present disclosure, the data fan-out line and the data line can be set in any layer, as long as the data line and the data fan-out line are in different conductive layers, and the present disclosure does not make any limitation here.

[0204] The structure of the display substrate and its preparation process shown in the present disclosure are merely exemplary. In an exemplary embodiment, the corresponding structure can be changed and the composition process can be increased or decreased according to actual needs, and the present disclosure does not limit this.

[0205] In a display substrate, a fan-out area is provided in a binding area, and data lines in a display area are led out through data fan-out lines in the fan-out area. Since there are many oblique lines in the fan-shaped area, the lower frame is wide, which is not conducive to realizing a narrow frame. In an exemplary embodiment of the present disclosure, a lead-out line is provided in the lead area of ​​the binding area, and a data fan-out line is provided in the display area. The lead-out line is connected to the corresponding data line through the data fan-out line, which not only realizes the corresponding connection between multiple lead-out lines and multiple data lines, but also makes it unnecessary to provide fan-shaped oblique lines in the lead area. Multiple lead-out lines are mutually parallel vertical lines, which can be directly introduced into the composite circuit area of ​​the binding area, effectively reducing the length of the lead area in the vertical direction, greatly reducing the width of the lower frame, so that the widths of the upper frame, lower frame, left frame and right frame of the display device are similar, all of which are less than 1.0 mm, thereby improving the screen-to-body ratio and facilitating the realization of full-screen display.

[0206] In addition, in the embodiment of the present disclosure, by making the data fan-out line 700 overlap with some fixed potential signal lines (the first power line 41, the plate connection line 35 and the initial signal line 31, etc.), it is possible to avoid the potential change on the data fan-out line 700 causing the potential jump of other signal lines in the pixel circuit when the data signal is written, thereby further improving the display quality.

[0207] Fig.29 FIG. 2 is a schematic diagram of another display substrate according to an exemplary embodiment of the present disclosure. Fig.29 As shown, the display area 100 includes a plurality of plate connection lines 35 and initial signal lines 31 , and the plurality of plate connection lines 35 and initial signal lines 31 have a second angle θ2 with the first direction D1 , and the second angle θ2 may be approximately greater than 0° and less than 90°.

[0208] In an exemplary embodiment, the second angle θ2 may be approximately 20° to 70°.

[0209] In this embodiment, by arranging the plate connection line 35 and the initial signal line 31 in an inclined manner, the length of the data fan-out line located above the plate connection line 35 and the initial signal line 31 can be reduced. Fig.29 As shown, since the electrode connection line 35 and the initial signal line 31 are arranged in the same layer as the second gate metal layer, the inclined arrangement of the electrode connection line 35 and the initial signal line 31 does not affect the arrangement of other film layer signal lines (such as scanning signal lines, light-emitting control lines, reset signal lines, first power lines, data lines, etc.).

[0210] The exemplary embodiments of the present disclosure can achieve the technical effects of the aforementioned embodiments, including effectively reducing the width of the lower frame, and effectively improving display uniformity and display quality. In addition, the present disclosure effectively reduces the length of the data fan-out line located above the plate connection line 35 and the initial signal line 31 by tilting the plate connection line 35 and the initial signal line 31, which is conducive to reducing the difficulty of wiring design.

[0211] In this exemplary embodiment, the film layer structures of the data lines, data fan-out lines and lead-out lines may be similar to those of the aforementioned exemplary embodiments, and will not be described in detail here.

[0212] The exemplary embodiment of the present disclosure also provides a method for preparing a display substrate. In an exemplary embodiment, the display substrate includes a display area and a binding area located on one side of the display area, and the binding area includes at least a lead area; the preparation method may include:

[0213] A plurality of data lines and a plurality of data fan-out lines are formed in the display area, and a plurality of lead-out lines are formed in the lead area; at least one lead-out line is connected to the data line through the data fan-out line; in a plane perpendicular to the display substrate, the display substrate comprises a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer, and insulating layers are arranged between the first conductive layer and the second conductive layer, between the second conductive layer and the third conductive layer, and between the third conductive layer and the fourth conductive layer; the data lines and the data fan-out lines are arranged in different conductive layers.

[0214] The exemplary embodiments of the present disclosure further provide a display device, including the display substrate of the aforementioned embodiment. The display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, an advertising panel, a watch phone, an e-book portable multimedia player, or a display screen of various Internet of Things products. In an exemplary embodiment, the display device may be a wearable display device that can be worn on a human body in some way, such as a smart watch, a smart bracelet, etc.

[0215] The drawings in this disclosure only relate to the structures involved in this disclosure, and other structures can refer to the general design. In the absence of conflict, the embodiments of this disclosure, that is, the features in the embodiments, can be combined with each other to obtain new embodiments.

[0216] Those skilled in the art should understand that the technical solutions of the present disclosure may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present disclosure, and all should be included in the scope of the claims of the present disclosure.

Claims

1. A display substrate, comprising a display area and a binding area located at one side of the display area, the binding area at least comprising a lead area; the display area comprises a plurality of data lines and a plurality of data fan-out lines, the lead area comprises a plurality of lead lines, the lead lines are arranged in parallel with the data lines; at least one lead line is connected to the data line through the data fan-out line; the display area comprises a pixel circuit, the pixel circuit comprises a storage capacitor; the display area further comprises a plate connection line; In a plane perpendicular to the display substrate, the display substrate comprises a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer, an insulating layer is arranged between the first conductive layer and the second conductive layer, between the second conductive layer and the third conductive layer, and between the third conductive layer and the fourth conductive layer; the data line and the data fan-out line are arranged in different conductive layers; wherein, The first conductive layer includes a first plate of the storage capacitor, the second conductive layer includes a second plate of the storage capacitor and a plate connecting line, each of the plate connecting lines being configured to connect the second plates in a row of sub-pixels to form an integrated structure; At least one of the data fan-out lines includes a first sub-line segment, and an orthographic projection of the first sub-line segment on the display substrate plane overlaps with an orthographic projection of the electrode plate connection line on the display substrate plane.

2. The display substrate according to claim 1, wherein: At least one of the data fan-out lines includes a first line segment and a second line segment; the first end of the first line segment is connected to the lead line, the second end of the first line segment extends in a direction away from the lead area and is then connected to the first end of the second line segment; the second end of the second line segment extends in a direction close to the lead area and is then connected to the data line through a via.

3. The display substrate according to claim 2, wherein: The first line segment is parallel to a first direction, and a first angle is formed between the second line segment and the first direction, and the first angle is in a range of 20° to 70°.

4. The display substrate according to claim 2, wherein: The second line segment includes an extension segment and a connection segment; the first end of the extension segment is located in the display area and is connected to the second end of the first line segment; the second end of the extension segment extends to the edge of the display area in the direction close to the lead area and is connected to the first end of the connection segment; the second end of the connection segment extends in the direction away from the display area and is connected to the data line extending to the lead area through a via; the edge of the display area is the edge of the display area close to the lead area.

5. The display substrate according to claim 4, wherein: The display area further includes a first power line, the first power line extends along a first direction, and the plate connection line extends along a second direction; the second direction intersects the first direction; The extended segment includes M1 first sub-line segments and M1 second sub-line segments, M1 is a natural number greater than or equal to 1, the first sub-line segments and the second sub-line segments are alternately connected, the first sub-line segment located on one side of the extended segment is connected to the first line segment, and the second sub-line segment located on the other side of the extended segment is connected to the connecting segment, and the orthographic projections of the first line segment and the second sub-line segment on the display substrate plane overlap with the orthographic projection of the first power line on the display substrate plane.

6. The display substrate according to claim 4, wherein: The display area further includes a first power line, the first power line extends along a first direction, a second angle is formed between the electrode connecting line and the first direction, and the second angle is 20° to 70°; The extended segment includes M1 first sub-line segments and M1 second sub-line segments, M1 is a natural number greater than or equal to 1, the first sub-line segments and the second sub-line segments are alternately connected, the first sub-line segment located on one side of the extended segment is connected to the first line segment, and the second sub-line segment located on the other side of the extended segment is connected to the connecting segment, and the orthographic projections of the first line segment and the second sub-line segment on the display substrate plane overlap with the orthographic projection of the first power line on the display substrate plane.

7. The display substrate according to claim 5 or 6, wherein: The first power line is located in the third conductive layer, and the data fan-out line is located in the fourth conductive layer.

8. The display substrate according to claim 1, wherein: The widths of the plurality of lead wires in the lead wire area along the second direction are the same, and the intervals between adjacent lead wires along the second direction are the same.

9. The display substrate according to claim 8, wherein: The plurality of lead wires of the lead wire area include a first lead wire group and a second lead wire group, and the lead wires of the first lead wire group and the lead wires of the second lead wire group are alternately arranged along a second direction; The plurality of lead wires in the first lead wire group are connected to the data lines via the plurality of data fan-out lines, and the plurality of lead wires in the second lead wire group are directly connected to the data lines.

10. A display device comprising the display substrate according to any one of claims 1 to 9.

11. A method for preparing a display substrate, the display substrate comprising a display area and a binding area located on one side of the display area, the binding area at least comprising a lead area; the preparation method comprising: A pixel circuit, a plurality of data lines, a plurality of data fan-out lines, and a plate connection line are formed in the display area, and a plurality of lead-out lines are formed in the lead area, wherein the lead-out lines are arranged in parallel with the data lines; at least one lead-out line is connected to the data line through the data fan-out line, and at least one of the data fan-out lines includes a first sub-line segment, and the orthographic projection of the first sub-line segment on the plane of the display substrate overlaps with the orthographic projection of the plate connection line on the plane of the display substrate; in a plane perpendicular to the display substrate, the display substrate includes a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer, and an insulating layer is arranged between the first conductive layer and the second conductive layer, between the second conductive layer and the third conductive layer, and between the third conductive layer and the fourth conductive layer; the data line and the data fan-out line are arranged in different conductive layers, the pixel circuit includes a storage capacitor, the first conductive layer includes a first plate of the storage capacitor, the second conductive layer includes a second plate of the storage capacitor and a plate connection line, and each of the plate connection lines is configured to connect the second plates in a row of sub-pixels to each other into an integrated structure.

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