Serial receiver equalization circuit

Abstract

An equalization circuit (200) includes a feed forward equalization (FFE) circuit (206) and a decision feedback equalization (DFE) circuit (220). The FFE circuit (206) includes a first FFE tap (208T), a second FFE tap (210T) coupled to the first FFE tap (208T), and a variable gain amplifier (218). The variable gain amplifier (218) includes an input and a programmable capacitor. The input is coupled to the first FFE tap (208T) and the second FFE tap (210T). The programmable capacitor is coupled to the input. The DFE circuit (220) includes an input and a DFE tap (224T). The input is coupled to the variable gain amplifier (218). The DFE tap (224T) is coupled to the input of the variable gain amplifier (218).

Description

Background Technology

[0001] Serial communication links experience high-frequency distortion (phase and amplitude) between the transmitter and receiver on lossy channels. This distortion manifests as inter-symbol interference (ISI) at the receiver, i.e., smearing of the transmitted data bits / symbols. Channel equalization is used to cancel ISI and other channel-induced distortions. Channel equalization is applied using transmit pre-emphasis, which pre-distorts the transmitted signal, and / or receiver equalization, which compensates for unwanted frequency effects on the channel. Summary of the Invention

[0002] This document discloses a receiver equalization circuit that integrates feedforward equalization (FFE), decision feedback equalization (DFE), and gain in a single equalization stage. In one example, the equalization circuit includes an FFE circuit and a DFE circuit. The FFE circuit includes a first FFE tap, a second FFE tap, and a variable gain amplifier. The variable gain amplifier includes an input and a programmable capacitor. The input is coupled to the first FFE tap and the second FFE tap. The programmable capacitor is coupled to the input. The DFE circuit includes a signal input and a DFE tap. The signal input is coupled to the variable gain amplifier. The DFE tap is coupled to the input of the variable gain amplifier.

[0003] In another example, a receiver equalization circuit includes an FFE circuit and a DFE circuit. The FFE circuit includes multiple FFE taps and a variable gain amplifier. The variable gain amplifier includes an input and a programmable capacitor. The input is coupled to the multiple FFE taps. The variable gain amplifier is configured to change the gain by varying the capacitance of the programmable capacitor. The DFE circuit includes a signal input and a DFE tap. The signal input is coupled to the output of the variable gain amplifier. The DFE tap is coupled to the input of the variable gain amplifier.

[0004] In another example, an equalizer circuit includes a linear equalizer circuit, an FFE circuit, a DFE circuit, and a reference circuit. The FFE circuit includes an input, a first FFE tap, a second FFE tap, a variable gain amplifier, a first switch, a second switch, and a third switch. The input is coupled to the output of the linear equalizer circuit. The variable gain amplifier includes an input coupled to the first and second FFE taps, and a programmable capacitor. The programmable capacitor is coupled to the input of the variable gain amplifier and configured to change its capacitance to adjust the gain of the variable gain amplifier. The first switch includes a first terminal coupled to the output of the variable gain amplifier. The second switch includes a first terminal coupled to the first terminal of the first switch and a second terminal coupled to a ground rail. The third switch includes a first terminal coupled to the second terminal of the first switch and a second terminal coupled to the ground rail. The DFE circuit includes a first limiter circuit, a second limiter circuit, a third limiter circuit, and a DFE tap. The first, second, and third limiter circuits are coupled to a second terminal of the first switch. The DFE tap is coupled to the input of the variable gain amplifier. The reference circuit includes a reference voltage source, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, and a sixth switch. The first switch of the reference circuit includes a first terminal coupled to a first output of the reference voltage source and a second terminal coupled to a reference input of the first limiter circuit. The second switch of the reference circuit includes a first terminal coupled to the first terminal of the first switch of the reference circuit and a second terminal coupled to a ground rail. The third switch of the reference circuit includes a first terminal coupled to the second terminal of the first switch of the reference circuit and a second terminal coupled to the ground rail. The fourth switch of the reference circuit includes a first terminal coupled to a second output of the reference voltage source and a second terminal coupled to a reference input of the second limiter circuit. The fifth switch of the reference circuit includes a first terminal coupled to the first terminal of the fourth switch of the reference circuit and a second terminal coupled to a ground rail. The sixth switch of the reference circuit includes a first terminal coupled to the second terminal of the fourth switch of the reference circuit and a second terminal coupled to the ground rail. Attached Figure Description

[0005] For detailed descriptions of various examples, please refer to the accompanying drawings, in which:

[0006] Figure 1 A block diagram illustrating an example serial communication system according to this disclosure;

[0007] Figure 2A block diagram of an example equalization circuit according to this disclosure is shown;

[0008] Figure 3 A block diagram of an example equalization circuit for use with four-level pulse amplitude modulation is shown according to this disclosure;

[0009] Figure 4A and 4B A schematic diagram of an example equalization circuit according to this disclosure is shown;

[0010] Figure 5 Example signals generated in an equalization circuit according to this disclosure are shown;

[0011] Figure 6A and 6B Examples of bias circuits and example reference limiter circuits applied in equalization circuits according to this disclosure are shown; and

[0012] Figure 7 An example of a nonlinear elimination circuit applied in an equalization circuit according to this disclosure is shown. Detailed Implementation

[0013] Certain terms have been used throughout this description and claims to refer to specific system components. Those skilled in the art will understand that different parties may refer to components by different names. This document does not intend to distinguish between components with different names but identical functions. In this invention and claims, the terms "comprising" and "including" are used in an open-ended manner and should therefore be interpreted as meaning "including but not limited to...". Furthermore, the term "couple" is intended to mean indirect or direct wired or wireless connection. Thus, if a first device is coupled to a second device, the connection can be a direct connection or an indirect connection via other devices and connections. The statement "based on" is intended to mean "at least partially based on". Thus, if X is based on Y, then X can vary depending on Y and any number of other factors.

[0014] As serial communication data rates increase, four-level pulse amplitude modulation (PAM4) is becoming increasingly popular. While PAM4 doubles the data rate, it also imposes stricter receiver specifications (compared to non-return-to-zero coding) due to the reduced amplitude of the PAM4 signal, increased inter-symbol interference, and lower signal amplitude.

[0015] In the serial communication system disclosed herein, the receiver includes an equalization stage that combines a feedforward equalization (FFE) circuit, a decision feedback equalization (FFE) circuit, and a variable gain amplifier. Reducing the number of filter stages lowers noise in the receiver. The FFE is implemented as an analog circuit that provides de-emphasis on low frequencies relative to high frequencies. The variable gain amplifier recovers the signal amplitude loss in the FFE circuit.

[0016] The variable gain amplifier includes a programmable capacitor that allows adjustment of the amplifier's gain by changing the capacitance used to integrate the current flowing into the amplifier from the taps of the FFE and DFE. The output of the variable gain amplifier is sampled for limiting in the DFE. To reduce the effect of clock jitter on limiting, the reference voltage supplied to the limiter is sampled using the same sampling clock used for sampling the output of the variable gain amplifier.

[0017] Figure 1 A block diagram of an example serial communication system 100 according to this disclosure is shown. The serial communication system 100 includes a transmitter 102, a channel 104, and a receiver 106. The channel 104 modulates data to be transmitted to the receiver 106 via the channel 104. For example, in some embodiments of the serial communication system 100, the transmitter 102 uses PAM4 modulation to transmit data. In some embodiments of the serial communication system 100, the channel 104 is a conductive or optically conductive medium.

[0018] Receiver 106 extracts clock and data signals from the transmission received via channel 104. Receiver 106 includes an equalizer 108 and a clock / data recovery circuit 110. The equalizer 108 compensates for distortion in the received signal caused by channel 104. For example, the equalizer 108 enhances the high-frequency content of the received signal to compensate for high-frequency attenuation in channel 104. The clock / data recovery circuit 110 extracts clock and data signals from the equalized signal provided by the equalizer 108.

[0019] Figure 2 A block diagram of an equalization circuit 200 according to an example of the present disclosure is shown. The equalization circuit 200 is an embodiment of the equalizer 108. The equalization circuit 200 includes a linear equalizer circuit 202, described as a continuous-time linear equalizer, a feedforward equalizer (FFE) circuit 206, and a decision feedback equalizer (DFE) circuit 220. The FFE circuit 206 and the DFE circuit 220 are combined in a single equalization stage or equalization circuit 204.

[0020] The linear equalizer circuit 202 enhances the high-frequency content of the received signal, including enhancing the high-frequency noise accompanying the signal.

[0021] The FFE circuit 206 includes delay circuits 208, 210, 212, and 214, and a variable gain amplifier 218. The FFE circuit 206 is an analog circuit, and the delay circuits 208, 210, 212, and 214 are implemented, for example, as a sample-and-hold circuit 216. The outputs of the delay circuits 208, 210, 212, and 214 form FFE taps 208T, 210T, 212T, and 214T, coupled to the input of the variable gain amplifier 218 for summation and amplification. A selected gain value is applied to the signal at each of the FFE taps 208T, 210T, 212T, and 214T. Although the FFE circuit 206... Figure 2 It is described as containing four FFE taps, but the implementation of FFE circuit 206 may contain any number of FFE taps.

[0022] DFE circuit 220 is coupled to the output of variable gain amplifier 218. DFE circuit 220 includes one or more limiters 222 and delay circuits 224, 226, and 228. In some embodiments of DFE circuit 220, a comparator is used to implement limiter 222, and flip-flops are used to implement delay circuits 224, 226, and 228. Limiter 222 compares the signal provided by variable gain amplifier 218 with a reference voltage to determine the bit value of the signal received by equalization circuit 200. The outputs of delay circuits 224, 226, and 228 form DFE taps 224T, 226T, and 228T coupled to the input of variable gain amplifier 218 for summation and amplification.

[0023] Figure 3 A block diagram of an example equalization circuit 300 for use with PAM4 modulation according to this disclosure is shown. The equalization circuit 300 is an embodiment of equalization circuit 200 and includes limiters 302, 304, and 306. A weighted sum of the (delayed) limiter outputs is provided to a variable gain amplifier 318. Similarly, a weighted sum of the tapped output signals of the FFE is provided to the variable gain amplifier 318. The variable gain amplifier 318 is an embodiment of variable gain amplifier 218, and limiters 302, 304, and 306 are examples of limiter 222.

[0024] With the help of the three limiters 302, 304 and 306 in the equalization circuit 300, the full-scale voltage (VFS) of the FFE output is adjusted to be the same across different FFE coefficients. Therefore, the variable gain amplifier 318 changes the gain applied to the FFE output to provide the desired VFS signal swing to the limiters 302, 304 and 306.

[0025] VFS=G(Vin-∑FFE)-∑DFE

[0026] G(Vin-∑FFE)=VFS+∑DFE

[0027] in:

[0028] G is the gain applied in the variable gain amplifier 318;

[0029] Vin is the FFE input signal;

[0030] ∑FFE is the sum of the output signals from the FFE taps; and

[0031] ∑DFE is the sum of the output signals from the DFE taps.

[0032] Figure 4A and 4B A schematic diagram of an example equalization circuit 400 according to this disclosure is shown. The equalization circuit 400 is an implementation of equalization circuit 200 or equalization circuit 300, and provides FFE, DFE, and gain in a single stage. The equalization circuit 400 includes an FFE circuit 402, a DFE circuit 404, and a reference circuit 406. The FFE circuit 402 is an implementation of FFE circuit 206, and the DFE circuit 404 is an implementation of DFE circuit 220. The FFE circuit 402 includes multiple FFE taps, shown as a main FFE tap 408 and a driver FFE tap 410, a variable gain amplifier 416, switches 418, 420, and 422. The driver FFE tap 410 can be a precursor or a successor tap. Although in Figure 4B The diagram shows two FFE taps, but implementations of FFE circuit 402 may include any number of FFE taps.

[0033] Each of the FFE taps (e.g., main FFE tap 408, driver FFE tap 410) includes a pair of transistors and degradation resistors 412, 414 to improve input linearity. The transconductance of the transistors varies depending on the gain factor applied at each tap.

[0034] The FFE taps are coupled to input 416B of the variable gain amplifier 416, and the current generated in each of the FFE taps is summed at input 416B of the variable gain amplifier 416. The variable gain amplifier 416 includes a programmable capacitor 424 coupled to input 416B. Changing the capacitance of the programmable capacitor 424 adjusts the gain of the variable gain amplifier 416. In some instances of the variable gain amplifier 416, the programmable capacitor 424 is implemented as a selectable capacitor bank. Using the programmable capacitor 424, the equalization circuit 400 operates as a current / capacitance (I / C) integrator, where... C is the capacitance of programmable capacitor 424, I is the current at input 416B of variable gain amplifier 416, and T is the integration time. The output 416A of variable gain amplifier 416 is coupled to signal input 404A of DFE circuit 404 via switch 418. Switch 420 is coupled to signal input 404A of DFE circuit 404 to reset the input voltage supplied to DFE circuit 404. Switch 422 is coupled to the output of variable gain amplifier 416 to reset the output of variable gain amplifier 416.

[0035] Switch 418 includes a terminal 418A coupled to the output 416A of variable gain amplifier 416 and a terminal 418B coupled to the signal input 404A of DFE circuit 404. Switch 420 includes a terminal 420A coupled to terminal 418B of switch 418 and a terminal 420B coupled to common-mode voltage source 434. Switch 422 includes a terminal 422A coupled to terminal 418A of switch 418 and a terminal 422B coupled to common-mode voltage source 434.

[0036] DFE circuit 404 includes limiter 426, limiter 428, limiter 430, and one or more DFE taps. Although in Figure 4B Only DFE tap 432 is shown, but embodiments of DFE circuit 404 may include any number of DFE taps. Each of limiters 426, 428, and 430 is coupled to signal input 404A of DFE circuit 404, and thereby coupled to terminal 418B of switch 418 for receiving the output of variable gain amplifier 416. Each of limiters 426, 428, and 430 compares the signal received at signal input 404A with a different reference voltage. The outputs of limiters 426, 428, and 430 are delayed, and the delayed outputs of limiters 426, 428, and 430 drive the DFE tap. For example, the delayed output of limiter 426, 428, or 430 drives DFE tap 432. DFE tap 432 (and each DFE tap of DFE circuit 404) is coupled to input 416B of variable gain amplifier 416, and the current output of DFE tap 432 is summed with the outputs of FFE taps 408 and 410 to charge programmable capacitor 424.

[0037] ISUM = IFFE + IDFE

[0038] IFFE=GMin1(Vin(main))+GMin2(Vin(tapa)…

[0039] IDFE=IDFE(TAP)(DFEB(TAP)-DFEZ(TAP))…

[0040] In the equalization circuit 400, jitter in the clock that generates the timing for switches 418, 420, and 422 causes variations in the integration time and noise in the signal supplied to the DFE circuit 404. The reference circuit 406 mitigates the effects of clock jitter by applying the same clock used to control the integration of the signal supplied to the DFE circuit 404 to generate a reference voltage for the DFE circuit 404. Therefore, the noise generated in the reference voltage is correlated with and cancels out the noise generated in the signal supplied to the DFE circuit 404 by the FFE circuit 402. The reference circuit 406 includes a reference voltage source 436, switches 438, 440, 442, 444, 446, and 448. Various embodiments of the equalization circuit also include, as per [reference to...] Figure 6A and 6B The reference current generation is explained based on clock rate, process, voltage, and temperature.

[0041] Switch 440 includes a terminal 440A coupled to the output 436A of reference voltage source 436 and a terminal 440B coupled to the reference input 430A of limiter 430. Switch 438 includes a terminal 438A coupled to terminal 440A of switch 440 and a terminal 438B coupled to common-mode voltage source 434. Switch 442 includes a terminal 442A coupled to terminal 440B of switch 440 and a terminal 442B coupled to common-mode voltage source 434.

[0042] Switch 446 includes a terminal 446A coupled to the output 436B of reference voltage source 436 and a terminal 446B coupled to the reference input 426A of limiter 426. Switch 444 includes a terminal 444A coupled to the terminal 446A of switch 446 and a terminal 444B coupled to common-mode voltage source 434. Switch 448 includes a terminal 448A coupled to the terminal 446B of switch 446 and a terminal 448B coupled to common-mode voltage source 434.

[0043] Figure 5 The following illustrates example signals generated in an implementation of the equalization circuit 400. The INTEGRATE signal 502 controls switches 418, 440, and 446. The RST (SLICER) signal 504 controls switches 420, 442, and 448. The RST (SUM) signal 506 controls switches 422, 438, and 444. The LATP (SLICER) signal controls the latches in limiters 426, 428, and 430. The VIN signal 510 is the integrated voltage provided at signal input 404A of the DFE circuit 404. The VREF signal 512 is the voltage reference signal provided at reference input 430A of the limiter 430. (The text repeats itself here.) Figure 5The description states that the jitter in the INTEGRATE signal 502 generates noise in the VREF signal 512, and the noise cancels out the effect of the jitter in the VIN signal 510.

[0044] Figure 6A and 6B An example bias circuit 602, according to this disclosure, is shown for application in an equalization circuit. The bias circuit 602 generates a bias current that maintains a constant I / C by tracking changes in the capacitor (C) with process, temperature, voltage, and / or clock rate. The bias circuit 602 includes an amplifier circuit 606, a replica capacitor 608, switches 610, 612, and 614. The bias circuit 602 uses an INTEGRATE signal 502 to control switches 610, 612, and 614 to generate a voltage across the replica capacitor 608. The replica capacitor 608 is similar to a programmable capacitor 424. The amplifier circuit 606 compares the voltage across the replica capacitor 608 with a voltage VBG and adjusts the bias current to correct for any discrepancies. The current charging the replica capacitor 608 is mirrored to the FFE circuit 402 and the DFE circuit 404.

[0045] Switch 610 includes a terminal 610A coupled to the output of amplifier circuit 606 and a second terminal 610B coupled to replica capacitor 608. Switch 612 includes a terminal 612A coupled to terminal 610B of switch 610 and a terminal 612B coupled to the inverting input of amplifier circuit 606. Switch 614 includes a terminal 614A coupled to terminal 610A of switch 610 and a terminal 614B coupled to ground rail.

[0046] Figure 6BAlso shown is a reference limiter circuit 604 that provides offset correction to the DFE circuit 404. The reference limiter circuit 604 includes an error limiter 616, a reference limiter 618, and a multiplexer 620. The error limiter 616 includes input 616A coupled to the signal input 404A of the DFE circuit 404. The reference limiter 618 includes input 618A coupled to the signal input 404A of the DFE circuit 404 and a reference input 618B coupled to the output 620A of the multiplexer 620. The reference limiter 618 compares the signal at the signal input 404A of the DFE circuit 404 with a reference voltage provided by the reference limiter from the multiplexer 620. The multiplexer 620 includes inputs 620B, 620C, and 620D connected to a precise reference generated by a resistor ladder. Input 620B is coupled to the output providing a resistor ladder of –VREF = +2 / 3 (VFS), which is the desired value at reference input 426A of limiter 426. Input 620C is coupled to the output providing a resistor ladder of 0 volts, which is the desired value at reference input 428A of limiter 428. Input 620D is coupled to the output providing a resistor ladder of VREF = +2 / 3 (VFS), which is the desired value at input 430A of limiter 430. Input 620E of multiplexer 620 is coupled to reference input 616B of error limiter 616 for receiving the error limiter reference voltage. Multiplexer 620 selects the reference limiter reference voltage from different reference voltages provided at its inputs.

[0047] Reference limiter 618 serves as a standard for relating the outputs of limiters 426, 428, and 430 to error limiter 616. Digital estimation circuit 622 generates an offset correction value based on the output of reference limiter 618 and provides this offset correction value to limiters 426, 428, 430, and error limiter 616. Therefore, limiters 426, 428, and 430 are referenced to reference limiter 618, and the I / C error estimated as offset is corrected for limiter offset by reference limiter circuit 604.

[0048] Figure 7An example of a nonlinear cancellation circuit 700 applied in an equalization circuit according to the present disclosure is shown. The nonlinear cancellation circuit 700 is coupled to the main FFE tap 408 of the equalization circuit 400. The nonlinear cancellation circuit 700 includes transistors 702 and 704. Transistor 702 includes a drain terminal 702D coupled to the drain terminal 708D of transistor 708 and a gate terminal 702G coupled to the gate terminal 708G of transistor 708. Transistor 704 includes a drain terminal 704D coupled to the drain terminal 706D of transistor 706 and a gate terminal 704G coupled to the gate terminal 706G of transistor 706. The source terminal 702S of transistor 702 is coupled to the source terminal 704S of transistor 704.

[0049] Nonlinearity causes three-eye asymmetry in the received PAM4 signal. The main FFE tap, which provides the largest signal from the FFE circuit 402, is the largest contributor to nonlinearity. The nonlinearity cancellation circuit 700 is biased to be cut off with a relatively small input signal and turned on when the input signal swing is large to produce a gain compression of >50 dB, thereby reducing the nonlinear contribution of the main FFE tap.

[0050] The foregoing discussion is intended to illustrate the principles of the invention and various embodiments. Once fully understanding the above disclosure, those skilled in the art will appreciate many variations and modifications. It is intended that the appended claims be interpreted as encompassing all such variations and modifications.

Claims

1. An equalization circuit, comprising: A feedforward equalizer (FFE) circuit, comprising: The first FFE tap and the second FFE tap; and A variable gain amplifier, comprising: Input, which is coupled to the first FFE tap and the second FFE tap; and A programmable capacitor coupled to the input; and A decision feedback equalization (DFE) circuit, comprising: A signal input, which is coupled to the variable gain amplifier; A DFE tap, coupled to the input of the variable gain amplifier; and One or more limiter circuits coupled to the signal input of the DFE circuit to compare the signal provided by the variable gain amplifier with a reference voltage.

2. The equalization circuit of claim 1, wherein the capacitance of the programmable capacitor can be changed to adjust the gain of the variable gain amplifier.

3. The equalization circuit according to claim 1, wherein the currents output from the first FFE tap, the second FFE tap, and the DFE tap are summed at the input of the variable gain amplifier.

4. The equalization circuit according to claim 1, wherein the one or more limiter circuits comprise: A first limiter circuit is coupled to the signal input of the DFE circuit; A second limiter circuit is coupled to the signal input of the DFE circuit; and A third limiter circuit is coupled to the signal input of the DFE circuit.

5. The equalization circuit according to claim 4, further comprising: Reference circuit, comprising: Reference voltage source; The first switch includes: A first terminal, which is coupled to a first output of the reference voltage source; and The second terminal is coupled to the reference input of the first limiter circuit; The second switch includes: The first terminal, which is coupled to the first terminal of the first switch; and The second terminal is coupled to the ground rail; and The third switch includes: The first terminal is coupled to the second terminal of the first switch; and The second terminal is coupled to the ground rail; The fourth switch includes: The first terminal is coupled to the second output of the reference voltage source; and The second terminal is coupled to the reference input of the second limiter circuit; The fifth switch includes: A first terminal, which is coupled to the first terminal of the fourth switch; and The second terminal is coupled to the grounding rail; and The sixth switch includes: The first terminal is coupled to the second terminal of the fourth switch; and The second terminal is coupled to the ground rail.

6. The equalization circuit according to claim 5, further comprising: An error limiter coupled to the signal input of the DFE circuit; A reference limiter, which is coupled to the signal input of the DFE circuit; Multiplexer, comprising: The first input, which is coupled to the first output of the resistive ladder; The second input is coupled to the second output of the resistive ladder; A third reference input, which is coupled to the third output of the resistive ladder; A fourth reference input, coupled to the reference input of the error limiter; and The output is coupled to the reference input of the reference limiter.

7. The equalization circuit according to claim 1, further comprising: The first switch includes: The first terminal is coupled to the variable gain amplifier; and The second terminal is coupled to the signal input of the DFE circuit; The second switch includes: The first terminal, which is coupled to the first terminal of the first switch; and The second terminal is coupled to the ground rail; and The third switch includes: The first terminal is coupled to the second terminal of the first switch; and The second terminal is coupled to the ground rail.

8. The equalization circuit according to claim 1, further comprising: Bias circuit, comprising: Amplifier circuit; Replica capacitor; The first switch includes: A first terminal, which is coupled to the replica capacitor; and The second terminal is coupled to the amplifier circuit; The second switch includes: The first terminal, which is coupled to the first terminal of the first switch; and The second terminal is coupled to the amplifier circuit; and The third switch includes: The first terminal is coupled to the second terminal of the first switch; and The second terminal is coupled to the ground rail.

9. The equalization circuit according to claim 1, further comprising: Nonlinear elimination circuit, coupled to the first FFE tap and comprising: The first transistor includes: Drain terminal, which is coupled to the drain terminal of the first transistor of the first FFE tap; and A gate terminal, which is coupled to the gate terminal of the first transistor at the first FFE tap; and The second transistor includes: Drain terminal, which is coupled to the drain terminal of the second transistor of the first FFE tap; A gate terminal, which is coupled to the gate terminal of the second transistor at the first FFE tap; and The source terminal is coupled to the source terminal of the first transistor of the nonlinear elimination circuit.

10. A receiver equalization circuit, comprising: A feedforward equalizer (FFE) circuit, comprising: Multiple FFE taps; and A variable gain amplifier, comprising: Input, which is coupled to the plurality of FFE taps; and A programmable capacitor, wherein the variable gain amplifier is configured to change the gain by changing the capacitance of the programmable capacitor; and A decision feedback equalization (DFE) circuit, comprising: A signal input, which is coupled to the output of the variable gain amplifier; A DFE tap, which is coupled to the input of the variable gain amplifier; and One or more limiter circuits coupled to the signal input of the DFE circuit to compare the signal provided by the variable gain amplifier with a reference voltage.

11. The receiver equalization circuit of claim 10, wherein the variable gain amplifier is configured to apply the sum of currents received from the plurality of FFE taps and the DFE tap to charge the programmable capacitor.

12. The receiver equalization circuit of claim 10, wherein the one or more limiter circuits comprise: A first limiter circuit is configured to compare a signal received from the variable gain amplifier with a first reference voltage. A second limiter circuit is configured to compare the signal received from the variable gain amplifier with a second reference voltage; and A third limiter circuit is configured to compare the signal received from the variable gain amplifier with a third reference voltage.

13. The receiver equalization circuit according to claim 12, further comprising: An error limiter coupled to the signal input of the DFE circuit; A multiplexer configured to select a reference limiter reference voltage from the first reference voltage, the second reference voltage, the third reference voltage, and the error limiter reference voltage; and A reference limiter is configured to compare the signal received from the variable gain amplifier with a reference voltage of the reference limiter.

14. The receiver equalization circuit according to claim 12, further comprising: A first switch is configured to connect the output of the variable gain amplifier to the input of the first limiter circuit, the input of the second limiter circuit, and the input of the third limiter circuit.

15. The receiver equalization circuit of claim 14, further comprising a reference circuit configured to generate the first reference voltage and the second reference voltage based on the same clock applied to control the first switch.

16. The receiver equalization circuit of claim 15, further comprising a bias circuit configured to: The tracking is attributed to changes in the first reference voltage caused by variations in capacitance with changes in the programmable capacitor's clock rate, process, voltage, or temperature; and The bias currents of the FFE circuit, the DFE circuit, and the reference circuit are generated.

17. The receiver equalization circuit of claim 10, further comprising a nonlinearity cancellation circuit coupled to the main FFE tap and configured to reduce the nonlinearity of the main FFE tap.

18. An equalizer circuit, comprising: Linear equalizer circuit; A feedforward equalizer (FFE) circuit, comprising: The input, which is coupled to the output of the linear equalizer circuit; First FFE tap and second FFE tap; A variable gain amplifier, comprising: The input is coupled to the first FFE tap and the second FFE tap; A programmable capacitor, coupled to the input of the variable gain amplifier, and configured to change its capacitance to adjust the gain of the variable gain amplifier; A first switch includes a first terminal coupled to the output of the variable gain amplifier; The second switch includes: The first terminal, which is coupled to the first terminal of the first switch; and The second terminal is coupled to the ground rail; and The third switch includes: A first terminal, which is coupled to a second terminal of the first switch; and The second terminal is coupled to the ground rail; The decision feedback equalization (DFE) circuit includes: A first limiter circuit is coupled to the second terminal of the first switch; A second limiter circuit is coupled to the second terminal of the first switch; A third limiter circuit is coupled to the second terminal of the first switch; A DFE tap, which is coupled to the input of the variable gain amplifier; and Reference circuit, comprising: Reference voltage source; The first switch includes: A first terminal, coupled to a first output of the reference voltage source; and The second terminal is coupled to the reference input of the first limiter circuit; The second switch includes: A first terminal, coupled to the first terminal of the first switch of the reference circuit; and The second terminal is coupled to the ground rail; and The third switch includes: A first terminal, coupled to the second terminal of the first switch of the reference circuit; and The second terminal is coupled to the ground rail; The fourth switch includes: A first terminal, which is coupled to a second output of the reference voltage source; and The second terminal is coupled to the reference input of the second limiter circuit; The fifth switch includes: A first terminal, coupled to the first terminal of the fourth switch of the reference circuit; and The second terminal, which is coupled to the ground rail; and The sixth switch includes: A first terminal, coupled to the second terminal of the fourth switch of the reference circuit; and The second terminal is coupled to the ground rail; The first, second, and third limiter circuits are coupled to the signal input of the DFE circuit to compare the signal provided by the variable gain amplifier with a reference voltage.

19. The equalizer circuit of claim 18, wherein the variable gain amplifier is configured to apply the sum of currents provided by the first FFE tap, the second FFE tap, and the DFE tap to charge the programmable capacitor.

20. The equalizer circuit according to claim 18, further comprising: An error limiter coupled to the second terminal of the first switch of the FFE circuit; A reference limiter, which is coupled to the second terminal of the first switch of the FFE circuit; Multiplexer, comprising: A first input, which is coupled to the reference input of the first limiter circuit; The second input is coupled to the reference input of the second limiter circuit; A third reference input, which is coupled to the reference input of the third limiter circuit; A fourth reference input, coupled to the reference input of the error limiter; and The output is coupled to the reference input of the reference limiter.

21. The equalizer circuit according to claim 18, further comprising: Bias circuit, comprising: Amplifier circuit; Replica capacitor; The first switch includes: A first terminal, which is coupled to the replica capacitor; and The second terminal is coupled to the amplifier circuit; The second switch includes: The first terminal, which is coupled to the first terminal of the first switch; and The second terminal is coupled to the ground rail; and The third switch includes: The first terminal is coupled to the second terminal of the first switch; and The second terminal is coupled to the ground rail.

22. The equalizer circuit according to claim 18, further comprising: Nonlinear elimination circuit, coupled to the first FFE tap and comprising: The first transistor includes: Drain terminal, which is coupled to the drain terminal of the first transistor of the first FFE tap; A gate terminal, which is coupled to the gate terminal of the second transistor of the first FFE tap; and The second transistor includes: Drain terminal, which is coupled to the drain terminal of the second transistor of the first FFE tap; A gate terminal, which is coupled to the gate terminal of the first transistor at the first FFE tap; and The source terminal is coupled to the source terminal of the first transistor of the nonlinear elimination circuit.

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