Rapid implementation methods, devices, and computer equipment for SSDs moving towards low power consumption
By checking the RAID stripe integrity and storing it in AON_SRAM when the SSD enters low power mode, and combining this with the power-down and power-up processing of SRAM, the problem of excessively long SSD low power mode entry and exit time in the prior art is solved, and a fast low power mode entry and exit process is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SUZHOU UNIONMEMORY INFORMATION SYST LTD
- Filing Date
- 2022-04-25
- Publication Date
- 2026-07-31
AI Technical Summary
Existing SSDs do not perform RAID stripe data integrity checks when transitioning between low-power and low-power operation, which requires reading and performing XOR operations when exiting low-power operation, increasing the time required.
When entering low power mode, the integrity of the RAID stripe data is checked and stored in AON_SRAM. When exiting low power mode, the power-down and power-on processes of SRAM are performed according to the AON_SRAM information to avoid reading Nand chip data for XOR operations.
By storing and controlling power domain processing in AON_SRAM, the time required for solid-state drives to enter and exit low-power mode is significantly reduced.
Smart Images
Figure CN115562569B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of solid-state drive technology, and in particular to a method, apparatus, computer device, and storage medium for rapidly implementing low-power SSD switching. Background Technology
[0002] Currently, most mainstream SSDs support enhanced data protection through RAID, using a 31-block User Data + 1-block Parity approach. The data in the first 31 blocks is valid, while the last block contains Parity data generated by XORing the User Data. If any data in the first 31 blocks is lost, it can be recovered using the Parity data, thus improving data reliability. During User Data writing, the Parity data is updated in real-time. Once all 31 User Data blocks are written to the NandFlash, the last updated Parity data is also written to the NandFlash. At this point, the RAID stripe data is complete; otherwise, it is considered incomplete. For incomplete RAID stripes, the Parity data is not written to the NandFlash.
[0003] However, existing SSDs, upon receiving the command to enter low-power mode, do not perform RAID stripe data integrity checks after the controller saves the management information and directly enter low-power mode. During the initialization phase before exiting low-power mode, the integrity of all RAID stripes is checked. For incomplete RAID stripes, a backend read command is sent to read the valid data, and then a command is sent to the backend to perform an XOR operation to generate parity data for the valid RAID stripe data. Thus, upon exiting low-power mode, to recover the stripe data, the data already written to the NandFlash in the incomplete stripe is read and XORed, increasing the time it takes for the SSD to exit low-power mode. Summary of the Invention
[0004] Therefore, it is necessary to provide a method, apparatus, computer device, and storage medium for rapidly implementing SSD low-power mode switching, which can shorten the time required for solid-state drives to switch to low-power mode.
[0005] A rapid method for implementing low-power SSD switching, the method comprising:
[0006] Upon receiving the low-power command, after the main controller completes the saving of management information, it checks whether all RAID stripe data is complete and saves the information at the fixed address of AON_SRAM.
[0007] Control the power domain to power down the SRAM space corresponding to the RAID stripe with complete data;
[0008] When exiting low power mode, the register indicating whether the RAID stripe is empty will be power-reset to all FF;
[0009] Different processing methods are applied based on the RAID stripe integrity information stored at the fixed address of AON_SRAM;
[0010] If the RAID stripe is incomplete, the corresponding bit in the register is cleared; if the RAID stripe is complete, the power domain is controlled to power on the SRAM corresponding to the RAID stripe.
[0011] In one embodiment, the step of checking whether all RAID stripe data is complete after the master controller has finished saving the management information, and saving the information at the fixed address of AON_SRAM, further includes:
[0012] Strip integrity is determined by reading the value of a register that indicates whether a RAID stripe is empty.
[0013] In one embodiment, the step of performing different processing based on the RAID stripe integrity information stored at the fixed address of AON_SRAM further includes:
[0014] Check if the RAID stripe stored in AON_SRAM has the value at the Parity data address;
[0015] The RAID initialization operation determines whether there is Parity data in the SRAM corresponding to the RAID stripe based on the value stored in AON_SRAM.
[0016] If the SRAM corresponding to the RAID stripe contains Parity data, then clear the corresponding bit in the register that indicates whether the RAID stripe is empty by writing 0;
[0017] If the SRAM corresponding to the RAID stripe does not have parity data, the control power domain will power on and process that SRAM segment.
[0018] In one embodiment, the step of controlling the power domain to power down the SRAM space corresponding to the RAID stripe with complete data further includes:
[0019] The SRAM space corresponding to each RAID in the RAID stripe is controlled separately by the power domain. When entering low power mode, the RAID stripe with complete data is powered down to reduce power consumption.
[0020] A device for rapidly implementing low-power SSD loading / unloading, the device comprising:
[0021] The data inspection module is used to check whether all RAID stripe data is complete after the main controller has finished saving the management information when a low-power command is received, and save the information at a fixed address in AON_SRAM.
[0022] A power-down module is used to control the power domain and perform power-down processing on the SRAM space corresponding to the RAID stripe with complete data.
[0023] A reset module, which is used to power-reset the register indicating whether the RAID stripe is empty to all FF when exiting low power mode;
[0024] The processing module is used to perform different processing based on the RAID stripe integrity information stored at the fixed address of AON_SRAM; if the RAID stripe is incomplete, the corresponding bit of the register is cleared; if the RAID stripe is complete, the power domain is controlled to power on the SRAM corresponding to the RAID stripe.
[0025] In one embodiment, the data inspection module is further configured to:
[0026] Strip integrity is determined by reading the value of a register that indicates whether a RAID stripe is empty.
[0027] In one embodiment, the processing module is further configured to:
[0028] Check if the RAID stripe stored in AON_SRAM has the value at the Parity data address;
[0029] The RAID initialization operation determines whether there is Parity data in the SRAM corresponding to the RAID stripe based on the value stored in AON_SRAM.
[0030] If the SRAM corresponding to the RAID stripe contains Parity data, then clear the corresponding bit in the register that indicates whether the RAID stripe is empty by writing 0;
[0031] If the SRAM corresponding to the RAID stripe does not have parity data, the control power domain will power on and process that SRAM segment.
[0032] In one embodiment, the power-down module is further configured to:
[0033] The SRAM space corresponding to each RAID in the RAID stripe is controlled separately by the power domain. When entering low power mode, the RAID stripe with complete data is powered down to reduce power consumption.
[0034] A computer device includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of any of the methods described above.
[0035] A computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of any of the above methods.
[0036] The aforementioned method, apparatus, computer equipment, and storage media for rapidly implementing SSD low-power transitions can accelerate the process of transitioning to and from low power by introducing this scheme. Specifically, during the low-power entry phase, the integrity of the RAID stripe data is determined by reading the value of a register indicating whether the RAID stripe is empty, and this value is saved to AON_SRAM, having almost no impact on the low-power entry time. During the low-power exit phase, only the register storing RAID stripe integrity information at a fixed address in AON_SRAM, indicating whether the RAID stripe is empty, needs to be configured. The power domain is then controlled to power on the SRAM corresponding to the RAID stripe with complete data. Since the time for storing and reading stripe integrity information at a fixed address in AON_SRAM and controlling the power domain for SRAM power-down and power-on processing is much faster than reading data from the Nand chip and performing an XOR operation to obtain parity data, the overall SSD low-power transition process is significantly accelerated. Attached Figure Description
[0037] Figure 1 This is a flowchart illustrating a method for rapidly implementing low-power SSD deployment and deployment in one embodiment.
[0038] Figure 2 This is a flowchart illustrating a method for rapidly implementing low-power SSD deployment and deployment in another embodiment.
[0039] Figure 3 This is a flowchart illustrating a method for rapidly implementing low-power SSD deployment and deployment in another embodiment.
[0040] Figure 4 This is a structural block diagram of a device for rapidly implementing low-power SSD loading and unloading in one embodiment;
[0041] Figure 5 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation
[0042] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.
[0043] In existing technologies, after receiving a command to enter low-power mode, the SSD controller saves management information and directly enters low-power mode without checking the integrity of RAID stripe data. During the initialization phase before exiting low-power mode, the integrity of all RAID stripes is checked. For incomplete RAID stripes, a backend read command is sent to read the valid data, and then a command is sent to the backend to perform an XOR operation to generate parity data for the valid RAID stripe data. Thus, upon exiting low-power mode, to recover the stripe data, the data already written to the NandFlash in the incomplete stripe is read and XORed, increasing the time it takes for the SSD to exit low-power mode.
[0044] This invention proposes a method to accelerate the transition of SSDs to and from low power consumption, aiming to shorten the time required for solid-state drives to transition to and from low power consumption.
[0045] In one embodiment, such as Figure 1 As shown, a fast implementation method for SSD low-power switching is provided, which includes:
[0046] Step 102: Upon receiving the low-power command, after the main controller completes the saving of management information, check whether all RAID stripe data is complete and save the information at the fixed address of AON_SRAM.
[0047] Step 104: Control the power domain to power down the SRAM space corresponding to the RAID stripe with complete data.
[0048] Step 106: When exiting low power mode, power-on reset the register indicating whether the RAID stripe is empty to all FF;
[0049] Step 108: Perform different processing based on the RAID stripe integrity information stored at the fixed address of AON_SRAM;
[0050] Step 110: If the RAID stripe is incomplete, clear the corresponding bit in the register; if the RAID stripe is complete, control the power domain to power on the SRAM corresponding to the RAID stripe.
[0051] In this embodiment, a method for accelerating the transition of an SSD to and from low power is provided. Specifically, after receiving the command to enter low power mode, the controller completes the saving of management information, checks whether the data of all RAID stripes is complete, and saves the information at a fixed address in AON_SRAM.
[0052] In one embodiment, the step of checking whether all RAID stripe data is complete after the master controller has finished saving the management information and saving the information at the fixed address of AON_SRAM further includes: determining the integrity of the stripe by reading the value of a register indicating whether the RAID stripe is empty.
[0053] Then, the power domain is controlled to power down the SRAM space corresponding to the RAID stripe with complete data, and then enters low-power mode.
[0054] In one embodiment, the step of controlling the power domain to power down the SRAM space corresponding to the RAID stripe with complete data further includes: the SRAM space corresponding to each RAID in the RAID stripe is individually controlled by the power domain, and the RAID stripe with complete data is power down when entering low power mode to reduce power consumption.
[0055] During the initialization phase after exiting low power consumption, different processing is performed based on the RAID stripe integrity information stored at the fixed address of AON_SRAM.
[0056] Specifically, the register indicating whether a RAID stripe is empty resets to all FF values upon power-up, indicating that the RAID stripe contains no parity data, i.e., the stripe is empty. After an XOR operation is performed on the stripe, the corresponding bits in the register are automatically cleared to 0 by the hardware, indicating that the current stripe contains parity data. When the parity data of the RAID stripe is written to the NandFlash, or when the RAID stripe is reused, the corresponding bit in the register is set to 1, indicating that the RAID stripe is empty, to prevent data within the stripe from participating in XOR operations again.
[0057] If a stripe is incomplete, the corresponding bit in the register indicating whether the RAID stripe is empty is cleared, informing the backend controller to continue using the parity data stored within the stripe for XOR operations when writing to that stripe. If the stripe is complete, the power domain is controlled to power on the SRAM corresponding to that RAID stripe. Since storing and retrieving information about the completeness of all stripes at a fixed address in AON_SRAM, and controlling the power domain to power on and off the SRAM, is much faster than reading the data already written to the Nand chip and performing an XOR operation to obtain the parity data, this significantly accelerates the overall process of transitioning from SSD to low-power operation.
[0058] In the above embodiment, when exiting the low-power phase, it is only necessary to control the power domain and power on the SRAM corresponding to the RAID stripe with complete data, by storing the RAID stripe integrity information configuration in the register at the fixed address of AON_SRAM that indicates whether the RAID stripe is empty. Since the time for storing and reading the stripe integrity information at the fixed address of AON_SRAM and controlling the power domain to power on and off the SRAM is much faster than the time for reading the data on the Nand chip and performing an XOR operation to obtain the parity data, the overall process of the solid-state drive entering and exiting low-power mode can be accelerated.
[0059] In one embodiment, such as Figure 2 As shown, a fast method for implementing low-power SSD switching is provided. This method includes steps for different processing based on the RAID stripe integrity information stored at a fixed address in AON_SRAM, further comprising:
[0060] Step 202: Read whether the RAID stripe stored in AON_SRAM has a value at the Parity data address;
[0061] Step 204, RAID initialization operation: Determine whether there is Parity data in the SRAM corresponding to the RAID stripe based on the value stored in AON_SRAM;
[0062] Step 206: If the SRAM corresponding to the RAID stripe has Parity data, then clear the corresponding bit of the register indicating whether the RAID stripe is empty by writing 0.
[0063] Step 208: If the SRAM corresponding to the RAID stripe does not have parity data, control the power domain to power on the SRAM segment.
[0064] For specific details, please refer to Figure 3 The method shown for accelerating the transition of a solid-state drive to and from low-power mode includes the following implementation steps in its low-power mode exit initialization process:
[0065] 1. The SSD receives a command from the Host to exit low-power mode.
[0066] 2. The SSD exits low-power mode, and the backend controller performs initialization operations.
[0067] 3. The hardware automatically resets the register indicating whether the RAID stripe is empty to all FF upon power-on, meaning there is no Parity data in the corresponding SRAM space.
[0068] 4. Check if the RAID stripes stored in AON_SRAM have the value at the Parity data address.
[0069] 5. RAID initialization operation: Determine whether there is Parity data in the SRAM corresponding to the RAID stripe based on the value stored in AON_SRAM.
[0070] 6. If the SRAM corresponding to the RAID stripe contains Parity data, clear the corresponding bit in the register indicating whether the RAID stripe is empty by writing 0.
[0071] 7. If the SRAM corresponding to the RAID stripe does not have parity data, control the power domain to power on that SRAM segment.
[0072] 8. The SSD backend completes the initialization process.
[0073] In this embodiment, by controlling the power domain to process the power-down and power-on of the SRAM, the time is much faster than the time to read the data that has been written to the Nand chip and perform an XOR operation to obtain the Parity data, thus shortening the time for the solid-state drive to switch between low power and low power consumption.
[0074] It should be understood that, although Figure 1-3 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 1-3 At least some of the steps in the process may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.
[0075] In one embodiment, such as Figure 4 As shown, a fast implementation device 400 for low-power SSD loading and unloading is provided, the device comprising:
[0076] Data inspection module 401 is used to check whether all RAID stripe data is complete after the main controller has finished saving the management information when a low power command is received, and save the information at a fixed address in AON_SRAM.
[0077] Power-down module 402, the power-down module is used to control the power domain and perform power-down processing on the SRAM space corresponding to the RAID stripe with complete data;
[0078] Reset module 403, the reset module is used to power-reset the register indicating whether the RAID stripe is empty to all FF when exiting low power;
[0079] The processing module 404 is used to perform different processing based on the RAID stripe integrity information stored at the fixed address of AON_SRAM; if the RAID stripe is incomplete, the corresponding bit of the register is cleared; if the RAID stripe is complete, the power domain is controlled to power on the SRAM corresponding to the RAID stripe.
[0080] In one embodiment, the data inspection module 401 is further configured to:
[0081] Strip integrity is determined by reading the value of a register that indicates whether a RAID stripe is empty.
[0082] In one embodiment, the processing module 404 is further configured to:
[0083] Check if the RAID stripe stored in AON_SRAM has the value at the Parity data address;
[0084] The RAID initialization operation determines whether there is Parity data in the SRAM corresponding to the RAID stripe based on the value stored in AON_SRAM.
[0085] If the SRAM corresponding to the RAID stripe contains Parity data, then clear the corresponding bit in the register that indicates whether the RAID stripe is empty by writing 0;
[0086] If the SRAM corresponding to the RAID stripe does not have parity data, the control power domain will power on and process that SRAM segment.
[0087] In one embodiment, the power-down module 402 is further configured to:
[0088] The SRAM space corresponding to each RAID in the RAID stripe is controlled separately by the power domain. When entering low power mode, the RAID stripe with complete data is powered down to reduce power consumption.
[0089] For specific limitations on the device for quickly implementing low-power SSD switching, please refer to the limitations on the method for quickly implementing low-power SSD switching mentioned above, which will not be repeated here.
[0090] In one embodiment, a computer device is provided, the internal structure of which can be shown as follows: Figure 5 As shown, the computer device includes a processor, memory, and a network interface connected via a system bus. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and databases. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The network interface is used for communication with external terminals via a network connection. When the computer program is executed by the processor, it implements a method for rapid, low-power SSD deployment and deployment.
[0091] Those skilled in the art will understand that Figure 5 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.
[0092] In one embodiment, a computer device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps in the various method embodiments described above.
[0093] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the steps in the various method embodiments described above.
[0094] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), Rambus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.
[0095] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0096] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.
Claims
1. A method for rapidly implementing low-power SSD switching, the method comprising: Upon receiving the low-power command, after the main controller completes the saving of management information, it checks whether all RAID stripe data is complete and saves the information at a fixed address in AON_SRAM; it also includes determining stripe integrity by reading the value of a register indicating whether a RAID stripe is empty; Control the power domain to power down the SRAM space corresponding to the RAID stripe with complete data; When exiting low power mode, the register indicating whether the RAID stripe is empty will be power-reset to all FF; Different processing is performed based on the RAID stripe integrity information stored at the fixed address of AON_SRAM; it also includes: Check if the RAID stripe stored in AON_SRAM has the value at the Parity data address; The RAID initialization operation determines whether there is Parity data in the SRAM corresponding to the RAID stripe based on the value stored in AON_SRAM. If the SRAM corresponding to the RAID stripe contains Parity data, then clear the corresponding bit in the register that indicates whether the RAID stripe is empty by writing 0; If the SRAM corresponding to the RAID stripe does not have parity data, the control power domain will power on and process that SRAM segment. If the RAID stripe is incomplete, the corresponding bit in the register is cleared; if the RAID stripe is complete, the power domain is controlled to power on the SRAM corresponding to the RAID stripe.
2. The method of claim 1, wherein, The step of power-down processing of the SRAM space corresponding to the complete RAID stripe in the control power domain further includes: The SRAM space corresponding to each RAID in the RAID stripe is controlled separately by the power domain. When entering low power mode, the RAID stripe with complete data is powered down to reduce power consumption.
3. A device for quickly implementing the advance and retreat of a SSD with low power consumption, characterized in that, The device for rapidly implementing low-power SSD loading and unloading includes: The data inspection module is used to check whether all RAID stripe data is complete after the main controller has finished saving the management information when a low-power command is received, and to save the information at a fixed address in AON_SRAM; it is also used to: determine stripe integrity by reading the value of a register that indicates whether a RAID stripe is empty; A power-down module is used to control the power domain and perform power-down processing on the SRAM space corresponding to the RAID stripe with complete data. A reset module, which is used to power-reset the register indicating whether the RAID stripe is empty to all FF when exiting low power mode; The processing module is used to perform different processing based on the RAID stripe integrity information stored at a fixed address in AON_SRAM; if the RAID stripe is incomplete, the corresponding bit in the register is cleared; if the RAID stripe is complete, the power domain is controlled to power on the SRAM corresponding to the RAID stripe; it is also used to: Check if the RAID stripe stored in AON_SRAM has the value at the Parity data address; The RAID initialization operation determines whether there is Parity data in the SRAM corresponding to the RAID stripe based on the value stored in AON_SRAM. If the SRAM corresponding to the RAID stripe contains Parity data, then clear the corresponding bit in the register that indicates whether the RAID stripe is empty by writing 0; If the SRAM corresponding to the RAID stripe does not have parity data, the control power domain will power on and process that SRAM segment.
4. The device of claim 3, wherein the device is a SSD. The power-down module is also used for: The SRAM space corresponding to each RAID in the RAID stripe is controlled separately by the power domain. When entering low power mode, the RAID stripe with complete data is powered down to reduce power consumption.
5. A computer device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the method of claim 1 or 2.
6. A computer-readable storage medium having stored thereon a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method of claim 1 or 2.