Task processing method and device, distributed chip, electronic equipment and medium

Abstract

The present disclosure provides a task processing method and device, a distributed chip, an electronic device and a medium, and belongs to the technical field of computers. The method comprises the following steps: determining an unoccupied first computing node and an occupied second computing node according to node occupation information of a distributed chip; selecting a target computing node from the second computing node, and copying content in storage resources corresponding to the target computing node to storage resources of the first computing node; and executing a to-be-processed task based on the first computing node and the second computing node. According to the embodiment of the present disclosure, the resource utilization rate of the extended chip can be improved, and the resource waste of the chip can be reduced.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and in particular to a task processing method and apparatus, a distributed chip, an electronic device, and a computer-readable medium. Background Technology

[0002] Technologies such as Artificial Intelligence (AI) and blockchain rely on parallel computing and distributed storage. Because distributed chips typically have multiple computing nodes, each configured with corresponding storage resources, they have been widely used in AI, blockchain, and other technological fields.

[0003] In related technologies, in a single distributed chip, or after cascading the current distributed chip with other distributed chips to obtain an extended chip, only a few rows or columns of computing nodes in the distributed chip may be used, resulting in unused computing nodes. The storage resources of these computing nodes are also unused, leading to a waste of computing and storage resources. Summary of the Invention

[0004] This disclosure provides a task processing method and apparatus, a distributed chip, an electronic device, and a computer-readable medium.

[0005] In a first aspect, this disclosure provides a task processing method. A distributed chip is configured with multiple computing nodes distributed in an array, and each computing node is allocated corresponding storage resources. The task processing method includes: determining an unoccupied first computing node and an occupied second computing node based on the node occupancy information of the distributed chip; selecting a target computing node from the second computing nodes; copying the content in the storage resources corresponding to the target computing node to the storage resources of the first computing node; and executing the task to be processed based on the first computing node and the second computing node.

[0006] Secondly, this disclosure provides a task processing device. A distributed chip is configured with multiple computing nodes arranged in an array, and each computing node is allocated corresponding storage resources. The task processing device includes: a determining module, used to determine an unoccupied first computing node and an occupied second computing node based on node occupancy information of the distributed chip; a selecting module, used to select a target computing node from the second computing nodes; a copying module, used to copy the contents of the storage resources corresponding to the target computing node to the storage resources of the first computing node; and an execution module, used to execute the task to be processed based on the first computing node and the second computing node.

[0007] Thirdly, this disclosure provides a distributed chip, which is provided with multiple computing nodes arranged in an array, and each computing node is allocated corresponding storage resources. The computing nodes include an unoccupied first computing node and an occupied second computing node. The second computing node includes a target computing node, which is a second computing node whose storage resources are connected to the storage resources of the first computing node.

[0008] Fourthly, this disclosure provides an electronic device comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores one or more computer programs executable by the at least one processor, the one or more computer programs being executed by the at least one processor to enable the at least one processor to perform the task processing method described above.

[0009] Fifthly, this disclosure provides a computer-readable medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the above-described task processing method.

[0010] The embodiments provided in this disclosure can, when there is an unoccupied first computing node in a distributed chip, copy the contents of the occupied storage resources of the second computing node to the storage resources of the first computing node as redundant storage of the distributed chip, and perform the task to be processed based on the joint execution of the first computing node and the second computing node, thereby improving the resource utilization of the distributed chip and reducing the waste of chip resources.

[0011] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0012] The accompanying drawings are provided to further illustrate the present disclosure and form part of the specification. They are used together with the embodiments of the present disclosure to explain the disclosure and do not constitute a limitation thereof. The above and other features and advantages will become more apparent to those skilled in the art from the detailed description of exemplary embodiments with reference to the accompanying drawings, in which:

[0013] Figure 1 A schematic diagram of a distributed chip provided in an embodiment of this disclosure;

[0014] Figure 2 A flowchart illustrating a task processing method based on a distributed chip, provided in this embodiment of the disclosure;

[0015] Figure 3(a) is a schematic diagram of a distributed chip provided in an embodiment of this disclosure;

[0016] Figure 3(b) is a schematic diagram of a distributed chip formed by chip cascading according to an embodiment of the present disclosure;

[0017] Figure 4 A schematic diagram of a distributed chip provided in an embodiment of this disclosure;

[0018] Figure 5 This is a schematic diagram of a distributed chip processing according to an embodiment of the present disclosure;

[0019] Figure 6 This is a schematic diagram of a distributed chip processing according to an embodiment of the present disclosure;

[0020] Figure 7 A schematic diagram of a distributed chip provided in an embodiment of this disclosure;

[0021] Figure 8 A schematic diagram of region division provided in an embodiment of this disclosure;

[0022] Figure 9 This is a schematic diagram of a distributed chip processing according to an embodiment of the present disclosure;

[0023] Figure 10 This is a schematic diagram of a distributed chip processing according to an embodiment of the present disclosure;

[0024] Figure 11 This is a schematic diagram of a distributed chip processing according to an embodiment of the present disclosure;

[0025] Figure 12 A block diagram of a task processing device based on a distributed chip provided in this disclosure embodiment;

[0026] Figure 13 This is a block diagram of an electronic device provided in an embodiment of the present disclosure. Detailed Implementation

[0027] To enable those skilled in the art to better understand the technical solutions of this disclosure, exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments of this disclosure to aid understanding. These should be considered merely exemplary. Therefore, those skilled in the art should recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this disclosure. Similarly, for clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0028] Where there is no conflict, the various embodiments of this disclosure and the features thereof in the embodiments may be combined with each other.

[0029] As used herein, the term “and / or” includes any and all combinations of one or more related enumerated entries.

[0030] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms “a” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that when the terms “comprising” and / or “made of” are used in this specification, the presence of the stated feature, integral, step, operation, element, and / or component is specified, but the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof is not excluded. Words such as “connected” or “linked” are not limited to physical or mechanical connections but can include electrical connections, whether direct or indirect.

[0031] Unless otherwise specified, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted as having an idealized or overly formal meaning, unless expressly so defined herein.

[0032] Artificial intelligence (AI) is the research and development of technologies used to simulate, extend, and expand human intelligence. In recent years, it has entered a phase of rapid development and has been applied in numerous fields. Blockchain is a new application model of computer technologies such as distributed data storage, peer-to-peer transmission, consensus mechanisms, and encryption algorithms. It uses decentralized, shared, and encrypted technologies for distributed ledger management, possessing significant characteristics such as disintermediation, openness, autonomy, information immutability, and anonymity, and has already been widely adopted. However, both AI and blockchain technologies typically require substantial computing power and distributed storage resources for their implementation.

[0033] Distributed chips contain multiple computing nodes arranged in an array. Typically, each computing node is allocated corresponding storage resources, and the computing nodes have management authority over the allocated storage resources. Therefore, distributed chips are suitable for processing various distributed tasks, making them applicable to fields such as artificial intelligence and blockchain.

[0034] Distributed chips can be arranged in rectangular, circular, trapezoidal, or other regular or irregular shapes.

[0035] Figure 1 This is a schematic diagram of a distributed chip provided in an embodiment of this disclosure. (Refer to...) Figure 1The distributed chip includes 16 computing nodes arranged in a 4x4 array, and each computing node is equipped with 4 storage units to provide storage resources for the computing nodes. The arrowed lines between the computing nodes represent the routes used to pass data.

[0036] In some possible implementations, computing nodes located at the edge row or column of a distributed chip are directly connected to computing nodes at the corresponding edge row or column on the other side (e.g., by connecting the corresponding nodes through encapsulation technology).

[0037] Taking node 0 as an example: Besides being directly connected to nodes 1 and 4, node 0 is also directly connected to nodes 3 and 12. This means that the hop count between node 0 and nodes 1, 4, 3, and 12 is always 1 hop. Therefore, when node 0 transmits data to node 12, it can either transmit the data directly to node 12 with a single hop, or it can transmit the data to node 12 with three hops, sequentially connecting to nodes 4 and 8. Similarly, node 1 is directly connected to nodes 0, 5, and 2, and also directly connected to node 13. Other nodes are similar to nodes 0 and 1, and will not be described again here.

[0038] It should be noted that by using the above node connection method, the computing nodes of the distributed chip can be connected into a ring structure, which can reduce the average number of hops between computing nodes, reduce latency, and improve the processing efficiency of the distributed chip.

[0039] In some possible implementations, if the current computing node learns that the data required for the (i+1)th step calculation is stored in the storage unit of another computing node after completing the i-th step calculation, the relevant data for the i-th step calculation can be transferred to the other computing node through the routing connection between computing nodes, and the other computing node can then perform the (i+1)th step calculation, where i is an integer greater than or equal to 1.

[0040] In one example, the computation order of the computing nodes can be determined in advance based on the storage status of the data in the storage unit. If the computation order is determined to be node 3->node 6->node 0, then node 3 first performs the first step of computation using the data in its storage unit. After completing the computation, it transmits the relevant data of the first step of computation (which includes any one or more of the computation results of node 3, intermediate computation data, etc.) to node 6 through routing. Node 6 then performs the second step of computation using the data in its storage unit and the relevant data transmitted by node 3. After node 6 completes the computation, it transmits the relevant data corresponding to node 6 to node 0 through routing. Node 0 then performs the third step of computation using the data in its storage unit and the relevant data transmitted by node 6, thereby obtaining the final computation result.

[0041] In some possible implementations, if a single distributed chip cannot meet the task processing requirements (including computing node requirements and / or storage requirements), multiple distributed chips can be cascaded to form an extended chip, which is then used to complete the task processing. This extended chip can be considered a distributed chip with a larger node scale. The task processing method provided in this disclosure is applicable to a single distributed chip as well as to extended chips formed through chip cascading; the storage resources include electronic devices capable of data storage, such as triggers, registers, latches, memories, and memory cards.

[0042] However, in some possible implementations, in a single distributed chip, or after cascading the current distributed chip with other distributed chips to obtain an extended chip, only a few rows or columns of computing nodes in the distributed chip may be used, resulting in unused computing nodes. The storage resources of these computing nodes are also unused, leading to a waste of computing and storage resources.

[0043] In view of this, the present disclosure provides a distributed chip, which is provided with multiple computing nodes distributed in an array, and each computing node is allocated corresponding storage resources. The computing nodes include an unoccupied first computing node and an occupied second computing node. The second computing node includes a target computing node, which is a second computing node whose storage resources are connected to the storage resources of the first computing node.

[0044] The number of target computing nodes is less than or equal to the number of first computing nodes.

[0045] The storage resources of the target computing node can be connected to an equal number of the storage resources of the first computing nodes to achieve data replication. During task processing, data transfer between nodes is completed, reducing the number of hops between computing nodes. The connection can be implemented by pre-determining the target computing node during encapsulation, then connecting its storage resources to the storage resources of the first computing nodes, and directly completing data transfer and replication during task processing. Alternatively, the storage resources of the second computing node can be pre-connected to the storage resources of the first computing node, and then, during task processing, a specific target computing node and a specific first computing node are selected to perform data transfer and copy the storage resources. In other words, the target computing node can be determined during encapsulation or confirmed after encapsulation based on the processing task requirements. Data replication can be achieved through a data transmission unit, which can be triggered by the main controller to realize data transfer and replication.

[0046] For reference Figure 1In the distributed chip shown, among nodes 0-15, some nodes may be unoccupied, belonging to the first computing nodes, while others may be occupied, belonging to the second computing nodes. For the first computing nodes, since their resources are not utilized, they are in an idle state, which may result in low resource utilization.

[0047] In view of this, the present disclosure also provides a task processing method and apparatus based on a distributed chip, which can copy the contents of at least a portion of the storage resources of a second computing node that have been occupied to the storage resources of a first computing node that have not been occupied, as redundant storage of the distributed chip, and execute the task to be processed based on the joint execution of the first computing node and the second computing node. That is, the data processing is still completed based on the second computing node, but only the storage resources of the first computing node are used to complete the data transfer between nodes, reducing the number of hops between computing nodes, improving the resource utilization of the distributed chip, and reducing the waste of chip resources.

[0048] Figure 2 A flowchart illustrating a task processing method based on a distributed chip, provided as an embodiment of this disclosure. (Refer to...) Figure 2 The method includes:

[0049] Step S201: Based on the node occupancy information of the distributed chip, determine the first unoccupied computing node and the second occupied computing node.

[0050] Step S202: Select a target computing node from the second computing nodes, and copy the contents of the storage resources corresponding to the target computing node to the storage resources of the first computing node.

[0051] Step S203: Execute the task to be processed based on the first computing node and the second computing node.

[0052] For example, a distributed chip can be a single distributed chip or an expanded chip obtained by cascading at least two chips. A distributed chip has multiple computing nodes arranged in an array, and each computing node is allocated corresponding storage resources. These storage resources can be used to store various content, including but not limited to processing results generated by the computing nodes in processing tasks, intermediate data generated during the processing of tasks by the computing nodes, data sent by other computing nodes, and data obtained from other storage spaces.

[0053] Figure 3(a) is a schematic diagram of a distributed chip provided in an embodiment of the present disclosure, and Figure 3(b) is a schematic diagram of a distributed chip formed by chip cascading provided in an embodiment of the present disclosure.

[0054] Referring to Figure 3(a), the distributed chip includes 4*4 arrayed computing units, each of which is allocated corresponding storage resources (storage resources are not shown in the figure).

[0055] Referring to Figure 3(b), this is an expansion chip obtained by cascading four 4x4 distributed chips. This expansion chip includes 64 computing units, and each computing unit is allocated corresponding storage resources (storage resources are not shown in the figure).

[0056] In some possible implementations, computing nodes located in edge rows or edge columns of a distributed chip can establish routing connections with corresponding computing nodes in the distributed chip cascaded with them, so that the extended chip can form a ring-shaped computing array both horizontally and vertically.

[0057] In one example, in the horizontal cascading direction, compute node 56 is directly connected to compute node 63, compute node 48 is directly connected to compute node 55, and so on. Compute node 0 is also directly connected to compute node 7, thus forming a ring-shaped compute array in the horizontal direction. Similarly, in the vertical cascading direction, compute node 56 is directly connected to compute node 0, compute node 57 is directly connected to compute node 1, and so on. Compute node 63 is also directly connected to compute node 7, thus forming a ring-shaped compute array in the vertical direction as well.

[0058] In some possible implementations, if there is an unoccupied first computing node in the distributed chip, it will lead to a waste of computing nodes and storage resources. Based on this, in step S201, a target computing node can be selected from the occupied second computing nodes according to the node occupancy information of the distributed chip, so as to copy the contents of the storage resources of the target computing node into the storage resources of the first computing node, thereby reducing the waste of resources.

[0059] In some possible implementations, node occupancy information is used to characterize the occupancy of computing nodes within the distributed chip. In one example, node occupancy information includes the row and column distribution information of the first computing node and the second computing node. For instance, the row and column distribution information of the first computing node includes which rows and / or columns of the distributed chip the first computing node occupies, and the row and column distribution information of the second computing node includes which rows and / or columns of the distributed chip the second computing node occupies. Based on the node occupancy information, the distribution of the first computing node and the second computing node within the distributed chip, as well as their relative positional relationship, can be clearly defined.

[0060] In some possible implementations, the node occupancy information includes the number of first computing nodes and second computing nodes, and the number of target computing nodes is less than or equal to the number of first computing nodes; the target computing node can be selected from the second computing nodes based on the number information.

[0061] In step S201, the number of unoccupied first computing nodes is determined to be N1, and N2 nodes are selected from the occupied second computing nodes as target computing nodes, where N2 ≤ N1. When selecting N2 second computing nodes, they can be selected randomly, by row and column, or based on preset information (e.g., node load information). This embodiment of the present disclosure does not impose any limitations on this selection.

[0062] In some possible implementations, node occupancy information includes the location information of the first and second computing nodes. Based on this location information, a target computing node can be selected from the second computing nodes. The location information can be represented as a planar distribution, a row / column distribution, or planar coordinate values. Based on the location information, the content of the target computing node's storage resources at a specific location can be copied to the unoccupied storage resources of the first computing node at random or specific locations. As long as data transfer between nodes is completed during task processing, the number of hops between computing nodes can be reduced.

[0063] In some possible implementations, the location information includes the row and column distribution information of the first and second computing nodes. Based on this information, a target computing node can be selected from the second computing nodes. The row and column distribution information more clearly and accurately reflects the specific location of a computing node, such as its row and column number. This allows the content of the target computing node's storage resources at a specific location to be copied to the unused storage resources of the first computing node according to a specific row and column arrangement rule, thereby completing data transfer between nodes and reducing the number of hops between computing nodes.

[0064] In some possible implementations, the content of the storage resources corresponding to the target computing node can be copied in a fixed direction to the storage resources of an unoccupied first computing node, based on the row and column distribution information. The fixed direction refers to the fixed direction of the target computing node, and some or all of the second computing nodes in the row and / or column directions can be selected as the target computing node.

[0065] In some possible implementations, step S202, selecting the target computing node, can be achieved as follows: First, determine the fixed direction of the target computing node based on the row and column distribution information of the first computing node; second, select the target computing node from the second computing nodes based on the row and column distribution information of the first computing node, the row and column distribution information of the second computing node, and the fixed direction of the target computing node.

[0066] The fixed direction can be either row-oriented or column-oriented, used to determine whether to select a row or column from the second computing node as the target computing node. In some possible implementations, if one or more rows of computing nodes in the distributed chip are occupied, the fixed direction is determined to be the row-oriented direction, meaning that several rows are selected from the second computing nodes of the distributed chip as the target computing node. Conversely, if one or more columns of computing nodes in the distributed chip are occupied, the fixed direction is determined to be the column-oriented direction, meaning that several columns are selected from the second computing nodes of the distributed chip as the target computing node.

[0067] In some possible implementations, with the fixed direction being the row direction, the target row number n1 is first determined based on the row and column distribution information of the first computing node; then, based on the row and column distribution information of the second computing node and the target row number n1, the second computing node in row n2 is selected as the target computing node, where n1 and n2 are both integers greater than or equal to 1, and n2 ≤ n1.

[0068] In other words, for the unoccupied n1 rows of the first computing node, all rows (i.e., n1 = n2) or some rows (i.e., n2 < n1) can be selected to achieve redundant storage for the second computing node. This disclosure does not limit this.

[0069] In one example, the target number of rows is the same as the number of rows in the first compute node, which means that all the first compute nodes are occupied, making all the first compute nodes redundant nodes.

[0070] In one example, the target number of rows is less than the number of rows in the first compute node, meaning that only a portion of the first compute node is occupied, and some first compute nodes remain unoccupied.

[0071] It should be noted that since the number of rows in the second computing node is usually greater than the number of rows in the unoccupied first computing node, in order to reduce the average number of hops between computing nodes and improve effective computing power, a sparse and uniform approach can be used to select the second computing node with n2 rows as the target computing node. In some possible implementations, the target computing node can be selected sparsely and uniformly based on the node row spacing.

[0072] In one example, firstly, the row interval of the node is determined based on the row and column distribution information of the second computing node and the target row number n1; secondly, based on the row interval, the second computing node in row n2 is selected as the target computing node.

[0073] It should be noted that for the same distributed chip, the node row spacing can be set to a uniform spacing or different spacings. Setting different node row spacings is mainly because in some application scenarios, it is impossible to set a uniform node row spacing based on the row and column distribution information of the first computing node and the row and column distribution information of the second computing node.

[0074] In one example, the distributed chip includes computing nodes arranged in a 10x5 array. The second computing node is located on top of the distributed chip, arranged in a 7x5 array, while the first computing node is located on the bottom, arranged in a 3x5 array. That is, the second computing node occupies rows 1 to 7 of the distributed chip, and the first computing node occupies rows 8 to 10. The selection direction for the target computing node is a row vector, and at most 3 rows can be selected from the second computing nodes in rows 1 to 7 as the target computing node (i.e., the number of target rows n1 equals 3). In this case, it is impossible to set a uniform node row spacing. However, to select target computing nodes as sparsely and evenly as possible, n2 can be set to 3, and the node row spacing can be set to 1, 1, and 2 respectively. In other words, the second computing node in row 1 is selected as the target computing node corresponding to the first computing node in row 8; after a 1-row interval, the second computing node in row 3 is selected as the target computing node corresponding to the first computing node in row 9; after a 2-row interval, the second computing node in row 6 is selected as the target computing node corresponding to the first computing node in row 10. Of course, n2 can also be set to 2, thus selecting 2 rows from the second compute nodes of rows 1 to 7 as target compute nodes. For example, the second compute nodes of rows 3 and 5 can be selected as the target compute nodes corresponding to the first compute nodes of rows 8 and 9, respectively. The case where n2 is 1 is similar to the above and will not be described in detail here.

[0075] It should be noted that the above examples of node line spacing are merely illustrative. Those skilled in the art can flexibly set node line spacing according to their needs, and this disclosure does not limit this.

[0076] The fixed direction also includes the column direction. In some possible implementations, when the fixed direction is the column direction, the target column number m1 is first determined based on the row and column distribution information of the first computing node; then, based on the row and column distribution information of the second computing node and the target column number m1, the second computing node with column m2 is selected as the target computing node, where m1 and m2 are both integers greater than or equal to 1, and m2 ≤ m1.

[0077] In other words, for the unoccupied first computing node in column m1, all columns (i.e., m1 = m2) or some columns (i.e., m2 < m1) can be selected to achieve redundant storage for the second computing node. This disclosure does not limit this.

[0078] In one example, the target number of columns is the same as the number of columns in the first compute node, which means that all the first compute nodes are occupied, making all the first compute nodes redundant nodes.

[0079] In one example, the number of target columns is less than the number of columns in the first compute node, meaning that only a portion of the first compute node is occupied, while some first compute nodes remain unoccupied.

[0080] It should be understood that when nodes copy storage resources, additional power is usually required. For the cases of n2 < n1 and m2 < m1, since only a portion of the first computing node is used, power consumption is saved compared to the cases of n2 = n1 and m2 = m1.

[0081] It should be noted that, since the number of columns in the second computing node is usually greater than the number of columns in the unoccupied first computing node, in order to reduce the average number of hops between computing nodes and improve effective computing power, the second computing node with m2 columns can be selected as the target computing node in a sparse and uniform manner. In some possible implementations, the target computing node can be selected sparsely and uniformly based on the node column interval.

[0082] In one example, firstly, the node column interval is determined based on the row and column distribution information of the second computing node and the target column number m1; secondly, based on the node column interval, the second computing node with column m2 is selected as the target computing node.

[0083] It should be noted that, similar to the node row interval, the node column interval can be set to a uniform interval or different intervals for the same distributed chip. For details, please refer to the previous section on setting the node row interval, which will not be repeated here.

[0084] It should also be noted that when selecting the second compute node based on the target number of rows or columns, you can select the second compute node for the entire row or column, or you can select a portion of the second compute nodes in a row or column, as long as the number of selected second compute nodes is the same as the number of the target compute nodes.

[0085] In some possible implementations, in step S202, selecting the target computing node from the second computing nodes includes:

[0086] Based on the load information of the second computing node, a target computing node is selected from the second computing nodes; wherein, the load information includes at least the computing frequency and the amount of computing.

[0087] In some possible implementations, load information can be obtained through simulation of distributed chips.

[0088] For example, for various tasks to be processed, simulations are performed in advance using distributed chips to obtain load information such as the computation frequency and computational load of the second computing nodes when executing various tasks. When selecting a target computing node from the second computing nodes, the second computing node with a higher computation frequency and / or higher computational load is preferred as the target computing node.

[0089] It should be noted that the above load information is only an example, and other information that can characterize the processing load of the second computing node is also within the protection scope of this disclosure.

[0090] After the target computing node is selected, in step S202, the contents of the storage resources corresponding to the target computing node can be copied to the storage resources of the first computing node to realize the utilization of the first computing node and its storage resources and reduce resource waste.

[0091] It should be noted that there is a correspondence between the target computing node and the first computing node. Therefore, during the content copying process, the content copying operation needs to be performed based on this correspondence.

[0092] In some possible implementations, if within the distributed chip, the target computing node in column 1 corresponds to the first computing node in column 1, and the target computing node in column 2 corresponds to the computing node in column 2, then the contents of the storage resources of the target computing node in column 1 should be copied to the storage resources of the first computing node in column 1, and the contents of the storage resources of the target computing node in column 2 should be copied to the storage resources of the first computing node in column 2.

[0093] After copying the contents of the target computing node's storage resources to the first computing node's storage resources, the pending task can be executed in step S203.

[0094] In some possible implementations, the first and second computing nodes of the distributed chip execute the tasks to be processed. In other words, after content replication, when the distributed chip executes the tasks to be processed, it no longer relies solely on the second computing node and its storage resources. Instead, it uses the first computing node, the second computing node, and the storage resources of each computing node to jointly execute the tasks to be processed. This allows for full utilization of the computing nodes and storage resources within the distributed chip, improving effective computing power and correspondingly enhancing the task processing capability of the distributed chip.

[0095] It should be noted that the task to be processed includes any one of image processing tasks, voice processing tasks, text processing tasks, video processing tasks, and blockchain computing tasks. This embodiment of the disclosure does not limit the type and content of the task to be processed.

[0096] It should also be noted that the task processing method based on a distributed chip provided in this disclosure can be executed by a controller, which can be either an on-chip controller or an off-chip controller. This disclosure does not impose any restrictions on this.

[0097] Figure 4 This is a schematic diagram of a distributed chip provided in an embodiment of this disclosure. (Refer to...) Figure 4 The distributed chip consists of four cascaded smaller distributed chips, from the first to the fourth chip. The second computing node is represented by a black circle, and the first computing node by a white circle. Therefore, all computing nodes on the first and second chips are occupied, while only the first column of computing nodes on the third and fourth chips is occupied, with the remaining three columns unoccupied. Based on this, the fixed direction of the target computing node can be determined as a column vector.

[0098] In this distributed chip, the first computing node occupies columns 6 to 8, therefore, the target number of columns is determined to be 3. The second computing node occupies columns 1 to 5, and since the target number of columns is 3, the column interval can be determined to be 1. That is, by sparsely and evenly selecting 3 columns of second computing nodes from columns 1 to 5 as target computing nodes with an interval of 1 column (i.e., m2 = m1 = 3). Therefore, the second computing nodes in columns 1, 3, and 5 are selected as target computing nodes, and the second computing node in column 1 corresponds to the first computing node in column 6, the second computing node in column 3 corresponds to the first computing node in column 7, and the second computing node in column 5 corresponds to the first computing node in column 8.

[0099] After determining the target compute node, the contents of the storage resources of the second compute node in column 1 are copied to the storage resources of the first compute node in column 6. Specifically, the contents of the storage resources of node 56 are copied to the storage resources of node 61, the contents of the storage resources of node 48 are copied to the storage resources of node 53, the contents of the storage resources of node 40 are copied to the storage resources of node 45, and so on, until the contents of the storage resources of node 0 are copied to the storage resources of node 5. The copying operations between the second compute node in column 3 and the first compute node in column 7, and between the second compute node in column 5 and the first compute node in column 7, are similar and will not be described again here.

[0100] Through the above operations, the distributed chip is... Figure 4 The chip shown is transformed into... Figure 5 The chip shown. Figure 5 This is a schematic diagram illustrating the processing of a distributed chip according to an embodiment of this disclosure. Figure 5 In the middle, node 56′ corresponds to Figure 4Node 61 in the distributed chip shown is obtained by copying the contents of node 56's storage resources to node 61's storage resources, thus transforming an unused computing node into an occupied computing node, and its storage resources are also utilized. Nodes 58', 60', etc., are similar and will not be described again here. Figure 5 In this distributed chip, all computing nodes are occupied and corresponding storage resources are utilized, making full use of both computing nodes and storage resources. Moreover, by using a sparse and uniform approach to determine the target computing node, the average number of hops between computing nodes can be reduced, thereby improving the effective computing power of the distributed chip.

[0101] It should be noted that if several consecutive rows or columns of second computing nodes are directly selected as target computing nodes, although the number of computing nodes and the amount of storage resources are increased, the average number of hops between computing nodes also increases accordingly, which may result in no improvement in effective computing power. Moreover, in some possible implementations, the above operation may also lead to a more significant disparity in the aspect ratio of computing nodes participating in task processing within the distributed chip, exacerbating narrow-edge congestion and severely affecting the utilization efficiency of computing power. Therefore, it is not suitable to process distributed chips by directly selecting several consecutive rows or columns of second computing nodes as target computing nodes. According to the method provided in the embodiments of this disclosure, a sparse and uniform method is used to select target computing nodes, which can reduce the increase in the average number of hops while increasing the number of computing nodes and storage resources, thereby improving the effective computing power of the distributed chip.

[0102] In some possible implementations, after determining that the target number of columns is 3, two second computation nodes can be selected from columns 1 to 5 as the target computation nodes (i.e., m1 = 3 and m2 = 2).

[0103] For example, the second computing nodes in columns 2 and 4 are selected as target computing nodes, and the second computing node in column 2 corresponds to the first computing node in column 6, the second computing node in column 4 corresponds to the first computing node in column 7, and the first computing node in column 8 is still in an unoccupied state.

[0104] After determining the target compute node, the contents of the storage resources of the second compute node in column 2 are copied to the storage resources of the first compute node in column 6. Specifically, the contents of the storage resources of node 57 are copied to the storage resources of node 61, the contents of the storage resources of node 49 are copied to the storage resources of node 53, the contents of the storage resources of node 41 are copied to the storage resources of node 45, and so on. The contents of the storage resources of node 1 are copied to the storage resources of node 5. The copying operation between the second compute node in column 4 and the first compute node in column 7 is similar and will not be described again here.

[0105] Through the above operations, the distributed chip is... Figure 4 The chip shown is transformed into... Figure 6 The chip shown.

[0106] Figure 6 This is a schematic diagram illustrating the processing of a distributed chip according to an embodiment of this disclosure. Figure 6 In the middle, node 57′ corresponds to Figure 4 Node 61 in the distributed chip shown is obtained by copying the contents of the storage resources of node 57 to the storage resources of node 61, thus transforming an unused computing node into an occupied computing node, and its storage resources are also utilized. Nodes 49', 41', etc. are similar and will not be described again here.

[0107] It should be noted that the case where m2 equals 1 is similar to the above, and will not be described in detail here.

[0108] It should also be noted that in the above description, the region shape of the first / second computing node is a regular rectangle. However, in some possible implementations, if the computing nodes within the distributed chip are not occupied in whole rows or columns, the region shape of the first / second computing node may be irregular. For irregular region shapes, the target computing node cannot be selected directly using the above method. Instead, it is necessary to divide the irregular region shape into multiple regular rectangular regions through region partitioning before selecting the target computing node.

[0109] In some possible implementations, before step S201, the task processing method according to the embodiments of this disclosure may further include: determining the region shape of the first computing node based on the node occupancy information of the distributed chip; and dividing the region of the first computing node into at least two rectangular regions if the region shape is not rectangular.

[0110] In one example, the node occupancy information of the distributed chip includes the row and column distribution information of the first computing node and the row and column distribution information of the second computing node. Based on the above information, the region shape of the first computing node can be determined relatively accurately and conveniently.

[0111] After dividing the irregular area corresponding to the first computing node into multiple regular rectangular areas, in some possible implementations, step S201 may include: first, determining the fixed direction of the target computing node in each rectangular area according to the row and column distribution information of the first computing node in each rectangular area; second, determining the target computing node corresponding to each rectangular area in sequence according to the fixed direction, the row and column distribution information of the first computing node and the row and column distribution information of the second computing node.

[0112] In some possible implementations, the target computing nodes corresponding to each rectangular region are determined sequentially based on a fixed direction, the row and column distribution information of the first computing node, and the row and column distribution information of the second computing node, including:

[0113] First, based on the fixed orientation of the first computing node within the first rectangular region, the row and column distribution information of the first computing node within the first rectangular region, and the row and column distribution information of the second computing node, a target computing node corresponding to the first rectangular region is selected from the second computing nodes. Second, based on the fixed orientation of the first computing node within the k-th rectangular region, the row and column distribution information of the first computing node within the k-th rectangular region, the distribution information of the target nodes within the first k-1 rectangular regions, and the row and column distribution information of the second computing node, a target computing node corresponding to the k-th rectangular region is selected from the second computing nodes and the target computing nodes corresponding to the first k-1 rectangular regions, where k is an integer greater than or equal to 2.

[0114] Figure 7 This is a schematic diagram of a distributed chip provided in an embodiment of this disclosure. (Refer to...) Figure 7 The distributed chip consists of four small distributed chips cascaded together, from the first chip to the fourth chip. The second computing node is represented by a black circle, and the first computing node is represented by a white circle. Figure 7 It can be seen that in this distributed chip, all computing nodes of the first chip are occupied; the computing nodes in the first and second rows of the second chip are occupied, while those in the third and fourth rows are not; the computing nodes in the first column of the third chip are occupied, while those in the remaining three columns are not; and the first two computing nodes in the first column of the fourth chip are occupied, while those in the remaining columns are not. Based on this, it can be determined that the region of the first computing node is shaped like an "L" rotated 90 degrees counterclockwise, which is not a regular rectangle. Therefore, the region of the first computing node needs to be divided into at least two rectangular regions.

[0115] Figure 8 This is a schematic diagram illustrating a region division according to an embodiment of this disclosure. (Refer to...) Figure 8 It divides the region of the first computing node into two rectangular regions, with the distribution of the first computing node in the two rectangular regions being 2*8 and 6*3, respectively.

[0116] For a 6*3 rectangular region, with its fixed direction being the column direction and the number of columns in this rectangular region being 3, the target number of columns is determined to be 3. Since the second computing node has 5 columns and the target number of columns is 3, the node column interval is determined to be 1. Based on this, the second computing nodes in columns 1, 3, and 5 are selected as the target computing nodes corresponding to columns 1, 2, and 3 in the 6*3 rectangular region, respectively. The resulting distributed chip... Figure 9 As shown.

[0117] Figure 9 This is a schematic diagram illustrating the processing of a distributed chip according to an embodiment of this disclosure. Figure 9 Within the distributed chip shown, the first computing node within the 6*3 rectangular area has been assigned a corresponding target computing node (for example, the first computing node 56' corresponds to...). Figure 6 Node 61 in the equation has a target computation node of node 56. Only the first computation node within the 2*8 rectangular area has not yet had its corresponding target computation node determined.

[0118] For a 2*8 rectangular region, with a fixed direction of rows and 2 rows, the target number of rows is determined to be 2. Since the new rectangular region formed by the second computing node and the 6*3 rectangular region has 6 rows of computing nodes, and the target number of rows is 2, the node row spacing is determined to be 2. Based on this, the computing nodes in the 1st and 4th rows of the new rectangular region are selected as the target computing nodes in the 1st and 2nd rows of the 2*8 rectangular region, respectively. The resulting distributed chip is as follows: Figure 10 As shown.

[0119] Figure 10 This is a schematic diagram illustrating the processing of a distributed chip according to an embodiment of this disclosure. Figure 10 In this process, all first computing nodes within the distributed chip are assigned corresponding target computing nodes. Taking node 56″ and node 56~ as examples: node 56″ corresponds to... Figure 7 Node 8 in the equation has a target computation node of node 56; node 56 corresponds to... Figure 7 Node 13 in the diagram has its target computing node as node 56'. Other nodes are similar to nodes 56″ and 56~, and will not be described again here. After the contents of the target computing node's storage resources are copied to each of the first computing nodes, all computing nodes within the distributed chip are in a state of occupancy, and the corresponding storage resources are utilized. When executing tasks, the distributed chip processes data based on all computing nodes and the storage resources within those nodes, thus improving task execution capabilities.

[0120] In some possible implementations, in obtaining Figure 8Following the distributed chip diagram, considering that nodes 56, 48, and 40 have already undergone redundant storage, there is no need to perform redundant storage again for nodes 56' and 48' in the remaining 2*8 rectangular area. Based on this, we can obtain... Figure 11 The distributed chip shown.

[0121] Figure 11 This is a schematic diagram illustrating the processing of a distributed chip according to an embodiment of this disclosure. (Refer to...) Figure 11 Since nodes 56′, 48′, etc. are no longer redundantly stored, nodes 13, 14, 15, 5, 6 and 7 are in an unoccupied state.

[0122] In some possible implementations, the region of the second computing node may be an irregular region. In this case, a similar approach can be used to configure node redundancy.

[0123] It should be noted that the above method for dividing the region of the first computing node is merely an example, and this disclosure does not limit its scope. In some possible implementations, the region of the first computing node can also be divided into two other rectangular regions, that is... Figure 6 The rightmost three columns and eight rows of the first computing nodes within the distributed chip are divided into a first rectangular region, with the first computing nodes distributed in an 8*3 pattern. The remaining two rows and five columns of the first computing nodes at the bottom of the distributed chip are divided into a second rectangular region, with the first computing nodes distributed in a 2*5 pattern. Accordingly, based on these two rectangular regions, the target computing nodes are determined using the method described above. After copying the contents of the target computing node's storage resources to the storage resources of the first computing nodes, the distributed chip can execute the task to be processed based on the first and second computing nodes.

[0124] In some possible implementations, when the region of the first computation node is an irregular region of other shapes, the region can be divided into two or more rectangular regions. Target computation nodes are then selected for each rectangular region, and their content is copied. The specific processing method is similar to that described above and will not be repeated here.

[0125] Figure 12 This is a block diagram of a task processing device based on a distributed chip, provided as an embodiment of this disclosure. (Refer to...) Figure 12 The task processing device includes:

[0126] The determination module 1201 is used to determine the first unoccupied computing node and the second occupied computing node based on the node occupancy information of the distributed chip.

[0127] Node occupancy information is used to characterize the occupancy status of computing nodes within a distributed chip.

[0128] The selection module 1202 is used to select a target computing node from the second computing nodes.

[0129] The copy module 1203 is used to copy the contents of the storage resources corresponding to the target computing node to the storage resources of the first computing node.

[0130] The execution module 1204 is used to execute the task to be processed based on the first computing node and the second computing node.

[0131] In some possible implementations, the node occupancy information includes the number of first computing nodes and second computing nodes, and the number of target computing nodes is less than or equal to the number of first computing nodes; the determination module 1201 is used to select the target computing node from the second computing nodes based on the number information.

[0132] In some possible implementations, the node occupancy information includes the location information of the first computing node and the second computing node; the determination module 1201 is used to select a computing node from the second computing nodes based on the location information.

[0133] Correspondingly, the copy module 1203 is used to copy the contents of the storage resources corresponding to the target computing node to the storage resources of the first computing node at random locations based on the location information.

[0134] In some possible implementations, the node occupancy information includes the row and column distribution information of the first computing node and the row and column distribution information of the second computing node. Correspondingly, the selection module 1202 includes a first direction determination unit and a first node selection unit. The first direction determination unit is used to determine a fixed direction of the target computing node based on the row and column distribution information of the first computing node, whereby the fixed direction may be a row direction or a column direction. The first node selection unit is used to select the target computing node from the second computing nodes based on the row and column distribution information of the first computing node, the row and column distribution information of the second computing node, and the fixed direction of the target computing node.

[0135] In some possible implementations, the node selection unit further includes a target row number determination unit and a first selection execution unit. The target row number determination unit is used to determine the target row number n1 based on the row and column distribution information of the first computing node, with the fixed direction being the row direction. The first selection execution unit is used to select n2 rows of the second computing node as the target computing node based on the row and column distribution information of the second computing node and the target row number n1, where n1 and n2 are both integers greater than or equal to 1, and n2 ≤ n1.

[0136] In some possible implementations, the first selection execution unit further includes a first interval determination subunit and a first execution subunit. The first interval determination subunit is used to determine the node row interval based on the row and column distribution information of the second computing node and the target row number n1; the first execution subunit is used to select n2 rows of the second computing node as the target computing node based on the node row interval.

[0137] In some possible implementations, the node selection unit further includes a target column number determination unit and a second selection execution unit. The target column number determination unit is used to determine the target column number m1 based on the row and column distribution information of the first computing node when the fixed direction is the column direction; the second selection execution unit is used to select m2 columns of the second computing node as the target computing node based on the row and column distribution information of the second computing node and the target column number m1, where m1 and m2 are both integers greater than or equal to 1, and m2 ≤ m1.

[0138] In some possible implementations, the second selection execution unit further includes: a second interval determination subunit and a second execution subunit. The second interval determination subunit is used to determine the node column interval based on the row and column distribution information of the second computing nodes and the target column number m1; the second execution subunit is used to select m2 columns of the second computing nodes as the target computing nodes based on the node column interval.

[0139] In some possible implementations, the task processing device further includes a shape determination module and a region partitioning module. The shape determination module is used to determine the region shape of the first computing node based on the node occupancy information of the distributed chip; the region partitioning module is used to divide the region of the first computing node into at least two rectangular regions if the region shape is not rectangular.

[0140] In some possible implementations, after the region partitioning module divides the region of the first computing node into at least two rectangular regions, the selection module includes: a second direction determination unit and a second node selection unit. The second direction determination unit is used to determine the fixed direction of the target computing node in each rectangular region based on the row and column distribution information of the first computing node within each rectangular region. The second node selection unit is used to sequentially determine the target computing node corresponding to each rectangular region based on the fixed direction, the row and column distribution information of the first computing node, and the row and column distribution information of the second computing node.

[0141] In some possible implementations, the second node selection unit is used to: select a target computing node corresponding to the first rectangular region from the second computing nodes based on the fixed direction of the first computing node in the first rectangular region, the row and column distribution information of the first computing node in the first rectangular region, and the row and column distribution information of the second computing node; and select a target computing node corresponding to the k-th rectangular region from the second computing nodes and the target computing nodes corresponding to the first k-1 rectangular regions based on the fixed direction of the first computing node in the k-th rectangular region, the row and column distribution information of the first computing node in the k-th rectangular region, the distribution information of the target nodes in the first k-1 rectangular regions, and the row and column distribution information of the second computing nodes, where k is an integer greater than or equal to 2.

[0142] In some possible implementations, the task to be processed includes any one of image processing, speech processing, text processing, and video processing tasks, and this disclosure does not limit this to any particular type.

[0143] Figure 13 This is a block diagram of an electronic device provided in an embodiment of the present disclosure.

[0144] Reference Figure 13 This disclosure provides an electronic device, which includes: at least one processor 1301; and a memory 1302 communicatively connected to at least one processor 1301; wherein the memory 1302 stores one or more computer programs that can be executed by at least one processor 1301, and the one or more computer programs are executed by at least one processor 1301 to enable at least one processor 1301 to perform the above-described task processing method.

[0145] In some embodiments, the electronic device may be a neuromorphic chip and / or a neural network chip, and may employ a vectorized computation method, requiring the loading of parameters such as weight information of the neural network model via external memory, such as Double Data Rate (DDR) synchronous dynamic random access memory. Therefore, the batch processing method used in the embodiments of this disclosure has high computational efficiency.

[0146] Furthermore, this disclosure also provides a computer-readable medium having a computer program stored thereon, wherein the computer program, when executed by a processor / processor core, implements the above-described task processing method.

[0147] It will be understood by those skilled in the art that all or some of the steps, systems, or apparatuses disclosed above, and their functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software may be distributed on a computer-readable medium, which may include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0148] Example embodiments have been disclosed herein, and while specific terminology has been used, it is for illustrative purposes only and should be construed as such, and is not intended to be limiting. In some instances, it will be apparent to those skilled in the art that features, characteristics, and / or elements described in connection with particular embodiments may be used alone, or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless otherwise expressly indicated. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the scope of this disclosure as set forth by the appended claims.

Claims

1. A task processing method, characterized in that, The distributed chip is configured with multiple computing nodes distributed in an array, and each computing node is allocated corresponding storage resources. The method includes: Based on the node occupancy information of the distributed chip, determine the first unoccupied computing node and the second occupied computing node; Based on a sparse and uniform approach, a target computing node is selected from the second computing node according to at least one of location information, quantity information, and load information, and the content in the storage resources corresponding to the target computing node is copied to the storage resources of the first computing node. The task to be processed is executed based on the first computing node and the second computing node.

2. The task processing method according to claim 1, wherein, The node occupancy information includes the number of the first computing node and the second computing node, and the number of the target computing nodes is less than or equal to the number of the first computing nodes; Selecting a target computing node from the second computing nodes includes: Based on the quantity information, the target computing node is selected from the second computing nodes.

3. The task processing method according to claim 1, wherein, The node occupancy information includes the location information of the first computing node and the second computing node; Selecting a target computing node from the second computing nodes includes: Based on the location information, the target computing node is selected from the second computing nodes.

4. The task processing method according to claim 3, wherein, The step of copying the contents of the storage resources corresponding to the target computing node to the storage resources of the first computing node includes: Based on the location information, the contents of the storage resources corresponding to the target computing node are copied to the storage resources of the first computing node at random locations.

5. The task processing method according to claim 3, wherein, The location information includes the row and column distribution information of the first computing node and the second computing node; Selecting a target computing node from the second computing nodes includes: Based on the row and column distribution information, the target computing node is selected from the second computing nodes.

6. The task processing method according to claim 5, wherein, The step of copying the contents of the storage resources corresponding to the target computing node to the storage resources of the first computing node includes: Based on the row and column distribution information, the content in the storage resource corresponding to the target computing node is copied to the storage resource of the first computing node in a fixed direction.

7. The task processing method according to claim 6, wherein, The fixed direction includes the row direction and / or the column direction; The step of copying the content from the storage resource corresponding to the target computing node to the storage resource of the first computing node in a fixed direction according to the row and column distribution information includes: The contents of the storage resources corresponding to the target computing node are copied to the unoccupied storage resources of the first computing node in the row and / or column directions.

8. The task processing method according to claim 7, wherein, The fixed direction is the row direction, and the target number of rows is determined to be n1 based on the row and column distribution information of the first calculation node; The selection of the target computing node includes: selecting the second computing node in row n2 as the target computing node based on the row and column distribution information of the second computing node and the target row number n1, where n2≤n1.

9. The task processing method according to claim 8, wherein, The step of selecting the second computing node in row n2 as the target computing node based on the row and column distribution information of the second computing node and the target row number n1 includes: The node row interval is determined based on the row and column distribution information of the second calculation node and the target row number n1; Based on the node row interval, the second computing node in row n2 is selected as the target computing node.

10. The task processing method according to claim 7, wherein, The fixed direction is the column direction, and the target number of columns is determined as m1 based on the row and column distribution information of the first calculation node; The selection of the target computing node includes: selecting the second computing node in column m2 as the target computing node based on the row and column distribution information of the second computing node and the target column number m1, where m2≤m1.

11. The task processing method according to claim 10, wherein, The step of selecting the second computing node with column m2 as the target computing node based on the row and column distribution information of the second computing node and the target column number m1 includes: The node column interval is determined based on the row and column distribution information of the second calculation node and the target column number m1; Based on the node column interval, the second calculation node in column m2 is selected as the target calculation node.

12. The task processing method according to claim 1, wherein, Before selecting a target computing node from the second computing nodes occupied by the distributed chip based on the node occupancy information of the distributed chip, the method further includes: The region shape of the first computing node is determined based on the node occupancy information of the distributed chip; If the shape of the region is not rectangular, the region of the first computing node is divided into at least two rectangular regions.

13. The task processing method according to claim 12, wherein, The step of selecting a target computing node from the second computing nodes occupied by the distributed chip based on the node occupancy information of the distributed chip includes: Based on the row and column distribution information of the first computing node in each rectangular region, the fixed direction of the target computing node in each rectangular region is determined respectively; Based on the fixed direction, the row and column distribution information of the first computing node, and the row and column distribution information of the second computing node, the target computing nodes corresponding to each rectangular region are determined sequentially.

14. The task processing method according to claim 1, wherein, The step of selecting a target computing node from the second computing nodes occupied by the distributed chip includes: Based on the load information of the second computing node, the target computing node is selected from the second computing nodes; The load information includes at least the calculation frequency and the amount of calculation.

15. The task processing method according to claim 1, wherein, The distributed chip includes a single chip or a distributed chip formed by cascading multiple chips.

16. The task processing method according to any one of claims 1-15, wherein, The task to be processed includes any one of image processing, speech processing, text processing, and video processing tasks.

17. A task processing device, characterized in that, The distributed chip is configured with multiple computing nodes distributed in an array, and each computing node is allocated corresponding storage resources. The device includes: The determination module is used to determine the first unoccupied computing node and the second occupied computing node based on the node occupancy information of the distributed chip; The selection module is used to select a target computing node from the second computing nodes based on at least one of location information, quantity information, and load information in a sparse and uniform manner. The copying module is used to copy the contents of the storage resources corresponding to the target computing node to the storage resources of the first computing node; An execution module is used to execute tasks to be processed based on the first computing node and the second computing node.

18. A distributed chip, characterized in that: The distributed chip is equipped with multiple computing nodes distributed in an array, and each computing node is allocated corresponding storage resources. The computing nodes include an unoccupied first computing node and an occupied second computing node. The second computing node includes a target computing node, which is a second computing node whose storage resources are connected to the storage resources of the first computing node. The distributed chip is used to execute the task processing method as described in any one of claims 1-16.

19. An electronic device comprising: At least one processor; as well as A memory communicatively connected to the at least one processor; wherein, The memory stores one or more computer programs that can be executed by the at least one processor, the one or more computer programs being executed by the at least one processor to enable the at least one processor to perform the task processing method as described in any one of claims 1-16.

20. A computer-readable medium having a computer program stored thereon, wherein, When the computer program is executed by a processor, it implements the task processing method as described in any one of claims 1-16.

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