A method, apparatus, and medium for signal quality assessment

Abstract

The application discloses a signal quality evaluation method, device and medium, and is applied to the technical field of communication. The method is used for quality testing of PCIE signals interconnected between on-board chips. When starting testing, a CPU sends a test signal to a PCIe device; then, the test signal returned by the PCIe device is received, and the critical values of the eye height and the eye width of the test signal are determined according to the sent and returned test signals; finally, the eye height and the eye width of the test signal are determined according to the critical values of the eye height and the eye width of the test signal, so that the quality of the test signal is obtained. The traditional oscilloscope point testing method is not accurate enough. The method provided by the application improves the above-mentioned defects, tests the signal quality in the chip, and finally obtains the eye diagram through the test signal, so that the test result is more accurate.

Description

Technical Field

[0001] This application relates to the field of communication technology, and in particular to a method, apparatus and medium for signal quality assessment. Background Technology

[0002] The current server platform's high-speed serial computer expansion bus standard (Peripheral Component Interconnect Express, PCIe) signal bus has reached up to PCIe Gen5 (speed 32Gbps), and is generally backward compatible with PCIe Gen4 (speed 16Gbps), PCIe Gen3 (speed 8Gbps), PCIe Gen2 (speed 5Gbps), and PCIe Gen1 (speed 2.5Gbps). Figure 1 This is a schematic diagram of a traditional hardware point testing scheme; such as Figure 1 As shown, currently, for PCIe signals interconnected within the board, since there is no external interface, it is impossible to use a PCIe test fixture to test signal quality. Therefore, an oscilloscope probe is used for testing. The probe is connected to a solder joint near the signal receiving end, close to the via at the end of the chip, to test the oscilloscope signal. The signal under test is the PCIe signal between the Central Processing Unit (CPU) and the PCIe Device Chip A chip. The test point is in the signal transmission direction (arrow direction), and the test point is the via closest to the CPU and PCIe Device Chip A ends. A high-speed probe is used to measure the signal at the test point, and the waveform is tested on an oscilloscope to reconstruct the signal eye diagram.

[0003] However, for the signal at the test point, the impedance of the oscilloscope probe itself is on the order of tens of kilohms, which causes a certain amount of current shunting to the signal. Therefore, it also affects the signal itself, and the higher the signal rate, the greater this effect, leading to inaccurate testing.

[0004] Therefore, ensuring the accuracy of PCIe signal quality testing within server boards is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] The purpose of this application is to provide a method, apparatus, and medium for signal quality assessment to ensure the accuracy of PCIe signal quality testing within server boards.

[0006] To address the aforementioned technical problems, this application provides a method for signal quality assessment, comprising:

[0007] A test signal is sent to the PCIe Device; wherein the PCIe Device is pre-configured to loopback mode, and the PCIe Device in loopback mode returns the received test signal to the CPU;

[0008] Receive the test signal returned by the PCIe Device;

[0009] The critical values ​​for eye height and eye width of the test signal are determined based on the transmitted test signal and the returned test signal.

[0010] The eye height and eye width of the test signal are determined based on the critical values ​​of the eye height and the eye width of the test signal to obtain the quality of the test signal.

[0011] Preferably, determining the critical values ​​for the eye height and eye width of the test signal based on the transmitted and returned test signals includes:

[0012] The sent test signal is compared with the returned test signal;

[0013] If the initial comparison result indicates that the bit error rate between the sent test signal and the returned test signal is not greater than the bit error rate threshold, then the eye height and eye width of the test signal are increased and the step of comparing the sent test signal with the returned test signal is returned until the comparison result indicates that the bit error rate between the sent test signal and the returned test signal is greater than the bit error rate threshold.

[0014] If the initial comparison result indicates that the bit error rate between the sent test signal and the returned test signal is greater than the bit error rate threshold, then the eye height and eye width of the test signal are reduced and the process of comparing the sent test signal with the returned test signal is returned until the comparison result indicates that the bit error rate between the sent test signal and the returned test signal is not greater than the bit error rate threshold.

[0015] The critical values ​​for eye height and eye width of the test signal are determined based on the current test signal.

[0016] Preferably, sending the test signal to the PCIe Device includes:

[0017] Send the test signal with a random code pattern to the PCIe Device.

[0018] Preferably, after determining the eye height and eye width of the test signal based on the critical values ​​of the eye height and the critical values ​​of the eye width of the test signal to obtain the quality of the test signal, the method further includes:

[0019] If the eye height and / or eye width of the test signal do not meet the preset test standards, then the test signal is optimized.

[0020] Preferably, if the eye height and / or eye width of the test signal do not meet the preset test standards, optimizing the test signal includes:

[0021] If the eye height and / or eye width of the test signal do not meet the preset test standard, the test signal is optimized by adjusting the TXEQ and CTLE of the CPU and the TXEQ and CTLE of the PCIe Device.

[0022] Preferably, obtaining the test standard includes:

[0023] Obtain the eye height and eye width of multiple normally functioning PCIe Devices;

[0024] Determine the average eye height and average eye width for multiple eye heights and eye widths;

[0025] The test criteria are determined based on the average eye height and the average eye width.

[0026] Preferably, in the loopback mode, the PCIe Device returns the test signal to the CPU without processing.

[0027] To address the aforementioned technical problems, this application also provides a signal quality assessment apparatus, comprising:

[0028] A sending module is used to send test signals to a PCIe Device; wherein the PCIe Device is pre-configured to loopback mode, and in loopback mode the PCIe Device returns the received test signals to the CPU;

[0029] A receiving module is used to receive the test signal returned by the PCIe Device;

[0030] The first determining module is used to determine the critical value of the eye height and the critical value of the eye width of the test signal based on the sent test signal and the returned test signal.

[0031] The second determining module is used to determine the eye height and eye width of the test signal based on the critical value of the eye height and the critical value of the eye width of the test signal to obtain the quality of the test signal.

[0032] Preferably, the signal quality assessment device further includes an optimization module, configured to optimize the test signal if the eye height and / or eye width of the test signal do not meet a preset test standard after determining the eye height and eye width of the test signal according to the critical value of the eye height and the critical value of the eye width of the test signal to obtain the quality of the test signal.

[0033] To address the aforementioned technical problems, this application also provides a signal quality assessment apparatus, comprising: a memory for storing a computer program;

[0034] A processor, used to implement the above-described method for signal quality assessment when executing a computer program.

[0035] To address the aforementioned technical problems, this application also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of the above-described signal quality assessment method.

[0036] This application provides a signal quality assessment method for testing the quality of PCIe signals interconnected between chips on a board. First, the PCIe Device is pre-set to loopback mode, where it returns received test signals to the CPU. At the start of the test, the CPU enters test mode to send test signals to the PCIe Device; then, it receives the returned test signals and determines the critical values ​​for eye height and eye width of the test signals based on the sent and returned signals. Finally, the eye height and eye width of the test signals are determined based on these critical values ​​to obtain the quality of the test signals. Traditional oscilloscope spot testing methods for signal quality between the CPU and PCIe Device cannot pinpoint the final signal point, resulting in inaccurate testing. Furthermore, the influence of probe impedance on the signal itself also affects the spot test signal, leading to inaccurate results. Additionally, human error at the contact points during spot testing can also cause inaccurate results. The method provided in this application improves upon the aforementioned shortcomings by testing signal quality inside the chip and obtaining the final eye diagram from the test signal, resulting in more accurate test results.

[0037] This application also provides a signal quality assessment apparatus and a computer-readable storage medium, which correspond to the above-described method and thus have the same beneficial effects as the above-described method. Attached Figure Description

[0038] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0039] Figure 1 This is a schematic diagram of a traditional hardware point measurement scheme;

[0040] Figure 2 A flowchart illustrating a signal quality assessment method provided in this application embodiment;

[0041] Figure 3 This is a schematic diagram of a test scheme provided in an embodiment of this application;

[0042] Figure 4 An eye diagram obtained by the signal quality assessment method provided in the embodiments of this application;

[0043] Figure 5 A flowchart for testing and optimizing signals is provided as an embodiment of this application;

[0044] Figure 6 A structural diagram of the signal quality assessment apparatus provided in the embodiments of this application;

[0045] Figure 7 A structural diagram of a signal quality assessment apparatus provided in another embodiment of this application. Detailed Implementation

[0046] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0047] The core of this application is to provide a method, apparatus, and medium for signal quality assessment to ensure the accuracy of PCIe signal quality testing within server boards.

[0048] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0049] Traditional signal testing methods can barely test waveforms and recover eye diagrams for lower signal transmission rates, such as PCIe Gen1 2.5Gbps or even PCIe Gen2 5Gbps. However, as the rate increases to PCIe Gen3 8Gbps, and if the receiver signal requires Rx CTLE equalization to recover the signal and eye diagram, the limitations of this testing method become more apparent. First, the oscilloscope probe's impedance at the test point is on the order of tens of kilohms, which causes a certain amount of current shunting to the signal, thus affecting the signal itself. The higher the signal rate, the greater this effect, leading to inaccurate measurements. Second, when using probes for point testing, human factors such as testing techniques or improper test point selection can cause the results to vary by tens of mV each time, resulting in inconsistent results and inaccurate measurements. Finally, the oscilloscope and probe need to have sufficiently high bandwidth (higher bandwidth oscilloscopes and probes are more expensive) to meet the requirements of point testing. Furthermore, the oscilloscope needs to support Rx CTLE equalization technology to perform spot measurements and recover the signal eye diagram. Also, the Continuous Time Linear Equalization (CTLE) used by the oscilloscope is not consistent with the CTLE parameters used internally by the chip, meaning the measured signal will differ from the actual signal, and complete accuracy cannot be guaranteed. CTLE is the equalization at the receiver (Rx), while TXEQ is the equalization at the transmitter (Tx).

[0050] To address the aforementioned issues and overcome the limitations of hardware testing, this application proposes a scheme for testing PCIe signal eye diagrams within the chip. This scheme utilizes an internal algorithm to test the final stage of signal transmission. The scheme simulates data transmission between the CPU and the PCIe Device under actual operating conditions by sending a randomly patterned test signal between them. It also controls the CPU to enter test mode and the PCIe Device to enter loopback mode. In loopback mode, the PCIe Device returns the received test signal to the CPU. Figure 2 A flowchart illustrating a signal quality assessment method provided in this application embodiment; as shown Figure 2 As shown, the method includes the following steps:

[0051] S10: Send a test signal to the PCIe Device.

[0052] S11: Receive the test signal returned by the PCIe Device.

[0053] S12: Determine the critical values ​​for eye height and eye width of the test signal based on the sent and returned test signals.

[0054] S13: Determine the eye height and eye width of the test signal based on the critical values ​​of the eye height and eye width of the test signal to obtain the quality of the test signal.

[0055] Figure 3 This is a schematic diagram of a test scheme provided in an embodiment of this application; as shown below. Figure 3 As shown, the CPU enters test mode and sends a test signal with a random pattern to simulate a real operating scenario. The PCIe Device (i.e., PCIe DeviceChip A chip) enters loopback mode and sends the received pattern signal back to the CPU. The CPU fixes its own TXEQ and CTLE to test the signal eye diagram quality under the current TXEQ and CTLE. By increasing or decreasing the eye height (EyeVoltage) and timing (Timing, i.e., eye width) of the transmitted data, the critical values ​​on the x-axis (Timing) and y-axis (Eye Voltage) of the data transmission can be found, thereby measuring the eye diagram and margin of the high-speed data signal and evaluating the signal quality.

[0056] The method for finding the critical value is as follows: the code signal sequence sent by the CPU is known and definite. After receiving the code signal sequence returned by the PCIeDevice, it is compared with the known code signal sequence sent by the CPU. Generally, it is set that no error occurs in the initial test signal. When an error occurs, it is considered that the critical value has been found. Specifically, when the bit error rate (BER) is greater than the bit error rate threshold, it is considered that an error has occurred. The bit error rate threshold can be set to 10e-12. Figure 4 An eye diagram obtained by the signal quality assessment method provided in the embodiments of this application; such as Figure 4As shown, the x-axis represents eye width, and the y-axis represents eye height. The critical points are the boundary values ​​under the current Timing and Eye Voltage combinations. The thickened part of the coordinate axis outside the boundary values ​​represents the failed portion. Eye diagram calculation: Eye height = Upper critical point - Lower critical point; Eye width = Right critical point - Left critical point. Eye diagram standard settings: According to signal integrity requirements, under normal speed (no PCIe speed reduction), the larger the eye height and the larger the eye width, the better the signal quality. Based on the test results of a large number (e.g., 50 motherboards) of normally functioning PCIe devices, the average eye height and average eye width of all devices are obtained. This is used as the standard for whether the test passes and to determine whether a motherboard under test meets the standard. The signal quality optimization scheme is as follows: When the signal eye diagram is found to not meet the above standards, within certain limits, the TXEQ and CTLE of both the CPU and the PCIe device can be dynamically adjusted to adjust the recovered eye diagram and automatically find the most suitable TXEQ and CTLE combination to obtain the best signal quality.

[0057] A pseudo-random binary sequence (PRBS) is a pseudo-random sequence containing only 0s and 1s. For example... Figure 3 As shown, the CPU enters test mode via firmware (such as the BIOS). Under the current TXEQ and CTLE combination parameters, the CPU issues a test pattern (PRBS) and prepares to receive a signal at the PCIe Rx. It compares the received test signal pattern with the issued one to check for errors. The firmware also controls the PCIe Device to enter loopback default mode. After receiving the PRBS pattern at the Device's PCIe Rx, it sends it back to the CPU's Rx without processing. Upon receiving the signal, the CPU's Rx performs error calculation and dynamically adjusts Eye Voltage (Y-axis, eye height) and Timing (X-axis, eye width) to find the critical points for eye height and eye width, thus calculating the current eye height and eye width. Furthermore, it can determine whether the motherboard meets the eye height and eye width requirements using pre-set standards. If the eye height and eye width are not ideal, the signal quality can be automatically adjusted by adjusting TXEQ and CTLE to find the optimal eye height and eye width, thereby optimizing the signal quality.

[0058] Figure 5 A flowchart for testing and optimizing signals is provided as an embodiment of this application; such as Figure 5 As shown, it includes the following steps:

[0059] S20: The CPU sends a PRBS code test signal to the PCIe Device.

[0060] S21: After receiving the test signal, the PCIe Device sends it back to the CPU.

[0061] S22: The CPU determines whether the bit error rate meets the requirements; if yes, proceed to step S23; otherwise, proceed to step S24.

[0062] S23: Find the critical values ​​for eye height and eye width, and calculate eye height and eye width.

[0063] S24: Increases eye height and eye width.

[0064] S25: Determine whether the eye height and eye width meet the standards; if yes, end the process; otherwise, proceed to step S26.

[0065] S26: Adjust TXEQ and CTLE to optimize test signal quality.

[0066] In practical applications, a smaller eye height and eye width can be set first so that the initial bit error rate is less than the bit error rate threshold. Then, the eye height and eye width can be gradually increased to increase the bit error rate. When the bit error rate is greater than the threshold (i.e., the bit error rate meets the requirements), the critical value is determined and the eye height and eye width are calculated.

[0067] Traditional spot testing methods cannot pinpoint the final signal point. Furthermore, the influence of probe impedance on the signal itself can affect the measured signal. Additionally, human error at the contact point can lead to inaccurate test results. This application uses the final eye diagram after signal recovery within the chip for signal quality testing, resulting in more accurate results. It also uses PRBS coding to calculate BER (Bit Error Rate) to determine eye height and eye width, thus accurately judging whether the signal quality meets signal integrity requirements. For cases where eye height and eye width standards are not met, TXEQ and CTLE can be dynamically adjusted within a certain range to optimize signal quality. The previously used eye diagram testing method can then be used to further assess whether the standards are met.

[0068] This application embodiment calculates the eye height and eye width within the chip by performing loopback PRBS testing and BER calculation on the PCIe signal interconnecting the CPU and PCIe Device on the motherboard, thus achieving accurate eye diagram calculation. By increasing the eye height and eye width values ​​of the PCIe signal between the CPU and Device in a set step, the critical points for eye height and eye width that lead to bit errors are identified, and the current maximum eye height and eye width are determined. Furthermore, through a large number of samples, reasonable eye height and eye width standards are identified to determine whether the motherboard being tested meets the standards. For cases where standards are not met, the eye height and eye width are optimized within a certain range using TXEQ and CTLE parameters. If the standards are still not met, further optimization is required, thus completing the entire process of testing and parameter optimization. This technical solution can, in principle, be applied to CPU interconnect bus signals on all domestic platforms, such as MIPS, ARM, and x86. It should be noted that the solution provided in this embodiment is only a partial example of this application and does not limit other solutions in this application.

[0069] This application provides a signal quality assessment method for testing the quality of PCIe signals interconnected between chips on a board. First, the PCIe Device is pre-set to loopback mode, where it returns received test signals to the CPU. At the start of the test, the CPU enters test mode to send test signals to the PCIe Device; then, it receives the test signals returned by the PCIe Device and determines the critical values ​​for eye height and eye width of the test signals based on the sent and returned signals. Finally, it determines the eye height and eye width of the test signals based on these critical values ​​to obtain the quality of the test signals. Traditional oscilloscope spot testing methods for signal quality between the CPU and the PCIe Device cannot pinpoint the final point of the signal, resulting in inaccurate testing. Furthermore, the influence of probe impedance on the signal itself also affects the measured signal, leading to inaccurate test results. Additionally, human error at the contact points during spot testing can also cause inaccurate results. The method provided in this application improves upon the above-mentioned shortcomings by testing the signal quality inside the chip and obtaining the final eye diagram through the test signal, resulting in more accurate test results.

[0070] As mentioned in the above embodiments, the bit error rate (BER) can be obtained based on the transmitted and returned test signals, thereby determining the critical values ​​for eye height and eye width of the test signal. The specific implementation scheme is not limited here. This embodiment provides one such scheme, including: comparing the transmitted and returned test signals; if the initial comparison result indicates that the BER between the transmitted and returned test signals is not greater than the BER threshold, then increasing the eye height and eye width of the test signal and returning to the step of comparing the transmitted and returned test signals, until the comparison result indicates that the BER between the transmitted and returned test signals is greater than the BER threshold. If the initial comparison result indicates that the BER between the transmitted and returned test signals is greater than the BER threshold, then decreasing the eye height and eye width of the test signal and returning to the step of comparing the transmitted and returned test signals, until the comparison result indicates that the BER between the transmitted and returned test signals is not greater than the BER threshold. Finally, the critical values ​​for eye height and eye width of the test signal are determined based on the current test signal. The solution provided in this embodiment can find the critical value regardless of whether the initial comparison result indicates that the bit error rate is greater than the bit error rate threshold. In application, the critical value can also be found through other methods. For example, a smaller eye height and eye width can be set first so that the initial bit error rate is less than the bit error rate threshold. Then, the eye height and eye width can be gradually increased to increase the bit error rate. When the bit error rate is greater than the threshold (i.e., the bit error rate meets the requirements), the critical value is determined and the eye height and eye width are calculated.

[0071] In practical applications, after determining the eye height and eye width of the test signal based on the critical values ​​for eye height and eye width to obtain the test signal quality, if the eye height and / or eye width of the test signal may not meet the preset test standards, the test signal needs to be optimized. The specific optimization scheme is as follows: if the eye height and / or eye width of the test signal does not meet the preset test standards, the test signal is optimized by adjusting the CPU's TXEQ and CTLE, as well as the PCIe Device's TXEQ and CTLE. Furthermore, the steps for obtaining the test standards include: obtaining the eye height and eye width of multiple normally functioning PCIe Devices; determining the average eye height and average eye width of the multiple eye heights and widths; and then determining the test standards based on the average eye height and average eye width. The specific values ​​of the test standards are not limited.

[0072] In the above embodiments, the method for signal quality assessment has been described in detail. This application also provides embodiments corresponding to the apparatus for signal quality assessment. It should be noted that this application describes the embodiments of the apparatus from two perspectives: one based on functional modules and the other based on hardware.

[0073] From the perspective of functional modules, this embodiment provides a device for signal quality assessment. Figure 6 A structural diagram of the signal quality assessment apparatus provided in the embodiments of this application is shown below. Figure 6 As shown, the device includes:

[0074] The transmitting module 10 is used to transmit test signals to the PCIe Device; wherein the PCIe Device is pre-configured to loopback mode, and the PCIe Device in loopback mode returns the received test signals to the CPU;

[0075] The receiving module 11 is used to receive the test signal returned by the PCIe Device;

[0076] The first determining module 12 is used to determine the critical value of the eye height of the test signal and the critical value of the eye width of the test signal based on the sent test signal and the returned test signal.

[0077] The second determining module 13 is used to determine the eye height and eye width of the test signal based on the critical value of the eye height and the critical value of the eye width of the test signal in order to obtain the quality of the test signal.

[0078] Since the embodiments of the apparatus and the embodiments of the method correspond to each other, please refer to the description of the embodiments of the method for the embodiments of the apparatus, which will not be repeated here.

[0079] In a preferred embodiment, the signal quality assessment apparatus further includes an optimization module, configured to optimize the test signal if the eye height and / or eye width of the test signal do not meet a preset test standard after determining the eye height and eye width of the test signal based on the critical value of the eye height and the critical value of the eye width of the test signal to obtain the quality of the test signal.

[0080] The signal quality assessment apparatus provided in this embodiment corresponds to the method described above, and therefore has the same beneficial effects as the method described above.

[0081] From a hardware perspective, this embodiment provides another device for signal quality assessment. Figure 7 A structural diagram of a signal quality assessment apparatus provided in another embodiment of this application is shown below. Figure 7 As shown, the signal quality assessment device includes: a memory 20 for storing computer programs;

[0082] The processor 21 is configured to implement the steps of the signal quality assessment method as described in the above embodiments when executing a computer program.

[0083] The processor 21 may include one or more processing cores, such as a quad-core processor or an octa-core processor. The processor 21 may be implemented using at least one of the following hardware forms: Digital Signal Processor (DSP), Field-Programmable Gate Array (FPGA), or Programmable Logic Array (PLA). The processor 21 may also include a main processor and a coprocessor. The main processor, also known as the CPU, is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, the processor 21 may integrate a Graphics Processing Unit (GPU), which is responsible for rendering and drawing the content to be displayed on the screen. In some embodiments, the processor 21 may also include an Artificial Intelligence (AI) processor, which is used to handle computational operations related to machine learning.

[0084] The memory 20 may include one or more computer-readable storage media, which may be non-transitory. The memory 20 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices or flash memory devices. In this embodiment, the memory 20 is used to store at least the following computer program 201, which, after being loaded and executed by the processor 21, is capable of implementing the relevant steps of the signal quality assessment method disclosed in any of the foregoing embodiments. In addition, the resources stored in the memory 20 may also include an operating system 202 and data 203, and the storage method may be temporary or permanent storage. The operating system 202 may include Windows, Unix, Linux, etc. The data 203 may include, but is not limited to, data involved in the signal quality assessment method.

[0085] In some embodiments, the signal quality assessment apparatus may further include a display screen 22, an input / output interface 23, a communication interface 24, a power supply 25, and a communication bus 26.

[0086] Those skilled in the art will understand that the structure shown in the figure does not constitute a limitation on the apparatus for signal quality assessment and may include more or fewer components than shown.

[0087] The signal quality assessment apparatus provided in this application includes a memory and a processor. When the processor executes a program stored in the memory, it can implement the following method: a signal quality assessment method.

[0088] The signal quality assessment apparatus provided in this embodiment corresponds to the method described above, and therefore has the same beneficial effects as the method described above.

[0089] Finally, this application also provides an embodiment corresponding to a computer-readable storage medium. The computer-readable storage medium stores a computer program, which, when executed by a processor, implements the steps described in the above method embodiments.

[0090] It is understood that if the methods in the above embodiments are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and executes all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0091] The computer-readable storage medium provided in this embodiment corresponds to the method described above, and therefore has the same beneficial effects as the method described above.

[0092] The foregoing has provided a detailed description of a signal quality assessment method, apparatus, and medium provided in this application. The various embodiments in the specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section. It should be noted that those skilled in the art can make several improvements and modifications to this application without departing from the principles of this application, and these improvements and modifications also fall within the protection scope of the claims of this application.

[0093] It should also be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the aforementioned element.

Claims

1. A method for signal quality assessment, applied in a CPU, characterized in that, include: A test signal is sent to the PCIe Device; wherein the PCIe Device is pre-configured to loopback mode, and the PCIe Device in loopback mode returns the received test signal to the CPU; Receive the test signal returned by the PCIe Device; The critical values ​​for eye height and eye width of the test signal are determined based on the transmitted test signal and the returned test signal. The eye height and eye width of the test signal are determined based on the critical values ​​of the eye height and the critical values ​​of the eye width of the test signal to obtain the quality of the test signal; The step of determining the critical values ​​for eye height and eye width of the test signal based on the transmitted and returned test signals includes: The sent test signal is compared with the returned test signal; If the initial comparison result indicates that the bit error rate between the sent test signal and the returned test signal is not greater than the bit error rate threshold, then the eye height and eye width of the test signal are increased and the step of comparing the sent test signal with the returned test signal is returned until the comparison result indicates that the bit error rate between the sent test signal and the returned test signal is greater than the bit error rate threshold. If the initial comparison result indicates that the bit error rate between the sent test signal and the returned test signal is greater than the bit error rate threshold, then the eye height and eye width of the test signal are reduced and the process of comparing the sent test signal with the returned test signal is returned until the comparison result indicates that the bit error rate between the sent test signal and the returned test signal is not greater than the bit error rate threshold. The critical values ​​for eye height and eye width of the test signal are determined based on the current test signal.

2. The signal quality assessment method according to claim 1, characterized in that, Sending the test signal to the PCIeDevice includes: Send the test signal with a random code pattern to the PCIe Device.

3. The signal quality assessment method according to claim 1, characterized in that, After determining the eye height and eye width of the test signal based on the critical values ​​of the eye height and the critical values ​​of the eye width of the test signal to obtain the quality of the test signal, the method further includes: If the eye height and / or eye width of the test signal do not meet the preset test standards, then the test signal is optimized.

4. The signal quality assessment method according to claim 3, characterized in that, If the eye height and / or eye width of the test signal do not meet the preset test standards, then optimizing the test signal includes: If the eye height and / or eye width of the test signal do not meet the preset test standard, the test signal is optimized by adjusting the TXEQ and CTLE of the CPU and the TXEQ and CTLE of the PCIe Device.

5. The signal quality assessment method according to claim 4, characterized in that, Obtaining the test standards includes: Obtain the eye height and eye width of multiple normally functioning PCIe Devices; Determine the average eye height and average eye width for multiple eye heights and eye widths; The test criteria are determined based on the average eye height and the average eye width.

6. The signal quality assessment method according to claim 1, characterized in that, In the loopback mode, the PCIe Device returns the test signal to the CPU without processing it.

7. A signal quality assessment apparatus, applied in a CPU, characterized in that, include: A sending module is used to send test signals to a PCIe Device; wherein the PCIe Device is pre-configured to loopback mode, and in loopback mode the PCIe Device returns the received test signals to the CPU; A receiving module is used to receive the test signal returned by the PCIe Device; The first determining module is used to determine the critical value of the eye height and the critical value of the eye width of the test signal based on the sent test signal and the returned test signal. The second determining module is used to determine the eye height and eye width of the test signal based on the critical value of the eye height and the critical value of the eye width of the test signal in order to obtain the quality of the test signal. The step of determining the critical values ​​for eye height and eye width of the test signal based on the transmitted and returned test signals includes: The sent test signal is compared with the returned test signal; If the initial comparison result indicates that the bit error rate between the sent test signal and the returned test signal is not greater than the bit error rate threshold, then the eye height and eye width of the test signal are increased and the step of comparing the sent test signal with the returned test signal is returned until the comparison result indicates that the bit error rate between the sent test signal and the returned test signal is greater than the bit error rate threshold. If the initial comparison result indicates that the bit error rate between the sent test signal and the returned test signal is greater than the bit error rate threshold, then the eye height and eye width of the test signal are reduced and the process of comparing the sent test signal with the returned test signal is returned until the comparison result indicates that the bit error rate between the sent test signal and the returned test signal is not greater than the bit error rate threshold. The critical values ​​for eye height and eye width of the test signal are determined based on the current test signal.

8. A device for signal quality assessment, characterized in that, Includes memory used to store computer programs; A processor for executing the computer program to implement the steps of the signal quality assessment method as described in any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps of the signal quality assessment method as described in any one of claims 1 to 6.

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