High speed interface, method and system suitable for chiplet interconnect

CN115563046BActive Publication Date: 2026-05-26STRANGE MOORE SHANGHAI INTEGRATED CIRCUIT DESIGN CO LTD
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
STRANGE MOORE SHANGHAI INTEGRATED CIRCUIT DESIGN CO LTD
Filing Date
2022-09-29
Publication Date
2026-05-26

AI Technical Summary

Technical Problem

The existing AXI bus has a large number of signals in chiplet interconnection, making it difficult to increase the clock frequency, and the interconnection reliability is low in 3D packaging; the PCIe protocol layer design is complex and not suitable for data interaction of chiplets.

Method used

The Flit protocol layer is used to adapt to different data buses. It combines the data link layer and the physical layer to exchange information in parallel, which simplifies the physical layer design, reduces the number of signal lines, and improves reliability through signal detection and calibration mechanisms.

Benefits of technology

It improves the bus bandwidth density of chiplet interconnects, reduces power consumption and cost, enhances the interconnect reliability of 3D packaging, and simplifies physical layer design.

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Abstract

The present invention relates to a high-speed interface, method and system applicable to Chiplet interconnection. It includes a protocol layer for adapting to the information interaction with the data bus within the corresponding Chiplet; a data link layer adaptively connected to the protocol layer, for forwarding the Flit protocol transmission information to the physical layer and for forwarding the Flit protocol reception information transmitted by the physical layer to the protocol layer; a physical layer adaptively connected to the data link layer, wherein the Flit protocol transmission information forwarded by the data link layer is mapped to the corresponding physical layer transmission port to parallelly transmit the Flit protocol transmission information; and parallelly receiving the Flit protocol reception information through the physical layer reception port and transmitting the received Flit protocol reception information to the data link layer. The present invention can effectively adapt to the data interaction during Chiplet interconnection, improve the reliability of data interaction and has good compatibility.
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