Storage circuits, chips, data processing methods, and electronic devices

Abstract

A storage circuit, a chip, a data processing method, and an electronic device are disclosed. The storage circuit includes an input control circuit and a memory. The input control circuit is configured to: receive n input data and an input control signal; perform a first data processing on the n input data based on the input control signal to obtain n intermediate data corresponding one-to-one with the n input data; write the n intermediate data and a flag signal corresponding to the n input data into the memory; the memory is configured to store the n intermediate data and the flag signal; different values ​​of the flag signal represent different types of the first data processing, where n is a positive integer.

Description

Technical Field

[0001] Embodiments of this disclosure relate to a storage circuit, a chip, a data processing method, and an electronic device. Background Technology

[0002] Cache memory is a type of memory located between the central processing unit (CPU) and main memory (DRAM). It is small in size but operates at high speed. Typically, cache memory consists of static random access memory (SRAM). When SRAM stores data, it is affected by negative bias temperature instability (NBTI), causing it to gradually age. NBTI leads to an increase in the threshold voltage of transistors within the SRAM, a decrease in leakage current, and a decrease in the static noise margin (SNM). SNM refers to the minimum voltage noise that can toggle the state of an SRAM cell. The smaller the SNM, the more unstable the SRAM data storage, and the more susceptible it is to voltage noise interference that can cause data errors. Current research on the stability of 14-nanometer (nm) SRAM has found that without any anti-aging technology, the probability of SRAM failure after three years of continuous use can reach 100%. Therefore, research on anti-aging design for cache memory is essential. Summary of the Invention

[0003] This content section is provided to briefly introduce the concepts, which will be described in detail in the subsequent detailed description section. This content section is not intended to identify key or essential features of the claimed technical solution, nor is it intended to limit the scope of the claimed technical solution.

[0004] At least one embodiment of this disclosure provides a storage circuit including: an input control circuit and a memory. The input control circuit is configured to: receive n input data and an input control signal; perform a first data processing on the n input data based on the input control signal to obtain n intermediate data corresponding one-to-one with the n input data; write the n intermediate data and a flag signal corresponding to the n input data into the memory; the memory is configured to store the n intermediate data and the flag signal; different values ​​of the flag signal represent different types of the first data processing, where n is a positive integer.

[0005] At least one embodiment of this disclosure also provides a chip including the memory circuitry described in any of the foregoing embodiments.

[0006] At least one embodiment of this disclosure also provides a data processing method applied to the storage circuit described in any embodiment of this disclosure, comprising: receiving the n input data and the input control signal; performing the first data processing on the n input data based on the input control signal to obtain the n intermediate data corresponding one-to-one with the n input data; and storing the n intermediate data and the flag signal corresponding to the n input data, wherein n is a positive integer.

[0007] This disclosure also provides an electronic device in at least one embodiment, including a processing device. The processing device includes a storage circuit according to any of the above embodiments. Attached Figure Description

[0008] The above and other features, advantages, and aspects of the embodiments of this disclosure will become more apparent from the accompanying drawings and the following detailed description. Throughout the drawings, the same or similar reference numerals denote the same or similar elements. It should be understood that the drawings are schematic, and the originals and elements are not necessarily drawn to scale.

[0009] Figure 1A A schematic diagram of a storage circuit provided for at least one embodiment of this disclosure;

[0010] Figure 1B A schematic diagram of another storage circuit provided for at least one embodiment of this disclosure;

[0011] Figure 2 This is a schematic diagram of the structure of a storage circuit provided in some embodiments of this disclosure;

[0012] Figure 3 A schematic diagram of a chip provided for at least one embodiment of this disclosure;

[0013] Figure 4 A flowchart illustrating a data processing method provided in at least one embodiment of this disclosure;

[0014] Figure 5 A schematic diagram of an electronic device provided for at least one embodiment of this disclosure;

[0015] Figure 6 This is a schematic diagram of the structure of an electronic device provided in at least one embodiment of the present disclosure. Detailed Implementation

[0016] Embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings. While some embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this disclosure. It should be understood that the accompanying drawings and embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of protection of this disclosure.

[0017] It should be understood that the steps described in the method embodiments of this disclosure may be performed in different orders and / or in parallel. Furthermore, the method embodiments may include additional steps and / or omit the steps shown. The scope of this disclosure is not limited in this respect.

[0018] The term "comprising" and its variations as used herein are open-ended inclusions, meaning "including but not limited to". The term "based on" means "at least partially based on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". Definitions of other terms will be given in the description below.

[0019] It should be noted that the concepts of "first" and "second" mentioned in this disclosure are used only to distinguish different devices, modules or units, and are not used to limit the order of functions performed by these devices, modules or units or their interdependencies.

[0020] It should be noted that the terms "a" and "a plurality of" used in this disclosure are illustrative rather than restrictive, and those skilled in the art should understand that, unless otherwise expressly indicated in the context, they should be understood as "one or more".

[0021] The names of messages or information exchanged between multiple devices in the embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of such messages or information.

[0022] Research has found that the core of anti-aging design for cache memory at the architectural level is to maintain a 50% duty cycle for SRAM cells. However, existing technologies are complex and require significant modifications to the cache memory, resulting in substantial area overhead.

[0023] This disclosure provides at least one embodiment of a storage circuit, a chip, a data processing method, and an electronic device. The storage circuit includes an input control circuit and a memory. The input control circuit is configured to: receive n input data and an input control signal; perform a first data processing on the n input data based on the input control signal to obtain n intermediate data corresponding one-to-one with the n input data; write the n intermediate data and a flag signal corresponding to the n input data into the memory; the memory is configured to store the n intermediate data and the flag signal. Different values ​​of the flag signal represent different types of the first data processing, where n is a positive integer.

[0024] In the storage circuit provided in the embodiments of this disclosure, an input control signal controls the input data to undergo first data processing to obtain intermediate data, thereby ensuring that the intermediate data stored in the memory meets the user's needs. For example, when the memory is a cache memory, the input data stored in the cache memory can be continuously inverted based on the input control signal, ensuring that the duty cycle of the data stored in the cache memory is close to or equal to 50%, thereby delaying the aging of the cache memory, effectively reducing the impact of aging effects on the cache memory, greatly extending the service life of the cache memory, and reducing design costs. Furthermore, a flag signal identifies the type of the first data processing, so that when outputting the intermediate data, the intermediate data can be processed based on the flag signal to obtain accurate output data (e.g., the same as the input data).

[0025] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings; however, this disclosure is not limited to these specific embodiments. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of some known functions and components have been omitted.

[0026] Figure 1A A schematic diagram of a storage circuit provided for at least one embodiment of this disclosure; Figure 1B This is a schematic diagram of another storage circuit provided for at least one embodiment of the present disclosure.

[0027] like Figure 1A As shown, in some embodiments of this disclosure, the storage circuit 10 includes an input control circuit 100 and a memory 200. For example, the memory 200 can be a cache memory, such as a Level 1 cache (L1 cache) or a Level 2 cache (L2 cache). It should be noted that the memory 200 can also be other types of memory, which are not limited in this disclosure.

[0028] For example, the input control circuit 100 is configured to: receive n input data and an input control signal; perform a first data processing on the n input data based on the input control signal to obtain n intermediate data corresponding one-to-one with the n input data; and write the n intermediate data and the flag signal corresponding to the n input data into the memory 200. The memory 200 is configured to store the n intermediate data and the flag signal.

[0029] For example, different values ​​of the flag signal represent different types of the first data processing, where n is a positive integer.

[0030] For example, each input data can be a single bit, such as a binary number, and the value of each input data can be either a binary number 1 or 0.

[0031] For example, in some embodiments, the input control circuit 100 is further configured to determine a flag signal corresponding to n input data based on the input control signal.

[0032] For example, in some embodiments, the input control signal can be a single bit of data (i.e., 1 bit), and the flag signal can also be a single bit of data. Both the input control signal and the flag signal can be binary numbers; for example, the input control signal can be 0 or 1, and the flag signal can also be 0 or 1. However, this disclosure is not limited to this; the input control signal and the flag signal can also be two bits of data, three bits of data, etc. For example, the input control signal can be 00, 01, 10, or 11, and the flag signal can also be 00, 01, 10, or 11. Furthermore, the input control signal and the flag signal can also be ternary, quaternary, or decimal numbers. This disclosure does not limit the specific form and value of the input control signal and the flag signal.

[0033] For example, in some examples, the flag signal is the same as the input control signal, that is, the input control circuit 100 directly outputs the input control signal as the flag signal. In this case, if the input control signal is 1, the flag signal is 1; if the input control signal is 0, the flag signal is 0. In other examples, the flag signal and the input control signal can be inverted, that is, the input control circuit 100 can invert the input control signal to obtain the flag signal. In this case, if the input control signal is 1, the flag signal is 0; if the input control signal is 0, the flag signal is 1. It should be noted that in the embodiments of this disclosure, the example described is that the input control signal and the flag signal are the same and are both one-bit data.

[0034] For example, such as Figure 1BAs shown, the storage circuit 10 further includes an input control signal generator 300. The input control signal generator 300 is configured to generate an input control signal and output the input control signal to the input control circuit 100. In the storage circuit provided in this embodiment, the input control signal is generated by the input control signal generator 300 located outside the memory 200 to control the first data processing of the input data. This allows for simple and flexible acquisition of the input control signal. By outputting input control signals that meet different requirements through the input control signal generator 300, different data processing of the input data can be achieved, facilitating the fulfillment of different design requirements.

[0035] For example, the different values ​​of the flag signal are randomly generated values. These different values ​​include a first value and a second value. The first value can be 1, and the second value can be 0. Therefore, the flag signal can be a random number sequence composed of 0s and 1s, for example, the flag signal can be represented as 00011010110111010010… For example, overall, such as throughout the entire lifespan of the cache memory, the ratio of the first value and the second value of the flag signal is within a predetermined range, which can be 2 / 3 to 3 / 2. Thus, in the random number sequence of the flag signal, the ratio between the number of first values ​​and the total number of values ​​in the random number sequence (i.e., the number of data bits included in the random number sequence) can be 40% to 60%. The embodiments of this disclosure are illustrated using the example of a first value of 1 and a second value of 0.

[0036] For example, in some embodiments, the flag signal is a 1-bit random number sequence in which a first value and a second value randomly occur, and the interval between any two adjacent values ​​in the flag signal is 1 minute. That is, the flag signal may change as follows: the flag signal has the first value in the first minute, the flag signal has the second value in the second minute, the flag signal has the second value in the third minute, the flag signal has the first value in the fourth minute, and so on. The duty cycle of this random number sequence is approximately 50%, meaning that the flag signal has the first value for 50% of the entire lifetime of the cache memory.

[0037] For example, since the input control signal and the flag signal are the same, different values ​​of the input control signal can also include a first value and a second value. Overall, that is, throughout the entire lifespan of the cache memory, the ratio of the first value and the second value of the input control signal is within a predetermined range. The input control signal generator 300 can randomly output a value of the input control signal every minute. That is, in the first minute, the input control signal generator 300 can output the first value, at which time the value of the input control signal is the first value; in the second minute, the input control signal generator 300 can output the second value, at which time the value of the input control signal is the second value; in the third minute, the input control signal generator 300 can output the second value; in the fourth minute, the input control signal generator 300 can output the first value, and so on. For example, within a one-month period, the ratio of the first value and the second value of the input control signal is within a predetermined range.

[0038] It should be noted that this disclosure does not limit the specific values ​​of the input control signals generated by the input control signal generator 300 in different time periods. For example, the input control signal generator 300 may output a first value from the first minute to the tenth minute (or from the first minute to the sixtieth minute, etc.), meaning that the value of the input control signal at this time is the first value. The input control signal generator 300 may output a second value from the eleventh minute to the twenty-fifth minute (or from the sixtieth minute to the eighty-fifth minute, etc.), meaning that the value of the input control signal at this time is the second value, and so on. The input control signal generator 300 may randomly assign either a first value or a second value, as long as the ratio of the first value to the second value of the input control signal is within a predetermined range overall (over the lifespan of the cache memory).

[0039] For example, the input control signal can be directly generated using the random number generation unit in the chip, that is, the input control signal generator 300 can be the random number generation unit in the chip.

[0040] For example, a first value for the flag signal indicates that the first data processing is inverted; a second value for the flag signal indicates that the first data processing is held. That is, when the input control signal is at its first value, the first data processing is inverted; when the input control signal is at its second value, the first data processing is held. In this case, when the input control circuit 100 performs the step of processing n input data based on the input control signal to obtain n intermediate data corresponding to each of the n input data, it executes the following steps: in response to the first value of the input control signal, inverting the n input data to obtain n intermediate data; and in response to the second value of the input control signal, holding the n input data to obtain n intermediate data, i.e., directly using the n input data as the n intermediate data.

[0041] For example, such as Figure 1B As shown, the storage circuit 10 also includes an output control circuit 400. The output control circuit 400 is configured to: read n intermediate data and a flag signal from the memory 200; perform a second data processing on the n intermediate data based on the flag signal to obtain n output data corresponding one-to-one with the n intermediate data; and output the n output data.

[0042] For example, a first value for the flag signal indicates that the second data processing is inverting; a second value for the flag signal indicates that the second data processing is holding. In this case, when the output control circuit 400 performs the step of processing n intermediate data based on the flag signal to obtain n output data corresponding to each of the n intermediate data, it executes the following steps: in response to a first value for the flag signal, inverting the n intermediate data to obtain n output data; and in response to a second value for the flag signal, holding the n intermediate data to obtain n output data, i.e., directly using the n intermediate data as the n output data.

[0043] For example, if n input data and n output data are the same, then the output data is guaranteed to be the same as the input data stored in the memory. For example, if n is 10 and the n input data are 0110001010, then the n output data are also 0110001010.

[0044] Figure 2 This is a schematic diagram of the structure of a storage circuit provided in some embodiments of this disclosure.

[0045] For example, such as Figure 2 As shown, the input control circuit 100 includes n input sub-circuits 101, each corresponding to one of the n input data. The memory 200 also includes a write data interface and an output data interface. The write data interface includes n write data bits 201, each corresponding to one of the n input sub-circuits. For example, Figure 2 Each black rectangle in the diagram represents a write data bit 201.

[0046] For example, the first input terminal of each input sub-circuit 101 receives a corresponding input data Is, the second input terminal of each input sub-circuit 101 receives an input control signal Cs, and the output terminal of each input sub-circuit 101 is connected to a corresponding write data bit 201 in the write data interface. Each input sub-circuit 101 is configured to perform a first data processing on the input data Is based on the input control signal Cs to obtain intermediate data Ms corresponding to the input data Is, and write the intermediate data to the write data bit 201. For example, in Figure 2 In the example shown, the input control signal Cs is directly output to the memory 200 as a flag signal corresponding to the input data.

[0047] For example, such as Figure 2 As shown, the output control circuit 400 includes n output sub-circuits 401 corresponding one-to-one with n intermediate data, and the output data interface includes n output data bits 202 corresponding one-to-one with the n output sub-circuits 401. For example, Figure 2 Each rectangle with a diagonal shading represents an output data bit 202.

[0048] For example, the first input terminal of each output sub-circuit 401 is connected to the corresponding output data bit 202 in the output data interface to receive a corresponding intermediate data Ms, the second input terminal of each output sub-circuit 401 receives a flag signal Ss, the output terminal of each output sub-circuit 401 is used to output output data Os corresponding to the intermediate data Ms, and each output sub-circuit 401 is configured to perform a second data processing on the intermediate data Ms based on the flag signal Ss to obtain the output data Os corresponding to the intermediate data Ms, and output the output data Os.

[0049] For example, each input sub-circuit 101 includes an XOR gate with two input terminals and one output terminal. If the input control signal has a first value (1), then when the input data is 1, the intermediate data output by the input sub-circuit 101 corresponding to that input data is 0; when the input data is 0, the intermediate data output by the input sub-circuit 101 corresponding to that input data is 1, thus achieving inversion of the input data. If the input control signal has a second value (0), then when the input data is 1, the intermediate data output by the input sub-circuit 101 corresponding to that input data is 1; when the input data is 0, the intermediate data output by the input sub-circuit 101 corresponding to that input data is 0, thus achieving data holding.

[0050] For example, each output sub-circuit 401 includes an XOR gate with two input terminals and one output terminal. In this case, if the value of the flag signal is the first value, i.e., 1, then when the intermediate data is 1, the output data corresponding to the intermediate data output by the output sub-circuit 401 is 0; when the intermediate data is 0, the output data corresponding to the intermediate data output by the output sub-circuit 401 is 1, thereby realizing the inversion of the intermediate data. If the value of the flag signal is the second value, i.e., 0, then when the intermediate data is 1, the output data corresponding to the intermediate data output by the output sub-circuit 401 is 1; when the intermediate data is 0, the output data corresponding to the intermediate data output by the output sub-circuit 401 is 0, thereby realizing the holding of the input data.

[0051] It should be noted that this disclosure is not limited to this. The input sub-circuit 101 can also be implemented as an XNOR gate, in which case the first value of the input control signal is 0 and the second value of the input control signal is 1. The output sub-circuit 401 can also be implemented as an XNOR gate, in which case the first value of the flag signal is 0 and the second value of the flag signal is 1. The input sub-circuit 101 and / or the output sub-circuit 401 can also be implemented with other circuit structures, as long as they can achieve the above functions.

[0052] For example, memory 200 can be a cache memory, such as... Figure 2 As shown, the cache memory includes multiple data static memories 210 and multiple flag static memories 220. n intermediate data Ms are stored in the corresponding n data static memories 210, and the flag signal Ss is stored in the corresponding flag static memory 220.

[0053] For example, when the input control circuit 100 executes the writing of n intermediate data and a flag signal into the memory 200, it includes performing the following operations: obtaining a first write address corresponding to the n input data and a second write address corresponding to the flag signal; determining n data static memories based on the first write address; determining a flag static memory based on the second write address; writing the n intermediate data into the n data static memories one by one; and writing the flag signal into the flag static memory.

[0054] For example, when the output control circuit 400 executes the reading of n intermediate data and a flag signal, it includes performing the following operations: obtaining a first read address corresponding to the n intermediate data and a second read address corresponding to the flag signal; determining n data static memories that store the n intermediate data based on the first read address; determining a flag static memory that stores the flag signal based on the second read address; reading the n intermediate data from the n data static memories and reading the flag signal from the flag static memory.

[0055] For example, the first read address and the first write address are the same, and the second read address and the second write address are the same.

[0056] For example, multiple data static memories 210 and multiple flag static memories 220 constitute multiple static memory rows, with n data static memories and flag static memories located in the same static memory row. For example, in some embodiments, n data static memories and flag static memories can constitute one static memory row, in which case the number of static memories in each static memory row is n+1, and each static memory row is used to store n intermediate data and one flag signal; in other embodiments, n data static memories and flag static memories can be part of the static memories in a static memory row, for example, each static memory row can include (2n+2) static memories, in which case each static memory row includes 2n data static memories and 2 flag static memories. This disclosure does not limit the number and arrangement of data static memories and flag static memories in memory 200.

[0057] For example, the number of data static memories and the number of flag static memories in each static memory row are determined by hardware. For example, in some embodiments, a static memory row includes 64 data static memories and 2 flag static memories. 32 input data can be written to the 1st to 32nd data static memories simultaneously. The data stored in the 1st to 32nd data static memories corresponds to a flag signal, which is stored in one flag static memory in the static memory row. Another 32 input data are written to the 33rd to 64th data static memories simultaneously. The data stored in the 33rd to 64th data static memories corresponds to a flag signal, which is stored in another flag static memory in the static memory row.

[0058] For example, such as Figure 2 As shown, the storage circuit 10 also includes an external write data interface 500 and an external read data interface 600. The external write data interface 500 is configured to output n input data Is to the input control circuit 100, and the external read data interface 600 is configured to receive n output data Os output from the output control circuit 400.

[0059] In existing cache memories, each static memory row includes only a plurality of static memories for storing input data. In contrast to existing cache memories, each static memory row of the cache memory provided in this disclosure embodiment may include a plurality of static memories (i.e., data static memories) for storing input data, and also includes at least one static memory (i.e., flag static memory) for storing flag signals corresponding to the input data.

[0060] For example, suppose each static memory row of the cache memory includes n static memory blocks, which can store n bits of data, i.e. n input data. The data written to the cache memory from the outside at the same time or the data output from the cache memory at the same time is also n bits. Then, the input control circuit 100 includes n two-input XOR gates, and the output control circuit 400 also includes n two-input XOR gates.

[0061] In the input control circuit 100, the first input terminal of each XOR gate is connected to the corresponding bit of the external write data interface 500, and the output terminal of each XOR gate is connected to the corresponding write data bit 201 in the write data interface of the cache memory. That is, the first input terminal of the i-th XOR gate is connected to the i-th bit of the external write data interface 500, and the output terminal of the i-th XOR gate is connected to the i-th write data bit 201 of the write data interface in the cache memory. The second input terminals of all XOR gates receive the input control signal. When the value of the input control signal is the first value, the input data is inverted before being written to the cache memory. For example, if the input data is 1 (high level), then after passing through the XOR gate, the intermediate data actually input to the cache memory is 0 (low level). When the value of the input control signal is the second value, the input data is written to the cache memory as is. For example, if the input data is 1 (high level), then after passing through the XOR gate, the intermediate data actually input to the cache memory is 1 (high level).

[0062] For example, in the output control circuit 400, the first input of each XOR gate is connected to the corresponding output data bit 202 in the output data interface of the cache memory, the output of each XOR gate is connected to the corresponding bit in the external read data interface 600, and the second input of each XOR gate is used to receive the flag signal output by the cache memory (for example, the flag signal can also be output to the output control circuit 400 through an output data bit 202). That is, the output of the i-th XOR gate is connected to the i-th bit in the external read data interface 600, the first input of the i-th XOR gate is connected to the i-th output data bit 202 of the cache memory, and the second input of all XOR gates receives the flag signal.

[0063] For example, in the cache memory provided in this embodiment, a static memory for storing flag signals is added to record whether the data corresponding to the flag signal has been inverted. For example, each static memory row in the original cache memory includes n static memories; after adding the static memory for storing flag signals, each static memory row includes n+1 static memories. When the value of the flag signal is a first value, it indicates that the data corresponding to the flag signal has been inverted and stored; when the value of the flag signal is a second value, it indicates that the data corresponding to the flag signal has remained in its original state.

[0064] Therefore, in the embodiments of this disclosure, depending on the value of the input control signal, the data written from the external data write interface 500 to the cache memory is either inverted or stored as is in the corresponding static data memory of the cache memory. Simultaneously, a flag signal corresponding to this data is stored in a flag static memory, which indicates whether the data stored in the cache memory has been inverted. When reading data from the cache memory, based on the flag signal corresponding to the data to be read, if the data to be read has been inverted, it is inverted again and output to the external data read interface 600; otherwise, it is directly output to the external data read interface 600.

[0065] Assuming that before anti-aging treatment is applied to the cache memory, the duty cycle of data stored in a certain static memory within the cache memory is x during the cache memory's lifespan, based on the storage circuit provided in this embodiment, since the flag signal is a random number sequence with a 50% duty cycle, the duty cycle of that static memory in the cache memory is adjusted to 50%*x + 50%*(1-x) = 50%. This achieves the goal of ensuring that the duty cycle of data stored in each static memory in the cache memory reaches 50%, reducing the impact of aging on the cache memory and extending the cache memory's lifespan.

[0066] In the storage circuit provided in the embodiments of this disclosure, only an additional static memory needs to be added to the cache memory to record the flag signal. Compared with using multi-bit error correction codes to check and correct the erroneous bits (correcting one bit of erroneous data requires seven error correction codes), the use of error correction codes is reduced, which greatly reduces the design overhead. At the same time, it does not affect the cache consistency of the cache memory, and the external interface does not need to be changed. It can directly read and write to the cache memory, which has good compatibility.

[0067] It should be noted that, in this disclosure, the input control circuit 100, memory 200, input control signal generator 300, output control circuit 400, etc. in the storage circuit 10 can be implemented by hardware circuits. For example, the hardware circuits may include components such as resistors, capacitors, diodes, and transistors.

[0068] Figure 3 This is a schematic diagram of a chip provided for at least one embodiment of the present disclosure.

[0069] like Figure 3 As shown, some embodiments of this disclosure also provide a chip 20, which is an integrated circuit and includes the storage circuit 10 described in any of the above embodiments.

[0070] For example, in some embodiments, chip 20 further includes a substrate on which storage circuitry 10 is disposed. For example, the substrate may be a semiconductor wafer.

[0071] For example, chip 20 can be integrated inside the central processing unit or on the motherboard.

[0072] For details regarding the technical effects achievable by chip 20, please refer to the relevant descriptions in the embodiments of the above-mentioned storage circuit; repeated details will not be elaborated upon here.

[0073] Figure 4 This is a flowchart illustrating a data processing method provided in at least one embodiment of the present disclosure.

[0074] For example, the data processing method provided in this disclosure can be applied to the storage circuit 10 described in any of the above embodiments. Figure 4 As shown, the data processing method includes the following steps S40 to S42.

[0075] Step S40: Receive n input data and input control signals.

[0076] Step S41: Based on the input control signal, perform first data processing on the n input data to obtain n intermediate data that correspond one-to-one with the n input data.

[0077] Step S42: Store n intermediate data and the flag signals corresponding to the n input data.

[0078] For example, different values ​​of the flag signal represent different types of the first data processing, where n is a positive integer.

[0079] For example, in some embodiments, the data processing method further includes determining a flag signal based on an input control signal. Different values ​​for the flag signal include a first value and a second value.

[0080] For example, based on the input control signal, a first data processing is performed on n input data to obtain n intermediate data corresponding one-to-one with the n input data, including: inverting the n input data to obtain n intermediate data in response to the value of the flag signal determined based on the input control signal being a first value; and using the n input data as n intermediate data in response to the value of the flag signal determined based on the input control signal being a second value.

[0081] For example, in some embodiments, the data processing method further includes: reading n intermediate data and a flag signal; performing a second data processing on the n intermediate data based on the flag signal to obtain n output data that correspond one-to-one with the n intermediate data; and outputting the n output data.

[0082] For example, when the different values ​​of the flag signal include a first value and a second value, based on the flag signal, a second data processing is performed on n intermediate data to obtain n output data that correspond one-to-one with the n intermediate data, including: in response to the value of the flag signal being the first value, inverting the n intermediate data to obtain n output data; and in response to the value of the flag signal being the second value, using the n intermediate data as n output data.

[0083] For the technical effects that the data processing method can achieve, please refer to the relevant descriptions in the embodiments of the above storage circuit; repeated details will not be repeated here.

[0084] Figure 5 This is a schematic diagram of an electronic device provided for at least one embodiment of the present disclosure.

[0085] like Figure 5 As shown, some embodiments of this disclosure also provide an electronic device 5000, which includes a processing device 5100, and the processing device 5100 includes the storage circuit 10 described in any of the above embodiments.

[0086] For example, the processing device 5100 can be a central processing unit (CPU), a graphics processing unit (GPU), etc. The storage circuit 10 can be integrated inside the central processing unit. The processing device 5100 can also be other forms of processing units with data processing capabilities and / or program execution capabilities, such as a field-programmable gate array (FPGA) or a tensor processing unit (TPU); for example, the central processing unit can have an x86 or ARM architecture, etc.

[0087] For details regarding the technical effects achievable by the electronic device 5000, please refer to the relevant descriptions in the embodiments of the above-mentioned storage circuit; repeated details will not be elaborated upon here.

[0088] The following is for reference. Figure 6 , Figure 6 A schematic diagram of the structure of an electronic device 600 suitable for implementing embodiments of the present disclosure is shown. The electronic devices in the embodiments of the present disclosure may include, but are not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), in-vehicle terminals (e.g., in-vehicle navigation terminals), wearable electronic devices, etc., as well as fixed terminals such as digital TVs, desktop computers, smart home devices, etc. Figure 6 The electronic device shown is merely an example and should not be construed as limiting the functionality and scope of the embodiments disclosed herein.

[0089] For example, the storage circuit 10 provided in this disclosure can be disposed in the electronic device 600.

[0090] like Figure 6 As shown, electronic device 600 may include a processing device (e.g., a central processing unit, a graphics processor, etc.) 601, which can perform various appropriate actions and processes according to a program stored in read-only memory (ROM) 602 or a program loaded from storage device 606 into random access memory (RAM) 603. RAM 603 also stores various programs and data required for the operation of electronic device 600. Processing device 601, ROM 602, and RAM 603 are interconnected via bus 604. Input / output (I / O) interface 605 is also connected to bus 604.

[0091] Typically, the following devices can be connected to I / O interface 605: input devices 606 including, for example, touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 607 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 606 including, for example, magnetic tapes, hard disks, etc.; and communication devices 609. Communication device 609 allows electronic device 600 to communicate wirelessly or wiredly with other devices to exchange data. Although Figure 6 An electronic device 600 with various devices is shown; however, it should be understood that it is not required to implement or possess all of the devices shown. More or fewer devices may be implemented or possessed alternatively.

[0092] In particular, according to embodiments of this disclosure, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of this disclosure include a computer program product comprising a computer program carried on a non-transitory computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts to execute one or more steps in the data processing method described above. In such embodiments, the computer program can be downloaded and installed from a network via communication device 609, or installed from storage device 606, or installed from ROM 602. When the computer program is executed by processing device 601, it performs the functions defined in the methods of embodiments of this disclosure.

[0093] It should be noted that, in the context of this disclosure, a computer-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A computer-readable medium can be a computer-readable signal medium or a computer-readable storage medium, or any combination thereof. A computer-readable storage medium can be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to, an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this disclosure, a computer-readable storage medium can be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. In this disclosure, a computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. The computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium, capable of transmitting, propagating, or transmitting a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium may be transmitted using any suitable medium, including but not limited to: wires, optical fibers, RF (radio frequency), etc., or any suitable combination thereof.

[0094] The aforementioned computer-readable medium may be included in the aforementioned electronic device; or it may exist independently and not assembled into the electronic device.

[0095] Computer program code for performing the operations of this disclosure can be written in one or more programming languages ​​or a combination thereof, including but not limited to object-oriented programming languages ​​such as Java, Smalltalk, and C++, as well as conventional procedural programming languages ​​such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network (including a local area network (LAN) or a wide area network (WAN)), or it can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0096] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0097] The units described in the embodiments of this disclosure can be implemented in software or hardware. The names of the units are not, in some cases, intended to limit the specific unit.

[0098] The functions described above in this document can be performed, at least in part, by one or more hardware logic components. For example, exemplary types of hardware logic components that can be used, without limitation, include: Field Programmable Gate Arrays (FPGAs), Application-Specific Integrated Circuits (ASICs), Application Standard Products (ASSPs), System-on-Chip (SoCs), Complex Programmable Logic Devices (CPLDs), and so on.

[0099] According to one or more embodiments of this disclosure, a storage circuit includes an input control circuit and a memory. The input control circuit is configured to: receive n input data and an input control signal; perform a first data processing on the n input data based on the input control signal to obtain n intermediate data corresponding one-to-one with the n input data; write the n intermediate data and a flag signal corresponding to the n input data into the memory; the memory is configured to store the n intermediate data and the flag signal; different values ​​of the flag signal represent different types of the first data processing, where n is a positive integer.

[0100] According to one or more embodiments of the present disclosure, the storage circuit further includes: an input control signal generator configured to generate an input control signal and output the input control signal to an input control circuit.

[0101] According to one or more embodiments of this disclosure, the flag signal is the same as the input control signal.

[0102] According to one or more embodiments of this disclosure, the different values ​​of the flag signal are randomly generated values.

[0103] According to one or more embodiments of this disclosure, different values ​​of the flag signal include a first value and a second value, and the ratio of the first value and the second value is within a predetermined range.

[0104] According to one or more embodiments of this disclosure, a first value of the flag signal indicates that the first data processing is an inversion process; a second value of the flag signal indicates that the first data processing is a hold process.

[0105] According to one or more embodiments of this disclosure, the predetermined range is 2 / 3 to 3 / 2.

[0106] According to one or more embodiments of the present disclosure, the storage circuit further includes: an output control circuit configured to: read n intermediate data and a flag signal from the memory; perform a second data processing on the n intermediate data based on the flag signal to obtain n output data corresponding one-to-one with the n intermediate data; and output the n output data.

[0107] According to one or more embodiments of this disclosure, different values ​​of the flag signal include a first value and a second value, the ratio of the first value and the second value is within a predetermined range, the value of the flag signal being the first value indicates that the second data processing is inversion processing; the value of the flag signal being the second value indicates that the second data processing is hold processing.

[0108] According to one or more embodiments of this disclosure, the input control circuit includes n input sub-circuits corresponding one-to-one with n input data. The memory further includes a write data interface and an output data interface. The write data interface includes n write data bits corresponding one-to-one with the n input sub-circuits. A first input terminal of each input sub-circuit receives a corresponding input data, a second input terminal of each input sub-circuit receives an input control signal, and an output terminal of each input sub-circuit is connected to a corresponding write data bit in the write data interface. Each input sub-circuit is configured to perform a first data processing on the input data based on the input control signal to obtain intermediate data corresponding to the input data. Intermediate data is written to the write data bit; the output control circuit includes n output sub-circuits corresponding one-to-one with n intermediate data, and the output data interface includes n output data bits corresponding one-to-one with n output sub-circuits. The first input terminal of each output sub-circuit is connected to the corresponding output data bit in the output data interface to receive a corresponding intermediate data. The second input terminal of each output sub-circuit receives a flag signal. The output terminal of each output sub-circuit is used to output output data corresponding to the intermediate data. Each output sub-circuit is configured to perform a second data processing on the intermediate data based on the flag signal to obtain the output data corresponding to the intermediate data and output the output data.

[0109] According to one or more embodiments of this disclosure, each input sub-circuit includes an XOR gate, and each output sub-circuit includes an XOR gate.

[0110] According to one or more embodiments of this disclosure, the memory is a cache memory, which includes multiple data static memories and multiple flag static memories. n intermediate data are respectively stored in the n corresponding data static memories of the multiple data static memories, and the flag signal is stored in one corresponding flag static memory of the multiple flag static memories.

[0111] According to one or more embodiments of this disclosure, a plurality of data static memories and a plurality of flag static memories constitute a plurality of static memory rows, and n data static memories and flag static memories are located in the same static memory row.

[0112] According to one or more embodiments of this disclosure, the storage circuitry further includes an external write data interface configured to output n input data to the input control circuitry.

[0113] According to one or more embodiments of the present disclosure, the storage circuitry further includes an external data read interface configured to receive n output data from the output control circuitry.

[0114] According to one or more embodiments of this disclosure, a chip includes the memory circuitry described in any of the above embodiments.

[0115] According to one or more embodiments of this disclosure, a data processing method is applied to the storage circuit described in any embodiment of this disclosure. The data processing method includes: receiving n input data and an input control signal; performing a first data processing on the n input data based on the input control signal to obtain n intermediate data corresponding one-to-one with the n input data; and storing the n intermediate data and a flag signal corresponding to the n input data, wherein n is a positive integer.

[0116] According to one or more embodiments of this disclosure, the data processing method further includes: determining a flag signal based on an input control signal; wherein different values ​​of the flag signal include a first value and a second value; and performing a first data processing on n input data based on the input control signal to obtain n intermediate data corresponding one-to-one with the n input data, including: inverting the n input data to obtain the n intermediate data in response to the value of the flag signal determined based on the input control signal being a first value; and using the n input data as the n intermediate data in response to the value of the flag signal determined based on the input control signal being a second value.

[0117] According to one or more embodiments of this disclosure, the data processing method further includes: reading n intermediate data and a flag signal; performing a second data processing on the n intermediate data based on the flag signal to obtain n output data corresponding one-to-one with the n intermediate data; and outputting the n output data.

[0118] According to one or more embodiments of this disclosure, when different values ​​of the flag signal include a first value and a second value, a second data processing is performed on n intermediate data based on the flag signal to obtain n output data corresponding one-to-one with the n intermediate data, including: inverting the n intermediate data in response to the value of the flag signal being a first value to obtain n output data; and using the n intermediate data as n output data in response to the value of the flag signal being a second value.

[0119] According to one or more embodiments of this disclosure, an electronic device includes a processing means. The processing means includes a storage circuit as described in any of the foregoing embodiments.

[0120] The above description is merely a preferred embodiment of this disclosure and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of this disclosure is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the above-described concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features disclosed in this disclosure that have similar functions.

[0121] Furthermore, while the operations are described in a specific order, this should not be construed as requiring these operations to be performed in the specific order shown or in a sequential order. In certain environments, multitasking and parallel processing may be advantageous. Similarly, while several specific implementation details are included in the above discussion, these should not be construed as limiting the scope of this disclosure. Certain features described in the context of individual embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments.

[0122] Although the subject matter has been described using language specific to structural features and / or methodological logic, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. Rather, the specific features and actions described above are merely illustrative examples of implementing the claims.

[0123] The following points should be noted regarding this disclosure:

[0124] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0125] (2) For clarity, the thickness and dimensions of layers or structures are enlarged in the drawings used to describe embodiments of the present disclosure. It will be understood that when an element such as a layer, film, region or substrate is referred to as being “above” or “below” another element, the element may be “directly” located “above” or “below” the other element, or there may be intermediate elements present.

[0126] (3) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0127] The above description is only a specific embodiment of this disclosure, but the protection scope of this disclosure is not limited thereto. The protection scope of this disclosure should be determined by the protection scope of the claims.

Claims

1. A storage circuit, comprising: Input control circuit and memory, The input control circuit is configured as follows: Receive n input data and input control signals; Based on the input control signal, the n input data are subjected to first data processing to obtain n intermediate data that correspond one-to-one with the n input data; Write the n intermediate data and the flag signal corresponding to the n input data into the memory; The memory is configured to store the n intermediate data and the flag signal; Wherein, the different values ​​of the flag signal represent different types of the first data processing, and n is a positive integer; The storage circuit further includes an external write data interface, which is configured to output the n input data to the input control circuit. The different values ​​of the flag signal include a first value and a second value. The flag signal is a random number sequence composed of the first value and the second value. During the entire life cycle of the memory, the ratio of the first value and the second value is within a predetermined range, which is 2 / 3 to 3 / 2.

2. The storage circuit according to claim 1 further includes: Input control signal generator, The input control signal generator is configured to generate the input control signal and output the input control signal to the input control circuit.

3. The storage circuit according to claim 1, wherein, The flag signal is the same as the input control signal.

4. The storage circuit according to claim 1, wherein, The different values ​​of the flag signal are randomly generated.

5. The storage circuit according to claim 1, wherein, The value of the flag signal is the first value, indicating that the first data processing is inversion processing; the value of the flag signal is the second value, indicating that the first data processing is hold processing.

6. The storage circuit according to claim 1, further comprising: Output control circuit The output control circuit is configured as follows: Read the n intermediate data and the flag signal from the memory; Based on the flag signal, the n intermediate data are subjected to a second data processing to obtain n output data that correspond one-to-one with the n intermediate data; Output the n output data.

7. The storage circuit according to claim 6, wherein, The value of the flag signal being the first value indicates that the second data processing is inverting processing; the value of the flag signal being the second value indicates that the second data processing is holding processing.

8. The storage circuit according to claim 6, wherein, The input control circuit includes n input sub-circuits, each corresponding to one of the n input data. The memory further includes a write data interface and an output data interface. The write data interface includes n write data bits, each corresponding to one of the n input sub-circuits. The first input terminal of each input sub-circuit receives a corresponding input data, the second input terminal of each input sub-circuit receives the input control signal, the output terminal of each input sub-circuit is connected to the corresponding write data bit in the write data interface, and each input sub-circuit is configured to perform the first data processing on the input data based on the input control signal to obtain intermediate data corresponding to the input data, and write the intermediate data into the write data bit. The output control circuit includes n output sub-circuits, each corresponding to one of the n intermediate data points, and the output data interface includes n output data bits, each corresponding to one of the n output sub-circuits. The first input terminal of each output sub-circuit is connected to the corresponding output data bit in the output data interface to receive a corresponding intermediate data. The second input terminal of each output sub-circuit receives the flag signal. The output terminal of each output sub-circuit is used to output output data corresponding to the intermediate data. Each output sub-circuit is configured to perform the second data processing on the intermediate data based on the flag signal to obtain output data corresponding to the intermediate data and output the output data.

9. The storage circuit according to claim 8, wherein, Each input sub-circuit includes an XOR gate, and each output sub-circuit includes an XOR gate.

10. The storage circuit according to any one of claims 1-9, wherein, The memory is a high-speed cache memory. The cache memory includes multiple static data memories and multiple static flag memories. The n intermediate data are respectively stored in the n corresponding data static memories of the plurality of data static memories, and the flag signal is stored in the corresponding flag static memory of the plurality of flag static memories.

11. The storage circuit according to claim 10, wherein, The plurality of data static memories and the plurality of flag static memories constitute a plurality of static memory rows. The n data static storages and the flag static storages are located in the same static storage row.

12. The storage circuit according to any one of claims 6-9, further comprising an external data read interface, wherein, The external data read interface is configured to receive the n output data from the output control circuit.

13. A chip comprising a storage circuit according to any one of claims 1-12.

14. A data processing method, applied to the storage circuit according to any one of claims 1-12, comprising: Receive the n input data and the input control signal; Based on the input control signal, the first data processing is performed on the n input data to obtain the n intermediate data that correspond one-to-one with the n input data; Store the n intermediate data and the flag signals corresponding to the n input data. Where n is a positive integer.

15. The data processing method according to claim 14, further comprising: The flag signal is determined based on the input control signal; Specifically, based on the input control signal, the first data processing is performed on the n input data to obtain the n intermediate data corresponding one-to-one with the n input data, including: In response to the value of the flag signal determined based on the input control signal being the first value, the n input data are inverted to obtain the n intermediate data; In response to the value of the flag signal determined based on the input control signal being the second value, the n input data are used as the n intermediate data.

16. The data processing method according to claim 14, further comprising: Read the n intermediate data and the flag signal; Based on the flag signal, the n intermediate data are subjected to a second data processing to obtain n output data that correspond one-to-one with the n intermediate data; Output the n output data.

17. The data processing method according to claim 16, wherein, In the case where the different values ​​of the flag signal include a first value and a second value, Based on the flag signal, the n intermediate data are subjected to a second data processing to obtain n output data corresponding one-to-one with the n intermediate data, including: In response to the value of the flag signal being the first value, the n intermediate data are inverted to obtain the n output data; In response to the value of the flag signal being the second value, the n intermediate data are used as the n output data.

18. An electronic device comprising: A processing apparatus, wherein the processing apparatus includes a storage circuit according to any one of claims 1-12.

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