Semiconductor structure manufacturing method

Abstract

This disclosure provides a method for manufacturing a semiconductor structure. Multiple first mask patterns are formed on a substrate in a memory region, and multiple second mask patterns are formed on a substrate in a peripheral region. Sidewalls are formed on the sidewalls of the first and second mask patterns. A fill layer is formed on the top surfaces of the first and second mask patterns, filling the gaps between adjacent sidewalls. The thickness of the fill layer in the memory region is equal to the thickness of the fill layer in the peripheral region. The fill layer is etched to expose the top surfaces of the sidewalls, the first mask patterns, and the second mask patterns. After removing the sidewalls located on the top and side surfaces of the first and second mask patterns, a portion of the substrate is etched away using the fill layer, the first mask pattern, and the second mask pattern as masks. This disclosure at least reduces the occurrence of under-etching or over-etching during the etching of a portion of the substrate.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor manufacturing, and in particular to a method for manufacturing a semiconductor structure. Background Technology

[0002] Memory is a storage device used to store information in modern information technology, and it is widely used in various electronic products. Memory can be divided into main memory and secondary storage based on whether it can be directly read by the central processing unit (CPU). Main memory can be further divided into Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), and Video Random Access Memory (VRAM), etc.

[0003] Currently, there are areas that are difficult to etch during the formation of the target layer. Summary of the Invention

[0004] This disclosure provides a method for manufacturing a semiconductor structure, which helps to improve the performance of the formed semiconductor structure.

[0005] According to some embodiments of this disclosure, an embodiment of this disclosure provides a method for manufacturing a semiconductor structure, comprising: providing a substrate, the substrate including a storage region and a peripheral region; forming an initial mask layer on the substrate; etching the initial mask layer such that the remaining initial mask layer in the storage region forms a plurality of discrete first mask patterns, and the remaining initial mask layer in the peripheral region forms a plurality of discrete second mask patterns; forming sidewalls, the sidewalls at least covering the sidewalls of the first mask patterns and the sidewalls of the second mask patterns; and forming a fill layer, the fill layer covering the top surface of the first mask patterns to... The filling layer in the storage area is equal to the thickness of the filling layer in the peripheral area, and the top surface of the second mask pattern is filled with the filling layer. The filling layer is etched to expose the top surface of the sidewall, the top surface of the first mask pattern, and the top surface of the second mask pattern. A portion of the sidewall is removed, including the sidewall located on the top and side surfaces of the first mask pattern and the sidewall located on the top and side surfaces of the second mask pattern. Using the filling layer, the first mask pattern, and the second mask pattern as masks, a portion of the substrate is etched away.

[0006] In some embodiments, the method of etching the initial mask layer includes: forming a patterned layer with openings on the initial mask layer, the openings including: a plurality of first openings located in the storage region and a plurality of second openings located in the peripheral region, wherein, along a first direction, the width of the first opening is smaller than the width of the second opening; using the patterned layer as a mask, patterning the initial mask layer along the first openings and the second openings, the remaining initial mask layer constituting the first mask pattern and the second mask pattern respectively; and removing the patterned layer.

[0007] In some embodiments, the width of the first opening ranges from 50 nm to 80 nm, and the width of the second opening ranges from 120 nm to 330 nm.

[0008] In some embodiments, the width of the first mask pattern formed along the first direction is smaller than the width of the second mask pattern formed.

[0009] In some embodiments, along the first direction, the width of the first mask pattern ranges from 30 nm to 50 nm, and the width of the second mask pattern ranges from 100 nm to 300 nm.

[0010] In some embodiments, the step of forming the sidewall includes: forming the sidewall that covers the substrate, the side and top surfaces of the first mask pattern, and the side and top surfaces of the second mask pattern.

[0011] In some embodiments, the thickness of the sidewall ranges from 10 nm to 15 nm.

[0012] In some embodiments, the substrate includes a layer to be etched; the step of etching a portion of the substrate using the fill layer, the first mask pattern, and the second mask pattern as masks includes: etching the layer to be etched using the fill layer, the first mask pattern, and the second mask pattern as masks, such that the remaining layer to be etched in the storage region constitutes a plurality of discrete first mask layers, and the remaining layer to be etched in the peripheral region constitutes a plurality of discrete second mask layers.

[0013] In some embodiments, the material of the sidewall is the same as the material of the layer to be etched.

[0014] In some embodiments, after etching a portion of the substrate using the filler layer, the first mask pattern, and the second mask pattern as masks, the method further includes: removing the filler layer, the sidewalls located on the substrate, the first mask pattern, and the second mask pattern.

[0015] In some embodiments, a third mask pattern is further formed between the first mask pattern adjacent to the peripheral region and the second mask pattern adjacent to the storage region; the step of etching a portion of the substrate using the filling layer, the first mask pattern, and the second mask pattern as masks further includes: removing a portion of the substrate using the third mask pattern as a mask; and removing the third mask pattern.

[0016] In some embodiments, the width of the third mask pattern is greater than the width of the first mask pattern along the first direction.

[0017] In some embodiments, the width of the third mask pattern along the first direction ranges from 550 nm to 600 nm.

[0018] In some embodiments, the initial mask layer includes a first initial mask layer and a second initial mask layer, wherein the second initial mask layer is formed between the first initial mask layer and the substrate.

[0019] In some embodiments, the material of the filling layer is the same as the material of the second initial mask layer.

[0020] The technical solutions provided in this disclosure have at least the following advantages:

[0021] The semiconductor structure manufacturing method provided in this disclosure forms multiple discrete first mask patterns on a substrate in the storage region and multiple discrete second mask patterns on a substrate in the peripheral region, which can reduce the difference between the mask pattern density in the storage region and the mask pattern density in the peripheral region. Sidewalls are formed on the sidewalls of the first and second mask patterns. Adjacent sidewalls can position the filling layer formed in subsequent steps, and the width of the filling layer formed between adjacent sidewalls along a first direction can be controlled by controlling the thickness of the sidewalls. The formed filling layer fills the gap between adjacent sidewalls. Because the difference in mask pattern density between the storage region and the peripheral region is small, the filling density in the storage region is relatively high. The thickness of the layer is equal to the thickness of the filling layer in the peripheral region. Therefore, during the etching process of the filling layer, the sidewalls located on the top surface of the first mask pattern and the sidewalls located on the top surface of the second mask pattern can be completely exposed and removed in subsequent steps. In the step of etching away part of the substrate using the filling layer, the first mask pattern, and the second mask pattern as masks, the thickness difference of the filling layer in the peripheral region and the memory region is small, which can achieve etching consistency. Thus, the embodiments of this disclosure can reduce the thickness difference of the filling layer formed in the gaps between the memory region and the gaps between the peripheral region, thereby reducing the probability of under-etching or over-etching during the etching process of the substrate, which is beneficial to improving the performance and yield of the formed semiconductor structure. Attached Figure Description

[0022] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figures 1 to 6 This is a schematic diagram of the structure corresponding to each step of a semiconductor structure manufacturing method.

[0024] Figures 7 to 14 This is a schematic diagram of the steps in a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure. Detailed Implementation

[0025] As can be seen from the background technology, there is currently a problem that there are areas that are difficult to etch during the formation of the target layer.

[0026] Figures 1 to 6 This is a schematic diagram illustrating the structural steps involved in the fabrication of a semiconductor structure. (Reference) Figure 1 A substrate 101 is provided, along with a first mask pattern 102 and a second mask pattern 103 located on the substrate 101. The substrate 101 may include a dielectric layer 108 and a substrate 109. The dielectric layer 108 is located on the substrate 109 and contacts the first mask pattern 102 and the second mask pattern 103. The substrate 101 may include a storage region 104 and a peripheral region 105. A plurality of discrete first mask patterns 102 are formed on the storage region 104, and a second mask pattern 103 is formed on the peripheral region 105, completely covering the entire peripheral region 105. (Reference) Figure 2 This forms sidewalls 106, which cover the sidewalls and top surface of the first mask pattern 102, the sidewalls and top surface of the second mask pattern 103, and the top surface of the dielectric layer 108; (Reference) Figure 3 This forms a filling layer 107, which covers the sidewalls 106 and fills the gaps between adjacent sidewalls 106; (Reference) Figure 4 The fill layer 107 is etched to expose the sidewalls 106 on the top surface of the first mask pattern 102 and the sidewalls 106 on the top surface of the second mask pattern 103; Reference Figure 5 The sidewalls 106 are removed, including: sidewalls 106 located on the top and side surfaces of the first mask pattern 102, and sidewalls 106 located on the top and side surfaces of the second mask pattern 103; (See reference) Figure 6Using the first mask pattern 102, the second mask pattern 103 and the filling layer 107 as masks, the dielectric layer 108 is etched to form a plurality of discrete first structures 111 on the storage area 104. The remaining dielectric layer 108 in the peripheral area 105 constitutes the second structure 110, and the sidewalls 106, the first mask pattern 102 and the second mask pattern 103 are removed.

[0027] Analysis revealed that the material currently used for the filler layer 107 may include SOH (Spin on Hard mask) material. SOH material is an oligomer with certain fluidity and adhesion, which can flow into the gap between adjacent sidewalls 106. The process of forming the filler layer 107 using SOH material may include a spin coating process, which includes a batching stage, a high-speed rotation stage, and a volatile film formation stage. During the high-speed rotation phase, due to the adhesiveness of the SOH material and the fact that the second mask pattern 103 is a continuous film layer with gaps between the first mask patterns 102 on the storage region 104, the thickness of the SOH material coated on the storage region 104 is lower than that of the SOH material in the peripheral region. On the other hand, during the evaporation film formation phase, small molecules in the SOH material can volatilize, and the SOH oligomers undergo further cross-linking and curing. The condensation of active groups in the SOH material causes shrinkage, which exacerbates the thickness difference between the SOH material coated on the storage region 104 and the SOH material in the peripheral region 105. Consequently, the thickness of the filling layer 107 formed on the storage region 104 is lower than that of the filling layer 107 formed on the peripheral region 105 (see reference). Figure 3 ). refer to Figure 4 Because the filling layer 107 varies in different regions, after etching the filling layer 107, the thickness of the filling layer 107 in the storage region 104 is still lower than the thickness of the filling layer 107 in the peripheral region 105, and the height of the filling layer 107 in the peripheral region 105 is higher than the height of the second mask pattern 103. This results in difficulties in the step of removing part of the sidewall 106 (see reference). Figure 5 The sidewalls 106 on the second mask pattern 103 and the sidewalls 106 on the first mask pattern 102 may not be completely removed. There may still be a partial thickness of the fill layer 107 on the second mask pattern 103 and the first mask pattern 102. This may result in some of the first structures 111 formed in the storage area 104 being under-etched or over-etched during the etching of the dielectric layer 108 using the first mask pattern 102, the second mask pattern 103 and the fill layer 107 as masks.

[0028] This disclosure provides a method for manufacturing a semiconductor structure, in which multiple discrete first mask patterns are formed in a memory region and multiple discrete second mask patterns are formed in a peripheral region. This reduces the difference in density between the first mask patterns in the memory region and the second mask patterns in the peripheral region, facilitating control over the thickness of the fill layer formed in subsequent steps in different areas. Sidewalls are formed on the sidewalls of the first and second mask patterns, at least covering both sidewalls. These sidewalls position the fill layer formed in subsequent steps, and the width of the fill layer formed between adjacent sidewalls along a first direction can be controlled by controlling the thickness of the sidewalls. The formed fill layer also covers the top surface of the first and second mask patterns. On the top surface, since the density of the mask pattern in the storage area is relatively small compared to the density of the mask pattern in the peripheral area, the thickness of the filling layer in the storage area is relatively small compared to the thickness of the filling layer in the peripheral area, or the thickness of the filling layer in the storage area is basically equal to or equal to the thickness of the filling layer in the peripheral area, the filling layer is etched to expose the top surface of the sidewalls, the top surface of the first mask pattern, and the top surface of the second mask pattern. In this step, the sidewalls located on the top surface of the first mask pattern and the top surface of the second mask pattern can be completely exposed and removed. Thus, in the process of etching away part of the substrate using the filling layer, the first mask pattern, and the second mask pattern as masks, the remaining part of the etched substrate has a relatively uniform thickness and a small height difference, which is beneficial to improving the performance and yield of the formed semiconductor structure.

[0029] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0030] Figures 7 to 14 This is a schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure.

[0031] refer to Figure 7 A substrate 201 is provided, which includes a storage area 21 and a peripheral area 22.

[0032] The storage region 21 is used to form a storage device in a semiconductor structure, and the peripheral region 22 is used to form a peripheral circuit in a semiconductor structure. The substrate 201 may include a substrate 202, a first film layer 203, a second film layer 204, and a third film layer 205, with the first film layer 203, the second film layer 204, and the third film layer 205 sequentially stacked on the substrate 202.

[0033] The substrate 201 may also include a layer to be etched 206, which is located on the third film layer 205.

[0034] The substrate 202 can be made of at least one of silicon, germanium, silicon-germanium, or silicon carbide. In other embodiments, the substrate 202 can also be silicon-on-insulator (SOI) or germanium-on-insulator (GOI). The first film layer 203 can be made of any one or more of copper, tungsten, aluminum, titanium, tantalum, etc. The second film layer 204 can be an ACL (alpha carbon layer). The third film layer 205 can be a hard mask layer, so that during subsequent etching to remove a portion of the substrate 201, a portion of the substrate 201 can be the etching layer 206, protecting the film layer below the third film layer 205 from erosion. The third film layer 205 can be made of any one or more of silicon oxynitride, tantalum nitride, titanium nitride, silicon carbide, aluminum nitride, tungsten nitride, etc. The etching layer 206 can be made of silicon oxide or silicon nitride.

[0035] Storage area 21 may also include array area 23 and core area 24, wherein core area 24 is located between array area 23 and peripheral area 22.

[0036] An intermediate area 25 can be set between the array area 23 and the core area 24, as well as between the core area 24 and the peripheral area 22.

[0037] Specifically, along the first direction X, the width of the array region 23 can range from 2µm to 3µm, depending on the process node. For example, the width of the array region 23 can be 2µm, 2.5µm, or 3µm. The width of the core region 24 can range from 300nm to 500nm. For example, the width of the core region can be 300nm, 400nm, or 500nm. The width of the peripheral region 22 can range from 3µm to 5µm. For example, the width of the peripheral region 22 can be 3µm, 4µm, or 5µm. The width of the middle region 25 can range from 550nm to 600nm. For example, the width of the middle region 25 can be 550nm, 580nm, or 600nm.

[0038] refer to Figure 8 An initial mask layer 207 is formed on the substrate 201, that is, the initial mask layer 207 covers the etchable layer 206 on the array region 23, the core region 24, the peripheral region 22 and the intermediate region 25.

[0039] The initial mask layer 207 may include a first initial mask layer 212 and a second initial mask layer 213, with the second initial mask layer 213 formed between the first initial mask layer 212 and the substrate 201. The material of the first initial mask layer 212 may be any one or more of silicon oxynitride, tantalum nitride, titanium nitride, silicon carbide, aluminum nitride, and tungsten nitride. The material of the second initial mask layer may be an SOH material.

[0040] Subsequent steps may further include etching the initial mask layer 207 so that the remaining initial mask layer 207 in the storage region 21 forms multiple discrete first mask patterns, and the remaining initial mask layer 207 in the peripheral region 22 forms multiple discrete second mask patterns. This reduces the difference in mask pattern density between the storage region 21 and the peripheral region 22, thereby reducing the thickness difference of the subsequently formed filling layer between the storage region 21 and the peripheral region 22. This, in turn, helps to reduce the occurrence of under-etching or over-etching during subsequent etching of the substrate 201. The etching process of the initial mask layer 207 described above will be explained in detail below with reference to the accompanying drawings.

[0041] refer to Figure 9 The method of etching the initial mask layer 207 may include forming a pattern layer 209 with openings 208 on the initial mask layer 207. The openings 208 may include a plurality of first openings 210 located in the storage area 21 and a plurality of second openings 211 located in the peripheral area 22.

[0042] The pattern layer 209 can be a photoresist layer. A bottom anti-reflection coating (BARC, not shown) can also be formed between the pattern layer 209 and the initial mask layer 207 to reduce the possibility of reflected light generated by the photolithography process reaching the initial mask layer 207 during the formation of the patterned photoresist using the photolithography process, and to act as a mask.

[0043] The graphics layer 209 may include a plurality of first graphics 214 located in the array region 23 and the core region 24 separated by a first opening 210, and a plurality of second graphics 215 located in the peripheral region 22 separated by a second opening 211.

[0044] Since the width of the peripheral region 22 is greater than the width of the array region 23 and the width of the core region 24 along the first direction X, to ensure the accuracy of the pattern layer 209 during the exposure stage of the photolithography process, the width of the first opening 210 can be smaller than the width of the second opening 211 along the first direction X. This facilitates the formation of the first pattern 214 and the second pattern 215 with the target width. It is understood that the width of the first pattern 214 formed along the first direction X is smaller than the width of the second pattern 215, which in turn causes the width of the subsequently formed first mask pattern to be smaller than the width of the second mask pattern.

[0045] Along the first direction X, the width of the first pattern 214 can be in the range of 30nm to 50nm, for example, the width of the first pattern 214 can be 30nm, 40nm or 50nm, and the width of the second pattern 215 can be in the range of 100nm to 300nm, for example, the width of the second pattern 215 can be 100nm, 200nm or 300nm.

[0046] Along the first direction X, the width of the first opening 210 ranges from 50nm to 80nm. For example, the width of the first opening 210 can be 50nm, 60nm, or 70nm. The width of the second opening 211 ranges from 120nm to 330nm. For example, the width of the second opening 211 can be 120nm, 200nm, or 300nm.

[0047] In other embodiments, the width of the first opening 210 along the first direction X may also be equal to the width of the second opening 211.

[0048] It is also understandable that the graphics layer 209 can also cover the initial mask layer 207 on the intermediate area 25.

[0049] refer to Figure 10 Using the pattern layer 209 as a mask, the initial mask layer 207 is patterned along the first opening 210 and the second opening 211. The remaining initial mask layers 207 respectively form a first mask pattern 216 located in the storage area 21 and a second mask pattern 217 located in the peripheral area 22. In this way, by forming multiple discrete first mask patterns 216 in the storage area 21 and multiple discrete second mask patterns 217 in the peripheral area 22, the difference in mask pattern density between the two areas can be reduced, thereby reducing the thickness difference of the subsequently formed filling layer in the storage area 21 and the peripheral area 22.

[0050] Along the first direction X, the width of the first mask pattern 216 is smaller than the width of the second mask pattern 217.

[0051] In some embodiments, along the first direction X, the width of the first mask pattern 216 may be equal to the width of the second mask pattern 217, and the spacing of the first mask pattern 216 may be the same as the spacing of the second mask pattern 217, thereby facilitating exposure.

[0052] Along the first direction X, the width of the first mask pattern 216 can be in the range of 30nm to 50nm. For example, the width of the first mask pattern 216 can be 30nm, 40nm or 50nm. The width of the second mask pattern 217 can be in the range of 100nm to 300nm. For example, the width of the second mask pattern 217 can be 100nm, 200nm or 300nm.

[0053] Continue to refer to Figure 10 A third mask pattern 218 is also formed between the first mask pattern 216 adjacent to the outer perimeter area 22 and the second mask pattern 217 adjacent to the storage area 21.

[0054] Specifically, the pattern layer 209 can also cover the initial mask layer 207 of the intermediate area 25 (see reference). Figure 8 During the etching process of the initial mask layer 207, the initial mask layer 207 located on the intermediate region 25 is also etched to form the third mask pattern 218.

[0055] The width of the third mask pattern 218 can be in the range of 550nm to 600nm. For example, the width of the third mask pattern 218 can be 550nm, 580nm or 600nm. Within this width range, the width of the third mask pattern 218 is relatively large. Since in the subsequent step of etching part of the substrate 201 using the first mask pattern 216, the second mask pattern 217 and the fill layer as masks, a mask plate needs to be set on the first mask pattern 216, the second mask pattern 217 and the fill layer to transfer the pattern on the first mask pattern 216, the second mask pattern 217 and the fill layer to the substrate 201 for exposure process transfer, the setting of the third mask pattern 218 with a larger width can prevent the pattern of the first mask pattern 216 located on the core region 24 from shifting to the peripheral region 22.

[0056] It is understandable that, along the first direction X, the width of the third mask pattern 218 is equal to the width of the intermediate region 25. For example, along the first direction X, the width of the intermediate region 25 can be 600nm, and the width of the third mask pattern 218 can be 600nm.

[0057] Since the width of the intermediate region 25 is greater than the width of the first mask pattern 216 along the first direction X, and the width of the intermediate region 25 is also greater than the width of the second mask pattern 217, the width of the third mask pattern 218 can be greater than the width of the first mask pattern 216, and the width of the third mask pattern 218 can also be greater than the width of the second mask pattern 217.

[0058] Subsequent steps may also include forming sidewalls that at least cover the sidewalls of the first mask pattern 216 and the sidewalls of the second mask pattern 217. Understandably, the pattern layer 209 needs to be removed before forming the sidewalls.

[0059] refer to Figure 11 A sidewall 219 is formed, which at least covers the sidewalls of the first mask pattern 216 and the second mask pattern 217. Thus, the position of the filling layer to be filled in subsequent steps and its width along the first direction X can be located by the position of the sidewall 219, and the width of the filling layer between adjacent openings 208 along the first direction X can be precisely controlled by controlling the thickness of the formed sidewall 219.

[0060] In some embodiments, the step of forming the sidewall 219 may include: forming the sidewall 219, wherein the formed sidewall 219 may cover the substrate 201, the side and top surfaces of the first mask pattern 216 and the side and top surfaces of the second mask pattern 217.

[0061] The sidewall 219 can be made of silicon oxide or silicon nitride.

[0062] The material of the sidewall 219 can be the same as the material of the layer to be etched 206. For example, the material of the layer to be etched 206 can be silicon oxide, and the material of the sidewall 219 can also be silicon oxide.

[0063] The thickness of the sidewall 219 can range from 10 nm to 15 nm. For example, the thickness of the sidewall 219 can be 10 nm, 13 nm or 15 nm.

[0064] Understandably, in order to ensure that the width of the filling layer in the storage area 211 within the gap between adjacent sidewalls 219 along the first direction X is equal to the width of the first mask pattern 216, and the width of the filling layer in the peripheral area 22 within the gap between adjacent sidewalls 219 is equal to the width of the second mask pattern 217, the thickness of the formed sidewalls 219 can be controlled based on the width range of the first opening 210 and the second opening 211. For example, along the first direction X, the width of the first mask pattern 216 can be 30 nm, the width of the first opening 210 can be 50 nm, the width of the second mask pattern 217 can be 100 nm, the width of the second opening 211 can be 120 nm, and correspondingly, the thickness of the sidewall 219 can be 10 nm. As another example, along the first direction X, the width of the first mask pattern 216 can be 40 nm, the width of the first opening 210 can be 64 nm, the width of the second mask pattern 217 can be 120 nm, the width of the second opening 211 can be 144 nm, and correspondingly, the thickness of the sidewall 219 can be 12 nm.

[0065] It is also understood that the sidewalls 219 located on the substrate 201, the top surface of the first mask pattern 216 and the top surface of the second mask pattern 217 can be etched away before the filling layer is formed in subsequent steps. The remaining sidewalls 219 located on the sidewalls of the first mask pattern 216 and the sidewalls of the second mask pattern 217 can control the position of the filling layer and its width along the first direction X.

[0066] refer to Figure 12 A filling layer 220 is formed, which can cover the top surface of the first mask pattern 216 and the top surface of the second mask pattern 217, and also fill the gap between adjacent sidewalls 219. The thickness of the filling layer 220 in the storage area 21 is equal to the thickness of the filling layer 220 in the peripheral area 22.

[0067] It is understandable that, since the aforementioned steps form the first mask pattern 216 and the second mask pattern 217, the difference in mask pattern density between the storage region 21 and the peripheral region 22 is small, and the first mask pattern 216 and the second mask pattern 217 have the same height, after spin-coating the fill layer 220, and after baking and other treatments, the fill layer 220 shrinks uniformly across the entire substrate 201. This allows the thickness of the fill layer 220 in the storage region 21 to be equal to the thickness of the fill layer 220 in the peripheral region 22. Consequently, during the subsequent etching of the fill layer 220, the top surface of the first mask pattern 216 and the second mask pattern 217 will be etched together. The sidewalls 219 on the top surface of 217 can be completely exposed and removed. In addition, the thickness of the remaining fill layer 220 is relatively close to the height of the first mask pattern 216 and the second mask pattern 217. After etching part of the sidewalls 219 in the subsequent steps, there are still sidewalls 219 between the remaining fill layer 220 and the substrate 201. These sidewalls 219 can reduce the difference between the thickness of the fill layer 220 and the height of the first mask pattern 216 and the second mask pattern 217. Therefore, during the etching of part of the substrate 201 using the fill layer 220, the first mask pattern 216, and the second mask pattern 217 as masks, the phenomenon of insufficient etching or over-etching can be reduced.

[0068] The filler layer 220 can be made of SOH material.

[0069] The material of the filling layer 220 can be the same as that of the second initial mask layer 213. Since the first mask pattern 216 and the second mask pattern 217 are obtained by etching the first initial mask layer 212 and the second initial mask layer 213, in the subsequent step of etching away part of the substrate 201 using the filling layer 220, the first mask pattern 216 and the second mask pattern 217 as masks, the difference between the etching rate of the filling layer 220 and the etching rates of the first mask pattern 216 and the second mask pattern 217 is small. This reduces the possibility of under-etching or over-etching of the substrate 201, which is beneficial to improving the performance and yield of the formed semiconductor structure.

[0070] By controlling the width of the first opening 210, the width of the second opening 211, and the thickness of the sidewall 219 formed in the aforementioned embodiment, the width of the filling layer 220 located between adjacent first openings 210 along the first direction X can be equal to the width of the first mask pattern 216, and the width of the filling layer 220 located between adjacent second openings 211 can be equal to the width of the second mask pattern 216. Thus, in the subsequent step of etching away part of the substrate 201 using the filling layer 220, the first mask pattern 216, and the second mask pattern 217 as masks, it can be ensured that in the remaining substrate 201 after etching, the width of the portion located in the storage area 21 along the first direction X is equal to the width of the first mask pattern 216, and the width of the portion located in the peripheral area 22 is equal to the width of the second mask pattern 217.

[0071] It is understood that in the aforementioned steps, the formed sidewall 219 can cover the base 201, the side and top surfaces of the first mask pattern 216, and the side and top surfaces of the second mask pattern 217. Thus, the formed filling layer 220 can cover the sidewall 219 located on the base 201, the side and top surfaces of the first mask pattern 216, and the side and top surfaces of the second mask pattern 217.

[0072] It is also understandable that, due to the fluidity and adhesion of the SOH material, and because the width of the third mask pattern 218 along the first direction X can be greater than the width of the first mask pattern 216 and the width of the second mask pattern 217, the thickness of the filling layer 220 on the third mask pattern 218 can be greater than the thickness of the filling layer 220 on the top surface of the first mask pattern 216, and the thickness of the filling layer 220 on the third mask pattern 218 can be greater than the thickness of the filling layer 220 on the top surface of the second mask pattern 217. However, the difference in thickness among the three is small or close to zero. After etching the filling layer 220 in subsequent steps, the filling layer 220 on the top surface of the third mask pattern 218 can be completely removed, thereby exposing the sidewalls 219 on the third mask pattern 218, which can be removed in subsequent steps.

[0073] refer to Figure 13The fill layer 220 is etched to expose the top surfaces of the sidewalls 219, the first mask pattern 216, and the second mask pattern 219. This fully exposes the sidewalls 219 located on the top surfaces of the first mask pattern 216 and the second mask pattern 217. As a result, during the subsequent etching of part of the sidewalls 219, the sidewalls 219 located on the top surfaces of the first mask pattern 216 and the second mask pattern 217 can be exposed and completely removed simultaneously. The thickness difference of the remaining fill layer 220 on the storage area 21 and the peripheral area 22 is small, the thickness difference of the remaining fill layer 220 with the height difference of the first mask pattern 216 is small, and the thickness difference of the remaining fill layer 220 with the height difference of the second mask pattern 217 is small. This reduces the occurrence of insufficient or over-etching during the etching of part of the substrate 201.

[0074] In some embodiments, after etching the fill layer 220, the top surface of the third mask pattern 218 may be exposed.

[0075] It is understandable that, since the height of the filling layer 220 on the third mask pattern 218 can be greater than the height of the filling layer 220 on the top surface of the first mask pattern 216, and the height of the filling layer 220 on the third mask pattern 218 can be greater than the height of the filling layer 220 on the top surface of the second mask pattern 217, and since the height difference between the three is small, after etching, the sidewalls 219 on the top surfaces of the first mask pattern 216, the second mask pattern 217, and the third mask pattern 218 can all be completely exposed and can all be completely removed synchronously in subsequent steps.

[0076] Subsequent steps may also include etching away a portion of the substrate 201 using the fill layer 220, the first mask pattern 216, and the second mask pattern 217 as masks. Before etching away the portion of the substrate 201, a portion of the sidewalls 219 may also be removed. These sidewalls 219 include sidewalls 219 located on the top and side surfaces of the first mask pattern 216 and sidewalls 219 located on the top and side surfaces of the second mask pattern 217, to expose the top and side surfaces of the first mask pattern 216, the second mask pattern 216, and the top and side surfaces of the fill layer 220 in the opening 208.

[0077] refer to Figure 14Using the filling layer 220, the first mask pattern 216, and the second mask pattern 217 as masks, a portion of the substrate 201 is etched away. Since the height difference between the portion of the filling layer 220 located in the storage region 21 and the portion of the peripheral region 22 is small, and the height difference between the filling layer 220 and the first mask pattern 216 and the second mask pattern 217 is small, the possibility of insufficient or excessive etching of the substrate 201 is reduced during the etching process of removing a portion of the substrate 201.

[0078] Specifically, the step of etching a portion of the substrate 201 using the fill layer 220, the first mask pattern 216, and the second mask pattern 217 as masks may include: etching the layer to be etched 206 using the fill layer 220, the first mask pattern 216, and the second mask pattern 217 as masks, so that the remaining layer to be etched 206 in the storage region 21 forms a plurality of discrete first mask layers 221, and the remaining layer to be etched 206 in the peripheral region 22 forms a plurality of discrete second mask layers 222.

[0079] After etching the layer 206 to be etched, the process may further include: removing the filler layer 220, the sidewalls 219 located on the substrate 201, the first mask pattern 216, and the second mask pattern 217.

[0080] In the step of etching a portion of the substrate 201 using the filling layer 220, the first mask pattern 216, and the second mask pattern 217 as masks, it may further include: using the third mask pattern 218 as a mask to remove a portion of the substrate 201, that is, etching the layer 206 to be etched located in the intermediate region 25; after etching the layer 206 to be etched, the third mask pattern 218 may also be removed.

[0081] The semiconductor structure manufacturing method provided in the above embodiments forms a plurality of discrete first mask patterns 216 on the substrate 201 of the storage region 21 and a plurality of discrete second mask patterns 217 on the substrate 201 of the peripheral region 22. This reduces the difference in mask pattern density between the storage region 21 and the peripheral region 22, which helps to reduce the thickness difference between the portion of the filling layer 220 formed in the storage region 21 and the portion in the peripheral region 22 in subsequent steps. Furthermore, sidewalls 219 are formed on the sidewalls of the first mask patterns 216 and the second mask patterns 217. By controlling the thickness of the formed sidewalls 219, the width of the filling layer 220 subsequently formed between adjacent sidewalls 219 in the first direction X can be controlled. The positions of the first mask patterns 216, the second mask patterns 217, and the sidewalls 219 are used to position the filling layer 220 to be filled. At the filling location, the filling layer 220 is also etched to expose the sidewalls 219 on the top surface of the first mask pattern 216, the second mask pattern 217, and the third mask pattern 218. This reduces the thickness difference between the formed filling layer 220 and the first and second mask patterns 216 and 217, and exposes and removes the sidewalls 219 on the top surfaces of the first, second, and third mask patterns 216, 217, and 218. Thus, after etching the layer 206 using the first, second, third, and filling layers 220 as masks, the first mask layer 221 and the second mask layer 222 with equal heights can be obtained. This is beneficial for the subsequent normal process of the semiconductor structure, thereby improving the performance and yield of the formed semiconductor structure.

[0082] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of this disclosure. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of this disclosure; therefore, the scope of protection of this disclosure should be determined by the scope defined in the claims.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including a storage area and a peripheral area; An initial mask layer is formed on the substrate; The initial mask layer is etched so that the remaining initial mask layer in the storage area forms a plurality of discrete first mask patterns, and the remaining initial mask layer in the peripheral area forms a plurality of discrete second mask patterns. A sidewall is formed, the sidewall at least covering the sidewall of the first mask pattern and the sidewall of the second mask pattern; A filling layer is formed, which covers the top surface of the first mask pattern and the top surface of the second mask pattern, and also fills the gap between adjacent sidewalls. The thickness of the filling layer in the storage area is equal to the thickness of the filling layer in the peripheral area. The filling layer is etched to expose the top surface of the sidewall, the top surface of the first mask pattern, and the top surface of the second mask pattern; Remove a portion of the sidewalls, the portion of which includes the sidewalls located on the top and side surfaces of the first mask pattern and the sidewalls located on the top and side surfaces of the second mask pattern; Using the filling layer, the first mask pattern, and the second mask pattern as masks, a portion of the substrate is etched away.

2. The method for manufacturing a semiconductor structure as described in claim 1, characterized in that, The method for etching the initial mask layer includes: A patterned layer with openings is formed on the initial mask layer. The openings include a plurality of first openings located in the storage area and a plurality of second openings located in the peripheral area, wherein, along a first direction, the width of the first opening is smaller than the width of the second opening. Using the graphic layer as a mask, the initial mask layer is patterned along the first opening and the second opening, and the remaining initial mask layers respectively constitute the first mask pattern and the second mask pattern; Remove the graphics layer.

3. The method for manufacturing a semiconductor structure as described in claim 2, characterized in that, The width of the first opening ranges from 50nm to 80nm, and the width of the second opening ranges from 120nm to 330nm.

4. The method for manufacturing a semiconductor structure as described in claim 2, characterized in that, Along the first direction, the width of the first mask pattern formed is smaller than the width of the second mask pattern formed.

5. The method for manufacturing a semiconductor structure as described in claim 4, characterized in that, Along the first direction, the width of the first mask pattern ranges from 30nm to 50nm, and the width of the second mask pattern ranges from 100nm to 300nm.

6. The method for manufacturing a semiconductor structure as described in claim 1, characterized in that, The step of forming the sidewall includes: forming the sidewall, the sidewall covering the substrate, the side and top surfaces of the first mask pattern and the side and top surfaces of the second mask pattern.

7. The method for manufacturing a semiconductor structure as described in claim 1, characterized in that, The thickness of the sidewall ranges from 10 nm to 15 nm.

8. The method for manufacturing a semiconductor structure as described in claim 1, characterized in that, The substrate includes a layer to be etched; the step of etching a portion of the substrate using the filling layer, the first mask pattern, and the second mask pattern as masks includes: using the filling layer, the first mask pattern, and the second mask pattern as masks to etch the layer to be etched, so that the remaining layer to be etched in the storage area constitutes a plurality of discrete first mask layers, and the remaining layer to be etched in the peripheral area constitutes a plurality of discrete second mask layers.

9. The method for manufacturing a semiconductor structure as described in claim 8, characterized in that, The material of the sidewall is the same as the material of the layer to be etched.

10. The method for manufacturing a semiconductor structure as described in claim 1, characterized in that, After etching a portion of the substrate using the filling layer, the first mask pattern, and the second mask pattern as masks, the method further includes: removing the filling layer, the sidewalls located on the substrate, the first mask pattern, and the second mask pattern.

11. The method for manufacturing a semiconductor structure as described in claim 2, characterized in that, A third mask pattern is also formed between the first mask pattern adjacent to the peripheral area and the second mask pattern adjacent to the storage area; The step of etching a portion of the substrate using the filling layer, the first mask pattern, and the second mask pattern as masks further includes: removing a portion of the substrate using the third mask pattern as a mask; Remove the third mask pattern.

12. The method for manufacturing a semiconductor structure as described in claim 11, characterized in that, Along the first direction, the width of the third mask pattern is greater than the width of the first mask pattern.

13. The method for manufacturing a semiconductor structure as described in claim 11, characterized in that, Along the first direction, the width of the third mask pattern ranges from 550 nm to 600 nm.

14. The method for manufacturing a semiconductor structure as described in claim 1, characterized in that, The initial mask layer includes a first initial mask layer and a second initial mask layer, wherein the second initial mask layer is formed between the first initial mask layer and the substrate.

15. The method for manufacturing a semiconductor structure as described in claim 14, characterized in that, The material of the filling layer is the same as the material of the second initial mask layer.

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