Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a forming method thereof, comprising: providing a substrate, the substrate comprising a base and a fin on the base, the fin comprising a buried region, a sacrifice region on the buried region, and a reserved region on the sacrifice region, the buried region, the sacrifice region and the reserved region being of the same material; and performing a modification treatment on the sacrifice region to form a sacrifice layer, the sacrifice layer being of a different material from the reserved region. Since the buried region, the sacrifice region and the reserved region of the fin are of the same material, the process difficulty in etching the fin can be effectively reduced, and the manufacturing process is simple and the manufacturing cost is low. After the fin is formed, the modification treatment is performed on the sacrifice region to form the sacrifice layer, and the sacrifice layer is of a different material from the reserved region, so that in the subsequent etching process for removing the sacrifice layer, the reserved region can be less damaged, and thus the performance of the finally formed semiconductor structure is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] Metal-oxide-semiconductor field-effect transistors (MOSFETs) are among the most important components in modern integrated circuits. The basic structure of a MOSFET includes: a semiconductor substrate; a gate structure located on the surface of the semiconductor substrate, the gate structure including: a gate dielectric layer located on the surface of the semiconductor substrate and a gate electrode layer located on the surface of the gate dielectric layer; and source and drain doped regions located in the semiconductor substrate on both sides of the gate structure.

[0003] With the further development of semiconductor technology and the shrinking of gate size, traditional fin field-effect transistors (FETs) face limitations in pinch-off current and increasing operating current. Specifically, traditional FETs control the channel only through three gate sides, and the channel region is limited to the area near the top surface and sidewalls of the fin. This is detrimental to gate control of the channel and results in a small volume of the channel region within the fin, limiting the increase in operating current. Therefore, a gate-all-around (GAA) MOSFET structure has been proposed. This structure allows for omnidirectional channel control by the gate, further reducing off-state current, while also increasing the volume of the channel region, thereby increasing the operating current of the GAA MOSFET.

[0004] In the industry, GAA (Glass Acrylic Aperture Structure) morphologies are broadly classified into two types: multilayer nanowires and multilayer nanosheets. At the same linewidth, multilayer nanowires can effectively reduce transistor off-state current, but they also reduce transistor operating current. Multilayer nanosheets can effectively reduce transistor off-state current and also effectively increase transistor operating current, but they require a wider active region, which is detrimental to chip miniaturization. Furthermore, the fabrication process for multilayer GAA structures still faces many challenges. Summary of the Invention

[0005] The technical problem solved by this invention is to provide a semiconductor structure and a method for forming the same, which can effectively improve the performance of the final semiconductor structure and reduce the width of the active region by using vertical nanosheets, thereby achieving chip miniaturization.

[0006] To address the aforementioned problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a base and a fin located on the base, the fin including a buried region, a sacrificial region located on the buried region, and a reserved region located on the sacrificial region, wherein the buried region, the sacrificial region, and the reserved region are made of the same material; and modifying the sacrificial region to form a sacrificial layer, wherein the material of the sacrificial layer is different from the material of the reserved region.

[0007] Optionally, the method of forming the substrate includes: providing an initial substrate; forming a patterned layer on the initial substrate, the patterned layer exposing a portion of the top surface of the initial substrate; and etching the initial substrate using the patterned layer as a mask to form the substrate.

[0008] Optionally, the patterning layer includes an etch stop layer and a mask layer located on the etch stop layer.

[0009] Optionally, before modifying the sacrificial region, the method further includes: forming an isolation material film on the substrate, the isolation material film covering the fin and a patterned layer located on the top surface of the fin; planarizing the isolation material film until the etch stop layer is exposed to form the isolation material layer; and etching back the isolation material layer to form an initial isolation layer, the initial isolation layer covering the sidewalls of the buried region and the sacrificial region.

[0010] Optionally, the method for modifying the sacrificial region to form a sacrificial layer includes: forming a protective layer on the sidewall of the reserved region; etching back the initial isolation layer to form an isolation layer, the isolation layer covering the sidewall of the buried region; forming a semiconductor layer on the exposed sidewall of the sacrificial region, the semiconductor layer containing semiconductor ions; and annealing the semiconductor layer to allow the semiconductor ions to diffuse into the sacrificial region to form a sacrificial layer.

[0011] Optionally, the method for forming the protective layer includes: forming a protective material layer on the initial isolation layer, the etch stop layer, and the sidewalls of the reserved area; and etching back the protective material layer until the top surfaces of the etch stop layer and the initial isolation layer are exposed to form the protective layer.

[0012] Optionally, the process for forming the protective material layer includes atomic layer deposition.

[0013] Optionally, the method for forming the semiconductor layer includes: forming an epitaxial layer on the sidewall of the sacrificial region using an epitaxial growth process; and doping the semiconductor ions during the formation of the epitaxial layer to form the semiconductor layer.

[0014] Optionally, the thickness of the semiconductor layer is 30 angstroms to 50 angstroms.

[0015] Optionally, the semiconductor layer is made of silicon-germanium, and the semiconductor ions include germanium ions.

[0016] Optionally, the annealing temperature is 650°C to 750°C; the annealing time is 20 minutes to 40 minutes.

[0017] Optionally, the material of the sacrificial layer includes silicon germanium.

[0018] Optionally, the materials of the protective layer and the etch stop layer include silicon nitride.

[0019] Optionally, after forming the sacrificial layer, the method further includes: forming a pseudo-gate structure across the fin on the substrate, the pseudo-gate structure covering a portion of the sidewalls and top surface of the fin; forming source / drain doped layers within the fins on both sides of the pseudo-gate structure; and forming a dielectric layer on the substrate, the dielectric layer covering the sidewalls of the pseudo-gate structure.

[0020] Optionally, after forming the dielectric layer, the method further includes: removing the dummy gate structure and forming a gate opening within the dielectric layer; removing the gate opening to expose the sacrificial layer and forming a gate trench between adjacent reserved regions and buried regions; and forming a gate structure within the gate opening and the gate trench, the gate structure surrounding the reserved regions.

[0021] Accordingly, the present invention also provides a semiconductor structure, comprising: a substrate, the substrate including a base and fins located on the base, the fins including a buried region and a reserved region located on the buried region, a gate trench between the buried region and the reserved region; an isolation layer located on the substrate, the isolation layer covering the sidewalls of the buried region, and the top surface of the isolation layer being lower than the top surface of the reserved region, the top surface of the isolation layer being flush with the bottom of the gate trench; inner sidewalls located at both ends of the gate trench; a gate structure located on the substrate and within the gate trench, the gate structure surrounding the reserved region; source / drain doped layers located within the fins on both sides of the gate structure, the outer surfaces of the inner sidewalls and the outer surfaces of the reserved region being perpendicular to the outer surfaces of the source / drain doped layers.

[0022] Optionally, the gate structure includes: a high-k dielectric layer, a work function layer located on the high-k dielectric layer, and a metal electrode layer located on the work function layer.

[0023] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0024] In the method for forming the technical solution of the present invention, the buried region, sacrificial region, and retained region of the fin are made of the same material, which can effectively reduce the process difficulty in the etching process of forming the fin, and the manufacturing process is simple and the process cost is also low. After forming the fin, the sacrificial region is modified to form a sacrificial layer, and the material of the sacrificial layer is different from that of the retained region, so as to ensure that the retained region is less damaged during the subsequent etching process to remove the sacrificial layer, thereby improving the performance of the finally formed semiconductor structure. Attached Figure Description

[0025] Figure 1 and Figure 2 This is a schematic diagram of a semiconductor structure.

[0026] Figures 3 to 21 This is a schematic diagram of the steps in an embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0027] As described in the background section, there are still many problems in the fabrication process of multilayer GAA structures. These will be explained in detail below with reference to the accompanying drawings.

[0028] Please refer to Figure 1 The method includes: providing a substrate 100; forming a fin material film on the substrate 100, the fin material film including a plurality of sacrificial material films 101 overlapping along the normal direction of the surface of the substrate 100, and a channel material film 102 located between two adjacent sacrificial material films 101, wherein the sacrificial material film 101 and the channel material film 102 are made of different materials.

[0029] Please refer to Figure 2 A patterned layer 103 is formed on the fin material film; the patterned layer 103 is used as a mask to etch the fin material film, and a plurality of mutually independent fins are formed on the substrate 100. The fins include a plurality of sacrificial layers 104 that overlap along the normal direction of the surface of the substrate 100, and a channel layer 105 located between two adjacent sacrificial layers 104.

[0030] In this embodiment, during the etching of the fin material film using the patterned layer 103 as a mask, the etching rates differ between the sacrificial material film 101 and the channel material film 102 due to their different materials, thus increasing the difficulty of etching the fin material film. Furthermore, the fin material film has a multi-layered structure, requiring multiple deposition processes to form, resulting in complex manufacturing processes and high costs.

[0031] Based on this, the present invention provides a semiconductor structure and its formation method. The buried region, sacrificial region, and retained region of the fin are made of the same material, which effectively reduces the process difficulty during the etching process of the fin, and the fabrication process is simple and cost-effective. After forming the fin, the sacrificial region is modified to form a sacrificial layer, and the material of the sacrificial layer is different from that of the retained region. This ensures that the retained region is minimally damaged during the subsequent etching process to remove the sacrificial layer, thereby improving the performance of the final semiconductor structure.

[0032] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0033] Figures 3 to 21 This is a schematic diagram of the formation process of a semiconductor structure according to an embodiment of the present invention.

[0034] Please refer to Figure 3 and Figure 4 , Figure 3 It is a 3D diagram of a semiconductor structure. Figure 4 yes Figure 3 A schematic cross-sectional view along line AA shows a substrate, which includes a base 200 and fins on the base 200. The fins include a buried region 201, a sacrificial region 202 on the buried region 201, and a retention region 203 on the sacrificial region 202. The buried region 201, the sacrificial region 202, and the retention region 203 are made of the same material.

[0035] In this embodiment, the method for forming the substrate includes: providing an initial substrate (not shown); forming a patterned layer on the initial substrate, the patterned layer exposing a portion of the top surface of the initial substrate; and etching the initial substrate using the patterned layer as a mask to form the substrate.

[0036] In this embodiment, the patterning layer includes an etch stop layer 204 and a mask layer 205 located on the etch stop layer 204.

[0037] In this embodiment, the etching stop layer 204 is made of silicon nitride.

[0038] In this embodiment, the substrate 200 is made of silicon; in other embodiments, the substrate may also be made of germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide.

[0039] In this embodiment, the fin is made of silicon; in other embodiments, the fin may also be made of germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide.

[0040] In this embodiment, the buried area 201, the sacrificial area 202, and the retained area 203 of the fin are made of the same material, which can effectively reduce the process difficulty in the etching process of the fin, and the manufacturing process is simple and the manufacturing cost is low.

[0041] Please refer to Figure 5 , Figure 5 and Figure 4 With the view orientation consistent, an isolation material film 206 is formed on the substrate, the isolation material film 206 covering the fin and the patterned layer covering the top surface of the fin.

[0042] In this embodiment, the insulating material film 206 is used to form an insulating layer, which serves to isolate adjacent fins, thereby reducing the problem of leakage current in adjacent fins.

[0043] The insulating material 206 is made of an insulating material. In this embodiment, the insulating material 206 is made of silicon oxide.

[0044] Please refer to Figure 6 The isolation material film 206 is planarized until the etching stop layer 204 is exposed, thus forming the isolation material layer 207.

[0045] In this embodiment, the planarization process for the isolation material film 206 is performed using a chemical mechanical masking process.

[0046] In this embodiment, the purpose of retaining the etching stop layer 204 is to protect the top surface of the fin from etching damage during subsequent etching processes.

[0047] Please refer to Figure 7 The isolation material layer 207 is etched back to form an initial isolation layer 208, which covers the sidewalls of the burial area 201 and the sacrificial area 202.

[0048] In this embodiment, the etching process for etching back the isolation material layer 207 is a wet etching process; in other embodiments, the etching process for etching back the isolation material layer can also be a dry etching process.

[0049] After forming the initial isolation layer 207, the process further includes: modifying the sacrificial region 202 to form a sacrificial layer, wherein the material of the sacrificial layer is different from the material of the retaining region 203. Please refer to [reference needed for details]. Figures 8 to 11 .

[0050] Please refer to Figure 8 A protective layer 209 is formed on the sidewall of the reserved area 203.

[0051] In this embodiment, the method for forming the protective layer 209 includes: forming a protective material layer (not shown) on the initial isolation layer 208, the etch stop layer 204, and the sidewall of the retention area 203; and etching the protective material layer back until the top surfaces of the etch stop layer 204 and the initial isolation layer 208 are exposed to form the protective layer 209.

[0052] In this embodiment, the protective material layer is formed using atomic layer deposition (ALD).

[0053] In this embodiment, the protective layer 209 is made of silicon nitride.

[0054] Please refer to Figure 9 The initial isolation layer 208 is etched back to form an isolation layer 210, which covers the sidewall of the burial area 201.

[0055] In this embodiment, the reserved area 203 and the buried area 201 of the fin are covered by the protective layer 209 and the isolation layer 210, respectively, thus ensuring that in the subsequent modification process, only the sacrificial area 202 is modified, reducing the impact on the reserved area 203 and the buried area 201.

[0056] In this embodiment, the etching process for etching back the initial isolation layer 208 is a wet etching process; in other embodiments, the etching process for etching back the initial isolation layer can also be a dry etching process.

[0057] Please refer to Figure 10 A semiconductor layer 211 is formed on the sidewall of the exposed sacrificial region 202, and semiconductor ions are present in the semiconductor layer 211.

[0058] In this embodiment, the method for forming the semiconductor layer 211 includes: forming an epitaxial layer (not shown) on the sidewall of the sacrificial region 202 using an epitaxial growth process; and doping the semiconductor ions during the formation of the epitaxial layer to form the semiconductor layer 211.

[0059] In this embodiment, the thickness of the semiconductor layer 211 is 30 angstroms to 50 angstroms, and the thickness direction is perpendicular to the sidewall of the fin.

[0060] In this embodiment, the semiconductor layer 211 is made of silicon-germanium, and the semiconductor ions are germanium ions.

[0061] Please refer to Figure 11 The semiconductor layer 211 is annealed to allow semiconductor ions to diffuse into the sacrificial region 202 to form a sacrificial layer 212.

[0062] In this embodiment, the process parameters for the annealing treatment include: annealing temperature of 650 degrees Celsius to 750 degrees Celsius; and annealing time of 20 minutes to 40 minutes.

[0063] In this embodiment, the annealing process is used to allow the semiconductor ions to diffuse into the sacrificial region 202 under high temperature, thereby forming the sacrificial layer 212 in the sacrificial region 202.

[0064] In this embodiment, the material of the sacrificial layer 212 includes silicon germanium.

[0065] In this embodiment, the purpose of forming the sacrificial layer 212 is to facilitate its removal during subsequent etching processes by using materials different from those of the reserved region 203. This allows the reserved region 203 to serve as the channel region of the final gate all-around (GAA) transistor, increasing the channel region's volume and further increasing the operating current of the GAA transistor.

[0066] Please continue to refer to this. Figure 11 After the sacrificial layer 212 is formed, the method further includes: removing the protective layer 209 and the etch stop layer 204.

[0067] Please refer to Figures 12 to 14 , Figure 12 This is a top view of the semiconductor structure. Figure 13 yes Figure 12 Schematic diagram of the cross section along line BB. Figure 14 yes Figure 12 A schematic cross-sectional view along the CC line shows that after the sacrificial layer 212 is formed, a pseudo-gate structure 213 is formed on the substrate that spans the fin. The pseudo-gate structure 213 covers part of the sidewalls and top surface of the fin.

[0068] In this embodiment, the pseudo-gate structure 213 includes: a pseudo-gate dielectric layer located on the fin, a pseudo-gate layer located on the pseudo-gate dielectric layer, and a sidewall (not shown) located on the sidewall of the pseudo-gate layer.

[0069] In this embodiment, the dummy gate layer is made of polycrystalline silicon; in other embodiments, the dummy gate layer may also be made of amorphous silicon.

[0070] The method for forming the sidewall includes: forming a sidewall material layer (not shown) on the top surface of the pseudo-gate dielectric layer, the sidewall of the pseudo-gate layer, and the sidewall and top surface of the protective layer; and etching the sidewall material layer back until the top surface of the pseudo-gate dielectric layer is exposed to form the sidewall.

[0071] The sidewall material layer is formed using one or more combinations of chemical vapor deposition, physical vapor deposition, or atomic layer deposition. In this embodiment, the sidewall material layer is formed using atomic layer deposition.

[0072] The sidewall material includes silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonate, silicon carbonitride, or silicon carbonitride. In this embodiment, the sidewall material is silicon nitride.

[0073] In this embodiment, the sidewall is used to define the location of the subsequent source / drain doped layers.

[0074] Please refer to Figure 15 , Figure 15 and Figure 14 With the view direction consistent, source and drain grooves 214 are formed in the fins on both sides of the pseudo-gate structure 213.

[0075] In this embodiment, the method for forming the source / drain groove 214 includes: etching the fin using the pseudo-gate structure 213 as a mask, and forming the source / drain groove 214 in the fin on both sides of the pseudo-gate structure 213.

[0076] In this embodiment, the source / drain groove 214 serves to provide space for the subsequently formed source / drain doped layer.

[0077] Please refer to Figure 16 The portion of the sacrificial layer 212 exposed on the sidewall of the source drain groove 214 is etched to form a fin groove 215 between the retention area 203 and the burial area 201.

[0078] In this embodiment, the function of the fin groove 215 is to provide space for the subsequently formed inner sidewall.

[0079] Please refer to Figure 17 An inner sidewall 216 is formed within the fin groove 215.

[0080] In this embodiment, the method for forming the inner sidewall 216 includes: forming a first initial inner sidewall (not shown) on the sidewall and bottom surface of the source / drain groove 215 and the sidewall and top surface of the pseudo-gate structure 213; etching back the first initial inner sidewall until the bottom surface of the source / drain groove 215 and the top surface of the pseudo-gate structure 213 are exposed, forming a second initial inner sidewall (not shown); etching back the second initial inner sidewall until the sidewall of the reserved area 203 is exposed, forming the inner sidewall 216.

[0081] In this embodiment, the inner wall 216 is made of silicon nitride.

[0082] The process for forming the first initial inner wall includes physical vapor deposition, chemical vapor deposition, or atomic layer deposition. In this embodiment, atomic layer deposition is used to form the first initial inner wall.

[0083] In this embodiment, the inner wall 216 can effectively isolate the subsequently formed gate structure and source / drain doped layers, preventing leakage problems between the gate structure and the source / drain doped layers.

[0084] Please refer to Figure 18 After the inner sidewall 216 is formed, a source / drain doped layer 217 is formed in the source / drain groove 214.

[0085] In this embodiment, the source / drain doped layer 217 contains source / drain ions; the formation process of the source / drain doped layer 217 includes an epitaxial growth process; and the process of doping source / drain ions in the source / drain doped layer 217 includes an in-situ doping process.

[0086] When the semiconductor structure is a P-type device, the material of the source / drain doped layer 217 includes silicon, germanium, or silicon-germanium; the source / drain ions are P-type ions, including boron ions and BF ions. 2- The source / drain doped layer 217 is made of silicon, gallium arsenide, or indium gallium arsenide when the semiconductor structure is an N-type device; the source / drain ions are N-type ions, including phosphorus ions or arsenic ions.

[0087] In this embodiment, the semiconductor structure is an N-type device, the source / drain doped layer 217 is made of silicon, and the source / drain ions are phosphorus ions.

[0088] Please refer to Figure 19 A dielectric layer 218 is formed on the substrate, and the dielectric layer 218 covers the sidewalls of the pseudo-gate structure.

[0089] In this embodiment, the method for forming the dielectric layer 218 includes: forming an initial dielectric layer (not shown) on the source / drain doped layer 217 and the dummy gate structure 213, the initial dielectric layer covering the top surface and sidewall surface of the dummy gate structure 213; planarizing the initial dielectric layer until the top of the dummy gate structure 213 is exposed, thereby forming the dielectric layer 218.

[0090] In this embodiment, the dielectric layer 218 is made of silicon oxide.

[0091] Please refer to Figure 20 Remove the pseudo-gate structure 213 and form a gate opening 219 in the dielectric layer 218.

[0092] In this embodiment, the pseudo-gate dielectric layer and pseudo-gate layer of the pseudo-gate structure 213 are specifically removed.

[0093] Please refer to Figure 21 Remove the gate opening 219 to expose the sacrificial layer 212, and form a gate trench (not shown) between the reserved region 203 and the buried region 201; form a gate structure 220 in the gate opening 219 and the gate trench, the gate structure 220 surrounding the reserved region 203.

[0094] In this embodiment, by forming a vertical nanosheet GAA structure, both the off-state current of the transistor and the operating current of the transistor can be effectively reduced. Simultaneously, the vertical nanosheet GAA structure can also reduce the width of the active region, enabling chip miniaturization.

[0095] In this embodiment, the gate structure 220 includes: a high-k dielectric layer, a work function layer, and a metal electrode layer (not shown).

[0096] The material of the metal electrode layer includes one or more combinations of copper, tungsten, nickel, chromium, titanium, tantalum, and aluminum. In this embodiment, the material of the metal electrode layer is tungsten.

[0097] Accordingly, an embodiment of the present invention also provides a semiconductor structure, please refer to [link / reference needed]. Figure 21 The system includes: a substrate, the substrate including a base 200 and fins located on the base 200, the fins including a buried region and a reserved region 203 located on the buried region 201, a gate trench (not shown) between the buried region 201 and the reserved region 203; an isolation layer 210 located on the substrate, the isolation layer 210 covering the sidewalls of the buried region 201, and the top surface of the isolation layer 210 being lower than the top surface of the reserved region 203, the top surface of the isolation layer 210 being flush with the bottom of the gate trench; inner sidewalls 216 located at both ends of the gate trench; a gate structure 220 located on the substrate and within the gate trench, the gate structure 220 surrounding the reserved region 203; source / drain doped layers 217 located within the fins on both sides of the gate structure 220, the outer surfaces of the inner sidewalls 216 and the outer surfaces of the reserved region 203 sharing a common vertical plane with the outer surfaces of the source / drain doped layers 217.

[0098] In this embodiment, the gate structure 220 includes: a high-k dielectric layer, a work function layer located on the high-k dielectric layer, and a metal electrode layer (not shown) located on the work function layer.

[0099] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including a base and a fin located on the base, the fin including a buried region, a sacrificial region located on the buried region, and a retention region located on the sacrificial region, the buried region, the sacrificial region and the retention region being made of the same material; The sacrificial region is modified to form a sacrificial layer, the material of which is different from that of the retention region; A method for modifying the sacrificial region to form a sacrificial layer includes: forming a protective layer on the sidewall of the retained region; The initial isolation layer is etched back to form an isolation layer that covers the sidewall of the buried region; a semiconductor layer is formed on the exposed sidewall of the sacrificial region, and the semiconductor layer contains semiconductor ions; the semiconductor layer is annealed to allow the semiconductor ions to diffuse into the sacrificial region to form a sacrificial layer.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The method for forming the substrate includes: providing an initial substrate; forming a patterned layer on the initial substrate, the patterned layer exposing a portion of the top surface of the initial substrate; and etching the initial substrate using the patterned layer as a mask to form the substrate.

3. The method for forming a semiconductor structure as described in claim 2, characterized in that, The patterning layer includes an etch stop layer and a mask layer located on the etch stop layer.

4. The method for forming a semiconductor structure as described in claim 3, characterized in that, Before modifying the sacrificial region, the method further includes: forming an isolation material film on the substrate, the isolation material film covering the fin and a patterned layer located on the top surface of the fin; planarizing the isolation material film until the etch stop layer is exposed to form the isolation material layer; and etching back the isolation material layer to form the initial isolation layer, the initial isolation layer covering the sidewalls of the buried region and the sacrificial region.

5. The method for forming a semiconductor structure as described in claim 1, characterized in that, The method for forming the protective layer includes: forming a protective material layer on the initial isolation layer, the etch stop layer, and the sidewalls of the reserved area; and etching back the protective material layer until the top surfaces of the etch stop layer and the initial isolation layer are exposed to form the protective layer.

6. The method for forming a semiconductor structure as described in claim 5, characterized in that, The process for forming the protective material layer includes atomic layer deposition.

7. The method for forming a semiconductor structure as described in claim 1, characterized in that, The method for forming the semiconductor layer includes: forming an epitaxial layer on the sidewall of the sacrificial region using an epitaxial growth process; and doping the semiconductor ions during the formation of the epitaxial layer to form the semiconductor layer.

8. The method for forming a semiconductor structure as described in claim 1, characterized in that, The thickness of the semiconductor layer is 30 to 50 angstroms.

9. The method for forming a semiconductor structure as described in claim 1, characterized in that, The semiconductor layer is made of silicon and germanium, and the semiconductor ions include germanium ions.

10. The method for forming a semiconductor structure as described in claim 1, characterized in that, The annealing process parameters include: annealing temperature of 650°C to 750°C; annealing time of 20 minutes to 40 minutes.

11. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the sacrificial layer includes silicon and germanium.

12. The method for forming a semiconductor structure as described in claim 1, characterized in that, The materials of the protective layer and the etch stop layer include silicon nitride.

13. The method for forming a semiconductor structure as described in claim 1, characterized in that, After forming the sacrificial layer, the method further includes: forming a pseudo-gate structure across the fin on the substrate, the pseudo-gate structure covering part of the sidewalls and top surface of the fin; forming source / drain doped layers in the fins on both sides of the pseudo-gate structure; and forming a dielectric layer on the substrate, the dielectric layer covering the sidewalls of the pseudo-gate structure.

14. The method for forming a semiconductor structure as described in claim 13, characterized in that, After forming the dielectric layer, the method further includes: removing the dummy gate structure and forming a gate opening within the dielectric layer; removing the gate opening to expose the sacrificial layer and forming a gate trench between adjacent reserved regions and buried regions; and forming a gate structure within the gate opening and the gate trench, the gate structure surrounding the reserved regions.

15. A semiconductor structure, characterized in that, include: A substrate, the substrate including a base and a fin located on the base, the fin including a buried region and a retained region located on the buried region, a gate trench being provided between the buried region and the retained region; An isolation layer is located on the substrate, the isolation layer covers the sidewall of the buried region, and the top surface of the isolation layer is lower than the top surface of the reserved region, and the top surface of the isolation layer is flush with the bottom of the gate trench; The inner walls located at both ends of the gate trench; A gate structure located on the substrate and within the gate trench, the gate structure surrounding the reserved region; The source and drain doped layers located in the fins on both sides of the gate structure have the outer side of the inner wall and the outer side of the reserved region sharing the same vertical plane as the outer side of the source and drain doped layers.

16. The semiconductor structure as described in claim 15, characterized in that, The gate structure includes: a high-k dielectric layer, a work function layer located on the high-k dielectric layer, and a metal electrode layer located on the work function layer.

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