Semiconductor devices, semiconductor integrated devices, and methods for manufacturing semiconductor devices

Abstract

This application discloses a semiconductor device, a semiconductor integrated device, and a method for manufacturing a semiconductor device. The semiconductor device includes a substrate; a dielectric layer on the substrate; and conductive channels within the dielectric layer. In the plane containing the cross-section of the conductive channel, the conductive channel forms a continuous first predetermined pattern around a portion of the dielectric layer, and the cross-section of the conductive channel is perpendicular to the thickness direction of the dielectric layer. By making the conductive channels within the dielectric layer continuous and surrounding a portion of the dielectric layer, this semiconductor device reduces the space occupied by the conductive channels while meeting the manufacturing process requirements.

Description

Technical Field

[0001] This invention relates to semiconductor technology, and more specifically, to a semiconductor device, a semiconductor integrated device, and a method for manufacturing a semiconductor device. Background Technology

[0002] The development trend of semiconductor technology is towards smaller feature sizes and higher integration density. For memory devices, the increase in storage density is closely related to advancements in semiconductor manufacturing processes. As the feature sizes of semiconductor manufacturing processes become smaller, the storage density of memory devices becomes higher.

[0003] To further increase storage density, three-dimensional memory devices (i.e., 3D memory devices) have been developed. These 3D memory devices comprise multiple memory cells stacked along a vertical direction, allowing for a significant increase in integration density on a unit wafer area while reducing costs. Furthermore, wafer bonding structures have been developed to bond the 3D memory device chip and the driver circuit chip together. These wafer bonding structures can improve the read / write speed of the memory device, while also increasing integration density, reducing device costs, and enhancing reliability.

[0004] In the above-described wafer bonding structure, the surfaces of the wafers that come into contact with each other are called bonding surfaces. After cleaning and activation treatment, the bonding surfaces of the wafers are made clean and flat. At least two wafers have their bonding surfaces in contact with each other, and under certain temperature and pressure conditions, the wafers are bonded together through molecular or atomic forces.

[0005] In existing technologies, to meet the requirements of electrostatic discharge (ESD), there is a minimum number of conductive vias between interconnects. If the number is too small, the total cross-sectional area of ​​the vias will be insufficient to handle the ESD current, causing the circuit to burn out. At the same time, due to process limitations, the distribution of multiple vias cannot be too dense. These two factors dictate that the vias must be distributed widely and in large numbers, increasing the space occupied by the vias. Since the vias must be completely covered by the interconnects, this leads to an increase in the interconnect area and an increase in the parasitic capacitance between the interconnects and other metals or substrates.

[0006] As 3D memory devices demand increasingly faster I / O response times, the parasitic capacitance caused by the large interconnect area of ​​I / O boards will become increasingly difficult to meet customer needs. Therefore, there is a desire to further improve wafer bonding processes to reduce interconnect area. Summary of the Invention

[0007] The purpose of this invention is to provide an improved semiconductor device, semiconductor integrated device, and semiconductor device manufacturing method, which reduces the space occupied by the conductive channels by setting the conductive channels in the dielectric layer to be continuous and also surrounding a portion of the dielectric layer, while meeting the manufacturing process conditions of the conductive channels.

[0008] According to a first aspect of the present invention, a semiconductor device is provided, comprising: a substrate; a dielectric layer on the substrate; and a conductive channel located within the dielectric layer; wherein, on a plane containing a cross-section of the conductive channel, the conductive channel forms a continuous first predetermined pattern around a portion of the dielectric layer, and the cross-section of the conductive channel is perpendicular to the thickness direction of the dielectric layer.

[0009] Optionally, the continuous first preset pattern is a closed pattern.

[0010] Optionally, the continuous first preset pattern includes a grid pattern. Optionally, it also includes interconnects located within the dielectric layer, the interconnects being longitudinally connected to the conductive channel, wherein, on the plane containing the cross-section of the interconnect, the interconnects form the continuous second preset pattern around a portion of the dielectric layer, and the cross-section of the interconnect is perpendicular to the thickness direction of the dielectric layer.

[0011] Optionally, the continuous second preset pattern has the same shape and position as the continuous first preset pattern, and the projection of the conductive channel is located within the projection of the interconnect in the thickness direction of the dielectric layer.

[0012] Optionally, the conductive channel is located above the interconnect line and exposed on the surface of the dielectric layer away from the substrate.

[0013] Optionally, the number of interconnects includes two, and the conductive path is located between the two interconnects.

[0014] According to a second aspect of the present invention, a semiconductor integrated device is provided, comprising: a first semiconductor device, including: a first dielectric layer; a first conductive channel located within the first dielectric layer, the first conductive channel being exposed on the surface of the first dielectric layer; a second semiconductor device, including: a second dielectric layer; a second conductive channel located within the second dielectric layer, the second conductive channel being exposed on the surface of the second dielectric layer; the first dielectric layer and the second dielectric layer are bonded together, and the first conductive channel and the second conductive channel are connected; wherein, on a plane containing the cross-section of the first conductive channel, the first conductive channel forms a continuous first preset pattern around a portion of the first dielectric layer, and / or on a plane containing the cross-section of the second conductive channel, the second conductive channel forms the continuous first preset pattern around a portion of the second dielectric layer, the cross-section of the first conductive channel being perpendicular to the thickness direction of the first dielectric layer, and the cross-section of the second conductive channel being perpendicular to the thickness direction of the second dielectric layer.

[0015] Optionally, the continuous first preset pattern is a closed pattern. Optionally, the continuous first preset pattern includes a crisscross pattern. Optionally, it further includes: a first interconnect line located within the first dielectric layer and longitudinally connected to the first conductive channel; and a second interconnect line located within the second dielectric layer and longitudinally connected to the second conductive channel, wherein, on the plane containing the cross-section of the first interconnect line, the first interconnect line surrounds a portion of the first dielectric layer to form the continuous second preset pattern, and the cross-section of the first interconnect line is perpendicular to the thickness direction of the first dielectric layer; on the plane containing the cross-section of the second interconnect line, the second interconnect line surrounds a portion of the second dielectric layer to form the continuous second preset pattern, and the cross-section of the second interconnect line is perpendicular to the thickness direction of the first dielectric layer.

[0016] Optionally, the continuous second preset pattern has the same shape and position as the continuous first preset pattern. In the thickness direction of the first dielectric layer, the projection of the first conductive channel is located within the projection of the first interconnect line, and in the thickness direction of the second dielectric layer, the projection of the second conductive channel is located within the projection of the second interconnect line.

[0017] Optionally, the second semiconductor device further includes: a second substrate, the second dielectric layer being located between the second substrate and the first dielectric layer; a third interconnect line located within the second dielectric layer, the third interconnect line being located on one side of the second conductive channel and laterally connected to the second interconnect line; a fourth interconnect line and a third conductive channel located within the second dielectric layer, the third conductive channel being located between the third interconnect line and the fourth interconnect line and longitudinally connected to the third interconnect line and the fourth interconnect line, respectively; a third dielectric layer located on the surface of the second substrate; a pad located within the third dielectric layer; and a fourth conductive channel located between the pad and the fourth interconnect line, the fourth conductive channel passing through the second substrate and longitudinally connected to the pad and the fourth interconnect line.

[0018] Optionally, on the plane where the cross-section of the third conductive channel is located, the third conductive channel forms a continuous third preset pattern around a portion of the second dielectric layer, and / or on the plane where the cross-section of the fourth conductive channel is located, the fourth conductive channel forms the continuous third preset pattern around a portion of the second dielectric layer, wherein the cross-section of the third conductive channel and the cross-section of the fourth conductive channel are both perpendicular to the thickness direction of the second dielectric layer.

[0019] Optionally, the first semiconductor device further includes a first substrate, and the first dielectric layer is located between the first substrate and the second substrate; the first semiconductor device includes peripheral circuit devices; and the second semiconductor device includes memory circuit devices.

[0020] Optionally, the first dielectric layer and the second dielectric layer are bonded. According to a third aspect of the present invention, a method for manufacturing a semiconductor device is provided, comprising:

[0021] A dielectric layer is formed on a substrate; and a conductive channel is formed through the dielectric layer, wherein, on the plane of the cross-section of the conductive channel, the conductive channel forms a continuous first predetermined pattern around a portion of the dielectric layer, and the cross-section of the conductive channel is perpendicular to the thickness direction of the dielectric layer.

[0022] Optionally, the continuous first preset pattern is a closed pattern.

[0023] Optionally, the continuous first preset pattern includes a grid pattern.

[0024] Optionally, it further includes forming interconnects located within the dielectric layer, the interconnects being longitudinally connected to the conductive channel, wherein, on the plane containing the cross-section of the interconnect, the interconnects form the continuous second preset pattern around a portion of the dielectric layer, and the cross-section of the interconnect is perpendicular to the thickness direction of the dielectric layer.

[0025] Optionally, the continuous second preset pattern has the same shape and position as the continuous first preset pattern, and the projection of the conductive channel is located within the projection of the interconnect in the thickness direction of the dielectric layer.

[0026] According to the semiconductor device, semiconductor integrated device, and semiconductor device manufacturing method of the present invention, a conductive channel is formed in the dielectric layer, and the pattern on the plane where the cross-section of the conductive channel is located is a continuous pattern. This conductive channel replaces multiple conductive vias in the prior art. When the volume of the conductive channel is the same as that of multiple conductive vias, the continuous conductive channel does not need to be dispersed, thereby reducing the space occupied by the conductive channel.

[0027] Furthermore, since the conductive channel surrounds part of the dielectric layer, the material distribution of the conductive channel and the dielectric layer is uniform when viewed from the plane where the cross-section of the conductive channel is located. This avoids problems such as dishing on the surface of the conductive channel during the planarization process after the conductive channel is formed.

[0028] Furthermore, by forming interconnects that are longitudinally connected to the conductive channels, and ensuring that the position and shape of the interconnects correspond to the conductive channels, the space occupied by the continuous conductive channels is reduced, and the area of ​​the corresponding interconnects is further reduced, thereby reducing the parasitic capacitance generated by the interconnects with other metals or substrates.

[0029] Therefore, the semiconductor device semiconductor integration apparatus and the semiconductor device manufacturing method according to embodiments of the present invention improve product yield and reliability. Attached Figure Description

[0030] The above and other objects, features and advantages of the present invention will become clearer from the following description of embodiments of the invention with reference to the accompanying drawings.

[0031] Figures 1a to 1c A schematic diagram of the structure of a semiconductor device according to a first embodiment of the present invention is shown.

[0032] Figure 2 A schematic diagram of the structure of a semiconductor device according to a second embodiment of the present invention is shown.

[0033] Figure 3 A schematic diagram of the structure of a semiconductor integrated device according to an embodiment of the present invention is shown.

[0034] Figures 4 to 9b A cross-sectional schematic diagram of different steps in the semiconductor device fabrication method according to the first embodiment of the present invention is shown.

[0035] Figure 10a and Figure 10bA schematic diagram illustrating the effect analysis of an embodiment of the present invention is shown. Detailed Implementation

[0036] The invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown. For simplicity, the semiconductor structure obtained after several steps can be depicted in a single figure.

[0037] It should be understood that when describing the structure of a device, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above another layer or region, or that there are other layers or regions between it and another layer or region. Furthermore, if the device is flipped, that layer or region will be located "below" or "under" another layer or region.

[0038] To describe a situation where it is located directly on another layer or another area, this article will use the expressions "directly on top of" or "on and adjacent to".

[0039] Many specific details of the invention, such as the structure, materials, dimensions, processing methods, and techniques of the devices, are described below to provide a clearer understanding of the invention. However, as those skilled in the art will understand, the invention may be implemented without following these specific details.

[0040] This invention can be presented in various forms, some of which will be described below.

[0041] Figure 1a A schematic diagram of the structure of a semiconductor device according to a first embodiment of the present invention is shown. Figure 1b It shows Figure 1a A cross-sectional view taken along line AA. Figure 1c It shows Figure 1a A cross-sectional view taken along line BB.

[0042] The semiconductor device includes a substrate 101, a dielectric layer 110, conductive channels 120, and interconnects 130. The dielectric layer 110 is located on the substrate 101, and the conductive channels 120 and interconnects 130 are vertically connected and both are located within the dielectric layer 110. For simplicity, in... Figure 1aThe functional layer located between the substrate and the dielectric layer is not shown. In this embodiment, the internal structure of the functional layer is related to the chip type, and the functional layer provides at least a portion of the transistor structure. For example, the source and drain regions of the transistor are formed in the substrate 101, and the gate stack structure of the transistor is formed in the functional layer. When the semiconductor device is a 3D memory circuit device, the gate stack structure in the functional layer includes multiple layers of gate conductor layers and multiple interlayer insulating layers for separating adjacent gate conductor layers, as well as channel pillars through the gate stack structure. When the semiconductor device is a driving circuit device, the gate stack structure in the functional layer includes, for example, a single layer of gate conductor layer.

[0043] In this embodiment, the conductive channel 120 is located above the interconnect 130 and exposed on the surface of the dielectric layer 110 away from the substrate 101, and can be used to connect to external circuitry of the semiconductor device. On the plane containing the cross-section (along line AA) of the conductive channel 120, the conductive channel 120 forms a continuous first predetermined pattern around a portion of the dielectric layer, such as... Figure 1b As shown, the cross-section of the conductive channel 120 is perpendicular to the thickness direction of the dielectric layer 110. In this embodiment, the first preset pattern is a closed grid pattern that surrounds the four regions of the dielectric layer 110. In some other embodiments, the closed first preset pattern can also be an O-shape or a square shape, etc.

[0044] However, the embodiments of the present invention are not limited thereto. Those skilled in the art can make other settings for the first preset pattern as needed, such as a semi-closed C-shaped pattern, a square pattern with one side removed, or an S-shaped, M-shaped, N-shaped, or other pattern surrounding a portion of the dielectric layer, or a combination of the above types of patterns, to ensure that the first preset pattern is a continuous pattern and surrounds a portion of the dielectric layer 110.

[0045] In this embodiment, on the plane containing the cross-section (along the BB line) of the interconnect 130, the interconnect 130 forms a continuous second preset pattern around a portion of the dielectric layer 110, such as... Figure 1c As shown, the cross-section of the interconnect 130 is perpendicular to the thickness direction of the dielectric layer 110. To ensure that the projection of the conductive channel 120 lies within the projection of the interconnect 130 along the thickness direction of the dielectric layer 110, the continuous second preset pattern has the same shape and corresponding position as the continuous first preset pattern. For example, when the first preset pattern is a closed grid pattern, the second preset pattern is also a closed grid pattern, and the lateral dimension of the second preset pattern is slightly larger than or equal to the lateral dimension of the first preset pattern. When the first preset pattern is another pattern, the second preset pattern is also changed accordingly.

[0046] Since the conductive channel 120 is continuous, with the same volume, the space occupied by the conductive channel 120 is smaller than that of dispersed conductive vias. Consequently, the area of ​​the corresponding interconnect 130 is further reduced, thereby lowering the parasitic capacitance C1 generated by the interconnect 130 with other metals or the substrate 101. It should be noted that... Figure 1a The parasitic capacitance C1 shown is merely an example and is not intended to limit the invention.

[0047] Figure 2 A schematic diagram of the structure of a semiconductor device according to a second embodiment of the present invention is shown, wherein the cross-sectional view taken along line AA and the cross-sectional view taken along line BB can be referred to respectively. Figure 1b and Figure 1c .

[0048] like Figure 2 As shown, the semiconductor device includes a substrate 201, a dielectric layer 210, a conductive channel 220, and interconnects. The dielectric layer 210 is located on the substrate 201, and the conductive channels 220 and interconnects are longitudinally connected and both are located within the dielectric layer 210. The structure of the semiconductor device in this embodiment is similar to that of the first embodiment, and will not be described in detail here. The difference from the first embodiment is that there are two interconnects in this embodiment, namely a first interconnect 231 and a second interconnect 232, and the conductive channel 220 is located between the two interconnects. The conductive channel 220, the first interconnect 231, and the second interconnect 232 can be used for interconnection of internal circuits of the semiconductor device. However, the embodiments of the present invention are not limited thereto, and those skilled in the art can make other settings for the number and position of interconnects and conductive channels as needed.

[0049] Figure 3 A schematic diagram of the structure of a semiconductor integrated device according to an embodiment of the present invention is shown.

[0050] like Figure 3 As shown, the semiconductor integrated device includes a first semiconductor device 10 and a second semiconductor device 20. The first semiconductor device 10 includes a first substrate 401, a first dielectric layer 410, a first conductive channel 421, and a first interconnect 431. The second semiconductor device 20 includes a second substrate 402, a second dielectric layer 420, a third dielectric layer 430, a second conductive channel 422, a third conductive channel 423, a fourth conductive channel 424, a second interconnect 432, a third interconnect 433, a fourth interconnect 434, and a pad 440. In this embodiment, the first semiconductor device 10 is a peripheral circuit device, and the second semiconductor device 20 is a storage circuit device. The relevant functional layer structures (not shown) in the first semiconductor device 10 and the second semiconductor device 20 can be referred to the description in the first embodiment, and will not be repeated here.

[0051] The first dielectric layer 410 is located on the first substrate 401. The first conductive channel 421 is longitudinally connected to the first interconnect 431 and is located within the first dielectric layer 410. The first conductive channel 421 is located above the first interconnect 431 and exposed on the surface of the first dielectric layer 410 away from the substrate 401. On the plane containing the cross-section of the first conductive channel 421, the first conductive channel 421 forms a continuous first preset pattern around a portion of the first dielectric layer 410. The first preset pattern can be referenced... Figure 1b The cross-section of the first conductive channel 421 is perpendicular to the thickness direction of the first dielectric layer 410. In this embodiment, the first preset pattern is a closed grid pattern that surrounds the four regions of the first dielectric layer 410. In some other embodiments, the closed first preset pattern can also be an O-shape or a square shape, etc.

[0052] However, the embodiments of the present invention are not limited thereto. Those skilled in the art can make other settings for the first preset pattern as needed, such as a semi-closed C-shaped pattern, a square pattern with one side removed, or an S-shaped, M-shaped, N-shaped, or other pattern surrounding a portion of the dielectric layer, or a combination of the above types of patterns, to ensure that the first preset pattern is a continuous pattern and surrounds a portion of the first dielectric layer 410.

[0053] On the plane containing the cross-section of the first interconnect 431, the first interconnect 431 forms a continuous second preset pattern around a portion of the first dielectric layer 410. The second preset pattern can be referred to as... Figure 1c In this configuration, the cross-section of the first interconnect 431 is perpendicular to the thickness direction of the first dielectric layer 410. To ensure that the projection of the first conductive channel 421 lies within the projection of the first interconnect 431 along the thickness direction of the first dielectric layer 410, the continuous second preset pattern has the same shape and corresponding position as the continuous first preset pattern. For example, when the first preset pattern is a closed grid pattern, the second preset pattern is also a closed grid pattern, and the lateral dimension of the second preset pattern is slightly larger than or equal to the lateral dimension of the first preset pattern. When the first preset pattern is another pattern, the second preset pattern is also changed accordingly.

[0054] The second dielectric layer 420 is located on the first surface of the second substrate 402. The third dielectric layer 430 is located on the second surface of the second substrate 402, with the first surface of the second substrate 402 opposite to the second surface. The second conductive channel 422, the third conductive channel 423, the second interconnect 432, the third interconnect 433, and the fourth interconnect 434 are all located within the second dielectric layer 420. The second conductive channel 422 is exposed on the surface of the second dielectric layer 420 away from the second substrate 402 and is longitudinally connected to the second interconnect 432. The third interconnect 433 is located on one side of the second conductive channel 422 and is laterally connected to the second interconnect 432. The third conductive channel 423 is located between the third interconnect 433 and the fourth interconnect 434, and is longitudinally connected to both the third interconnect 433 and the fourth interconnect 434. The pad 440 is located within the third dielectric layer 430. The fourth conductive channel 424 is located between the pad 440 and the fourth interconnect 434. The fourth conductive channel 424 passes through the second substrate 402 and is longitudinally connected to the pad 440 and the fourth interconnect 434.

[0055] On the plane containing the cross-section of the second conductive channel 422, the second conductive channel 422 forms a continuous first preset pattern around a portion of the second dielectric layer 420. On the plane containing the cross-section of the second interconnect 432, the second interconnect 432 forms a continuous second preset pattern around a portion of the second dielectric layer 420. In this embodiment, the first dielectric layer 410 and the second dielectric layer 420 are bonded, and the first conductive channel 421 and the second conductive channel 422 are connected, wherein the bonding method includes bonding or adhesive bonding. In some preferred embodiments, the first preset patterns corresponding to the first conductive channel 421 and the second conductive channel 422 coincide.

[0056] On the plane containing the cross-section of the third conductive channel 423, the third conductive channel 423 forms a continuous third preset pattern around a portion of the second dielectric layer 420. On the plane containing the cross-section of the fourth conductive channel 424, the fourth conductive channel 424 forms a continuous fourth preset pattern around a portion of the second dielectric layer 420. On the plane containing the cross-section of the third interconnect 433, the third interconnect 433 forms a continuous fifth preset pattern around a portion of the second dielectric layer 420. On the plane containing the cross-section of the fourth interconnect 434, the fourth interconnect 434 forms a continuous sixth preset pattern around a portion of the second dielectric layer 420. The cross-sections of the second conductive channels 422 to 424 and the second interconnects 432 to 434 are all perpendicular to the thickness direction of the first dielectric layer. The arrangement of the third and fourth preset patterns corresponding to the third conductive channels 423 and 424 can refer to the first preset pattern of this embodiment, and the arrangement of the fifth and sixth preset patterns corresponding to the third interconnects 433 to 434 can refer to the second preset pattern of this embodiment.

[0057] Since the first conductive channel 421 to the fourth conductive channel 424 are continuous, with the same channel volume, the space occupied by the conductive channel is smaller than that of dispersed conductive vias. Consequently, the area of ​​the corresponding interconnects is further reduced, thereby lowering the parasitic capacitances C1, C2, and C3 generated by the interconnects with other metals or substrates. It should be noted that... Figure 3 The parasitic capacitances C1, C2, and C3 shown are merely examples and are not intended to limit the invention.

[0058] Figures 4 to 9b A cross-sectional schematic diagram of different steps in the semiconductor device fabrication method according to the first embodiment of the present invention is shown.

[0059] like Figure 4 As shown, the method begins with a substrate 101 on which a functional layer is formed. For simplicity, the functional layer and internal conductive channels located between the substrate and the dielectric layer are not shown in the figure. The structure of the functional layer can be found in [reference needed]. Figure 1a The relevant descriptions will not be repeated here. In this step, for example, a dielectric material is first deposited on the substrate 101 to form a first wiring layer 111.

[0060] Furthermore, anisotropic etching is used to form trenches 102 in the first wiring layer 111, such as... Figure 5a and Figure 5b As shown, where, Figure 5a Top view, Figure 5b It shows Figure 5a A cross-sectional view taken along the CC line.

[0061] In this step, anisotropic etching can be performed using dry etching methods such as ion milling, plasma etching, reactive ion etching, or laser ablation. For example, the etching time can be controlled so that etching stops near the middle of the first wiring layer 111. After etching, the photoresist mask is removed by dissolving in a solvent or ashing.

[0062] In this embodiment, the pattern of the trench 102 is a connected grid pattern. However, the embodiments of the present invention are not limited to this. Those skilled in the art can make other settings for the connected pattern of the trench 102 as needed to ensure that the pattern of the trench 102 is a continuous pattern and surrounds part of the first wiring layer 111.

[0063] Furthermore, a metal layer is deposited on the first wiring layer 111, and then a chemical mechanical planarization process is used to remove the portion of the metal layer located on the upper surface of the first wiring layer 111 to form interconnects 130, such as... Figure 6a and Figure 6b As shown. Among them, Figure 6a Top view, Figure 6b It shows Figure 6aA cross-sectional view taken along line DD.

[0064] This step, for example, uses magnetron sputtering to form a metal layer. This metal layer is composed, for example, of a metal or alloy selected from platinum, silver, copper, and aluminum, preferably copper. The metal layer fills trench 102 and extends laterally across the surface of the first wiring layer 111. A chemical mechanical planarization process is employed, using the first wiring layer 111 as a stop layer, thereby completely removing the portion of the metal layer located on the surface of the first wiring layer 111. The portion of the metal layer located in trench 102 forms interconnects 130. During the polishing process, because the metal material is uniformly distributed with the material of the first wiring layer, problems such as dishing on the surface of the interconnects 130 are avoided.

[0065] Furthermore, a second wiring layer 112 is formed by depositing a dielectric material over the first wiring layer 111 and the interconnect 130, wherein the first wiring layer 111 and the second wiring layer 112 constitute a dielectric layer 110, as shown below. Figure 7 As shown.

[0066] Furthermore, anisotropic etching is used to form trenches 103 in the second wiring layer 112, such as... Figure 8a and Figure 8b As shown. Among them, Figure 8a Top view, Figure 8b It shows Figure 8a A cross-sectional view taken along line EE.

[0067] In this step, anisotropic etching can be performed using dry etching methods such as ion milling, plasma etching, reactive ion etching, or laser ablation. For example, by controlling the etching time, the etching stops at the surface of interconnect 130, exposing at least a portion of interconnect 130. The photoresist mask is removed after etching by dissolving in a solvent or ashing.

[0068] In this step, the pattern and position of the trench 103 correspond to the interconnect 130. The pattern of the trench 103 is no larger than the pattern of the interconnect 130. In this embodiment, the size of the trench 103 is slightly smaller than the size of the pad, so that the projection of the trench 103 onto the substrate 101 falls within the interconnect 130. However, the embodiments of the present invention are not limited to this. Those skilled in the art can match the size of the interconnect pattern of the trench 103 with the size of the interconnect pattern of the interconnect 130 as needed.

[0069] Furthermore, a metal layer is deposited on the second wiring layer 112, and then a chemical mechanical planarization process is used to remove the portion of the metal layer located on the upper surface of the second wiring layer 112 to form a conductive channel 120, such as... Figure 9a and Figure 9b As shown. Among them, Figure 9a Top view, Figure 9b It shows Figure 9a A cross-sectional view taken along line FF.

[0070] This step, for example, uses magnetron sputtering to form a metal layer. This metal layer is composed, for example, of a metal or alloy selected from platinum, silver, copper, and aluminum, preferably copper. The metal layer fills the trench 103 and extends laterally across the surface of the second wiring layer 112. A chemical mechanical planarization process is employed, using the second wiring layer 112 as a stop layer, thereby completely removing the portion of the metal layer located on the surface of the second wiring layer 112. The portion of the metal layer located in the trench 103 forms a conductive channel 120. During the polishing process, the uniform distribution of the metal material and the dielectric layer avoids problems such as dishing on the surface of the conductive channel 120.

[0071] Figure 10a and Figure 10b A schematic diagram illustrating the effect analysis of an embodiment of the present invention is shown.

[0072] like Figure 10a As shown, in existing technologies, to meet the requirements of electrostatic discharge (ESD), there is a minimum limit to the number of conductive vias 120' between interconnects 130'. If the number is too small, the total cross-sectional area of ​​the conductive vias will be insufficient to handle the ESD current and burn out the circuit. At the same time, due to process limitations, the distribution of multiple conductive vias 120' cannot be too dense. These two factors dictate that the conductive vias 120' must be distributed widely and in large numbers, increasing the space occupied by the conductive vias 120'. Furthermore, the conductive vias 120' must be completely covered by the interconnects 130', thus increasing the area of ​​the interconnects 130'. If this interconnect structure is used for circuit interconnection in semiconductor devices, the parasitic capacitance generated between the interconnects 130' and other metals or substrates on the wafer surface is very large. As the requirements for I / O response speed in 3D memory devices increase, the parasitic capacitance caused by the area of ​​the I / O board interconnects 130' will become increasingly difficult to meet customer needs.

[0073] Figure 8b An interconnect structure according to an embodiment of the present invention is shown, which can also be used for circuit interconnection within or between semiconductor devices.

[0074] like Figure 8b As shown, by forming a conductive channel 120 in the dielectric layer and making the pattern on the plane where the cross-section of the conductive channel 120 is located a continuous pattern, the conductive channel 120 replaces the multiple conductive vias of the prior art. When the conductive channel 120 and the multiple conductive vias have the same volume, the continuous conductive channel 120 does not need to be dispersed, thereby reducing the space occupied by the conductive channel 120.

[0075] Furthermore, since the conductive channel 120 surrounds part of the dielectric layer, the material distribution of the conductive channel 120 and the dielectric layer is uniform when viewed from the plane where the cross-section of the conductive channel 120 is located. This avoids problems such as dishing on the surface of the conductive channel 120 during the planarization process after the conductive channel 120 is formed.

[0076] Furthermore, by forming interconnects that are longitudinally connected to the conductive channel 120, and making the position and shape of the interconnects correspond to the conductive channel 120, the space occupied by the conductive channel 120 is reduced since the conductive channel 120 is continuous. The area of ​​the corresponding interconnect 130 is also further reduced, thereby reducing the parasitic capacitance generated by the interconnect 130 with other metals or substrates.

[0077] Therefore, the semiconductor device semiconductor integration apparatus and the semiconductor device manufacturing method according to embodiments of the present invention improve product yield and reliability.

[0078] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0079] The embodiments of the present invention have been described above. However, these embodiments are merely illustrative and not intended to limit the scope of the invention. The scope of the invention is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of the invention, and all such substitutions and modifications should fall within the scope of the invention.

Claims

1. A semiconductor device, characterized by, include: Dielectric layer; as well as Conductive channels located within the dielectric layer; Specifically, on the plane containing the cross-section of the conductive channel, the conductive channel forms a continuous first predetermined pattern around a portion of the dielectric layer. The cross-section of the conductive channel is perpendicular to the thickness direction of the dielectric layer. It also includes interconnects located within the dielectric layer, the interconnects being longitudinally connected to the conductive channels. Wherein, in the thickness direction of the dielectric layer, the projection of the conductive channel lies within the projection of the interconnect; On the plane containing the cross-section of the interconnect, the interconnect forms a continuous second preset pattern around a portion of the dielectric layer, and the cross-section of the interconnect is perpendicular to the thickness direction of the dielectric layer; the continuous second preset pattern has the same shape and position as the continuous first preset pattern; the semiconductor device includes two conductive channels, and the two conductive channels are connected by bonding.

2. The semiconductor device according to claim 1, characterized in that, The continuous first preset pattern is a closed pattern.

3. The semiconductor device according to claim 2, characterized in that, The continuous first preset pattern includes a grid pattern.

4. The semiconductor device according to claim 1, characterized in that, The conductive channel is located above the interconnect line, and two conductive channels are bonded together on the surface of the dielectric layer.

5. The semiconductor device according to claim 1, characterized in that, The number of interconnects includes two, and the two bonded conductive channels are located between the two interconnects.

6. A semiconductor integrated device, characterized in that, include: A first semiconductor device includes: a first dielectric layer; and a first conductive channel located within the first dielectric layer. The second semiconductor device includes: a second dielectric layer; and a second conductive channel located within the second dielectric layer. The first dielectric layer is bonded to the second dielectric layer, and the first conductive channel is in contact with the second conductive channel; Specifically, on the plane containing the cross-section of the first conductive channel, the first conductive channel forms a continuous first preset pattern around a portion of the first dielectric layer, and / or on the plane containing the cross-section of the second conductive channel, the second conductive channel forms the continuous first preset pattern around a portion of the second dielectric layer. The cross-section of the first conductive channel is perpendicular to the thickness direction of the first dielectric layer, and the cross-section of the second conductive channel is perpendicular to the thickness direction of the second dielectric layer. The semiconductor integrated device further includes: a first interconnect line located within the first dielectric layer and longitudinally connected to the first conductive channel; and a second interconnect line located within the second dielectric layer and longitudinally connected to the second conductive channel, wherein, on the plane where the cross-section of the first interconnect line is located, the first interconnect line forms a continuous second preset pattern around a portion of the first dielectric layer, and the cross-section of the first interconnect line is perpendicular to the thickness direction of the first dielectric layer. On the plane containing the cross-section of the second interconnect line, the second interconnect line forms the continuous second preset pattern around a portion of the second dielectric layer, and the cross-section of the second interconnect line is perpendicular to the thickness direction of the first dielectric layer; The continuous second preset pattern has the same shape and position as the continuous first preset pattern. In the thickness direction of the first dielectric layer, the projection of the first conductive channel is located within the projection of the first interconnect line. In the thickness direction of the second dielectric layer, the projection of the second conductive channel is located within the projection of the second interconnect line.

7. The semiconductor integrated device according to claim 6, characterized in that, The continuous first preset pattern is a closed pattern.

8. The semiconductor integrated device according to claim 7, characterized in that, The continuous first preset pattern includes a grid pattern.

9. The semiconductor integrated device according to claim 6, characterized in that, The second semiconductor device further includes: The second substrate, wherein the second dielectric layer is located between the second substrate and the first dielectric layer; A third interconnect located within the second dielectric layer, the third interconnect located on one side of the second conductive channel and laterally connected to the second interconnect; A fourth interconnect and a third conductive channel are located within the second dielectric layer. The third conductive channel is located between the third interconnect and the fourth interconnect and is longitudinally connected to the third interconnect and the fourth interconnect, respectively. A third dielectric layer located on the surface of the second substrate; Pads located within the third dielectric layer; A fourth conductive channel is located between the pad and the fourth interconnect, the fourth conductive channel passes through the second substrate, and is longitudinally connected to the pad and the fourth interconnect.

10. The semiconductor integrated device according to claim 9, characterized in that, On the plane containing the cross-section of the third conductive channel, the third conductive channel forms a continuous third preset pattern around a portion of the second dielectric layer, and / or on the plane containing the cross-section of the fourth conductive channel, the fourth conductive channel forms the continuous third preset pattern around a portion of the second dielectric layer. The cross-section of the third conductive channel and the cross-section of the fourth conductive channel are both perpendicular to the thickness direction of the second dielectric layer.

11. The semiconductor integrated device according to claim 9, characterized in that, The first semiconductor device further includes a first substrate, and the first dielectric layer is located between the first substrate and the second substrate; The first semiconductor device includes peripheral circuit devices; The second semiconductor device includes a memory circuit device.

12. The semiconductor integrated device according to claim 11, characterized in that, The first dielectric layer and the second dielectric layer are bonded together.

13. A method for manufacturing a semiconductor device, characterized in that, include: Forming a dielectric layer; as well as Forming a conductive channel through the dielectric layer, Specifically, on the plane containing the cross-section of the conductive channel, the conductive channel forms a continuous first predetermined pattern around a portion of the dielectric layer. The cross-section of the conductive channel is perpendicular to the thickness direction of the dielectric layer; It also includes forming interconnects located within the dielectric layer, the interconnects being longitudinally connected to the conductive channels. Wherein, on the plane where the cross-section of the interconnect line is located, the interconnect line forms a continuous second preset pattern around a portion of the dielectric layer, and the cross-section of the interconnect line is perpendicular to the thickness direction of the dielectric layer; the continuous second preset pattern has the same shape and position as the continuous first preset pattern, and the projection of the conductive channel is located within the projection of the interconnect line in the thickness direction of the dielectric layer; two conductive channels are formed, and the two conductive channels are bonded together.

14. The manufacturing method according to claim 13, characterized in that, The continuous first preset pattern is a closed pattern.

15. The manufacturing method according to claim 14, characterized in that, The continuous first preset pattern includes a grid pattern.

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