Thermal management apparatus for three-dimensional stacked integrated circuits

Abstract

A heat treatment device for three-dimensional stacked integrated circuits, two rows of processors are located adjacent to the left side, and the memory is located on the right side; the heat transfer mode includes single-phase convection heat transfer and flow boiling phase change heat transfer; for single-phase convection heat transfer: the cold fluid flows in from the fluid outlet (6), after internal microchannel convection heat exchange, it flows out from the fluid inlet (5), and the fluid flows from right to left in the channel; the microchannel is encrypted in stages along the flow direction, the spacing is maximum at the corresponding position of the memory, and the microchannel is encrypted for the first time at the corresponding position of the right row of processors; the microchannel is encrypted for the second time at the corresponding position of the left row of processors; for flow boiling phase change heat transfer: the cold fluid flows in from the fluid inlet (5), after internal microchannel convection heat exchange, it flows out from the fluid outlet (6), and the fluid flows from left to right in the microchannel; the microchannel is most dense at the inflow, and the channel is widened in stages along the flow direction.

Description

Technical Field

[0001] This invention relates to the technical field of integrated circuit heat dissipation, and in particular to a heat dissipation device for three-dimensional stacked integrated circuits. It is designed for situations where two rows of processors are adjacent on the left and memory is on the right. It can effectively remove the heat from the processors, reduce the maximum temperature of the chip, greatly improve the convective heat transfer effect, and improve the uniformity of temperature distribution. Compared with the overall dense microchannels, it can increase the minimum temperature, reduce the temperature difference, and effectively reduce flow loss. Background Technology

[0002] In recent years, with the rapid development of industrial technology, especially the increasing demands on microelectronic devices in the military field, three-dimensional stacked integrated circuits have attracted significant attention from scholars and engineers both domestically and internationally. These circuits can simultaneously meet multiple requirements such as high frequency, high speed, low latency, low noise, and low power consumption. Researchers have conducted extensive studies on the integration technology, architecture design, cost analysis, temperature control, circuit planning, and reliability analysis of three-dimensional stacked multi-core processors. However, with the continuous increase in industrial demands, the vertical stacking of highly integrated circuits leads to an exponential increase in processor power density over the same area, resulting in a sharp increase in heat generation. Simultaneously, due to the low thermal conductivity of the insulating dielectric layers connecting different circuit layers, this can lead to problems such as heat concentration, localized overheating, and even high-temperature failure. Research data shows that more than 50% of electronic device failures are caused by heat dissipation problems; for every 1°C increase in temperature above 80°C, device reliability decreases by 5%. Traditional cooling methods and external microchannel heat sinks used in two-dimensional devices are no longer effective in removing the heat generated by the devices. Therefore, there is an urgent need to develop solutions for heat dissipation in three-dimensional stacked multi-core processors to guide their design and application.

[0003] Currently, research on the heat dissipation performance of 3D stacked multi-core processors both domestically and internationally mainly focuses on two aspects: 1) rationally arranging the functional modules of the chip to balance the power density of each module and the power density between modules in each layer, preventing circuit failure caused by local overheating; 2) adopting advanced heat transfer enhancement technology to transfer heat from the chip to the external environment. However, with the high integration of 3D stacked multi-core processors, power increases dramatically. Even with rational arrangement of functional modules, the maximum temperature of high-power chips can still reach around 150℃. Simultaneously, due to the low thermal conductivity of the insulating dielectric layer between the layers of the 3D stacked structure, even with external heat transfer enhancement devices such as forced convection fans, back-mounted thermal expansion plates, and liquid-cooled micro-heat sinks, the heat generated by the circuit layers that are not directly in contact with the heat transfer devices is still difficult to dissipate, creating many thermal hazards. The continuously accumulating heat will seriously damage the chip's performance and may even lead to chip failure. The use of thermal vias with high thermal conductivity materials in 3D stacked structures enhances internal heat conduction and balances heat between layers, but the large amount of heat generated internally is still difficult to remove. Furthermore, the layout of thermal vias is limited by wiring resources, and too many thermal vias will reduce chip reliability. Summary of the Invention

[0004] To overcome the shortcomings of the prior art, the technical problem to be solved by the present invention is to provide a heat dissipation device for three-dimensional stacked integrated circuits. When two rows of processors are adjacent on the left and the memory is on the right, it can effectively remove the heat of the processors, reduce the maximum temperature of the chip, greatly improve the convective heat transfer effect, improve the uniformity of temperature distribution, increase the minimum temperature and reduce the temperature difference compared to the overall dense microchannels, and effectively reduce flow loss.

[0005] This heat treatment device for three-dimensional stacked integrated circuits includes: a sealing sheet (1), a cooling layer (2), a multi-core processor layer (3), a connection layer (4), a fluid inlet (5), a fluid outlet (6), a liquid storage tank (7), a non-uniform complex structure microchannel (8), a channel bottom (9), a metal through hole (10), a processor (11), a memory (12), and an insulating dielectric (13).

[0006] The sealing sheet, cooling layer, multi-core processor layer, and connecting layer are arranged in an upper and lower structure, in the following order: sealing sheet, upper cooling layer, upper multi-core processor layer, connecting layer, middle cooling layer, middle multi-core processor layer, connecting layer, middle cooling layer, middle multi-core processor layer, connecting layer, bottom cooling layer, bottom multi-core processor layer.

[0007] The liquid storage tanks on the left and right sides and the microchannels of the four parallel cooling layers are vertically connected. The fluid inlet and fluid outlet of the sealing sheet are connected to the liquid storage tanks to form a fluid circuit. The metal through holes in the cooling layer are electrically connected to the connecting layer and the insulating dielectric of the connecting layer to achieve effective connection of the circuits of each layer.

[0008] Two rows of processors are located adjacent to each other on the left, and the memory is located on the right; the heat transfer methods include single-phase relative heat transfer and flow boiling phase change heat transfer.

[0009] For single-phase heat transfer: cold fluid flows in from fluid outlet (6), undergoes microchannel convection heat transfer inside, and then flows out from fluid inlet (5). The fluid flows from right to left in the channel.

[0010] The microchannels are encrypted in stages along the flow direction, with the largest spacing at the corresponding positions in the memory. The microchannels at the corresponding positions in the right row of processors are encrypted for the first time, and the microchannels at the corresponding positions in the left row of processors are encrypted for the second time.

[0011] For flow boiling phase change heat transfer: cold fluid flows in from the fluid inlet (5), undergoes microchannel convection heat transfer inside, and then flows out from the fluid outlet (6). The fluid flows from left to right in the microchannel. The microchannel is densest at the inlet and gradually widens in stages along the flow direction.

[0012] This invention employs two rows of processors adjacent to each other on the left, with the memory located on the right. Heat transfer methods include one-way relative flow heat transfer and flow-boiling phase change heat transfer. For one-way relative flow heat transfer: cold fluid flows in from the fluid outlet, undergoes microchannel convection heat transfer internally, and then flows out from the fluid inlet, flowing from right to left within the channels. The microchannels are progressively denser along the flow direction, with the largest spacing at the corresponding location in the memory. The microchannels are first denser at the location corresponding to the right row of processors, and then denser again at the location corresponding to the left row of processors. For flow-boiling phase change heat transfer: cold fluid flows in from the fluid inlet, undergoes microchannel convection heat transfer internally, and then flows out from the fluid outlet, flowing from left to right within the microchannels. The microchannels are densest at the inlet and gradually widen along the flow direction. Therefore, it effectively removes heat from the processors, reduces the chip's maximum temperature, significantly improves convection heat transfer, enhances temperature distribution uniformity, and, compared to a denser overall microchannel configuration, increases the minimum temperature, reduces temperature differences, and effectively minimizes flow losses. Attached Figure Description

[0013] Figure 1 A perspective view of a heat dissipation device for a three-dimensional stacked integrated circuit according to the present invention is shown.

[0014] Figure 2(a) is Figure 1 AA section view;

[0015] The components are: 1. Sealing sheet; 2. Cooling layer; 3. Multi-core processor layer; 4. Connecting layer; 5. Fluid inlet; 6. Fluid outlet; 7. Liquid reservoir; 8. Non-uniform complex structure microchannel; 9. Channel bottom; 10. Metal through-hole; 11. Processor; 12. Memory; 13. Insulating dielectric.

[0016] Figure 2(b) is Figure 1 The main view;

[0017] Figure 2(c) is a BB cross-sectional view of Figure 2(b);

[0018] Figure 2(d) is a CC sectional view of Figure 2(b);

[0019] Figure 2(e) is a DD cross-sectional view of Figure 2(b);

[0020] Figure 2(f) is a cross-sectional view of the EE in Figure 2(b);

[0021] Figure 2(g) is the FF cross-sectional view of Figure 2(b);

[0022] Figure 2(h) is a GG cross-sectional view of Figure 2(b);

[0023] Figure 2(i) is the HH cross-sectional view of Figure 2(b);

[0024] Figure 2(j) is a cross-sectional view II of Figure 2(b);

[0025] Figure 2(k) is a cross-sectional view of the JJ section of Figure 2(b);

[0026] Figure 2(l) is a KK cross-sectional view of Figure 2(b);

[0027] Figure 3 This is a schematic diagram of the microchannel structure of the present invention. Detailed Implementation

[0028] like Figure 1-3 As shown, this heat dissipation device for three-dimensional stacked integrated circuits includes: a sealing sheet 1, a cooling layer 2, a multi-core processor layer 3, a connection layer 4, a liquid storage tank 7, a non-uniform complex structure microchannel 8, a channel bottom 9, and an insulating dielectric 13.

[0029] The sealing sheet, cooling layer, multi-core processor layer, and connecting layer are arranged in a top-bottom structure, as follows: sealing sheet, upper cooling layer, upper multi-core processor layer, connecting layer, middle cooling layer, middle multi-core processor layer, connecting layer, middle cooling layer, middle multi-core processor layer, connecting layer, bottom cooling layer, bottom multi-core processor layer; the liquid storage tanks on the left and right sides and the microchannels of the four parallel cooling layers are vertically connected. The fluid inlet and fluid outlet of the sealing sheet are connected to the liquid storage tanks to form a fluid loop; the metal through holes in the cooling layer are electrically connected to the connecting layer, and the insulating dielectric of the connecting layer enables effective communication between the circuits of each layer.

[0030] Two rows of processors are located adjacent to each other on the left, and the memory is located on the right; the heat transfer methods include single-phase relative heat transfer and flow boiling phase change heat transfer.

[0031] For single-phase relative heat transfer: Cold fluid flows in through fluid outlet 6, undergoes microchannel convection heat transfer inside, and then flows out through fluid inlet 5. The fluid flows from right to left within the channel. The microchannels are densified in stages along the flow direction, with the largest spacing at the corresponding position in the memory. The microchannels at the corresponding position of the right row of processors undergo the first densification, and the microchannels at the corresponding position of the left row of processors undergo the second densification. The densification of the channels increases the convection heat transfer area, enhances fluid disturbance, and improves the convection heat transfer effect, overcoming the heat transfer deterioration caused by the increase in fluid temperature and improving the uniformity of temperature distribution. At the same time, compared with the overall denser microchannels, the minimum temperature can be increased, the temperature difference can be reduced, and the flow loss can be effectively reduced.

[0032] For flow-boiling phase change heat transfer: Cold fluid flows in through fluid inlet 5, undergoes microchannel convection heat transfer inside, and then flows out through fluid outlet 6. The fluid flows from left to right within the microchannels. The microchannels are densest at the inlet and gradually widen in stages along the flow direction. The periodically variable cross-section microchannel structure increases the nucleation centers for boiling, enhancing nucleated boiling heat transfer. Simultaneously, the periodically variable cross-section channels easily retain liquid, enhancing annular flow boiling heat transfer. The periodically variable cross-section also increases liquid film disturbance, further improving the boiling heat transfer effect.

[0033] This invention employs two rows of processors adjacent to each other on the left, with the memory located on the right. Heat transfer methods include one-way relative flow heat transfer and flow-boiling phase change heat transfer. For one-way relative flow heat transfer: cold fluid flows in from the fluid outlet, undergoes microchannel convection heat transfer internally, and then flows out from the fluid inlet, flowing from right to left within the channels. The microchannels are progressively denser along the flow direction, with the largest spacing at the corresponding location in the memory. The microchannels are first denser at the location corresponding to the right row of processors, and then denser again at the location corresponding to the left row of processors. For flow-boiling phase change heat transfer: cold fluid flows in from the fluid inlet, undergoes microchannel convection heat transfer internally, and then flows out from the fluid outlet, flowing from left to right within the microchannels. The microchannels are densest at the inlet and gradually widen along the flow direction. Therefore, it effectively removes heat from the processors, reduces the chip's maximum temperature, significantly improves convection heat transfer, enhances temperature distribution uniformity, and, compared to a denser overall microchannel configuration, increases the minimum temperature, reduces temperature differences, and effectively minimizes flow losses.

[0034] Preferably, the inflow point of each microchannel has the same width.

[0035] Preferably, the width of the leftmost channel of the densest channel is 50 micrometers, and the thickness of the rib wall on the leftmost side of the channel is 50 micrometers.

[0036] Preferably, one side of the rib wall has a periodic serrated pit structure with a length of 100 micrometers and a depth of 25 micrometers. The short side of the pit is 30 micrometers away from the flow direction, and the long side is 70 micrometers away from the flow direction. The other side of the rib wall first has a straight structure with a length of 75 micrometers, followed by a periodic pit with a length of 100 micrometers. The short side of the pit is 30 micrometers away from the flow direction, and the long side is 70 micrometers away from the flow direction.

[0037] Preferably, the microchannel structure with a denser middle section is formed by dividing the three densest channels into two channels, and the rib wall is formed by symmetrically creating serrated pit structures on both sides of a rectangular strip rib with a thickness of 75 micrometers.

[0038] Preferably, the pit depth of the serrated pit structure is 25 micrometers, the distance of the short side of the pit along the flow direction is 30 micrometers, and the distance of the long side along the flow direction is 70 micrometers.

[0039] Preferably, the vertical distance between the densest rib structure and the intermediate denser rib structure is 25 micrometers, and the rib thickness at the outlet is 50 micrometers.

[0040] Preferably, the most sparse channel structure is formed by removing the wider ribs of the denser microchannels in the middle, with a channel width of at least 250 micrometers and at most 300 micrometers, and the rib structure is the same as that of the densest channel.

[0041] The present invention has the following advantages and effects:

[0042] 1. With denser channels, the convective heat transfer area increases, fluid disturbance is enhanced, and the convective heat transfer effect is improved. This overcomes the deterioration of heat transfer caused by increased fluid temperature and improves the uniformity of temperature distribution. At the same time, compared with the denser microchannels, it can increase the minimum temperature, reduce the temperature difference, and effectively reduce flow loss.

[0043] 2. The periodically variable cross-section microchannel structure increases the nucleation center of boiling and enhances nucleation boiling heat transfer; at the same time, the periodically variable cross-section channel is easy to retain liquid, which enhances the annular flow boiling heat transfer, and the periodically variable cross-section enhances the disturbance of the liquid film, which increases the boiling heat transfer effect.

[0044] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention shall still fall within the protection scope of the present invention.

Claims

1. A heat dissipation device for three-dimensional stacked integrated circuits, comprising: Sealing sheet (1), cooling layer (2), multi-core processor layer (3), connecting layer (4), fluid inlet (5), fluid outlet (6), liquid storage tank (7), non-uniform complex structure microchannel (8), channel bottom (9), metal through hole (10), processor (11), memory (12), insulating dielectric (13); The sealing sheet, cooling layer, multi-core processor layer, and connecting layer are arranged in a top-bottom structure, as follows: sealing sheet, upper cooling layer, upper multi-core processor layer, connecting layer, middle cooling layer, middle multi-core processor layer, connecting layer, middle cooling layer, middle multi-core processor layer, connecting layer, bottom cooling layer, bottom multi-core processor layer; the liquid storage tanks on the left and right sides and the microchannels of the four parallel cooling layers are vertically connected. The fluid inlet and fluid outlet of the sealing sheet are connected to the liquid storage tanks to form a fluid loop; the metal through holes in the cooling layer are electrically connected to the connecting layer, and the insulating dielectric of the connecting layer enables effective communication between the circuits of each layer. Its features are: Two rows of processors are located adjacent to each other on the left, and the memory is located on the right; the heat transfer methods include single-phase relative heat transfer and flow boiling phase change heat transfer. For single-phase heat transfer: cold fluid flows in from fluid outlet (6), undergoes microchannel convection heat transfer inside, and then flows out from fluid inlet (5). The fluid flows from right to left in the channel. The microchannels are densified in stages along the flow direction. The spacing is largest at the corresponding position of the memory. The microchannels at the corresponding position of the right row processor are densified for the first time. The microchannels at the corresponding position of the left row processor are densified for the second time. For flow boiling phase change heat transfer: cold fluid flows in from the fluid inlet (5), undergoes microchannel convection heat transfer inside, and then flows out from the fluid outlet (6). The fluid flows from left to right in the microchannel. The microchannel is densest at the inlet and gradually widens in stages along the flow direction.

2. The heat dissipation device for three-dimensional stacked integrated circuits according to claim 1, characterized in that: The inflow point of each microchannel has the same width.

3. The heat dissipation device for three-dimensional stacked integrated circuits according to claim 2, characterized in that: The leftmost width of the densest channel is 50 micrometers, and the rib wall thickness of the leftmost channel is 50 micrometers.

4. The heat dissipation device for three-dimensional stacked integrated circuits according to claim 3, characterized in that: One side of the rib wall has a periodic serrated pit structure with a length of 100 micrometers and a depth of 25 micrometers. The short side of the pit is 30 micrometers away from the flow direction, and the long side is 70 micrometers away from the flow direction. The other side of the rib wall first has a straight structure with a length of 75 micrometers, followed by a periodic pit with a length of 100 micrometers. The short side of the pit is 30 micrometers away from the flow direction, and the long side is 70 micrometers away from the flow direction.

5. The heat dissipation device for three-dimensional stacked integrated circuits according to claim 4, characterized in that: The denser microchannel structure in the middle is formed by dividing the three densest channels into two channels. The rib wall is formed by symmetrically creating a serrated pit structure on both sides of a rectangular strip rib with a thickness of 75 micrometers.

6. The heat dissipation device for three-dimensional stacked integrated circuits according to claim 5, characterized in that: The pits in the serrated pit structure are 25 micrometers deep, with the short side of the pit being 30 micrometers along the flow direction and the long side being 70 micrometers along the flow direction.

7. The heat dissipation device for three-dimensional stacked integrated circuits according to claim 6, characterized in that: The vertical distance between the densest rib structure and the intermediate denser rib structure is 25 micrometers, and the rib thickness at the exit is 50 micrometers.

8. The heat dissipation device for three-dimensional stacked integrated circuits according to claim 7, characterized in that: The most sparse channel structure is formed by removing the wider ribs of the denser microchannels in the middle. The channel width is a minimum of 250 micrometers and a maximum of 300 micrometers. The rib structure is the same as that of the densest channel.

Images