Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a method for forming the same. The method comprises: providing a substrate, the substrate comprising a substrate and a device structure, the substrate further comprising a first dielectric layer on the substrate and the device structure, and a first conductive layer in the first dielectric layer, a surface of the second dielectric layer exposing a surface of the first conductive layer; forming a second dielectric layer on the surface of the first dielectric layer; forming a first opening in the second dielectric layer, a bottom of the first opening exposing a top surface of the first conductive layer; forming a second conductive layer on the exposed surface of the first conductive layer, a top surface of the second conductive layer being lower than a surface of the second dielectric layer; after forming the second conductive layer, forming a sidewall layer on sidewall surfaces exposed in the first opening; after forming the sidewall layer, forming a third conductive layer in the first opening. Thus, the performance of the semiconductor structure can be improved, and the manufacturing process is easy to implement with small difficulty and large process window.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] Currently, in semiconductor manufacturing, it is a widely used process to form openings in the interlayer dielectric layer using etching, and then fill the openings with conductive material to form an electrical connection structure for electrical connection between semiconductor devices.

[0003] However, the performance of existing semiconductor structures is still relatively poor. Summary of the Invention

[0004] The technical problem solved by this invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of the semiconductor structure and make the manufacturing process simple, with a large process window and easy to implement.

[0005] To address the aforementioned technical problems, the present invention provides a semiconductor structure comprising: a substrate, the substrate including a substrate and a device structure, the substrate further including a first dielectric layer on the substrate and the device structure, and a first conductive layer within the first dielectric layer, wherein the surface of the second dielectric layer exposes the surface of the first conductive layer; a second dielectric layer located on the surface of the first dielectric layer, the second dielectric layer having a first opening therein, the first opening exposing the top surface of the first conductive layer; a second conductive layer located within the first opening, the second conductive layer also located on the top surface of the first conductive layer; a third conductive layer located within the first opening, the third conductive layer also located on the top surface of the second conductive layer, and the width of the third conductive layer being smaller than the width of the second conductive layer; and a sidewall layer located on the top surface of the second conductive layer, the sidewall layer also located between the sidewall of the third conductive layer and the sidewall of the second dielectric layer.

[0006] Optionally, the thickness of the sidewall layer is 2 nanometers to 5 nanometers.

[0007] Optionally, the sidewall layer may be made of at least one of silicon nitride and silicon oxide.

[0008] Optionally, the material of the first conductive layer includes cobalt, the material of the second conductive layer includes tungsten, and the material of the third conductive layer includes tungsten.

[0009] Optionally, the device structure includes a plurality of channel structures, a plurality of gate structures located on the surfaces of the plurality of channel structures, and a plurality of source / drain structures located on both sides of the plurality of gate structures. The substrate further includes an isolation layer surrounding the plurality of channel structures, the plurality of gate structures, and the plurality of source / drain structures. Optionally, the first conductive layer is electrically connected to the gate structure or the source / drain structure.

[0010] Accordingly, the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a substrate and a device structure, the substrate further including a first dielectric layer located on the substrate and the device structure, and a first conductive layer located within the first dielectric layer, wherein the surface of the second dielectric layer exposes the surface of the first conductive layer; forming a second dielectric layer on the surface of the first dielectric layer; forming a first opening within the second dielectric layer, wherein the bottom of the first opening exposes the top surface of the first conductive layer; forming a second conductive layer on the exposed surface of the first conductive layer, wherein the top surface of the second conductive layer is lower than the surface of the second dielectric layer; after forming the second conductive layer, forming a sidewall layer on the sidewall surface exposed within the first opening; and after forming the sidewall layer, forming a third conductive layer within the first opening.

[0011] Optionally, the process for forming the second conductive layer includes a selective metal deposition process.

[0012] Optionally, the material of the second conductive layer includes tungsten.

[0013] Optionally, the method for forming the third conductive layer includes: after forming the sidewall layer, forming a third conductive material layer in the first opening, wherein the surface of the third conductive material layer is higher than the surface of the second dielectric layer; and planarizing the third conductive material layer until the third conductive layer is formed.

[0014] Optionally, the process for forming the third conductive material layer includes selective metal deposition, and the process for planarizing the third conductive material layer includes chemical mechanical polishing.

[0015] Optionally, the method for forming the sidewall layer includes: after forming the second conductive layer, forming a sidewall material film on the sidewall surface inside the first opening, the top surface of the second conductive layer, and the surface of the second dielectric layer; and etching the sidewall material film using an anisotropic etching process until the sidewall material film on the top surface of the second conductive layer and the surface of the second dielectric layer is removed.

[0016] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0017] In the semiconductor structure formation method provided by the present invention, a sidewall layer is formed on the sidewall surface within the first opening after the formation of the second conductive layer and before the formation of the third conductive layer. This reduces the width of the first opening, which provides space for the formation of the third conductive layer after the formation of the second conductive layer. Therefore, after filling the first opening with the material of the third conductive layer, the difficulty of the polishing slurry penetrating into the first conductive layer during the planarization of the third conductive layer material to form the third conductive layer is increased. This reduces the amount of polishing slurry penetrating into the first conductive layer, reduces damage to the first conductive layer caused by the polishing slurry, and improves the performance of the semiconductor structure. Specifically, after the formation of the second conductive layer, the width of the unfilled portion of the first opening is reduced. Therefore, the gap paths between the sidewall surface and part of the top surface of the second conductive layer, and between the sidewall surface of the third conductive layer and the surrounding dielectric layer, are long and complex. This increases the difficulty of the polishing slurry penetrating into the first conductive layer through these gaps. This reduces the amount of polishing slurry penetrating into the first conductive layer through these gaps, thereby reducing damage to the first conductive layer caused by the polishing slurry and improving the performance of the semiconductor structure. Meanwhile, by forming the second conductive layer, the sidewall layer, and the third conductive layer in sequence, the materials of the second and third conductive layers are easy to fill, and the structures of the second and third conductive layers are regular. As a result, the process of forming the second and third conductive layers is less difficult, has a larger process window, and is easier to implement.

[0018] Furthermore, by employing a selective metal deposition process, the material for forming the second conductive layer can be selectively formed on the exposed top surface of the first conductive layer. This makes the process of forming the second conductive layer less difficult, has a larger process window, and is easier to implement. Thus, while improving the performance of the semiconductor structure, the semiconductor structure is formed with simple process steps. Attached Figure Description

[0019] Figures 1 to 2 This is a cross-sectional structural diagram of each step in a method for forming a semiconductor structure;

[0020] Figures 3 to 9 This is a cross-sectional schematic diagram of the semiconductor structure formation process according to an embodiment of the present invention. Detailed Implementation

[0021] As described in the background section, semiconductor structures have poor performance, which will be explained in detail below with reference to the accompanying drawings.

[0022] Figures 1 to 2 This is a cross-sectional schematic diagram of the steps in a method for forming a semiconductor structure.

[0023] Please refer to Figure 1 A substrate 100 is provided, wherein the substrate 100 has a first conductive layer 110 therein, and the surface of the first conductive layer 110 is exposed on the surface of the substrate 100.

[0024] Please continue to refer to this. Figure 1 A first dielectric layer 120 is formed on the surface of the substrate 100; an opening 121 is formed in the first dielectric layer.

[0025] Please refer to Figure 2 The material of the second conductive layer 130 is filled into the opening 121 to form a second conductive material layer (not shown); the second conductive material layer is planarized until the second conductive layer 130 is formed.

[0026] However, in the above embodiments, the gap path m formed between the sidewall of the second conductive layer 130 and the first dielectric layer 120 (e.g.) Figure 2 As shown, the process is simple and short. During the planarization of the second conductive material layer, the polishing slurry of the planarization process can easily penetrate the first conductive layer 110 through the gap, which will corrode and etch the first conductive layer 110, causing damage to the first conductive layer 110 and resulting in poor semiconductor structure performance.

[0027] To address the aforementioned technical problems, embodiments of the present invention provide a semiconductor structure and a method for forming the same. By sequentially forming a second conductive layer, a sidewall layer, and a third conductive layer within a first opening, the amount of polishing slurry penetrating into the first conductive layer is reduced, thus minimizing damage to the first conductive layer caused by the polishing slurry and improving the performance of the semiconductor structure. Furthermore, the materials for the second and third conductive layers are easy to fill, resulting in a lower process difficulty, a larger process window, and easier implementation for forming the second and third conductive layers.

[0028] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0029] Figures 3 to 9 This is a cross-sectional schematic diagram of the semiconductor structure formation process according to an embodiment of the present invention.

[0030] Please refer to Figure 3 Provides a base of 200.

[0031] The substrate 200 includes a substrate (not shown) and a device structure (not shown).

[0032] The substrate is made of semiconductor material.

[0033] In this embodiment, the substrate is made of silicon.

[0034] In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI), etc. The multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP, etc.

[0035] The device structure includes a plurality of channel structures (not shown), a plurality of gate structures (not shown) located on the surfaces of the plurality of channel structures, and a plurality of source / drain structures (not shown) located on both sides of the plurality of gate structures.

[0036] The channel structure is, for example, a fin structure or a channel located in a planar substrate.

[0037] In this embodiment, the substrate 200 further includes an isolation layer (not shown) surrounding a plurality of channel structures, a plurality of gate structures and a plurality of source / drain structures.

[0038] In this embodiment, the substrate 200 may further include an interconnect structure electrically connected to the device structure, and an insulating layer surrounding the device structure and the interconnect structure.

[0039] The substrate 200 further includes: a first dielectric layer (not shown) located on the substrate and device structure, and a first conductive layer 210 located within the first dielectric layer, wherein the surface of the first dielectric layer exposes the surface of the first conductive layer 210.

[0040] Specifically, the surface of the substrate 200 includes the surface of the first dielectric layer and the surface of the first conductive layer 210.

[0041] In this embodiment, the first conductive layer 210 is electrically connected to the gate structure or the source-drain structure.

[0042] The material of the first dielectric layer includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon carbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon carbide nitride.

[0043] In this embodiment, the material of the first dielectric layer includes silicon oxide.

[0044] In this embodiment, the material of the first conductive layer 210 includes cobalt.

[0045] In other embodiments, the material of the first conductive layer also includes one or more combinations of copper, tungsten, titanium nitride, titanium, tantalum, tantalum nitride, ruthenium, ruthenium nitride, and aluminum.

[0046] Please refer to Figure 4 A second dielectric layer 220 is formed on the surface of the substrate 200.

[0047] The material of the second dielectric layer 220 includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon carbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide, and silicon carbide.

[0048] In this embodiment, the material of the second dielectric layer 220 includes silicon oxide.

[0049] Specifically, in this embodiment, the method for forming the second dielectric layer 220 includes: forming a first dielectric material layer (not shown) on the surface of the substrate 200; planarizing the first dielectric material layer to form the second dielectric layer 220.

[0050] By performing a planarization step on the first dielectric material layer, the surface flatness of the second dielectric layer 220 can be improved, thereby enhancing the performance and reliability of the semiconductor structure.

[0051] In this embodiment, the process for forming the first dielectric material layer includes at least one of spin coating, chemical vapor deposition, and physical vapor deposition.

[0052] In this embodiment, the process for planarizing the first dielectric material layer includes a chemical mechanical polishing process.

[0053] In other embodiments, the second dielectric layer is formed directly on the substrate surface.

[0054] Please refer to Figure 5 A first opening 221 is formed in the second dielectric layer 220, and the bottom of the first opening 221 exposes the top surface of the first conductive layer 210.

[0055] The first opening 221 provides space and support for the subsequent formation of the second conductive layer, the third conductive layer and the sidewall layer.

[0056] In this embodiment, the method for forming a first opening 221 within the second dielectric layer 220 includes: forming an opening mask material layer (not shown) on the surface of the second dielectric layer 220; forming an opening photolithography layer (not shown) on the surface of the opening mask material layer, the opening photolithography layer exposing at least a portion of the surface of the opening mask material layer on the first conductive layer 210; using the opening photolithography layer as a mask, etching the opening mask material layer until the surface of the second dielectric layer 220 is exposed to form an opening mask layer (not shown), the opening mask layer having a first mask opening, the first mask opening exposing at least a portion of the surface of the second dielectric layer 220 on the first conductive layer 210; using the opening mask layer as a mask, etching the second dielectric layer 220 until the surface of the first conductive layer 210 is exposed to form the first opening 221.

[0057] The etching process for the second dielectric layer 220 includes one or a combination of dry etching and wet etching processes.

[0058] In this embodiment, the second dielectric layer 220 is etched using a dry etching process, which helps to improve the morphology of the formed first opening 221, thereby improving the performance of the formed semiconductor structure.

[0059] In this embodiment, after the first opening 221 is formed, the opening mask layer is removed.

[0060] Please refer to Figure 6 A second conductive layer 230 is formed on the exposed surface of the first conductive layer 210, and the top surface of the second conductive layer 230 is lower than the surface of the second dielectric layer 220.

[0061] The purpose of making the top surface of the second conductive layer 230 lower than the surface of the second dielectric layer 220 is to reserve space for the subsequent formation of the sidewall layer and the third conductive layer.

[0062] In this embodiment, the second conductive layer 230 has a width W1.

[0063] In this embodiment, the material of the second conductive layer 230 includes tungsten.

[0064] In this embodiment, the process for forming the second conductive layer 230 includes a selective metal deposition process.

[0065] By employing a selective metal deposition process, the material for forming the second conductive layer 230 can be selectively formed on the exposed top surface of the first conductive layer 210. This makes the process of forming the second conductive layer 230 less difficult, has a larger process window, and is easier to implement. Furthermore, the formed second conductive layer 230 has good adhesion to the first conductive layer 210. Thus, while improving the performance of the semiconductor structure, the semiconductor structure is formed with simple process steps.

[0066] Specifically, the parameters of the selective metal growth process include: the gases used include tungsten fluoride and hydrogen, the flow rate of the tungsten fluoride is 20 standard milliliters / minute to 150 standard milliliters / minute, the flow rate of the hydrogen is 5000 standard milliliters / minute to 8000 standard milliliters / minute, and the temperature is 200 degrees Celsius to 400 degrees Celsius.

[0067] Next, after forming the second conductive layer 230, a sidewall layer is formed on the sidewall surface exposed within the first opening 221. For details on the process of forming the sidewall layer, please refer to [link to documentation]. Figures 7 to 8 .

[0068] Please refer to Figure 7After the second conductive layer 230 is formed, a sidewall material film 240 is formed on the sidewall surface exposed in the first opening 221, the top surface of the second conductive layer 230, and the surface of the second dielectric layer 220.

[0069] The sidewall material membrane 240 provides material for forming the sidewall membrane.

[0070] The material of the sidewall material membrane 240 is different from the material of the second dielectric layer 220.

[0071] In this embodiment, the material of the sidewall material film 240 includes silicon nitride.

[0072] In other embodiments, the sidewall material film is made of silicon oxide.

[0073] In other embodiments, the material of the sidewall material membrane may also include silicon nitride and silicon oxide.

[0074] The process for forming the sidewall material film 240 includes at least one of chemical vapor deposition, physical vapor deposition, and atomic layer deposition (ALD).

[0075] In this embodiment, the sidewall material film 240 is formed using an atomic layer deposition process.

[0076] Atomic layer deposition (ALD) is a process with a relatively low deposition rate, but it produces materials with good density. Therefore, by employing ALD, on the one hand, the thickness of the sidewall material film 240 is well-controllable, which is beneficial for forming a sidewall layer that meets the required thickness. On the other hand, it facilitates the subsequent filling of the third conductive layer, reducing the risk of defects such as voids in the third conductive layer material, thereby improving the performance and reliability of the semiconductor structure.

[0077] Please refer to Figure 8 The sidewall material film 240 is etched using an anisotropic etching process until the sidewall material film 240 on the top surface of the second conductive layer 230 and the surface of the second dielectric layer 220 is removed, and a sidewall layer 241 is formed on the sidewall surface exposed in the first opening 221.

[0078] The sidewall layer 241 serves to reduce the width of the first opening 221.

[0079] In this embodiment, the thickness of the sidewall layer 241 is 2 nanometers to 5 nanometers.

[0080] If the thickness of the sidewall layer 241 is too small, it is not conducive to increasing the gap path length, resulting in poor resistance to polishing slurry penetration and hindering the improvement of semiconductor structure performance and reliability. If the thickness of the sidewall layer 241 is too large, it reduces the space for filling the third conductive layer. Therefore, on the one hand, it has a significant impact on the conductivity of the semiconductor structure; on the other hand, the aspect ratio of the space is too large, making it difficult to fill the third conductive layer and easily leading to voids and defects within the third conductive layer, thus hindering the improvement of semiconductor structure performance and reliability. Therefore, choosing an appropriate thickness for the sidewall layer 241, i.e., a thickness of 2 nanometers to 5 nanometers, allows for easy filling of the third conductive layer, provides good resistance to polishing slurry penetration, and minimizes the impact on the conductivity of the semiconductor structure, thereby improving the performance and reliability of the semiconductor structure.

[0081] The material of the sidewall layer 241 is different from the material of the second dielectric layer 220, and the material of the sidewall layer 241 is different from the material of the second conductive layer 230. Therefore, when the sidewall material film 240 is etched using an anisotropic etching process, the anisotropic etching process can achieve different etching rates for the materials of the sidewall layer 241 and the second dielectric layer 220, and also for the materials of the second conductive layer 230. Consequently, the anisotropic etching process can stop at the surfaces of the second dielectric layer 220 and the second conductive layer 230.

[0082] In this embodiment, the material of the sidewall layer 241 includes silicon nitride.

[0083] In other embodiments, the sidewall layer is made of silicon oxide.

[0084] In other embodiments, the sidewall layer may also include silicon nitride and silicon oxide.

[0085] In this embodiment, the anisotropic etching process includes a dry etching process.

[0086] In this embodiment, the dry etching process includes a plasma etching process.

[0087] Specifically, the parameters of the plasma etching process include: the gas used is argon, and the flow rate of the argon is in the range of 15 standard milliliters / minute to 25 standard milliliters / minute; the first radio frequency power range is 400 watts to 600 watts; and the second radio frequency power range is 200 watts to 500 watts.

[0088] The first radio frequency power is the ionization power, used to dissociate the argon plasma. The second radio frequency power is the etching power.

[0089] Preferably, the argon flow rate is 20 standard milliliters per minute.

[0090] Please refer to Figure 9 After the sidewall 241 is formed, a third conductive layer 250 is formed in the first opening 221, the third conductive layer 250 having a width W2.

[0091] Because after the formation of the second conductive layer 230 and before the formation of the third conductive layer 250, in the first opening 221 (e.g. Figure 8 As shown, the exposed sidewalls form a sidewall layer 241, which reduces the width of the first opening 221 that provides space for the formation of the third conductive layer 250 after the formation of the second conductive layer 230. Therefore, after filling the first opening 221 with the material of the third conductive layer 250, it is possible to increase the difficulty of the polishing slurry penetrating into the first conductive layer 210 during the process of planarizing the material of the third conductive layer 250 to form the third conductive layer 250. This reduces the amount of polishing slurry penetrating into the first conductive layer 210, reduces the damage caused by the polishing slurry to the first conductive layer 210, and improves the performance of the semiconductor structure.

[0092] Specifically, after the second conductive layer 230 is formed, the width of the unfilled portion of the first opening 221 is reduced. Therefore, the sidewalls and part of the top surface of the second conductive layer 230 (such as...) Figure 8 As shown in region A), the gap path between the sidewall of the third conductive layer 250 and the surrounding sidewall layer 241 and the second dielectric layer 220 is long and complex, which increases the difficulty for the polishing slurry to penetrate into the first conductive layer 210 through the gap. As a result, the amount of polishing slurry penetrating into the first conductive layer 210 through the gap can be reduced, thereby reducing the damage caused by the polishing slurry to the first conductive layer 210 and improving the performance of the semiconductor structure.

[0093] Meanwhile, since a wide second conductive layer 230 (width W1) is formed first, and then a narrow third conductive layer 250 (W2) is formed subsequently through the sidewall layer 241, the opening spaces used to fill the material of the second conductive layer 230 have a consistent width in the direction perpendicular to the substrate surface and a simple structure. Similarly, the opening spaces used to fill the material of the third conductive layer 250 have a consistent width in the direction perpendicular to the substrate surface and a simple structure. Therefore, the materials for the second conductive layer 230 and the third conductive layer 250 are easy to fill, and the structures of the second conductive layer 230 and the third conductive layer 250 are regular. Consequently, the process difficulty for forming the second conductive layer 230 and the third conductive layer 250 is low, the process window is large, and it is easy to implement.

[0094] In this embodiment, the material of the third conductive layer 250 includes tungsten.

[0095] In this embodiment, the method for forming the third conductive layer 250 includes: after forming the sidewall layer 241, forming a third conductive material layer (not shown) in the first opening 221, wherein the surface of the third conductive material layer is higher than the surface of the second dielectric layer 220; planarizing the third conductive material layer until it is flush with the surface of the second dielectric layer 220 to form the third conductive layer 250.

[0096] In this embodiment, the process for forming the third conductive material layer includes a selective metal deposition process.

[0097] By employing a selective metal deposition process, a third conductive material layer can be selectively formed on the exposed top surface of the second conductive layer 230. This makes the formation of the third conductive layer 250 less difficult, has a larger process window, and is easier to achieve. Furthermore, the formed third conductive layer 250 has good adhesion to the second conductive layer 230. Thus, while improving the performance of the semiconductor structure, the semiconductor structure is formed with simple process steps.

[0098] Specifically, the parameters of the selective metal growth process include: the gases used include tungsten fluoride and hydrogen, the flow rate of the tungsten fluoride is 20 standard milliliters / minute to 150 standard milliliters / minute, the flow rate of the hydrogen is 5000 standard milliliters / minute to 8000 standard milliliters / minute, and the temperature is 200 degrees Celsius to 400 degrees Celsius.

[0099] In this embodiment, the process for planarizing the third conductive material layer includes a chemical mechanical polishing process.

[0100] Accordingly, one embodiment of the present invention also provides a semiconductor structure formed by the above method. Please refer to [further details]. Figure 9 The semiconductor structure includes: a substrate 200, the substrate 200 including a substrate (not shown) and a device structure (not shown), the substrate 200 further including a first dielectric layer (not shown) located on the substrate and the device structure, and a first conductive layer 210 located within the first dielectric layer, wherein the surface of the first dielectric layer exposes the surface of the first conductive layer 210; a second dielectric layer 220 located on the surface of the first dielectric layer, the second dielectric layer 220 having a first opening 221 (e.g., ...). Figure 5As shown, the first opening 221 exposes the top surface of the first conductive layer 210; a second conductive layer 230 is located within the first opening 221, and the second conductive layer 230 is also located on the top surface of the first conductive layer 210; a third conductive layer 250 is located within the first opening 221, and the third conductive layer 250 is also located on the top surface of the second conductive layer 230, and the width of the third conductive layer 250 is smaller than the width of the second conductive layer 230; a sidewall layer 241 is located on the top surface of the second conductive layer 230, and the sidewall layer 241 is also located between the sidewall of the third conductive layer 250 and the sidewall of the second dielectric layer 220.

[0101] The substrate is made of semiconductor material.

[0102] In this embodiment, the substrate is made of silicon.

[0103] In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI), etc. The multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP, etc.

[0104] The device structure includes a plurality of channel structures (not shown), a plurality of gate structures (not shown) located on the surfaces of the plurality of channel structures, and a plurality of source / drain structures (not shown) located on both sides of the plurality of gate structures.

[0105] The channel structure is, for example, a fin structure or a channel located in a planar substrate.

[0106] In this embodiment, the first conductive layer 210 is electrically connected to the gate structure or the source-drain structure.

[0107] Specifically, the width of the third conductive layer 250 is smaller than the width of the second conductive layer 230, that is, the third conductive layer 250 and the second conductive layer 230 are distributed in an inverted T shape.

[0108] In this embodiment, the substrate 200 further includes an isolation layer (not shown) surrounding a plurality of channel structures, a plurality of gate structures and a plurality of source / drain structures.

[0109] In this embodiment, the substrate 200 may further include an interconnect structure electrically connected to the device structure, and an insulating layer surrounding the device structure and the interconnect structure.

[0110] The material of the first dielectric layer includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon carbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon carbide nitride.

[0111] In this embodiment, the material of the first dielectric layer includes silicon oxide.

[0112] In this embodiment, the material of the first conductive layer 210 includes cobalt.

[0113] In other embodiments, the material of the first conductive layer also includes one or more combinations of copper, tungsten, titanium nitride, titanium, tantalum, tantalum nitride, ruthenium, ruthenium nitride, and aluminum.

[0114] Specifically, the surface of the substrate 200 includes the surface of the first dielectric layer and the surface of the first conductive layer 210.

[0115] The material of the second dielectric layer 220 includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon carbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide, and silicon carbide.

[0116] In this embodiment, the material of the second dielectric layer 220 includes silicon oxide.

[0117] In this embodiment, the material of the second conductive layer 230 includes tungsten.

[0118] In this embodiment, the material of the third conductive layer 250 includes tungsten.

[0119] In this embodiment, the second conductive layer 230 has a width W1.

[0120] In this embodiment, the third conductive layer 250 has a width W2.

[0121] In this embodiment, the thickness of the sidewall layer 241 is 2 nanometers to 5 nanometers.

[0122] The material of the sidewall layer 241 is different from the material of the second dielectric layer 220, and the material of the sidewall layer 241 is different from the material of the second conductive layer 230.

[0123] In this embodiment, the sidewall layer 241 is made of silicon nitride. In other embodiments, the sidewall layer may be made of silicon oxide, or may include both silicon nitride and silicon oxide.

[0124] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: The substrate includes a substrate and a device structure, and the substrate further includes a first dielectric layer located on the substrate and the device structure, and a first conductive layer located within the first dielectric layer, wherein the surface of the first dielectric layer exposes the surface of the first conductive layer. A second dielectric layer is located on the surface of the first dielectric layer, and the second dielectric layer has a first opening that exposes the top surface of the first conductive layer. A second conductive layer is located within the first opening, and the second conductive layer is also located on the top surface of the first conductive layer. The width of the second conductive layer is smaller than the width of the first conductive layer. A third conductive layer is located within the first opening, and the third conductive layer is also located on the top surface of the second conductive layer, and the width of the third conductive layer is smaller than the width of the second conductive layer; A sidewall layer is located on the top surface of the second conductive layer, and the sidewall layer is also located between the sidewall of the third conductive layer and the sidewall of the second dielectric layer.

2. The semiconductor structure as described in claim 1, characterized in that, The thickness of the sidewall layer is 2 nanometers to 5 nanometers.

3. The semiconductor structure as described in claim 1, characterized in that, The material of the sidewall layer includes at least one of silicon nitride and silicon oxide.

4. The semiconductor structure as described in claim 1, characterized in that, The first conductive layer is made of cobalt, the second conductive layer is made of tungsten, and the third conductive layer is made of tungsten.

5. The semiconductor structure as described in claim 1, characterized in that, The device structure includes a plurality of channel structures, a plurality of gate structures located on the surfaces of the plurality of channel structures, and a plurality of source / drain structures located on both sides of the plurality of gate structures. The substrate further includes an isolation layer surrounding the plurality of channel structures, the plurality of gate structures, and the plurality of source / drain structures.

6. The semiconductor structure as described in claim 5, characterized in that, The first conductive layer is electrically connected to the gate structure or the source / drain structure.

7. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including a substrate and a device structure, the substrate further including a first dielectric layer on the substrate and the device structure, and a first conductive layer within the first dielectric layer, the surface of the first dielectric layer exposing the surface of the first conductive layer; A second dielectric layer is formed on the surface of the first dielectric layer; A first opening is formed within the second dielectric layer, and the bottom of the first opening exposes the top surface of the first conductive layer; A second conductive layer is formed on the exposed surface of the first conductive layer, the top surface of the second conductive layer is lower than the surface of the second dielectric layer, and the width of the second conductive layer is smaller than the width of the first conductive layer. After the second conductive layer is formed, a sidewall layer is formed on the sidewall surface exposed in the first opening; After the sidewall layer is formed, a third conductive layer is formed inside the first opening.

8. The method for forming a semiconductor structure as described in claim 7, characterized in that, The process for forming the second conductive layer includes selective metal deposition.

9. The method for forming a semiconductor structure as described in claim 7, characterized in that, The material of the second conductive layer includes tungsten.

10. The method for forming a semiconductor structure as described in claim 7, characterized in that, The method for forming the third conductive layer includes: after forming the sidewall layer, forming a third conductive material layer in the first opening, wherein the surface of the third conductive material layer is higher than the surface of the second dielectric layer; and planarizing the third conductive material layer until the third conductive layer is formed.

11. The method for forming a semiconductor structure as described in claim 10, characterized in that, The process for forming the third conductive material layer includes selective metal deposition, and the process for planarizing the third conductive material layer includes chemical mechanical polishing.

12. The method for forming a semiconductor structure as described in claim 7, characterized in that, The method for forming a sidewall layer includes: after forming a second conductive layer, forming a sidewall material film on the sidewall surface inside the first opening, the top surface of the second conductive layer, and the surface of the second dielectric layer; and etching the sidewall material film using an anisotropic etching process until the sidewall material film on the top surface of the second conductive layer and the surface of the second dielectric layer is removed.

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